Intel£AdvancedBootBlockFlash
Memory(B3)
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet
ProductFeatures
TheIntel®
AdvancedBootBlockFlashMemory(B3)device,manufacturedonIntel’slatest0.13
µmand0.18µmtechnologies,representsafeature-richsolutionatoveralllowersystemcost.
TheB3deviceinx16willbeavailablein48-leadTSOPand48-ballCSPpackages.Thex8
optionofthisproductfamilyisavailableonlyin40-leadTSOPand48-ballµBGA*packages.
AdditionalinformationonthisproductfamilycanbeobtainedbyaccessingIntel’swebsiteat:
http://www.intel.com/design/flash.
•FlexibleSmartVoltageTechnology
—2.7V–3.6VRead/Program/Erase
—12VVPPFastProductionProgramming
•1.65 V–2.5 Vor2.7 V–3.6 VI/OOption
—ReducesOverallSystemPower
•HighPerformance
—2.7V–3.6V:70nsMaxAccessTime
•OptimizedBlockSizes
—Eight8-KBBlocksforData,Topor
BottomLocations
—UptoOneHundredTwenty-Seven64-
KBBlocksforCode
•BlockLocking
—VCC-LevelControlthroughWP#
•LowPowerConsumption
—9mATypicalReadCurrent
•AbsoluteHardware-Protection
—VPP=GNDOption
—VCCLockoutVoltage
•ExtendedTemperatureOperation
—–40°Cto+85°C
•AutomatedProgramandBlockErase
—StatusRegisters
•Intel®FlashDataIntegratorSoftware
—FlashMemoryManager
—SystemInterruptManager
—SupportsParameterStorage,Streaming
Data(e.g.,Voice)
•ExtendedCyclingCapability
—Minimum100,000BlockEraseCycles
Guaranteed
•AutomaticPowerSavingsFeature
—TypicalICCSafterBusInactivity
•StandardSurfaceMountPackaging
—48-BallCSPPackages
—40-and48-LeadTSOPPackages
•DensityandFootprintUpgradeablefor
commonpackage
—8-,16-,32-and64-MbitDensities
•ETOX™VIII(0.13µm)Flash
Technology
—16and32-MbitDensities
•ETOX™VII(0.18µm) FlashTechnology
—16-,32-and64-MbitDensities
•ETOX™VI(0.25µm) FlashTechnology
—8-,16-,and32-MbitDensities
•Thex8optionnotrecommendedfornew
designs
OrderNumber:290580-017
May2003
Notice:Thisspecificationissubjecttochangewithoutnotice.VerifywithyourlocalIntelsales
officethatyouhavethelatestdatasheetbeforefinalizingadesign.
2Datasheet
INFORMATIONINTHISDOCUMENTISPROVIDEDINCONNECTIONWITHINTEL®PRODUCTS.NOLICENSE,EXPRESSORIMPLIED,BY
ESTOPPELOROTHERWISE,TOANYINTELLECTUALPROPERTYRIGHTSISGRANTEDBYTHISDOCUMENT.EXCEPTASPROVIDEDIN
INTEL'STERMSANDCONDITIONSOFSALEFORSUCHPRODUCTS,INTELASSUMESNOLIABILITYWHATSOEVER,ANDINTELDISCLAIMS
ANYEXPRESSORIMPLIEDWARRANTY,RELATINGTOSALEAND/ORUSEOFINTELPRODUCTSINCLUDINGLIABILITYORWARRANTIES
RELATINGTOFITNESSFORAPARTICULARPURPOSE,MERCHANTABILITY,ORINFRINGEMENTOFANYPATENT,COPYRIGHTOROTHER
INTELLECTUALPROPERTYRIGHT.Intelproductsarenotintendedforuseinmedical,lifesaving,orlifesustainingapplications.
Intelmaymakechangestospecificationsandproductdescriptionsatanytime,withoutnotice.
Designersmustnotrelyontheabsenceorcharacteristicsofanyfeaturesorinstructionsmarked"reserved"or"undefined."Intelreservesthesefor
futuredefinitionandshallhavenoresponsibilitywhatsoeverforconflictsorincompatibilitiesarisingfromfuturechangestothem.
The28F008/800B3,28F016/160B3,28F320B3,28F640B3maycontaindesigndefectsorerrorsknownaserratawhichmaycausetheproductto
deviatefrompublishedspecifications.Currentcharacterizederrataareavailableonrequest.
ContactyourlocalIntelsalesofficeoryourdistributortoobtainthelatestspecificationsandbeforeplacingyourproductorder.
Copiesofdocumentswhichhaveanorderingnumberandarereferencedinthisdocument,orotherIntelliteraturemaybeobtainedbycalling1-800-
548-4725orbyvisitingIntel'swebsiteathttp://developer.intel.com/design/flash.
Copyright©IntelCorporation2003.
*Othernamesandbrandsmaybeclaimedasthepropertyofothers.
Datasheet 3
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Contents
1.0 Introduction..................................................................................................................7
1.1 ProductOverview..................................................................................................8
2.0 ProductDescription..................................................................................................9
2.1 PackagePinouts ...................................................................................................9
2.2 BlockOrganization..............................................................................................13
2.2.1 ParameterBlocks...................................................................................14
2.2.2 MainBlocks............................................................................................14
3.0 PrinciplesofOperation..........................................................................................14
3.1 BusOperation .....................................................................................................14
3.1.1 Read.......................................................................................................15
3.1.2 OutputDisable........................................................................................15
3.1.3 Standby..................................................................................................15
3.1.4 DeepPower-Down/Reset.....................................................................15
3.1.5 Write.......................................................................................................16
3.2 ModesofOperation.............................................................................................16
3.2.1 ReadArray .............................................................................................16
3.2.2 ReadIdentifier........................................................................................17
3.2.3 ReadStatusRegister.............................................................................18
3.2.3.1 ClearingtheStatusRegister .....................................................18
3.2.4 ProgramMode........................................................................................19
3.2.4.1 SuspendingandResumingProgram ........................................19
3.2.5 EraseMode............................................................................................19
3.2.5.1 SuspendingandResumingErase.............................................20
3.3 BlockLocking......................................................................................................21
3.3.1 WP#=VILforBlockLocking ..................................................................21
3.3.2 WP#=VIHforBlockUnlocking ..............................................................22
3.4 VPPProgramandEraseVoltages.......................................................................22
3.4.1 VPP=VILforCompleteProtection .........................................................22
3.5 PowerConsumption............................................................................................22
3.5.1 ActivePower ..........................................................................................23
3.5.2 AutomaticPowerSavings(APS)............................................................23
3.5.3 StandbyPower.......................................................................................23
3.5.4 DeepPower-DownMode .......................................................................23
3.6 PowerandResetConsiderations........................................................................23
3.6.1 Power-Up/DownCharacteristics ............................................................23
3.6.2 RP#ConnectedtoSystemReset...........................................................24
3.6.3 VCC,VPPandRP#Transitions...............................................................24
3.7 PowerSupplyDecoupling...................................................................................24
4.0 ThermalandDCCharacteristics........................................................................25
4.1 AbsoluteMaximumRatings.................................................................................25
4.2 OperatingConditions...........................................................................................26
4.3 DCCurrentCharacteristics .................................................................................26
4.4 DCVoltageCharacteristics.................................................................................29
28F008/800B3,28F016/160B3,28F320B3,28F640B3
4Datasheet
5.0 ACCharacteristics...................................................................................................30
5.1 ACReadCharacteristics.....................................................................................30
5.2 ACWriteCharacteristics.....................................................................................34
5.3 EraseandProgramTimings ...............................................................................38
5.4 ResetSpecifications............................................................................................39
5.5 ACI/OTestConditions .......................................................................................40
5.6 DeviceCapacitance............................................................................................40
6.0 ResetOperations .....................................................................................................41
7.0 OrderingInformation..............................................................................................42
8.0 AdditionalInformation...........................................................................................44
AppendixAWriteStateMachineCurrent/NextStates.................................................45
AppendixB ArchitectureBlockDiagram...........................................................................46
AppendixC Word-WideMemoryMapDiagrams.............................................................47
AppendixD Byte-WideMemoryMapDiagrams..............................................................53
AppendixEProgramandEraseFlowcharts....................................................................56
AppendixF MechanicalSpecifications..............................................................................60
Datasheet 5
28F008/800B3,28F016/160B3,28F320B3,28F640B3
RevisionHistory
Number Description
-001 Originalversion
-002
Section3.4,VPPProgramandEraseVoltages,added
UpdatedFigure9:AutomatedBlockEraseFlowchart
UpdatedFigure10:EraseSuspend/ResumeFlowchart(addedprogramtotable)
UpdatedFigure16:ACWaveform:ProgramandEraseOperations(updatednotes)
IPPRmaximumspecificationchangefrom±25µAto±50µA
ProgramandEraseSuspendLatencyspecificationchange
UpdatedAppendixA:OrderingInformation(included8Mand4Minformation)
UpdatedFigure,AppendixD:ArchitectureBlockDiagram(Blockinfo.inwordsnotbytes)
Minorwordingchanges
-003
Combinedbyte-widespecification(previously290605)withthisdocument
Improvedspeedspecificationto80ns(3.0V)and90ns(2.7V)
Improved1.8VI/Ooptiontominimum1.65V(Section3.4)
ImprovedseveralDCcharacteristics(Section4.4)
ImprovedseveralACcharacteristics(Sections4.5and4.6)
Combined2.7Vand1.8VDCcharacteristics(Section4.4)
Added5VVPPreadspecification(Section3.4)
Removed120nsand150nsspeedofferings
MovedOrderingInformationfromAppendixtoSection6.0;updatedinformation
MovedAdditionalInformationfromAppendixtoSection7.0
UpdatedfigureAppendixB,AccessTimevs.CapacitiveLoad
UpdatedfigureAppendixC,ArchitectureBlockDiagram
MovedProgramandEraseFlowchartstoAppendixE
UpdatedProgramFlowchart
UpdatedProgramSuspend/ResumeFlowchart
Minortexteditsthroughout
-004
Added32-Mbitdensity
Added98Hasareservedcommand(Table4)
A1–A20=0wheninreadidentifiermode(Section3.2.2)
StatusregisterclarificationforSR3(Table7)
VCCandVCCQabsolutemaximumspecification=3.7V(Section4.1)
CombinedIPPW
andICCWintoonespecification(Section4.4)
CombinedIPPE
andICCEintoonespecification(Section4.4)
MaxParameterBlockEraseTime(tWHQV2/tEHQV2)reducedto4sec(Section4.7)
MaxMainBlockEraseTime(tWHQV3/tEHQV3)reducedto5sec(Section4.7)
Erasesuspendtime@12V(tWHRH2/tEHRH2)changedto5µstypicaland20µsmaximum
(Section4.7)
OrderingInformationupdated(Section6.0)
WriteStateMachineCurrent/NextStatesTableupdated(AppendixA)
ProgramSuspend/ResumeFlowchartupdated(AppendixF)
EraseSuspend/ResumeFlowchartupdated(AppendixF)
Textclarificationsthroughout
-005
µBGApackagediagramscorrected(Figures3and4)
IPPDtestconditionscorrected(Section4.4)
32-Mbitorderinginformationcorrected(Section6)
µBGApackagetopsidemarkinformationadded(Section6)
-006
VIH
and
VILSpecificationchange(Section4.4)
ICCStestconditionsclarification(Section4.4)
AddedCommandSequenceErrorNote(Table7)
DatasheetrenamedfromSmart3AdvancedBootBlock4-Mbit,8-Mbit,16-MbitFlash
MemoryFamily.
AddeddeviceIDinformationfor4-Mbitx8device
Removed32-Mbitx8toreflectproductofferings
Minortextchanges
-007 CorrectedRP#pindescriptioninTable2,3VoltAdvancedBootBlockPinDescriptions
CorrectedtypographicalerrorfixedinOrderingInformation
28F008/800B3,28F016/160B3,28F320B3,28F640B3
6Datasheet
-008 4-Mbitpackagingandaddressinginformationcorrectedthroughoutdocument
-009 Corrected4-MbitmemoryaddressingtablesinAppendicesDandE
-010 MaxICCDchangedto25µA
VCCMaxon32M(28F320B3)changedto3.3V
-011 Added64-Mbitdensityandfasterspeedofferings
Removedaccesstimevs.capacitanceloadcurve
-012
Changedreferencesof32Mbit80nsdevicesto70nsdevicestoreflectthefasterproduct
offering.
ChangedVccMax=3.3Vreferencetoindicatetheaffectedproductisthe0.25µm32Mbit
device.
Minortexteditsthroughoutdocument.
-013 AddedNewPin-1indicatorinformationon40and48LeadTSOPpackages.
Minortexteditsthroughoutdocument.
-014 Addedspecificationsfor0.13micronproductofferingsthroughoutdocument
-015 Minortexteditsthroughoutdocument.
-016
Adjustedorderinginformation.
Adjustedspecificationsfor0.13micronproductofferings.
RevisedandcorrectedDCCharacteristicsTable.
Adjustedpackagediagraminformation.
Minortexteditsthroughoutdocument.
-017
Updatedorderinginformation.
Adjustedspecificationsfor0.13micronproductofferings.
UpdatedAC/DCCharacteristicsTable.
AddedTSOPandµBGA*packagediagraminformation.
Minortexteditsthroughoutdocument.
Number Description
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 7
1.0 Introduction
ThisdatasheetcontainsthespecificationsfortheIntel£AdvancedBootBlockFlashMemory(B3)
device,whichisoptimizedforportable,low-power,systems.Thisfamilyofproductsfeatures
1.65 V–2.5 Vor2.7 V–3.6 VI/Os,andalowVCC/VPPoperatingrangeof2.7 V–3.6 VforRead,
Program,andEraseoperations.Inaddition,thisfamilyiscapableoffastprogrammingat12 V.
Throughoutthisdocument,theterm“2.7 V”referstothefullvoltagerange2.7 V–3.6 V(except
wherenotedotherwise)and“VPP=12 V”refersto12 V±5%.
Section1.0and2.0provideanoverviewoftheB3device,includingapplications,pinouts,andpin
descriptions.Section3.0describesthememoryorganizationandoperation.Sections4.0and5.0
containtheoperatingspecifications.Finally,Sections6.0and7.0provideorderingandother
referenceinformation.
TheB3devicefeaturesthefollowing:
•Enhancedblockingforeasysegmentationofcodeanddataoradditionaldesignflexibility
•ProgramSuspendtoReadcommand
•VCCQinputof1.65 V–2.5 Vor2.7 V–3.6 VonallI/Os.SeeFigures1through4forpinout
diagramsandVCCQlocation
•Maximumprogramanderasetimespecificationforimproveddatastorage.
Table1. B3DeviceFeatureSummary
Feature 28F008B3,28F016B3 28F800B3,28F160B3,
28F320B3(3),28F640B3 Reference
VCCReadVoltage 2.7V–3.6VSection4.2,
Section4.4
VCCQI/OVoltage 1.65V–2.5Vor2.7V–3.6V Section4.2,4.4
VPPProgram/EraseVoltage 2.7V–3.6Vor11.4V–12.6V Section4.2,4.4
BusWidth 8bit 16bit Table3
Speed 70ns,80ns,90ns,100ns,110ns Section5.1
MemoryArrangement 1024Kbitx8(8Mbit),
2048Kbitx8(16Mbit)
512Kbitx16(8Mbit),
1024Kbitx16(16Mbit),
2048Kbitx16(32Mbit),
4096Kbitx16(64Mbit)
Section2.2
Blocking(toporbottom)
Eight8-Kbyteparameterblocksand
Fifteen64-Kbyteblocks(8Mbit)or
Thirty-one64-Kbytemainblocks(16Mbit)
Sixty-three64-Kbytemainblocks(32Mbit)
Onehundredtwenty-seven64-Kbytemainblocks(64Mbit)
Section2.2
AppendixC
Locking WP#locks/unlocksparameterblocks
AllotherblocksprotectedusingVPPSection3.3
Table8
OperatingTemperature Extended:–40°Cto+85°CSection4.2,
Section4.4
Program/EraseCycling 100,000cycles Section4.2,
Section4.4
Packages 40-leadTSOP(1),
48-BallµBGA*CSP(2) 48-LeadTSOP,
48-BallµBGACSP(2),
48-BallVFBGA Figure4,Figure5
NOTES:
1. 32-Mbitand64-Mbitdensitiesnotavailablein40-leadTSOP.
2. 8-MbitdensitiesnotavailableinµBGA*CSP.
3. VCCMaxis3.3Von0.25µm32-Mbitdevices.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
8Datasheet
1.1 ProductOverview
Intelprovidesthemostflexiblevoltagesolutionintheflashindustry,providingthreediscrete
voltagesupplypins:VCCforReadoperation,VCCQforoutputswing,andVPPforProgramand
Eraseoperation.AllB3productsprovideprogram/erasecapabilityat2.7 Vor12 V(forfast
productionprogramming),andreadwithVCCat2.7 V.Sincemanydesignsreadfromtheflash
memoryalargepercentageofthetime,2.7 VVCCoperationcanprovidesubstantialpower
savings.
TheB3productsareavailableineitherx8orx16packagesinthefollowingdensities:(seeSection
7.0,“OrderingInformation”onpage 42foravailability.)
•8-Mbit(8,388,608-bit)flashmemoryorganizedas512Kwordsof16bitseachor1024
Kbytesof8-bitseach
•16-Mbit(16,777,216-bit)flashmemoryorganizedas1024Kwordsof16bitseachor
2048Kbytesof8-bitseach
•32-Mbit(33,554,432-bit)flashmemoryorganizedas2048Kwordsof16bitseach
•64-Mbit(67,108,864-bit)flashmemoryorganizedas4096Kwordsof16bitseach
Theparameterblocksarelocatedateitherthetop(denotedby-Tsuffix)orthebottom(-Bsuffix)
oftheaddressmapinordertoaccommodatedifferentmicroprocessorprotocolsforkernelcode
location.Theuppertwo(orlowertwo)parameterblockscanbelockedtoprovidecompletecode
securityforsysteminitializationcode.LockingandunlockingiscontrolledbyWP#(seeSection
3.3,“BlockLocking”onpage 21fordetails).
TheCommandUserInterface(CUI)servesastheinterfacebetweenthemicroprocessoror
microcontrollerandtheinternaloperationoftheflashmemory.TheinternalWriteStateMachine
(WSM)automaticallyexecutesthealgorithmsandtimingsnecessaryforProgramandErase
operations,includingverification,therebyunburdeningthemicroprocessorormicrocontroller.The
statusregisterindicatesthestatusoftheWSMbysignifyingblockeraseorwordprogram
completionandstatus.
TheB3flashmemorydeviceisalsodesignedwithanAutomaticPowerSavings(APS)feature,
whichminimizessystemcurrentdrainandallowsforverylowpowerdesigns.Thismodeisentered
followingthecompletionofareadcycle(approximately300nslater).
TheRP#pinprovidesadditionalprotectionagainstunwantedcommandwritesthatmayoccur
duringsystemresetandpower-up/downsequencesduetoinvalidsystembusconditions(see
Section3.6,“PowerandResetConsiderations”onpage 23).
Section3.0,“PrinciplesofOperation”onpage 14givesdetailedexplanationofthedifferentmodes
ofoperation.Section4.0,“ThermalandDCCharacteristics”onpage 25providescompletecurrent
andvoltagespecifications.RefertoSection5.1,“ACReadCharacteristics”onpage 30forread,
program,anderaseperformancespecifications.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 9
2.0 ProductDescription
Thissectionexplainsdevicepindescriptionandpackagepinouts.
2.1 PackagePinouts
TheB3flashmemorydeviceisavailablein40-leadTSOP(x8,Figure1),
48-leadTSOP(x16,Figure2),48-ballµBGA(x8andx16,Figure4andFigure5,respectively),and
48-ballVFBGA(x16,Figure5)packages.
0580_01
NOTES:
1. 40-LeadTSOPavailablefor8-Mbitand16-Mbitdensitiesonly.
2. LowerdensitieshaveNContheupperaddresspins.Forexample,an8-MbitdevicewillhaveNConPin38.
0580_02
Figure1.40-LeadTSOPPackageforx8Configurations
A
17
GND
A
20
A
19
A
10
DQ
7
DQ
6
DQ
5
DQ
4
V
CCQ
V
CC
NC
DQ
3
DQ
2
DQ
1
DQ
0
OE#
GND
CE#
A
0
A
16
A
15
A
14
A
13
A
12
A
11
A
9
A
8
WE#
RP#
V
PP
WP#
A
18
A
7
A
6
A
5
A
4
A
3
A
2
A
1
16M
8M
AdvancedBootBlock
40-LeadTSOP
10mmx20mm
TOPVIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
4M
Figure2.48-LeadTSOPPackageforx16Configurations
AdvancedBootBlock
48-LeadTSOP
12mmx20mm
TOPVIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
16
V
CCQ
GND
DQ
15
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
21
A
20
WE#
RP#
V
PP
WP#
A
19
A
18
A
17
A
7
A
6
A
5
21
22
23
24
OE#
GND
CE#
A
0
28
27
26
25
A
4
A
3
A
2
A
1
32M
16M
64M
28F008/800B3,28F016/160B3,28F320B3,28F640B3
10 Datasheet
Note: Thetopsidemarkingon8Mb,16Mb,and32MbIntel£AdvancedBootBlock40Land48LTSOP
productswillconverttoawhiteinktriangleasaPin-1indicator.Productswithoutthewhite
trianglewillcontinuetouseadimpleasaPin-1indicator.Therearenootherchangesinpackage
size,materials,functionality,customerhandling,ormanufacturability.Productwillcontinueto
meetstringentIntelqualityrequirements.TheproductsaffectedarethefollowingIntelOrdering
Codes:
Figure3.NewMarkforPin-1indicatorfor40-Lead8Mb,16MbTSOPand48-Lead8Mb,16
Mband32MbTSOP
CurrentMark:
NewMark:
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 11
0580_04
NOTES:
1. A19andA20indicatetheupgradeaddressconnections.Lowerdensitydeviceswillnothavetheupper
addresssolderballs.Routingisnotrecommendedinthisarea.A20
istheupgradeaddressforthe
16-Mbitdevice.
OrderingInformationValidCombinations
40-LeadTSOP 48-LeadTSOP
Ext.Temp.64
Mbit TE28F640B3TC70
TE28F640B3BC70
Ext.Temp.32
Mbit
TE28F320B3TD70
TE28F320B3BD70
TE28F320B3TC70
TE28F320B3BC70
TE28F320B3TC90
TE28F320B3BC90
TE28F320B3TA100
TE28F320B3BA100
TE28F320B3TA110
TE28F320B3BA110
Ext.Temp.16
Mbit
TE28F160B3TC70
TE28F160B3BC70
TE28F160B3TC80
TE28F160B3BC80
TE28F016B3TA90 TE28F160B3TA90
TE28F016B3BA90 TE28F160B3BA90
TE28F016B3TA110 TE28F160B3TA110
TE28F016B3BA110 TE28F160B3BA110
Ext.Temp.8
Mbit
TE28F008B3TA90 TE28F800B3TA90
TE28F008B3BA90 TE28F800B3BA90
TE28F008B3TA110 TE28F800B3TA110
TE28F008B3BA110 TE28F800B3BA110
Figure4.x848-BallµBGA*ChipSizePackage(TopView,BallDown)
A14
A15
A16
A17
VCCQ
A12
A10
A13
NC
A11
A8
WE#
A9
D5
D6
VPP
RP#
NC
WP#
A19
D2
D3
A20
A18
A6
NC
NC
A7
A5
A3
CE#
D0
A4
A2
A1
A0
GND
GND D7 NC D4 VCC NC D1 OE#
A
B
C
D
E
F
13254768
16M
8M
NC
28F008/800B3,28F016/160B3,28F320B3,28F640B3
12 Datasheet
0580_03
NOTES:
1. A19,A20,andA21indicatetheupgradeaddressconnections.Lowerdensitydeviceswillnothavetheupper
addresssolderballs.Routingisnotrecommendedinthisarea.A19istheupgradeaddressforthe
16-Mbitdevice.A20istheupgradeaddressforthe32-Mbitdevice.A21istheupgradeaddressforthe64-Mbit
device.
2. Table 2,“B3DevicePinDescriptions”onpage 13detailstheusageofeachdevicepin.
Figure5.x1648-BallVeryFinePitchBGAandµBGA*ChipSizePackage(TopView,Ball
Down)
A
B
C
D
E
F
13254768
A13
A14
A15
A16
VCCQ
A11
A10
A12
D14
D15
A8
WE#
A9
D5
D6
VPP
RP#
A21
D11
D12
WP#
A18
A20
D2
D3
A19
A17
A6
D8
D9
A7
A5
A3
CE#
D0
A4
A2
A1
A0
Vss
Vss D7 D13 D4 VCC D10 D1 OE#
16M
32M64M
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 13
2.2 BlockOrganization
TheB3deviceisanasymmetricallyblockedarchitecturethatenablessystemintegrationofcode
anddatawithinasingleflashdevice.Eachblockcanbeerasedindependentlyoftheothersupto
100,000times.Fortheaddresslocationsofeachblock,seethememorymapsinAppendixC.
Table2. B3DevicePinDescriptions
Symbol Type NameandFunction
A0–A21 INPUT
ADDRESSINPUTSformemoryaddresses.Addressesareinternallylatchedduringaprogramor
erasecycle.
28F008B3:A[0-19],28F016B3:A[0-20],
28F800B3:A[0-18],28F160B3:A[0-19],
28F320B3:A[0-20],28F640B3:A[0-21]
DQ0–DQ7INPUT/
OUTPUT
DATAINPUTS/OUTPUTS:InputsarraydataonthesecondCE#andWE#cycleduringaProgram
command.InputscommandstotheCommandUserInterfacewhenCE#andWE#areactive.Datais
internallylatched.Outputsarray,identifierandstatusregisterdata.Thedatapinsfloattotri-statewhen
thechipisde-selectedortheoutputsaredisabled.
DQ8–
DQ15 INPUT/
OUTPUT
DATAINPUTS/OUTPUTS:InputsarraydataonthesecondCE#andWE#cycleduringaProgram
command.Dataisinternallylatched.Outputsarrayandidentifierdata.Thedatapinsfloattotri-state
whenthechipisde-selected.Notincludedonx8products.
CE# INPUT CHIPENABLE:Activatestheinternalcontrollogic,inputbuffers,decodersandsenseamplifiers.CE#
isactivelow.CE#highde-selectsthememorydeviceandreducespowerconsumptiontostandby
levels.
OE# INPUT OUTPUTENABLE:Enablesthedevice’soutputsthroughthedatabuffersduringaReadoperation.
OE#isactivelow.
WE# INPUT WRITEENABLE:ControlswritestotheCommandRegisterandmemoryarray.WE#isactivelow.
AddressesanddataarelatchedontherisingedgeofthesecondWE#pulse.
RP# INPUT
RESET/DEEPPOWER-DOWN:Usestwovoltagelevels(VIL,VIH)tocontrolreset/deeppower-down
mode.
WhenRP#isatlogiclow,thedeviceisinreset/deeppower-downmode,whichdrivestheoutputs
toHigh-Z,resetstheWriteStateMachine,andminimizescurrentlevels(ICCD).
WhenRP#isatlogichigh,thedeviceisinstandardoperation.WhenRP#transitionsfromlogic-
lowtologic-high,thedevicedefaultstothereadarraymode.
WP# INPUT
WRITEPROTECT:Providesamethodforlockingandunlockingthetwolockableparameterblocks.
WhenWP#isatlogiclow,thelockableblocksarelocked,preventingProgramandErase
operationstothoseblocks.IfaProgramorEraseoperationisattemptedonalockedblock,SR.1and
eitherSR.4[program]orSR.5[erase]willbesettoindicatetheoperationfailed.
WhenWP#isatlogichigh,thelockableblocksareunlockedandcanbeprogrammedorerased.
SeeSection3.3fordetailsonwriteprotection.
VCCQ INPUT
OUTPUTVCC:Enablesalloutputstobedrivento1.8 V–2.5 VwhiletheVCCisat2.7 V–3.3 V.Ifthe
VCCisregulatedto2.7V–2.85V,VCCQcanbedrivenat1.65 V–2.5 Vtoachievelowestpower
operation(seeSection4.4).
ThisinputmaybetieddirectlytoVCC(2.7 V–3.6 V).
VCC DEVICEPOWERSUPPLY:2.7 V–3.6 V
VPP
PROGRAM/ERASEPOWERSUPPLY:SuppliespowerforProgramandEraseoperations.VPPmay
bethesameasVCC(2.7 V–3.6 V)forsinglesupplyvoltageoperation.Forfastprogrammingat
manufacturing,11.4 V–12.6 VmaybesuppliedtoVPP.Thispincannotbeleftfloating.Applying
11.4 V–12.6 VtoVPP
canonlybedoneforamaximumof1000cyclesonthemainblocksand2500
cyclesontheparameterblocks.
VPPmaybeconnectedto12 Vforatotalof80hoursmaximum(see
Section3.4fordetails).
VPP<VPPLKprotectsmemorycontentsagainstinadvertentorunintendedprogramanderase
commands.
GND GROUND:Forallinternalcircuitry.Allgroundinputsmustbeconnected.
NC NOCONNECT:Pinmaybedrivenorleftfloating.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
14 Datasheet
2.2.1 ParameterBlocks
TheB3flashmemoryarchitectureincludesparameterblockstofacilitatestorageoffrequently
updatedsmallparameters(i.e.,datathatwouldnormallybestoredinanEEPROM).Theword-
rewritefunctionalityofEEPROMscanbeemulatedusingsoftwaretechniques.Eachdevice
containseightparameterblocksof8Kbytes/4Kwords(8192bytes/4,096words)each.
2.2.2 MainBlocks
Aftertheparameterblocks,theremainderofthearrayisdividedintoequal-sizemainblocks
(65,536bytes/32,768words)fordataorcodestorage.The8-Mbitdevicecontains15mainblocks;
16-Mbitflashhas31mainblocks;32-Mbithas63mainblocks;64-Mbithas127mainblocks.
3.0 PrinciplesofOperation
FlashmemorycombinesEEPROMfunctionalitywithin-circuitelectricalprogram-and-erase
capability.TheB3devicefamilyutilizesaCommandUserInterface(CUI)andautomated
algorithmstosimplifyProgramandEraseoperations.TheCUIallowsfor100%CMOS-level
controlinputsandfixedpowersuppliesduringerasureandprogramming.
WhenVPP<VPPLK,thedevicewillexecuteonlythefollowingcommandssuccessfully:Read
Array,ReadStatusRegister,ClearStatusRegister,andReadIdentifier.Thedeviceprovides
standardEEPROMread,standby,andOutput-Disableoperations.Manufactureridentificationand
deviceidentificationdatacanbeaccessedthroughtheCUI.Allfunctionsassociatedwithaltering
memorycontents,namelyprogramanderase,areaccessibleviatheCUI.TheinternalWriteState
Machine(WSM)completelyautomatesProgramandEraseoperations,whiletheCUIsignalsthe
startofanoperationandthestatusregisterreportsstatus.TheCUIhandlestheWE#interfacetothe
dataandaddresslatches,aswellassystemstatusrequestsduringWSMoperation.
3.1 BusOperation
TheB3flashmemorydeviceperformsread,program,anderasein-systemviathelocalCPUor
microcontroller.Allbuscyclestoorfromtheflashmemoryconformtostandardmicrocontroller
buscycles.Fourcontrolpinsdictatethedataflowinandoutoftheflashcomponent:CE#,OE#,
WE#,andRP#.Table3summarizesthesebusoperations.
Table3. BusOperations(1)
Mode Note RP# CE# OE# WE# DQ0–7 DQ8–15
Read(Array,Status,orIdentifier) 2–4 VIH VIL VIL VIH DOUT DOUT
OutputDisable 2 VIH VIL VIH VIH HighZ HighZ
Standby 2 VIH VIH XXHighZ HighZ
Reset 2,7V
IL XXXHighZ HighZ
Write 2,5–7 VIH VIL VIH VIL DIN DIN
NOTES:
1. 8-bitdevicesuseonlyDQ[0:7],16-bitdevicesuseDQ[0:15].
2. XmustbeVIL,VIHforcontrolpinsandaddresses.
3. SeeDCCharacteristicsforVPPLK,VPP1,VPP2,VPP3,VPP4
voltages.
4. Manufactureranddevicecodesmayalsobeaccessedinreadidentifiermode(A1–A21 =0).SeeTable5.
5. RefertoTable6forvalidDIN
duringaWriteoperation.
6. Toprogramorerasethelockableblocks,holdWP#atVIH.
7. RP#mustbeatGND± 0.2 Vtomeetthemaximumdeeppower-downcurrentspecified.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 15
3.1.1 Read
Theflashmemoryhasfourreadmodesavailable:readarray,readidentifier,readstatus,andread
query.ThesemodesareaccessibleindependentoftheVPPvoltage.TheappropriateReadMode
commandmustbeissuedtotheCUItoenterthecorrespondingmode.Uponinitialdevicepower-
uporafterexitfromreset,thedeviceautomaticallydefaultstoread-arraymode.
CE#andOE#mustbedrivenactivetoobtaindataattheoutputs.CE#isthedeviceselection
control;whenactive,itenablestheflashmemorydevice.OE#isthedataoutputcontrol,andit
drivestheselectedmemorydataontotheI/Obus.Forallreadmodes,WE#andRP#mustbeat
VIH.Figure6illustratesareadcycle.
3.1.2 OutputDisable
WithOE#atalogic-highlevel(VIH),thedeviceoutputsaredisabled.Outputpinsareplacedina
high-impedancestate.
3.1.3 Standby
DeselectingthedevicebybringingCE#toalogic-highlevel(VIH)placesthedeviceinstandby
mode,whichsubstantiallyreducesdevicepowerconsumptionwithoutanylatencyforsubsequent
readaccesses.Instandby,outputsareplacedinahigh-impedancestateindependentofOE#.If
deselectedduringProgramorEraseoperation,thedevicecontinuestoconsumeactivepoweruntil
theProgramorEraseoperationiscomplete.
3.1.4 DeepPower-Down/Reset
Fromreadmode,RP#atVILfortimetPLPHdeselectsthememory,placesoutputdriversinahigh-
impedancestate,andturnsoffallinternalcircuits.Afterreturnfromreset,atimetPHQVisrequired
untiltheinitialread-accessoutputsarevalid.Adelay(tPHWLortPHEL)isrequiredafterreturnfrom
resetbeforeawritecanbeinitiated.Afterthiswake-upinterval,normaloperationisrestored.The
CUIresetstoread-arraymode,andthestatusregisterissetto80H.Figure11Aillustratesthiscase.
IfRP#istakenlowfortimetPLPHduringaProgramorEraseoperation,theoperationwillbe
abortedandthememorycontentsattheabortedlocation(foraprogram)orblock(foranerase)are
nolongervalid,sincethedatamaybepartiallyerasedorwritten.Theabortprocessgoesthrough
thefollowingsequence:
1. WhenRP#goeslow,thedeviceshutsdowntheoperationinprogress,aprocessthattakestime
tPLRHtocomplete.
2. AfterthistimetPLRH,thepartwilleitherresettoread-arraymode(ifRP#hasgonehighduring
tPLRH,Figure11B),orenterresetmode(ifRP#isstilllogiclowaftertPLRH,Figure11C).
3. Inbothcases,afterreturningfromanabortedoperation,therelevanttimetPHQVortPHWL/
tPHELmustbewaitedbeforeaReadorWriteoperationisinitiated,asdiscussedintheprevious
paragraph.However,inthiscase,thesedelaysarereferencedtotheendoftPLRHratherthan
whenRP#goeshigh.
Aswithanyautomateddevice,itisimportanttoassertRP#duringsystemreset.Whenthesystem
comesoutofreset,theprocessorexpectstoreadfromtheflashmemory.Automatedflash
memoriesprovidestatusinformationwhenreadduringprogramorBlock-Eraseoperations.Ifa
CPUresetoccurswithnoflashmemoryreset,properCPUinitializationmaynotoccurbecausethe
flashmemorymaybeprovidingstatusinformationinsteadofarraydata.Intel®Flashmemories
allowproperCPUinitializationfollowingasystemresetthroughtheuseoftheRP#input.Inthis
application,RP#iscontrolledbythesameRESET#signalthatresetsthesystemCPU.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
16 Datasheet
3.1.5 Write
AwriteoccurswhenbothCE#andWE#arelowandOE#ishigh.Commandsarewrittentothe
CommandUserInterface(CUI)usingstandardmicroprocessorwritetimingstocontrolFlash
operations.TheCUIdoesnotoccupyanaddressablememorylocation.Theaddressanddatabuses
arelatchedontherisingedgeofthesecondWE#orCE#pulse,whicheveroccursfirst.Table6
showstheavailablecommands,andAppendixAprovidesdetailedinformationonmovingbetween
thedifferentmodesofoperationusingCUIcommands.
Twocommandsmodifyarraydata:Program(40H),andErase(20H).Writingeitherofthese
commandstotheinternalCommandUserInterface(CUI)initiatesasequenceofinternallytimed
functionsthatculminateinthecompletionoftherequestedtask(unlessthatoperationisabortedby
eitherRP#beingdriventoVILfortPLRH
oranappropriateSuspendcommand).
3.2 ModesofOperation
Theflashmemoryhasfourreadmodes(readarray,readidentifier,readstatus,andreadquery;see
AppendixB),andtwowritemodes(programandblockerase).Threeadditionalmodes(erase
suspendtoprogram,erasesuspendtoread,andprogramsuspendtoread)areavailableonlyduring
suspendedoperations.Table4summarizesthecommandsusedtoreachthesemodes.AppendixA
isacomprehensivechartshowingthestatetransitions.
3.2.1 ReadArray
WhenRP#transitionsfromVIL(reset)toVIH,thedevicedefaultstoread-arraymodeandwill
respondtotheread-controlinputs(CE#,addressinputs,andOE#)withoutanyadditionalCUI
commands.
Whenthedeviceisinread-arraymode,fourcontrolsignalscontroldataoutput.
•WE#mustbelogichigh(VIH)
•CE#mustbelogiclow(VIL)
•OE#mustbelogiclow(VIL)
•RP#mustbelogichigh(VIH)
Inaddition,theaddressofthepreferredlocationmustbeappliedtotheaddresspins.Ifthedeviceis
notinread-arraymode,aswouldbethecaseafteraProgramorEraseoperation,theReadArray
command(FFH)mustbewrittentotheCUIbeforearrayreadscanoccur.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 17
NOTE: SeeAppendixAformodetransitioninformation.
3.2.2 ReadIdentifier
Toreadthemanufactureranddevicecodes,thedevicemustbeinread-identifiermode,whichcan
bereachedbywritingtheReadIdentifiercommand(90H).Onceinread-identifiermode,A0=0
outputsthemanufacturer’sidentificationcode,andA0=1outputsthedeviceidentifier(see
Table5)Note:A1–A21=0.Toreturntoread-arraymode,writetheRead-Arraycommand(FFH).
Table4. CommandCodesandDescriptions
Code DeviceMode Description
00,01,
60,2F,
C0,98
Invalid/
Reserved Unassignedcommandsthatshouldnotbeused.Intelreservestherighttoredefinethese
codesforfuturefunctions.
FF ReadArray Placesthedeviceinread-arraymode,suchthatarraydatawillbeoutputonthedatapins.
40 ProgramSet-Up
Thisisatwo-cyclecommand.ThefirstcyclepreparestheCUIforaprogramoperation.The
secondcyclelatchesaddressesanddatainformationandinitiatestheWSMtoexecutethe
programalgorithm.TheflashoutputsstatusregisterdatawhenCE#orOE#istoggled.ARead
Arraycommandisrequiredafterprogrammingtoreadarraydata.SeeSection3.2.4.
10 Alternate
ProgramSet-Up (See40H/ProgramSet-Up)
20 EraseSet-Up
PreparestheCUIfortheEraseConfirmcommand.IfthenextcommandisnotanErase
Confirmcommand,thentheCUIwill(a)setbothSR.4andSR.5ofthestatusregistertoa“1,”
(b)placethedeviceintotheread-status-registermode,and(c)waitforanothercommand.See
Section3.2.5.
D0
EraseConfirm
Program/Erase
Resume
IfthepreviouscommandwasanEraseSet-Upcommand,thentheCUIwillclosetheaddress
anddatalatches,andbeginerasingtheblockindicatedontheaddresspins.Duringerase,the
devicewillonlyrespondtotheReadStatusRegisterandEraseSuspendcommands.The
devicewilloutputstatus-registerdatawhenCE#orOE#istoggled.
IfaProgramorEraseoperationwaspreviouslysuspended,thiscommandwillresumethat
operation.
B0 Program/Erase
Suspend
IssuingthiscommandwillbegintosuspendthecurrentlyexecutingProgram/Eraseoperation.
Thestatusregisterwillindicatewhentheoperationhasbeensuccessfullysuspendedby
settingeithertheprogramsuspend(SR.2)orerasesuspend(SR.6),andtheWSMstatusbit
(SR.7)toa“1”(ready).TheWSMwillcontinuetoidleintheSUSPENDstate,regardlessofthe
stateofallinput-controlpinsexceptRP#,whichwillimmediatelyshutdowntheWSMandthe
remainderofthechip,ifitisdriventoVIL.SeeSection3.2.4.1andSection3.2.4.1.
70 ReadStatus
Register
Thiscommandplacesthedeviceintoread-status-registermode.Readingthedevicewilloutput
thecontentsofthestatusregister,regardlessoftheaddresspresentedtothedevice.The
deviceautomaticallyentersthismodeafteraProgramorEraseoperationhasbeeninitiated.
SeeSection3.2.3.
50 ClearStatus
Register
TheWSMcansettheblock-lockstatus(SR.1),VPPstatus(SR.3),programstatus(SR.4),and
erasestatus(SR.5)bitsinthestatusregisterto“1,”butitcannotclearthemto“0.”Issuingthis
commandclearsthosebitsto“0.”
90 ReadIdentifier Putsthedeviceintotheintelligent-identifier-readmode,sothatreadingthedevicewilloutput
themanufactureranddevicecodes(A0=0formanufacturer,A0=1fordevice,allother
addressinputsmustbe0).SeeSectionSection3.2.2.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
18 Datasheet
3.2.3 ReadStatusRegister
ThedevicestatusregisterindicateswhenaProgramorEraseoperationiscomplete,andthesuccess
orfailureofthatoperation.Toreadthestatusregister,issuetheReadStatusRegister(70H)
commandtotheCUI.ThiscausesallsubsequentReadoperationstooutputdatafromthestatus
registeruntilanothercommandiswrittentotheCUI.Toreturntoreadingfromthearray,issuethe
ReadArray(FFH)command.
Thestatus-registerbitsareoutputonDQ0–DQ7.Theupperbyte,DQ8–DQ15,outputs00Hduringa
ReadStatusRegistercommand.
ThecontentsofthestatusregisterarelatchedonthefallingedgeofOE#orCE#,whichprevents
possibleBuserrorsthatmightoccurifstatus-registercontentschangewhilebeingread.CE#or
OE#mustbetoggledwitheachsubsequentstatusread,orthestatusregisterwillnotindicate
completionofaProgramorEraseoperation.
WhentheWSMisactive,SR.7willindicatethestatusoftheWSM;theremainingbitsinthestatus
registerindicatewhetherornottheWSMwassuccessfulinperformingthepreferredoperation(see
Table7onpage 21).
3.2.3.1 ClearingtheStatusRegister
TheWSMsetsstatusbits1through7to“1,”andclearsbits2,6,and7to“0,”butcannotclear
statusbits1or3through5to“0.”Becausebits1,3,4,and5indicatevariouserrorconditions,
thesebitscanbeclearedonlythroughtheClearStatusRegister(50H)command.Byallowingthe
systemsoftwaretocontroltheresettingofthesebits,severaloperationsmaybeperformed(suchas
cumulativelyprogrammingseveraladdressesorerasingmultipleblocksinsequence)before
readingthestatusregistertodetermineifanerroroccurredduringthatseries.Clearthestatus
registerbeforebeginninganothercommandorsequence.Note,again,thattheReadArray
commandmustbeissuedbeforedatacanbereadfromthememoryarray.
Table5. ReadIdentifierTable
Size Mfr.ID
DeviceIdentifier
-T
(TopBoot) -B
(BottomBoot)
28F004B3 0089H D4H D5H
28F400B3 8894H 8895H
28F008B3
0089H
D2H D3H
28F800B3 8892H 8893H
28F016B3 D0H D1H
28F160B3
0089H
8890H 8891H
28F320B3 8896H 8897H
28F640B3 8898H 8899H
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 19
3.2.4 ProgramMode
Programmingisexecutedusingatwo-writesequence.TheProgramSetupcommand(40H)is
writtentotheCUIfollowedbyasecondwritethatspecifiestheaddressanddatatobe
programmed.TheWSMwillexecuteasequenceofinternallytimedeventstoprogrampreferred
bitsoftheaddressedlocation,thenverifythebitsaresufficientlyprogrammed.Programmingthe
memoryresultsinspecificbitswithinanaddresslocationbeingchangedtoa“0.”Ifusersattempt
toprogram“1”s,thememorycellcontentsdonotchangeandnoerroroccurs.
Thestatusregisterindicatesprogrammingstatus:whiletheprogramsequenceexecutes,statusbit7
is“0.”ThestatusregistercanbepolledbytogglingeitherCE#orOE#.Whileprogramming,the
onlyvalidcommandsareReadStatusRegister,ProgramSuspend,andProgramResume.
Whenprogrammingiscomplete,theprogram-statusbitsshouldbechecked.Iftheprogramming
operationwasunsuccessful,bitSR.4ofthestatusregisterissettoindicateaprogramfailure.If
SR.3isset,thenVPPwasnotwithinacceptablelimits,andtheWSMdidnotexecutetheprogram
command.IfSR.1isset,aprogramoperationwasattemptedonalockedblockandtheoperation
wasaborted.
Thestatusregistershouldbeclearedbeforeattemptingthenextoperation.AnyCUIinstructioncan
followafterprogrammingiscompleted;however,topreventinadvertentstatus-registerreads,be
suretoresettheCUItoread-arraymode.
3.2.4.1 SuspendingandResumingProgram
TheProgramSuspendhaltsthein-progressprogramoperationtoreaddatafromanotherlocationof
memory.Oncetheprogrammingprocessstarts,writingtheProgramSuspendcommandtotheCUI
requeststhattheWSMsuspendtheprogramsequence(atpredeterminedpointsintheprogram
algorithm).Thedevicecontinuestooutputstatus-registerdataaftertheProgramSuspend
commandiswritten.Pollingstatus-registerbitsSR.7andSR.2willdeterminewhentheprogram
operationhasbeensuspended(bothwillbesetto“1”).tWHRH1/tEHRH1specifytheprogram-
suspendlatency.
AReadArraycommandcannowbewrittentotheCUItoreaddatafromblocksotherthanthat
whichissuspended.TheonlyothervalidcommandswhileprogramissuspendedareReadStatus
Register,ReadIdentifier,andProgramResume.AftertheProgramResumecommandiswrittento
theflashmemory,theWSMwillcontinuewiththeprogramprocessandstatus-registerbitsSR.2
andSR.7willautomaticallybecleared.AftertheProgramResumecommandiswritten,thedevice
automaticallyoutputsstatus-registerdatawhenread(seeAppendixEforProgramSuspendand
ResumeFlowchart).VPPmustremainatthesameVPPlevelusedforprogramwhileinprogram-
suspendmode.RP#mustalsoremainatVIH.
3.2.5 EraseMode
Toeraseablock,writetheEraseSet-upandEraseConfirmcommandstotheCUI,alongwithan
addressidentifyingtheblocktobeerased.ThisaddressislatchedinternallywhentheErase
Confirmcommandisissued.Blockerasureresultsinallbitswithintheblockbeingsetto“1.”Only
oneblockcanbeerasedatatime.TheWSMwillexecuteasequenceofinternallytimedeventsto
programallbitswithintheblockto“0,”eraseallbitswithintheblockto“1,”thenverifythatall
bitswithintheblockaresufficientlyerased.Whiletheeraseexecutes,statusbit7isa“0.”
Whenthestatusregisterindicatesthaterasureiscomplete,checktheerase-statusbittoverifythat
theEraseoperationwassuccessful.IftheEraseoperationwasunsuccessful,SR.5ofthestatus
registerwillbesettoa“1,”indicatinganerasefailure.IfVPPwasnotwithinacceptablelimitsafter
28F008/800B3,28F016/160B3,28F320B3,28F640B3
20 Datasheet
theEraseConfirmcommandwasissued,theWSMwillnotexecutetheerasesequence;instead,
SR.5ofthestatusregisterissettoindicateanEraseerror,andSR.3issettoa“1”toidentifythat
VPPsupplyvoltagewasnotwithinacceptablelimits.
AfteranEraseoperation,clearthestatusregister(50H)beforeattemptingthenextoperation.Any
CUIinstructioncanfollowaftererasureiscompleted;however,topreventinadvertentstatus-
registerreads,itisadvisabletoplacetheflashinread-arraymodeaftertheeraseiscomplete.
3.2.5.1 SuspendingandResumingErase
SinceanEraseoperationrequiresontheorderofsecondstocomplete,anEraseSuspendcommand
isprovidedtoallowerase-sequenceinterruptioninordertoreaddatafrom—orprogramdatato—
anotherblockinmemory.Oncetheerasesequenceisstarted,writingtheEraseSuspendcommand
totheCUIrequeststhattheWSMpausetheerasesequenceatapredeterminedpointintheerase
algorithm.Thestatusregisterwillindicateif/whentheEraseoperationhasbeensuspended.
AReadArray/ProgramcommandcannowbewrittentotheCUIinordertoreaddatafrom/
programdatatoblocksotherthantheonecurrentlysuspended.TheProgramcommandcan
subsequentlybesuspendedtoreadyetanotherarraylocation.Theonlyvalidcommandswhile
EraseissuspendedareEraseResume,Program,ReadArray,ReadStatusRegister,orRead
Identifier.Duringerase-suspendmode,thechipcanbeplacedinapseudo-standbymodebytaking
CE#toVIH,whichreducesactivecurrentconsumption.
EraseResumecontinuestheerasesequencewhenCE#=VIL.AswiththeendofastandardErase
operation,thestatusregistermustbereadandclearedbeforethenextinstructionisissued.
NOTES:
PA:ProgramAddress PD:ProgramData BA:BlockAddress
IA:IdentifierAddress ID:IdentifierData SRD:StatusRegisterData
1. BusoperationsaredefinedinTable3.
2. FollowingtheIntelligentIdentifiercommand,twoReadoperationsaccessmanufactureranddevicecodes.
A
0=0formanufacturercode,A0=1fordevicecode.A1–A21
=0.
3. Either40Hor10Hcommandisvalidalthoughthestandardis40H.
4. Whenwritingcommandstothedevice,theupperdatabus[DQ
8–DQ15]shouldbeeitherVILorVIH,to
minimizecurrentdraw.
Table6. CommandBusDefinitions
(1,4)
FirstBusCycle SecondBusCycle
Command Notes Oper Addr Data Oper Addr Data
ReadArray Write X FFH
ReadIdentifier 2 Write X 90H Read IA ID
ReadStatusRegister Write X 70H Read X SRD
ClearStatusRegister Write X 50H
Program 3 Write X 40H/
10H Write PA PD
BlockErase/Confirm Write X 20H Write BA D0H
Program/EraseSuspend Write X B0H
Program/EraseResume Write X D0H
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 21
3.3 BlockLocking
TheB3devicearchitecturefeaturestwohardware-lockableparameterblocks.
3.3.1 WP#=VILforBlockLocking
ThelockableblocksarelockedwhenWP#=VIL;anyprogramorEraseoperationtoalocked
blockwillresultinanerror,whichwillbereflectedinthestatusregister.Fortopconfiguration,the
toptwoparameterblocks(blocks#133and#134forthe64Mbit,#69and#70forthe32Mbit,
blocks#37and#38forthe16Mbit,blocks#21and#22forthe8Mbit,blocks#13and#14forthe
4Mbit)arelockable.Forthebottomconfiguration,thebottomtwoparameterblocks(blocks#0
and#1for4/8/16/32/64Mbit)arelockable.Unlockedblockscanbeprogrammedorerased
normally(unlessVPPisbelowVPPLK).
Table7. StatusRegisterBitDefinition
WSMS ESS ES PS VPPS PSS BLS R
76543210
NOTES:
SR.7=WRITESTATEMACHINESTATUS(WSMS)
1=Ready
0=Busy
CheckWriteStateMachinebitfirsttodeterminewordprogram
orblock-erasecompletion,beforecheckingprogramorerase-
statusbits.
SR.6=ERASE-SUSPENDSTATUS(ESS)
1=EraseSuspended
0=EraseInProgress/Completed
Whenerasesuspendisissued,WSMhaltsexecutionandsets
bothWSMSandESSbitsto“1.”ESSbitremainssetat“1”until
anEraseResumecommandisissued.
SR.5=ERASESTATUS(ES)
1=ErrorInBlockErasure
0=SuccessfulBlockErase
Whenthisbitissetto“1,”WSMhasappliedthemax.number
oferasepulsestotheblockandisstillunabletoverify
successfulblockerasure.
SR.4=PROGRAMSTATUS(PS)
1=ErrorinWordProgram
0=SuccessfulWordProgram
Whenthisbitissetto“1,”WSMhasattemptedbutfailedto
programaword.
SR.3=VPPSTATUS(VPPS)
1=VPPLowDetect,OperationAbort
0=VPPOK
TheVPP
statusbitdoesnotprovidecontinuousindicationof
VPP
level.TheWSMinterrogatesVPPlevelonlyafterthe
ProgramorErasecommandsequenceshavebeenentered,
andinformsthesystemifVPPhasnotbeenswitchedon.The
VPPisalsocheckedbeforetheoperationisverifiedbythe
WSM.TheVPP
statusbitisnotguaranteedtoreportaccurate
feedbackbetweenVPPLKmaxandVPP1
minorbetweenVPP1
maxandVPP4
min.
SR.2=PROGRAMSUSPENDSTATUS(PSS)
1=ProgramSuspended
0=PrograminProgress/Completed
Whenprogramsuspendisissued,WSMhaltsexecutionand
setsbothWSMSandPSSbitsto“1.”PSSbitremainssetto“1”
untilaProgramResumecommandisissued.
SR.1=BLOCKLOCKSTATUS
1=Program/Eraseattemptedonlockedblock;
Operationaborted
0=Nooperationtolockedblocks
IfaProgramorEraseoperationisattemptedtooneofthe
lockedblocks,thisbitissetbytheWSM.Theoperation
specifiedisabortedandthedeviceisreturnedtoreadstatus
mode.
SR.0=RESERVEDFORFUTUREENHANCEMENTS(R) Thisbitisreservedforfutureuseandshouldbemaskedout
whenpollingthestatusregister.
NOTE: ACommandSequenceErrorisindicatedwhenSR.4,SR.5,andSR.7areset.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
22 Datasheet
3.3.2 WP#=VIHforBlockUnlocking
WP#=VIHunlocksalllockableblocks.
Theseblockscannowbeprogrammedorerased.
NotethatRP#doesnotoverrideWP#lockingasinpreviousBootBlockdevices.WP#controlsall
blocklockingandVPPprovidesprotectionagainstspuriouswrites.Table8definesthewrite-
protectionmethods.
3.4 VPPProgramandEraseVoltages
TheB3productsprovidein-systemprogramminganderaseat2.7 V.Forcustomersrequiringfast
programmingintheirmanufacturingenvironment,B3deviceincludesanadditionallow-cost12-V
programmingfeature.
The12-V VPPmodeenhancesprogrammingperformanceduringtheshortperiodoftimetypically
foundinmanufacturingprocesses;however,itisnotintendedforextendeduse.12 Vmaybe
appliedtoVPPduringprogramandEraseoperationsforamaximumof1000cyclesonthemain
blocks,and2500cyclesontheparameterblocks.VPPmaybeconnectedto12 Vforatotalof80
hoursmaximum.
Warning: Stressingthedevicebeyondtheselimitsmaycausepermanentdamage.
DuringReadoperationsoridletimes,VPPmaybetiedtoa5-Vsupply.ForProgramandErase
operations,a5-Vsupplyisnotpermitted.TheVPPmustbesuppliedwitheither2.7 V–3.6 Vor
11.4 V–12.6 VduringProgramandEraseoperations.
3.4.1 VPP=VILforCompleteProtection
TheVPPprogrammingvoltagecanbeheldlowforcompletewriteprotectionofallblocksinthe
flashdevice.WhenVPPisbelowVPPLK,anyProgramorEraseoperationwillresultinaerror,
promptingthecorrespondingstatus-registerbit(SR.3)tobeset.
3.5 PowerConsumption
Intelflashdeviceshaveatieredapproachtopowersavingsthatcansignificantlyreduceoverall
systempowerconsumption.TheAutomaticPowerSavings(APS)featurereducespower
consumptionwhenthedeviceisselectedbutidle.IftheCE#isdeasserted,theflashentersits
standbymode,wherecurrentconsumptionisevenlower.Thecombinationofthesefeaturescan
minimizememorypowerconsumption,andtherefore,overallsystempowerconsumption.
Table8. Write-ProtectionTruthTablefortheB3DeviceFamily
VPP WP# RP# WriteProtectionProvided
XXV
IL AllBlocksLocked
VIL XV
IH AllBlocksLocked
≥VPPLK VIL VIH LockableBlocksLocked
≥VPPLK VIH VIH AllBlocksUnlocked
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 23
3.5.1 ActivePower
WithCE#atalogic-lowlevelandRP#atalogic-highlevel,thedeviceisintheactivemode.Refer
totheDCCharacteristictablesforICCcurrentvalues.Activepoweristhelargestcontributorto
overallsystempowerconsumption.Minimizingtheactivecurrentcouldhaveaprofoundeffecton
systempowerconsumption,especiallyforbattery-operateddevices.
3.5.2 AutomaticPowerSavings(APS)
AutomaticPowerSavingsprovideslow-poweroperationduringreadmode.Afterdataisreadfrom
thememoryarrayandtheaddresslinesarequiescent,APScircuitryplacesthedeviceinamode
wheretypicalcurrentiscomparabletoICCS.Theflashstaysinthisstaticstatewithoutputsvalid
untilanewlocationisread.
3.5.3 StandbyPower
WithCE#atalogic-highlevel(VIH)andthedeviceinreadmode,theflashmemoryisinstandby
mode,whichdisablesmuchofthedevicecircuitry,andsubstantiallyreducespowerconsumption.
Outputsareplacedinahigh-impedancestateindependentofthestatusoftheOE#signal.IfCE#
transitionstoalogic-highlevelduringEraseorProgramoperations,thedevicewillcontinueto
performtheoperationandconsumecorrespondingactivepoweruntiltheoperationiscompleted.
Systemengineersshouldanalyzethebreakdownofstandbytimeversusactivetime,andquantify
therespectivepowerconsumptionineachmodefortheirspecificapplication.Thisapproachwill
provideamoreaccuratemeasureofapplication-specificpowerandenergyrequirements.
3.5.4 DeepPower-DownMode
Thedeeppower-downmodeisactivatedwhenRP#=V
IL(GND ±0.2 V).Duringreadmodes,
RP#goinglowde-selectsthememoryandplacestheoutputsinahigh-impedancestate.Recovery
fromdeeppower-downrequiresaminimumtimeoftPHQV(See“ACReadCharacteristics”on
page 30.)
Duringprogramorerasemodes,RP#transitioninglowwillabortthein-progressoperation.The
memorycontentsoftheaddressbeingprogrammedortheblockbeingerasedarenolongervalidas
thedataintegrityhasbeencompromisedbytheabort.Duringdeeppower-down,allinternal
circuitsareswitchedtoalow-powersavingsmode(RP#transitioningtoVILorturningoffpower
tothedeviceclearsthestatusregister).
3.6 PowerandResetConsiderations
3.6.1 Power-Up/DownCharacteristics
Topreventanyconditionthatmayresultinaspuriouswriteoreraseoperation,itisrecommended
topower-upVCCandVCCQtogether.Conversely,VCCandVCCQmustpower-downtogether.Itis
alsorecommendedtopower-upVPPwithorslightlyafterVCC.Conversely,VPPmustpowerdown
withorslightlybeforeVCC.
IfVCCQand/orVPParenotconnectedtotheVCC
supply,thenVCCshouldattainVCCMinbefore
applyingVCCQandVPP.Deviceinputsshouldnotbedrivenbeforesupplyvoltage=VCCMin.
PowersupplytransitionsshouldonlyoccurwhenRP#islow.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
24 Datasheet
3.6.2 RP#ConnectedtoSystemReset
TheuseofRP#duringsystemresetisimportantwithautomatedprogram/erasedevicesbecausethe
systemexpectstoreadfromtheflashmemorywhenitexitsreset.IfaCPUresetoccurswithouta
flashmemoryreset,properCPUinitializationwillnotoccurbecausetheflashmemorymaybe
providingstatusinformationinsteadofarraydata.IntelrecommendsconnectingRP#tothesystem
CPURESET#signaltoallowproperCPU/flashinitializationfollowingsystemreset.
SystemdesignersmustguardagainstspuriouswriteswhenVCCvoltagesareaboveVLKO.Because
bothWE#andCE#mustbelowforacommandwrite,drivingeithersignaltoVIHwillinhibit
writestothedevice.TheCUIarchitectureprovidesadditionalprotectionsincealterationof
memorycontentscanoccuronlyaftersuccessfulcompletionofthetwo-stepcommandsequences.
ThedeviceisalsodisableduntilRP#isbroughttoVIH,regardlessofthestateofitscontrolinputs.
Byholdingthedeviceinreset(RP#connectedtosystemPOWERGOOD)duringpower-up/down,
invalidbusconditionsduringpower-upcanbemasked,providingyetanotherlevelofmemory
protection.
3.6.3 VCC,VPPandRP#Transitions
TheCUIlatchescommandsasissuedbysystemsoftwareandisnotalteredbyVPPorCE#
transitionsorWSMactions.Itsdefaultstateuponpower-up,afterexitfromresetmodeorafter
VCCtransitionsaboveVLKO(Lockoutvoltage),isread-arraymode.
AfteranyprogramorBlock-Eraseoperationiscomplete(evenafterVPPtransitionsdownto
VPPLK),theCUImustberesettoread-arraymodeviatheReadArraycommandifaccesstothe
flash-memoryarrayisrequired.
3.7 PowerSupplyDecoupling
Flashmemorypower-switchingcharacteristicsrequirecarefuldevicedecoupling.System
designersshouldconsiderthefollowingthreesupplycurrentissues:
1. Standbycurrentlevels(ICCS)
2. Readcurrentlevels(ICCR)
3. TransientpeaksproducedbyfallingandrisingedgesofCE#.
Transientcurrentmagnitudesdependonthedeviceoutputs’capacitiveandinductiveloading.Two-
linecontrolandproperdecouplingcapacitorselectionwillsuppressthesetransientvoltagepeaks.
Eachflashdeviceshouldhavea0.1µFceramiccapacitorconnectedbetweeneachVCCandGND,
andbetweenitsVPPandGND.Thesehigh-frequency,inherentlylow-inductancecapacitorsshould
beplacedascloseaspossibletothepackageleads.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 25
4.0 ThermalandDCCharacteristics
4.1 AbsoluteMaximumRatings
Warning: Stressingthedevicebeyondthe“AbsoluteMaximumRatings”maycausepermanentdamage.
Thesearestressratingsonly.Operationbeyondthe“OperatingConditions”isnotrecommended,
andextendedexposurebeyondthe“OperatingConditions”mayaffectdevicereliability.
.
NOTICE:Specificationsaresubjecttochangewithoutnotice.VerifywithyourlocalIntelSalesofficethatyouhave
thelatestdatasheetbeforefinalizingadesign.
Parameter MaximumRating Notes
ExtendedOperatingTemperature
DuringRead –40°Cto+85°C
DuringBlockEraseandProgram –40°Cto+85°C
TemperatureunderBias –40°Cto+85°C
StorageTemperature –65°Cto+125°C
VoltageOnAnyPin(exceptVCCandVPP)withRespecttoGND –0.5 Vto+3.7 V 1
VPPVoltage(forBlockEraseandProgram)withRespecttoGND –0.5 Vto+13.5 V 1,2,3
VCCandVCCQ
SupplyVoltagewithRespecttoGND –0.2Vto+3.6V
OutputShortCircuitCurrent 100mA 4
NOTES:
1. MinimumDCvoltageis–0.5 Voninput/outputpins.Duringtransitions,thislevelmay
undershootto–2.0 Vforperiods<20ns.MaximumDCvoltageoninput/outputpinsisVCC
+0.5 Vwhich,duringtransitions,mayovershoottoVCC+2.0 Vforperiods<20ns.
2. MaximumDCvoltageonVPPmayovershootto+14.0 Vforperiods<20ns.
3. VPPProgramvoltageisnormally1.65 V–3.6 V.Connectiontoa11.4 V–12.6 Vsupplycanbe
doneforamaximumof1000cyclesonthemainblocksand2500cyclesontheparameter
blocksduringprogram/erase.VPPmaybeconnectedto12 Vforatotalof80hoursmaximum.
4. Outputshortedfornomorethanonesecond.Nomorethanoneoutputshortedatatime.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
26 Datasheet
4.2 OperatingConditions
4.3 DCCurrentCharacteristics
Table9. TemperatureandVoltageOperatingConditions
Symbol Parameter Notes Min Max Units
TAOperatingTemperature –40 +85 °C
VCC1 VCCSupplyVoltage 1,2 2.7 3.6 Volts
VCC2 1,23.03.6
VCCQ1
I/OSupplyVoltage
12.73.6
VoltsVCCQ2 1.65 2.5
VCCQ3 1.8 2.5
VPP1 SupplyVoltage 1 1.65 3.6 Volts
VPP2 1,3 11.4 12.6 Volts
Cycling BlockEraseCycling 3 100,000 Cycles
NOTES:
1. VCCandVCCQmustsharethesamesupplywhentheyareintheVCC1range.
2. VCCMax=3.3Vfor0.25µm32-Mbitdevices.
3. ApplyingVPP = 11.4 V–12.6 Vduringaprogram/erasecanonlybedoneforamaximumof1000cycleson
themainblocksand2500cyclesontheparameterblocks.VPPmaybeconnectedto12 Vforatotalof
80hoursmaximum.
Table10.DCCurrentCharacteristics(Sheet1of3)
Sym Parameter
VCC 2.7V–3.6V2.7V–2.85V2.7V–3.3V
Unit Test
Conditions
VCCQ 2.7V–3.6V 1.65V–2.5V1.8V–2.5V
Note Typ Max Typ Max Typ Max
ILI InputLoadCurrent 1,2 ±1 ±1 ±1µA
VCC=
VCCMax
VCCQ=
VCCQMax
VIN=VCCQ
orGND
ILO OutputLeakage
Current 1,2 ±10 ±10 ±10 µA
VCC=
VCCMax
VCCQ=
VCCQMax
VIN=VCCQ
orGND
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 27
ICCS
VCC
StandbyCurrent
for0.13and0.18
MicronProduct 1 7 15 20 50 150 250 µA VCC=
VCCMax
CE#=RP#
=VCCQ
orduring
Program/
Erase
Suspend
WP#=
VCCQor
GND
VCC
StandbyCurrent
for0.25Micron
Product 1 10 25 20 50 150 250 µA
ICCD
VCCPower-Down
Currentfor0.13and
0.18MicronProduct 1,2 7 15 7 20 7 20 µA VCC=
VCCMax
VCCQ=
VCCQMax
VIN=VCCQ
orGND
RP#=GND
±0.2V
VCCPower-Down
Currentfor0.25
Product 1,2 7 25 7 25 7 25 µA
ICCR
VCCReadCurrentfor
0.13and0.18Micron
Product 1,2,3 9 18 8 15 9 15 mA VCC=
VCCMax
VCCQ=
VCCQMax
OE#=VIH,
CE#=VIL
f=5MHz,
IOUT=0mA
Inputs=VIL
orVIH
VCCReadCurrentfor
0.25MicronProduct 1,2,3 10 18 8 15 9 15 mA
IPPD VPPDeepPower-
DownCurrent 1 0.2 5 0.2 5 0.2 5 µA RP#=GND
±0.2V
VPP
≤VCC
ICCW VCCProgramCurrent 1,4
18 55 18 55 18 55 mA VPP=VPP1,
Programin
Progress
82210301030mA
VPP
=VPP2
(12v)
Programin
Progress
ICCE VCCEraseCurrent 1,4
16 45 21 45 21 45 mA VPP=VPP1,
Erasein
Progress
81516451645mA
VPP=VPP2
(12v),
Erasein
Progress
ICCES/
ICCWS
VCCEraseSuspend
Currentfor0.13and
0.18MicronProduct 1,4,5
7 15 50 200 50 200 µA CE#=VIH,
Erase
Suspendin
Progress
VCCEraseSuspend
Currentfor0.25
MicronProduct 10 25 50 200 50 200 µA
Table10.DCCurrentCharacteristics(Sheet2of3)
Sym Parameter
VCC 2.7V–3.6V2.7V–2.85V2.7V–3.3V
Unit Test
Conditions
VCCQ 2.7V–3.6V1.65V–2.5V1.8V–2.5V
Note Typ Max Typ Max Typ Max
28F008/800B3,28F016/160B3,28F320B3,28F640B3
28 Datasheet
IPPR VPPReadCurrent 1,4 2±15 2 ±15 2 ±15 µA VPP
≤VCC
50 200 50 200 50 200 µA VPP
>VCC
IPPW VPPProgramCurrent 1,4
0.05 0.1 0.05 0.1 0.05 0.1 mA VPP=VPP1,
Programin
Progress
8228 22 8 22mA
VPP
=VPP2
(12v)
Programin
Progress
IPPE VPP
EraseCurrent 1,4
0.05 0.1 0.05 0.1 0.05 0.1 mA VPP=VPP1,
Erasein
Progress
82216451645mA
VPP=VPP2
(12v),
Erasein
Progress
IPPES/
IPPWS VCCEraseSuspend
Current 1,4
0.2 5 0.2 5 0.2 5 µA
VPP=VPP1,
Programor
Erase
Suspendin
Progress
50 200 50 200 50 200 µA
VPP=VPP2
(12v),
Programor
Erase
Suspendin
Progress
NOTES:
1. AllcurrentsareinRMSunlessotherwisenoted.TypicalvaluesatnominalVCC,TA=+25°C.
2. ThetestconditionsVCCMax,VCCQMax,VCCMin,andVCCQMinrefertothemaximumorminimumVCCor
VCCQvoltagelistedatthetopofeachcolumn.VCCMax=3.3Vfor0.25µm32-Mbitdevices.
3. AutomaticPowerSavings(APS)reducesICCRtoapproximatelystandbylevelsinstaticoperation(CMOS
inputs).
4. Sampled,not100%tested.
5. ICCESorICCWSisspecifiedwithdevicede-selected.Ifdeviceisreadwhileinerasesuspend,currentdraw
issumofICCESandICCR.Ifthedeviceisreadwhileinprogramsuspend,currentdrawisthesumofICCWS
andICCR.
Table10.DCCurrentCharacteristics(Sheet3of3)
Sym Parameter
VCC 2.7V–3.6V2.7V–2.85V2.7V–3.3V
Unit Test
Conditions
VCCQ 2.7V–3.6V 1.65V–2.5V1.8V–2.5V
Note Typ Max Typ Max Typ Max
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 29
4.4 DCVoltageCharacteristics
Table11.DCVoltageCharacteristics
Sym Parameter
VCC 2.7V–3.6V2.7V–2.85V2.7V–3.3V
Unit TestConditionsVCCQ 2.7V–3.6V1.65V–2.5V1.8V–2.5V
Note Min Max Min Max Min Max
VIL InputLow
Voltage –0.4 VCC*
0.22 V –0.4 0.4 –0.4 0.4 V
VIH InputHigh
Voltage 2.0 VCCQ
+0.3V VCCQ–
0.4V VCCQ
+0.3V VCCQ–
0.4V VCCQ
+0.3V V
VOL OutputLow
Voltage –0.1 0.1 -0.1 0.1 -0.1 0.1 V VCC=VCCMin
VCCQ=VCCQMin
IOL=100µA
VOH OutputHigh
Voltage VCCQ
–0.1V VCCQ–
0.1V VCCQ–
0.1V V
VCC=VCCMin
VCCQ=VCCQMin
IOH=–100µA
VPPLK VPPLock-
OutVoltage 1 1.0 1.0 1.0 V CompleteWrite
Protection
VPP1 VPPduring
Program/
Erase
Operations
1 1.65 3.6 1.65 3.6 1.65 3.6 V
VPP2 1,2 11.4 12.6 11.4 12.6 11.4 12.6 V
VLKO
VCC
Prog/
Erase
Lock
Voltage
1.5 1.5 1.5 V
VLKO2
VCCQ
Prog/
Erase
Lock
Voltage
1.2 1.2 1.2 V
NOTES:
1. EraseandProgramareinhibitedwhenVPP<VPPLKandnotguaranteedoutsidethevalidVPPrangesofVPP1andVPP2.
2. ApplyingVPP = 11.4 V–12.6 Vduringprogram/erasecanonlybedoneforamaximumof1000cyclesonthemainblocksand
2500cyclesontheparameterblocks.VPPmaybeconnectedto12 Vforatotalof80hoursmaximum.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
30 Datasheet
5.0 ACCharacteristics
5.1 ACReadCharacteristics
Table12.ReadOperations—8MbitDensity
#SymParameter
Density 8Mbit
Unit
Product 90ns 110ns
VCC 3.0V–3.6V2.7V–3.6V3.0V–3.6V2.7V–3.6V
Note Min Max Min Max Min Max Min Max
R1 tAVAV ReadCycleTime 3,4 80 90 100 110 ns
R2 tAVQV AddresstoOutputDelay 3,4 80 90 100 110 ns
R3 tELQV CE#toOutputDelay 1,3,4 80 90 100 110 ns
R4 tGLQV OE#toOutputDelay 1,3,4 30 30 30 30 ns
R5 tPHQV RP#toOutputDelay 3,4 150 150 150 150 ns
R6 tELQX CE#toOutputinLowZ 2,3,4 0 0 0 0 ns
R7 tGLQX OE#toOutputinLowZ 2,3,4 0 0 0 0 ns
R8 tEHQZ CE#toOutputinHighZ 2,3,4 20 20 20 20 ns
R9 tGHQZ OE#toOutputinHighZ 2,3,4 20 20 20 20 ns
R10 tOH
OutputHoldfrom
Address,CE#,orOE#
Change,Whichever
OccursFirst
2,3,4 0 0 0 0 ns
NOTES:
1. OE#maybedelayeduptotELQV–tGLQVafterthefallingedgeofCE#withoutimpactontELQV.
2. Sampled,butnot100%tested.
3. SeeFigure6,“ReadOperationWaveform”onpage 33.
4. SeeFigure9,“ACInput/OutputReferenceWaveform”onpage 40fortimingmeasurementsandmaximumallowableinput
slewrate.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 31
Table13.ReadOperations—16MbitDensity
#Sym
Para-
mete
r
Density 16Mbit
Unit Notes
Product 70ns 80ns 90ns 110ns
VCC 2.7V–3.6V2.7V–3.6V3.0V–3.6V2.7V–3.6V3.0V–3.6V 2.7V–3.6V
Min Max Min Max Min Max Min Max Min Max Min Max
R1 tAVAV ReadCycleTime 70 80 80 90 100 110 ns 3,4
R2 tAVQ
VAddressto
OutputDelay 70 80 80 90 100 110 ns 3,4
R3 tELQ
VCE#toOutput
Delay 70 80 80 90 100 110 ns 1,3,4
R4 tGLQ
VOE#toOutput
Delay 20 20 30 30 30 30 ns 1,3,4
R5 tPHQ
VRP#toOutput
Delay 150 150 150 150 150 150 ns 3,4
R6 tELQ
XCE#toOutputin
LowZ000000
ns 2,3,4
R7 tGLQ
XOE#toOutputin
LowZ000000
ns 2,3,4
R8 tEHQ
ZCE#toOutputin
HighZ20 20 20 20 20 20 ns 2,3,4
R9 tGHQ
ZOE#toOutputin
HighZ20 20 20 20 20 20 ns 2,3,4
R10 tOH
OutputHoldfrom
Address,CE#,or
OE#Change,
Whichever
OccursFirst
000000
ns 2,3,4
NOTES:
1. OE#maybedelayeduptotELQV–tGLQVafterthefallingedgeofCE#withoutimpactontELQV.
2. Sampled,butnot100%tested.
3. SeeFigure6,“ReadOperationWaveform”onpage 33.
4. SeeFigure9,“ACInput/OutputReferenceWaveform”onpage 40fortimingmeasurementsandmaximumallowableinput
slewrate.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
32 Datasheet
Table14.ReadOperations—32MbitDensity
#Sym
Para-
meter
Density 32Mbit
Unit Notes
Product 70ns 90ns 100ns 110ns
VCC 2.7V–3.6V2.7V–3.6V3.0V–3.3V2.7V–3.3V3.0V–3.3V2.7V–3.3V
Min Max Min Max Min Max Min Max Min Max Min Max
R1 tAVAV ReadCycleTime 70 90 90 100 100 110 ns 3,4
R2 tAVQ
VAddresstoOutput
Delay 70 90 90 100 100 110 ns 3,4
R3 tELQ
VCE#toOutput
Delay 70 90 90 100 100 110 ns 1,3,4
R4 tGLQ
VOE#toOutput
Delay 20 20 30 30 30 30 ns 1,3,4
R5 tPHQ
VRP#toOutput
Delay 150 150 150 150 150 150 ns 3,4
R6 tELQ
XCE#toOutputin
LowZ000000
ns 2,3,4
R7 tGLQ
XOE#toOutputin
LowZ000000
ns 2,3,4
R8 tEHQ
ZCE#toOutputin
HighZ20 20 20 20 20 20 ns 2,3,4
R9 tGHQ
ZOE#toOutputin
HighZ20 20 20 20 20 20 ns 2,3,4
R10 tOH
OutputHoldfrom
Address,CE#,or
OE#Change,
Whichever
OccursFirst
000000
ns 2,3,4
NOTES:
1. OE#maybedelayeduptotELQV–tGLQVafterthefallingedgeofCE#withoutimpactontELQV.
2. Sampled,butnot100%tested.
3. SeeFigure6,“ReadOperationWaveform”onpage 33.
4. SeeFigure9,“ACInput/OutputReferenceWaveform”onpage 40fortimingmeasurementsandmaximumallowable
inputslewrate.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 33
Table15.ReadOperations
—64MbitDensity
#Sym Parameter
Density 64Mbit
Unit
Product 70ns 80ns
VCC 2.7V–3.6V2.7V–3.6V
Note Min Max Min Max
R1 tAVAV ReadCycleTime 3,4 70 80 ns
R2 tAVQV AddresstoOutputDelay 3,4 70 80 ns
R3 tELQV CE#toOutputDelay 1,3,4 70 80 ns
R4 tGLQV OE#toOutputDelay 1,3,4 20 20 ns
R5 tPHQV RP#toOutputDelay 3,4 150 150 ns
R6 tELQX CE#toOutputinLowZ 2,3,4 0 0 ns
R7 tGLQX OE#toOutputinLowZ 2,3,4 0 0 ns
R8 tEHQZ CE#toOutputinHighZ 2,3,4 20 20 ns
R9 tGHQZ OE#toOutputinHighZ 2,3,4 20 20 ns
R10 tOH OutputHoldfromAddress,CE#,orOE#
Change,WhicheverOccursFirst 2,3,4 0 0 ns
NOTES:
1. OE#maybedelayeduptotELQV–tGLQVafterthefallingedgeofCE#withoutimpactontELQV.
2. Sampled,butnot100%tested.
3. SeeFigure6,“ReadOperationWaveform”onpage 33.
4. SeeFigure9,“ACInput/OutputReferenceWaveform”onpage 40fortimingmeasurementsandmaximum
allowableinputslewrate.
Figure6.ReadOperationWaveform
R5
R10
R7
R6
R9R4
R8R3
R1
R2 R1
A
ddress[A]
CE#[E]
OE#[G]
WE#[W]
Data[D/Q]
RST#[P]
28F008/800B3,28F016/160B3,28F320B3,28F640B3
34 Datasheet
5.2 ACWriteCharacteristics
Table16.WriteOperations—8MbitDensity
#Sym Parameter
Density 8Mbit
Unit
Product 90ns 110ns
VCC
3.0V–3.6V80 100
2.7V–3.6V90110
Note Min Min Min Min
W1 tPHWL/
tPHEL RP#HighRecoverytoWE#(CE#)GoingLow 4,5 150 150 150 150 ns
W2 tELWL/
tWLEL CE#(WE#)SetuptoWE#(CE#)GoingLow 4,5 0 0 0 0 ns
W3 tWLWH/
tELEH WE#(CE#)PulseWidth 4,5 50 60 70 70 ns
W4 tDVWH/
tDVEH DataSetuptoWE#(CE#)GoingHigh 2,4,5 50 50 60 60 ns
W5 tAVWH/
tAVEH AddressSetuptoWE#(CE#)GoingHigh 2,4,5 50 60 70 70 ns
W6 tWHEH/
tEHWH CE#(WE#)HoldTimefromWE#(CE#)High 4,5 0 0 0 0 ns
W7 tWHDX/
tEHDX DataHoldTimefromWE#(CE#)High 2,4,5 0 0 0 0 ns
W8 tWHAX/
tEHAX AddressHoldTimefromWE#(CE#)High 2,4,5 0 0 0 0 ns
W9 tWHWL/
tEHEL WE#(CE#)PulseWidthHigh 2,4,5 30 30 30 30 ns
W10 tVPWH/
tVPEH VPPSetuptoWE#(CE#)GoingHigh 3,4,5 200 200 200 200 ns
W11 tQVVL VPP
HoldfromValidSRD 3,4 0 0 0 0 ns
W12 tBHWH/
tBHEH WP#SetuptoWE#(CE#)GoingHigh 3,4 0 0 0 0 ns
W13 tQVBL WP#
HoldfromValidSRD 3,4 0 0 0 0 ns
W14 tWHGL WE#HightoOE#GoingLow 3,4 30 30 30 30 ns
NOTES:
1. Writepulsewidth(tWP)isdefinedfromCE#orWE#goinglow(whichevergoeslowlast)
toCE#orWE#goinghigh(whichever
goeshighfirst).Hence,tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.Similarly,writepulsewidthhigh(tWPH)isdefinedfromCE#or
WE#goinghigh(whichevergoeshighfirst)
toCE#orWE#goinglow(whichevergoeslowlast).Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2. RefertoTable 3,“BusOperations(1)”onpage 14forvalidAINorDIN.
3. Sampled,butnot100%tested.
4. SeeFigure9,“ACInput/OutputReferenceWaveform”onpage 40fortimingmeasurementsandmaximumallowableinput
slewrate.
5. SeeFigure7,“WriteOperationsWaveform”onpage 38.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 35
Table17.WriteOperations—16MbitDensity
#SymParameter
Density 16Mbit
Unit
Product 70ns 80ns 90ns 110ns
VCC
3.0V–3.6V80100
2.7V–3.6V7080 90 110
Note Min Min Min Min Min Min
W1 tPHWL/
tPHEL RP#HighRecoverytoWE#(CE#)Going
Low 4,5 150 150 150 150 150 150 ns
W2 tELWL/
tWLEL CE#(WE#)SetuptoWE#(CE#)GoingLow 4,5 0 0 0 0 0 0 ns
W3 tWLWH/
tELEH WE#(CE#)PulseWidth 1,4,5 45 50 50 60 70 70 ns
W4 tDVWH/
tDVEH DataSetuptoWE#(CE#)GoingHigh 2,4,5 40 40 50 50 60 60 ns
W5 tAVWH/
tAVEH AddressSetuptoWE#(CE#)GoingHigh 2,4,5 50 50 50 60 70 70 ns
W6 tWHEH/
tEHWH CE#(WE#)HoldTimefromWE#(CE#)
High 4,5 0 0 0 0 0 0 ns
W7 tWHDX/
tEHDX DataHoldTimefromWE#(CE#)High 2,4,5 0 0 0 0 0 0 ns
W8 tWHAX/
tEHAX AddressHoldTimefromWE#(CE#)High 2,4,5 0 0 0 0 0 0 ns
W9 tWHWL/
tEHEL WE#(CE#)PulseWidthHigh 1,4,5 25 30 30 30 30 30 ns
W10 tVPWH/
tVPEH VPPSetuptoWE#(CE#)GoingHigh 3,4,5 200 200 200 200 200 200 ns
W11 tQVVL VPP
HoldfromValidSRD 3,4 0 0 0 0 0 0 ns
W12 tBHWH/
tBHEH WP#SetuptoWE#(CE#)GoingHigh 3,4 0 0 0 0 0 0 ns
W13 tQVBL WP#
HoldfromValidSRD 3,4 0 0 0 0 0 0 ns
W14 tWHGL WE#HightoOE#GoingLow 3,4 30 30 30 30 30 30 ns
NOTES:
1. Writepulsewidth(tWP)isdefinedfromCE#orWE#goinglow(whichevergoeslowlast)
toCE#orWE#goinghigh
(whichevergoeshighfirst).Hence,tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.Similarly,writepulsewidthhigh(tWPH)isdefined
fromCE#orWE#goinghigh(whichevergoeshighfirst)
toCE#orWE#goinglow(whichevergoeslowlast).Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2. RefertoTable 3,“BusOperations(1)”onpage 14forvalidAINorDIN.
3. Sampled,butnot100%tested.
4. SeeFigure9,“ACInput/OutputReferenceWaveform”onpage 40fortimingmeasurementsandmaximumallowableinput
slewrate.
5. SeeFigure7,“WriteOperationsWaveform”onpage 38.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
36 Datasheet
Table18.WriteOperations—32MbitDensity
#Sym Parameter
Density 32Mbit
Unit
Product 70ns 90ns 100ns 110ns
VCC
3.0V–3.6V690 100
2.7V–3.6V70 90 100 110
Note Min Min Min Min Min Min
W1 tPHWL/
tPHEL RP#HighRecoverytoWE#(CE#)
GoingLow 4,5 150 150 150 150 150 150 ns
W2 tELWL/
tWLEL CE#(WE#)SetuptoWE#(CE#)
GoingLow 4,5000000ns
W3 tWLWH
/
tELEH WE#(CE#)PulseWidth 1,4,5 45 60 60 70 70 70 ns
W4 tDVWH/
tDVEH DataSetuptoWE#(CE#)GoingHigh 2,4,5 40 40 50 60 60 60 ns
W5 tAVWH/
tAVEH AddressSetuptoWE#(CE#)Going
High 2,4,5 50 60 60 70 70 70 ns
W6 tWHEH/
tEHWH CE#(WE#)HoldTimefromWE#
(CE#)High 4,5000000ns
W7 tWHDX/
tEHDX DataHoldTimefromWE#(CE#)
High 2,4,5000000ns
W8 tWHAX/
tEHAX AddressHoldTimefromWE#(CE#)
High 2,4,5000000ns
W9 tWHWL/
tEHEL WE#(CE#)PulseWidthHigh 1,4,5 25 30 30 30 30 30 ns
W10 tVPWH/
tVPEH VPPSetuptoWE#(CE#)GoingHigh 3,4,5 200 200 200 200 200 200 ns
W11 tQVVL VPP
HoldfromValidSRD 3,4000000ns
W12 tBHWH/
tBHEH WP#SetuptoWE#(CE#)Going
High 3,4000000ns
W13 tQVBL WP#
HoldfromValidSRD 3,4000000ns
W14 tWHGL WE#HightoOE#GoingLow 3,4 30 30 30 30 30 30 ns
NOTES:
1. Writepulsewidth(tWP)isdefinedfromCE#orWE#goinglow(whichevergoeslowlast)
toCE#orWE#goinghigh(whichever
goeshighfirst).Hence,tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.Similarly,writepulsewidthhigh(tWPH)isdefinedfromCE#or
WE#goinghigh(whichevergoeshighfirst)
toCE#orWE#goinglow(whichevergoeslowlast).Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2. RefertoTable 3,“BusOperations(1)”onpage 14forvalidAINorDIN.
3. Sampled,butnot100%tested.
4. SeeFigure9,“ACInput/OutputReferenceWaveform”onpage 40fortimingmeasurementsandmaximumallowableinput
slewrate.
5. SeeFigure7,“WriteOperationsWaveform”onpage 38.
6. VCCMax=3.3Vfor32-Mbit0.25Micronproduct.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 37
Table19.WriteOperations—64MbitDensity
#Sym Parameter
Density 64Mbit
UnitProduct 80ns
VCC 2.7V–3.6VNote Min
W1 tPHWL/
tPHEL RP#HighRecoverytoWE#(CE#)GoingLow 4,5 150 ns
W2 tELWL/
tWLEL CE#(WE#)SetuptoWE#(CE#)GoingLow 4,5 0 ns
W3 tWLWH/
tELEH WE#(CE#)PulseWidth 1,4,5 60 ns
W4 tDVWH/
tDVEH DataSetuptoWE#(CE#)GoingHigh 2,4,5 40 ns
W5 tAVWH/
tAVEH AddressSetuptoWE#(CE#)GoingHigh 2,4,5 60 ns
W6 tWHEH/
tEHWH CE#(WE#)HoldTimefromWE#(CE#)High 4,5 0 ns
W7 tWHDX/
tEHDX DataHoldTimefromWE#(CE#)High 2,4,5 0 ns
W8 tWHAX/
tEHAX AddressHoldTimefromWE#(CE#)High 2,4,5 0 ns
W9 tWHWL/
tEHEL WE#(CE#)PulseWidthHigh 1,4,5 30 ns
W10 tVPWH/
tVPEH VPPSetuptoWE#(CE#)GoingHigh 3,4,5 200 ns
W11 tQVVL VPP
HoldfromValidSRD 3,4 0 ns
W12 tBHWH/
tBHEH WP#SetuptoWE#(CE#)GoingHigh 3,4 0 ns
W13 tQVBL WP#
HoldfromValidSRD 3,4 0 ns
W14 tWHGL WE#HightoOE#GoingLow 3,4 30 ns
NOTES:
1. Writepulsewidth(tWP)isdefinedfromCE#orWE#goinglow(whichevergoeslowlast)
toCE#or
WE#goinghigh(whichevergoeshighfirst).Hence,tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.
Similarly,writepulsewidthhigh(tWPH)isdefinedfromCE#orWE#goinghigh(whichevergoes
highfirst)
toCE#orWE#goinglow(whichevergoeslowlast).Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2. RefertoTable 3,“BusOperations(1)”onpage 14forvalidAINorDIN.
3. Sampled,butnot100%tested.
4. SeeFigure9,“ACInput/OutputReferenceWaveform”onpage 40fortimingmeasurementsand
maximumallowableinputslewrate.
5. SeeFigure7,“WriteOperationsWaveform”onpage 38.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
38 Datasheet
5.3 EraseandProgramTimings
Table20.EraseandProgramTimings
Figure7.WriteOperationsWaveform
Symbol Parameter VPP 1.65V–3.6V 11.4V–12.6VUnit
NoteTypMaxTypMax
tBWPB 4-KWParameterBlock
WordProgramTime 1,2,3 0.10 0.30 0.03 0.12 s
tBWMB 32-KWMainBlock
WordProgramTime 1,2,3 0.8 2.4 0.24 1 s
tWHQV1
/tEHQV1
WordProgramTimefor0.13
and0.18MicronProduct 1,2,312 200 8 185 µs
WordProgramTimefor0.25
MicronProduct 1,2,322 200 8 185 µs
tWHQV2/tEHQV2 4-KWParameterBlock
EraseTime 1,2,30.5 4 0.4 4 s
tWHQV3/tEHQV3 32-KWMainBlock
EraseTime 1,2,31 5 0.6 5 s
tWHRH1/tEHRH1 ProgramSuspendLatency1,3510510µs
tWHRH2/tEHRH2 EraseSuspendLatency 1,3 5 20 5 20 µs
NOTES:
1. TypicalvaluesmeasuredatTA=+25°Candnominalvoltages.
2. Excludesexternalsystem-leveloverhead.
3. Sampled,butnot100%tested.
W10
W1
W7W4
W9W9
W3W3
W2
W6
W8W5
A
ddress[A]
CE#[E]
WE#[W]
OE#[G]
Data[D/Q]
RP#[P]
Vpp[V]
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 39
5.4 ResetSpecifications
Table21.ResetSpecifications
Symbol Parameter Notes VCC2.7V–3.6VUnit
Min Max
tPLPH RP#LowtoResetduringRead
(IfRP#istiedtoVCC,thisspecificationisnot
applicable) 1,2100 ns
tPLRH1 RP#LowtoResetduringBlockErase 3 22 µs
tPLRH2 RP#LowtoResetduringProgram 3 12 µs
NOTES:
1. IftPLPHis<100nsthedevicemaystillresetbutthisisnotguaranteed.
2. IfRP#isassertedwhileaBlockEraseor
WordProgramoperationisnotexecuting,theresetwillcomplete
within100ns.
3. Sampled,butnot100%tested.
Figure8.ResetOperationsWaveforms
IH
V
IL
V
RP#(P)
PLPH
t
IH
V
IL
V
RP#(P)
PLPH
t
(A)ResetduringReadMode
Abort
Complete PHQV
tPHWL
tPHEL
t
PHQV
tPHWL
tPHEL
t
(B)ResetduringProgramorBlockErase,<
PLPH
tPLR
H
t
PLRH
t
IH
V
IL
V
RP#(P)
PLPH
t
Abort
Complete PHQV
tPHWL
tPHEL
t
PLRH
t
Deep
Power-
Down
(C)ResetProgramorBlockErase,>
PLPH
tPLRH
t
28F008/800B3,28F016/160B3,28F320B3,28F640B3
40 Datasheet
5.5 ACI/OTestConditions
NOTE: Inputtimingbegins,andoutputtimingends,atVCCQ/2.Inputriseandfalltimes(10%to90%)<5ns.
WorstcasespeedconditionsarewhenVCC=VCCMin.
NOTE: SeeTable17forcomponentvalues.
5.6 DeviceCapacitance
TA=25°C,f=1MHz
F.
Figure9.ACInput/OutputReferenceWaveform
V
CCQ
0V
V
CCQ
/2 V
CCQ
/2
Test
Points
Input Output
Figure10.TransientEquivalentTestingLoadCircuit
Device
UnderTest
V
CCQ
C
L
R
2
R
1
Out
Table22.TestConfigurationComponentValuesforWorstCaseSpeedConditions
TestConfiguration CL(pF) R1(kΩ)R
2(kΩ)
VCCQMinStandardTest 50 25 25
NOTE: CLincludesjigcapacitance.
Symbol Parameter§Typ Max Unit Condition
CIN InputCapacitance 6 8 pF VIN=0.0 V
COUT OutputCapacitance 8 12 pF VOUT=0.0 V
§Sampled,not100%tested.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 41
6.0 ResetOperations
0580_09
NOTES:
1. IftPLPHis<100nsthedevicemaystillRESETbutthisisnotguaranteed
2. .Sampled,butnot100%tested.
3. IfRP#isassertedwhileablockeraseor
wordprogramoperationisnotexecuting,theresetwillcomplete
within100ns.
Figure11.ACWaveform:DeepPower-Down/ResetOperation
IH
V
IL
V
RP#(P)
PLPH
t
IH
V
IL
V
RP#(P)
PLPH
t
(A)ResetduringReadMode
Abort
Complete PHQV
tPHWL
tPHEL
t
PHQV
tPHWL
tPHEL
t
(B)ResetduringProgramorBlockErase,<
PLPH
tPLR
H
t
PLRH
t
IH
V
IL
V
RP#(P)
PLPH
t
Abort
Complete PHQV
tPHWL
tPHEL
t
PLRH
t
Deep
Power-
Down
(C)ResetProgramorBlockErase,>
PLPH
tPLRH
t
ResetSpecifications
Symbol Parameter Notes VCC=2.7V–3.6VUnit
Min Max
tPLPH RP#LowtoResetduringRead
(IfRP#istiedtoVCC,thisspecificationisnotapplicable) 1,2 100 ns
tPLRH RP#LowtoResetduringBlockEraseorProgram 2,3 22 µs
28F008/800B3,28F016/160B3,28F320B3,28F640B3
42 Datasheet
7.0 OrderingInformation
Figure12.OrderingInformation
Table23.
OrderingInformationValidCombinations(Sheet1of2)
40-LeadTSOP 48-LeadTSOP 48-BallµBGACSP(1,2) 48-BallVFBGA
Ext.Temp.64Mbit TE28F640B3TC80
TE28F640B3BC80 GE28F640B3TC80
GE28F640B3BC80
Ext.Temp.32Mbit TE28F320B3TD70
TE28F320B3BD70
TE28F320B3TC70
TE28F320B3BC70
TE28F320B3TC90
TE28F320B3BC90
TE28F320B3TA100
TE28F320B3BA100
TE28F320B3TA110
TE28F320B3BA110
GE28F320B3TD70
GE28F320B3BD70
GE28F320B3TC70
GE28F320B3BC70
GE28F320B3TC90
GE28F320B3BC90
Ext.Temp.16Mbit
TE28F016B3TA90
TE28F016B3BA90
TE28F016B3TA110
TE28F016B3BA110
TE28F160B3TD70
TE28F160B3BD70
TE28F160B3TC70
TE28F160B3BC70
TE28F160B3TC80
TE28F160B3BC80
TE28F160B3TC90
TE28F160B3BC90
TE28F160B3TA90
TE28F160B3BA90
TE28F160B3TA110
TE28F160B3BA110
GT28F160B3TA90(3)
GT28F160B3BA90(3)
GT28F160B3TA110(3)
GT28F160B3BA110(3)
GE28F160B3TD70
GE28F160B3BD70
GE28F160B3TC70
GE28F160B3BC70
GE28F160B3TC80
GE28F160B3BC80
GE28F160B3TC90
GE28F160B3BC90
Productlinedesignator
forallIntel®Flashproducts
2 8 F 3 2 0 3 T C7 0
Package
TE=48-LeadTSOP
GT=48-BallµBGA*CSP
GE=VFBGACSP
T E B
DeviceDensity
640=x16(64Mbit)
320=x16(32Mbit)
160=x16(16Mbit)
800=x16(8Mbit)
016=x8(16Mbit)
008=x8(8Mbit)
Lithography
NotPresent=0.4µm
A=0.25µm
C=0.18µm
D=0.13µm
ProductFamily
B3=3VoltAdvanced+BootBlock
VCC=2.7V–3.6V
VPP=2.7V–3.6Vor
11.4V–12.6V
T=TopBlocking
B=BottomBlocking
AccessSpeed(ns)
(70,80,90,100,110)
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 43
Ext.Temp.8Mbit TE28F008B3TA90
TE28F008B3BA90
TE28F008B3TA110
TE28F008B3BA110
TE28F800B3TA90
TE28F800B3BA90
TE28F800B3TA110
TE28F800B3BA110
GE28F800B3TA70
GE28F800B3BA70
GE28F008B3TA70
GE28F008B3BA70
GE28F800B3TA90
GE28F800B3BA90
GE28F008B3TA90
GE28F008B3BA90
NOTES:
1. The48-ballµBGApackagetopsidemarkreadsF160B3.Thismarkisidenticalforbothx8andx16products.Allproduct
shippingboxesortraysprovidethecorrectinformationregardingbusarchitecture.However,oncethedevicesareremoved
fromtheshippingmedia,itmaybedifficulttodifferentiatebasedonthetopsidemark.Thedeviceidentifier(accessible
throughtheDeviceIDcommand:seeSection3.2.2forfurtherdetails)enablesx8andx16µBGApackageproduct
differentiation.
2. Thesecondlineofthe48-ballµBGApackagetopsidemarkspecifiesassemblycodes.Forsamplesonly,thefirstcharacter
signifieseither“E”forengineeringsamplesor“S”forsilicondaisy-chainsamples.Allotherassemblycodeswithoutan“E”or
“S”asthefirstcharacterareproductionunits.
3. Intelrecommendsusing.18µmIntel£AdvancedBootBlockProducts.
Table23.OrderingInformationValidCombinations(Sheet2of2)
40-LeadTSOP 48-LeadTSOP 48-BallµBGACSP(1,2) 48-BallVFBGA
28F008/800B3,28F016/160B3,28F320B3,28F640B3
44 Datasheet
8.0 AdditionalInformation
OrderNumber Document/Tool
297948 Intel£AdvancedBootBlockFlashMemoryFamilySpecificationUpdate
292199 AP-641AchievingLowPowerwiththe3VoltAdvancedBootBlockFlashMemory
292200 AP-642DesigningforUpgradetothe3VoltAdvancedBootBlockFlashMemory
Note23VoltAdvancedBootBlockAlgorithms(‘C’andassembly)
http://developer.intel.com/design/flash/swtools
ContactyourIntelRepresentative Intel®FlashDataIntegrator(IFDI)SoftwareDeveloper’sKit
297874 IFDIInteractive:PlaywithIntel®FlashDataIntegratoronYourPC
NOTES:
1. PleasecalltheIntelLiteratureCenterat(800)548-4725torequestInteldocumentation.Internationalcustomersshould
contacttheirlocalIntelordistributionsalesoffice.
2. VisitIntel’sWorldWideWebhomepageathttp://www.Intel.comorhttp://developer.intel.comfortechnicaldocumentationand
tools.
3. ForthemostcurrentinformationonIntel£AdvancedBootBlockFlashmemoryandIntel£Advanced+BootBlockFlash
memory,visitourmicrositeathttp://developer.intel.com/design/flash/abblock.
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 45
AppendixAWriteStateMachineCurrent/NextStates
CommandInput(andNextState)
CurrentState SR.7 Data
When
Read
Read
Array
(FFH)
Program
Setup(10/
40H)
Erase
Setup
(20H)
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Prog/Ers
Resume
(D0H)
Read
Status
(70H)
Clear
Status
(50H)
Read
Identifier.
(90H)
ReadArray “1” Array Read
Array Program
Setup Erase
Setup ReadArray Read
Status Read
Array Read
Identifier
ReadStatus “1” Status Read
Array Program
Setup Erase
Setup ReadArray Read
Status Read
Array Read
Identifier
Read
Identifier “1” Identifier Read
Array Program
Setup Erase
Setup ReadArray Read
Status Read
Array Read
Identifier
Prog.Setup “1” Status Program(CommandInput=DatatobeProgrammed)
Program
(continue) “0” Status Program(continue) Prog.
Sysop.to
Rd.Status Program(continue)
Program
Suspendto
ReadStatus “1” Status Prog.
Susp.to
Read
Array
ProgramSuspend
toReadArray Program
(continue) Program
Susp.to
ReadArray Program
(continue)
Prog.
Susp.to
Read
Status
Prog.
Susp.to
Read
Array
Prog.
Susp.to
Read
Identifier
Program
Suspendto
ReadArray “1” Array Prog.
Susp.to
Read
Array
ProgramSuspend
toReadArray Program
(continue) Program
Susp.to
ReadArray Program
(continue)
Prog.
Susp.to
Read
Status
Prog.
Sus.to
Read
Array
Prog.
Susp.to
Read
Identifier
Prog.Susp.to
Read
Identifier “1” Identifier Prog.
Susp.to
Read
Array
ProgramSuspend
toReadArray Program
(continue) Program
Susp.to
ReadArray Program
(continue)
Prog.
Susp.to
Read
Status
Prog.
Sus.to
Read
Array
Prog.
Susp.to
Read
Identifier
Program
(complete) “1” Status Read
Array Program
Setup Erase
Setup ReadArray Read
Status Read
Array Read
Identifier
EraseSetup “1” Status EraseCommandError Erase
(continue) Erase
Cmd.Error Erase
(continue) EraseCommandError
EraseCmd.
Error “1” Status Read
Array Program
Setup Erase
Setup ReadArray Read
Status Read
Array Read
Identifier
Erase
(continue) “0” Status Erase(continue) EraseSus.
toRead
Status Erase(continue)
Erase
Suspendto
Status “1” Status Erase
Susp.to
Read
Array
Program
Setup
Erase
Susp.to
Read
Array Erase Erase
Susp.to
ReadArray Erase Erase
Susp.to
Read
Status
Erase
Susp.to
Read
Array
Ers.Susp.
toRead
Identifier
EraseSusp.
toRead
Array “1” Array Erase
Susp.to
Read
Array
Program
Setup
Erase
Susp.to
Read
Array Erase Erase
Susp.to
ReadArray Erase Erase
Susp.to
Read
Status
Erase
Susp.to
Read
Array
Ers.Susp.
toRead
Identifier
EraseSusp.
toRead
Identifier “1” Identifier Erase
Susp.to
Read
Array
Program
Setup
Erase
Susp.to
Read
Array Erase Erase
Susp.to
ReadArray Erase Erase
Susp.to
Read
Status
Erase
Susp.to
Read
Array
Ers.Susp.
toRead
Identifier
Erase
(complete) “1” Status Read
Array Program
Setup Erase
Setup ReadArray Read
Status Read
Array Read
Identifier
28F008/800B3,28F016/160B3,28F320B3,28F640B3
46 Datasheet
AppendixBArchitectureBlockDiagram
0580-C1
Output
Multiplexer
4-KWord
ParameterBlock
32-KWord
MainBlock
32-KWord
MainBlock
4-KWord
ParameterBlock
Y-Gating/Sensing WriteState
Machine Program/Erase
VoltageSwitch
Data
Comparator
Status
Register
Identifier
Register
Data
Register
I/OLogic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Power
Reduction
Control
InputBuffer
OutputBuffer
GND
V
CC
V
PP
CE#
WE#
OE#
RP#
Command
User
Interface
InputBuffer
A
0
-A
19
DQ
0
-DQ
15
V
CCQ
WP#
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 47
AppendixCWord-WideMemoryMapDiagrams
16-Mbitand32-MbitWord-WideMemoryAddressing
TopBoot BottomBoot
Size
(KW) 16Mbit 32Mbit Size
(KW) 8Mbit 16Mbit 32Mbit
4FF000-FFFFF 1FF000-1FFFFF 32 1F8000-1FFFFF
4FE000-FEFFF 1FE000-1FEFFF 32 1F0000-1F7FFF
4FD000-FDFFF 1FD000-1FDFFF 32 1E8000-1EFFFF
4FC000-FCFFF 1FC000-1FCFFF 32 1E0000-1E7FFF
4FB000-FBFFF 1FB000-1FBFFF 32 1D8000-1DFFFF
4FA000-FAFFF 1FA000-1FAFFF 32 1D0000-1D7FFF
4F9000-F9FFF 1F9000-1F9FFF 32 1C8000-1CFFFF
4F8000-F8FFF 1F8000-1F8FFF 32 1C0000-1C7FFF
32 F0000-F7FFF 1F0000-1F7FFF 32 1B8000-1BFFFF
32 E8000-EFFFF 1E8000-1EFFFF 32 1B0000-1B7FFF
32 E0000-E7FFF 1E0000-1E7FFF 32 1A8000-1AFFFF
32 D8000-DFFFF 1D8000-1DFFFF 32 1A0000-1A7FFF
32 D0000-D7FFF 1D0000-1D7FFF 32 198000-19FFFF
32 C8000-CFFFF 1C8000-1CFFFF 32 190000-197FFF
32 C0000-C7FFF 1C0000-1C7FFF 32 188000-18FFFF
32 B8000-BFFFF 1B8000-1BFFFF 32 180000-187FFF
32 B0000-B7FFF 1B0000-1B7FFF 32 178000-17FFFF
32 A8000-AFFFF 1A8000-1AFFFF 32 170000-177FFF
32 A0000-A7FFF 1A0000-1A7FFF 32 168000-16FFFF
32 98000-9FFFF 198000-19FFFF 32 160000-167FFF
32 90000-97FFF 190000-197FFF 32 158000-15FFFF
32 88000-8FFFF 188000-18FFFF 32 150000-157FFF
32 80000-87FFF 180000-187FFF 32 148000-14FFFF
32 78000-7FFFF 178000-17FFFF 32 140000-147FFF
32 70000-77FFF 170000-177FFF 32 138000-13FFFF
32 68000-6FFFF 168000-16FFFF 32 130000-137FFF
32 60000-67FFF 160000-167FFF 32 128000-12FFFF
32 58000-5FFFF 158000-15FFFF 32 120000-127FFF
32 50000-57FFF 150000-157FFF 32 118000-11FFFF
32 48000-4FFFF 148000-14FFFF 32 110000-117FFF
32 40000-47FFF 140000-147FFF 32 108000-10FFFF
32 38000-3FFFF 138000-13FFFF 32 100000-107FFF
32 30000-37FFF 130000-137FFF 32 F8000-FFFFF 0F8000-0FFFFF
32 28000-2FFFF 128000-12FFFF 32 F0000-F7FFF 0F0000-0F7FFF
32 20000-27FFF 120000-127FFF 32 E8000-EFFFF 0E8000-0EFFFF
32 18000-1FFFF 118000-11FFFF 32 E0000-E7FFF 0E0000-0E7FFF
32 10000-17FFF 110000-117FFF 32 D8000-DFFFF 0D8000-0DFFFF
32 08000-0FFFF 108000-10FFFF 32 D0000-D7FFF 0D0000-0D7FFF
32 00000-07FFF 100000-107FFF 32 C8000-CFFFF 0C8000-0CFFFF
Thiscolumncontinuesonnextpage Thiscolumncontinuesonnextpage
28F008/800B3,28F016/160B3,28F320B3,28F640B3
48 Datasheet
16-Mbitand32-MbitWord-WideMemoryAddressing(Continued)
TopBoot BottomBoot
Size
(KW) 16Mbit 32Mbit Size
(KW) 16Mbit 32Mbit
32 0F8000-0FFFFF 32 C0000-C7FFF 0C0000-0C7FFF
32 0F0000-0F7FFF 32 B8000-BFFFF 0B8000-0BFFFF
32 0E8000-0EFFFF 32 B0000-B7FFF 0B0000-0B7FFF
32 0E0000-0E7FFF 32 A8000-AFFFF 0A8000-0AFFFF
32 0D8000-0DFFFF 32 A0000-A7FFF 0A0000-0A7FFF
32 0D0000-0D7FFF 32 98000-9FFFF 098000-09FFFF
32 0C8000-0CFFFF 32 90000-97FFF 090000-097FFF
32 0C0000-0C7FFF 32 88000-8FFFF 088000-08FFFF
32 0B8000-0BFFFF 32 80000-87FFF 080000-087FFF
32 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF
32 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF
32 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF
32 098000-09FFFF 32 60000-67FFF 60000-67FFF
32 090000-097FFF 32 58000-5FFFF 58000-5FFFF
32 088000-08FFFF 32 50000-57FFF 50000-57FFF
32 080000-087FFF 32 48000-4FFFF 48000-4FFFF
32 078000-07FFFF 32 40000-47FFF 40000-47FFF
32 070000-077FFF 32 38000-3FFFF 38000-3FFFF
32 068000-06FFFF 32 30000-37FFF 30000-37FFF
32 060000-067FFF 32 28000-2FFFF 28000-2FFFF
32 058000-05FFFF 32 20000-27FFF 20000-27FFF
32 050000-057FFF 32 18000-1FFFF 18000-1FFFF
32 048000-04FFFF 32 10000-17FFF 10000-17FFF
32 040000-047FFF 32 08000-0FFFF 08000-0FFFF
32 038000-03FFFF 4 07000-07FFF 07000-07FFF
32 030000-037FFF 4 06000-06FFF 06000-06FFF
32 028000-02FFFF 4 05000-05FFF 05000-05FFF
32 020000-027FFF 4 04000-04FFF 04000-04FFF
32 018000-01FFFF 4 03000-03FFF 03000-03FFF
32 010000-017FFF 4 02000-02FFF 02000-02FFF
32 008000-00FFFF 4 01000-01FFF 01000-01FFF
32 000000-007FFF 4 00000-00FFF 00000-00FFF
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 49
4-Mbitand8-MbitWord-WideMemoryAddressing
TopBoot BottomBoot
Size
(KW) 4Mbit Size
(KW) 4Mbit 8Mbit
3F000-3FFFF 7F000-7FFFF 32 78000-7FFFF
3E000-3EFFF 7E000-7EFFF 32 70000-77FFF
3D000-3DFFF 7D000-7DFFF 32 68000-6FFFF
3C000-3CFFF 7C000-7CFFF 32 60000-67FFF
3B000-3BFFF 7B000-7BFFF 32 58000-5FFFF
3A000-3AFFF 7A000-7AFFF 32 50000-57FFF
39000-39FFF 79000-79FFF 32 48000-4FFFF
38000-38FFF 78000-78FFF 32 40000-47FFF
4 30000-37FFF 70000-77FFF 32 38000-3FFFF 38000-3FFFF
4 28000-2FFFF 68000-6FFFF 32 30000-37FFF 30000-37FFF
4 20000-27FFF 60000-67FFF 32 28000-2FFFF 28000-2FFFF
4 18000-1FFFF 58000-5FFFF 32 20000-27FFF 20000-27FFF
4 10000-17FFF 50000-57FFF 32 18000-1FFFF 18000-1FFFF
4 08000-0FFFF 48000-4FFFF 32 10000-17FFF 10000-17FFF
4 00000-07FFF 40000-47FFF 32 08000-0FFFF 08000-0FFFF
438000-3FFFF 4 07000-07FFF 07000-07FFF
32 30000-37FFF 4 06000-06FFF 06000-06FFF
32 28000-2FFFF 4 05000-05FFF 05000-05FFF
32 20000-27FFF 4 04000-04FFF 04000-04FFF
32 18000-1FFFF 4 03000-03FFF 03000-03FFF
32 10000-17FFF 4 02000-02FFF 02000-02FFF
32 08000-0FFFF 4 01000-01FFF 01000-01FFF
32 00000-07FFF 4 00000-00FFF 00000-00FFF
28F008/800B3,28F016/160B3,28F320B3,28F640B3
50 Datasheet
16-Mbit,32-Mbit,and64-MbitWord-WideMemoryAddressing
TopBoot BottomBoot
Size
(KW) 16Mbit 32Mbit 64Mbit Size
(KW) 16Mbit 32Mbit 64Mbit
4 FF000-FFFFF 1FF000-1FFFFF 3FF000-3FFFFF 32 3F8000-3FFFFF
4 FE000-FEFFF 1FE000-1FEFFF 3FE000-3FEFFF 32 3F0000-3F7FFF
4 FD000-FDFFF 1FD000-1FDFFF 3FD000-3FDFFF 32 3E8000-3EFFFF
4 FC000-FCFFF 1FC000-1FCFFF 3FC000-3FCFFF 32 3E0000-3E7FFF
4 FB000-FBFFF 1FB000-1FBFFF 3FB000-3FBFFF 32 3D8000-3DFFFF
4 FA000-FAFFF 1FA000-1FAFFF 3FA000-3FAFFF 32 3D0000-3D7FFF
4 F9000-F9FFF 1F9000-1F9FFF 3F9000-3F9FFF 32 3C8000-3CFFFF
4 F8000-F8FFF 1F8000-1F8FFF 3F8000-3F8FFF 32 3C0000-3C7FFF
32 F0000-F7FFF 1F0000-1F7FFF 3F0000-3F7FFF 32 3B8000-3BFFFF
32 E8000-EFFFF 1E8000-1EFFFF 3E8000-3EFFFF 32 3B0000-3B7FFF
32 E0000-E7FFF 1E0000-1E7FFF 3E0000-3E7FFF 32 3A8000-3AFFFF
32 D8000-DFFFF 1D8000-1DFFFF 3D8000-3DFFFF 32 3A0000-3A7FFF
32 D0000-D7FFF 1D0000-1D7FFF 3D0000-3D7FFF 32 398000-39FFFF
32 C8000-CFFFF 1C8000-1CFFFF 3C8000-3CFFFF 32 390000-397FFF
32 C0000-C7FFF 1C0000-1C7FFF 3C0000-3C7FFF 32 388000-38FFFF
32 B8000-BFFFF 1B8000-1BFFFF 3B8000-3BFFFF 32 380000-387FFF
32 B0000-B7FFF 1B0000-1B7FFF 3B0000-3B7FFF 32 378000-37FFFF
32 A8000-AFFFF 1A8000-1AFFFF 3A8000-3AFFFF 32 370000-377FFF
32 A0000-A7FFF 1A0000-1A7FFF 3A0000-3A7FFF 32 368000-36FFFF
32 98000-9FFFF 198000-19FFFF 398000-39FFFF 32 360000-367FFF
32 90000-97FFF 190000-197FFF 390000-397FFF 32 358000-35FFFF
32 88000-8FFFF 188000-18FFFF 388000-38FFFF 32 350000-357FFF
32 80000-87FFF 180000-187FFF 380000-387FFF 32 348000-34FFFF
32 78000-7FFFF 178000-17FFFF 378000-37FFFF 32 340000-347FFF
32 70000-77FFF 170000-177FFF 370000-377FFF 32 338000-33FFFF
32 68000-6FFFF 168000-16FFFF 368000-36FFFF 32 330000-337FFF
32 60000-67FFF 160000-167FFF 360000-367FFF 32 328000-32FFFF
32 58000-5FFFF 158000-15FFFF 358000-35FFFF 32 320000-327FFF
32 50000-57FFF 150000-157FFF 350000-357FFF 32 318000-31FFFF
32 48000-4FFFF 148000-14FFFF 348000-34FFFF 32 310000-317FFF
32 40000-47FFF 140000-147FFF 340000-347FFF 32 308000-30FFFF
32 38000-3FFFF 138000-13FFFF 338000-33FFFF 32 300000-307FFF
32 30000-37FFF 130000-137FFF 330000-337FFF 32 2F8000-2FFFFF
32 28000-2FFFF 128000-12FFFF 328000-32FFFF 32 2F0000-2F7FFF
32 20000-27FFF 120000-127FFF 320000-327FFF 32 2E8000-2EFFFF
32 18000-1FFFF 118000-11FFFF 318000-31FFFF 32 2E0000-2E7FFF
32 10000-17FFF 110000-117FFF 310000-317FFF 32 2D8000-2DFFFF
32 08000-0FFFF 108000-10FFFF 308000-30FFFF 32 2D0000-2D7FFF
32 00000-07FFF 100000-107FFF 300000-307FFF 32 2C8000-2CFFFF
32 0F8000-0FFFFF 2F8000-2FFFFF 32 2C0000-2C7FFF
32 0F0000-0F7FFF 2F0000-2F7FFF 32 2B8000-2BFFFF
32 0E8000-0EFFFF 2E8000-2EFFFF 32 2B0000-2B7FFF
32 0E0000-0E7FFF 2E0000-2E7FFF 32 2A8000-2AFFFF
32 0D8000-0DFFFF 2D8000-2DFFFF 32 2A0000-2A7FFF
32 0D0000-0D7FFF 2D0000-2D7FFF 32 298000-29FFFF
32 0C8000-0CFFFF 2C8000-2CFFFF 32 290000-297FFF
32 0C0000-0C7FFF 2C0000-2C7FFF 32 288000-28FFFF
32 0B8000-0BFFFF 2B8000-2BFFFF 32 280000-287FFF
32 0B0000-0B7FFF 2B0000-2B7FFF 32 278000-27FFFF
Thiscolumncontinuesonnextpage Thiscolumncontinuesonnextpage
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 51
16-Mbit,32-Mbit,and64-MbitWord-WideMemoryAddressing(Continued)
TopBoot BottomBoot
Size
(KW) 16Mbit 32Mbit 64Mbit Size
(KW) 16Mbit 32Mbit 64Mbit
32 0A8000-0AFFFF 2A8000-2AFFFF 32 270000-277FFF
32 0A0000-0A7FFF 2A0000-2A7FFF 32 268000-26FFFF
32 098000-09FFFF 298000-29FFFF 32 260000-267FFF
32 090000-097FFF 290000-297FFF 32 258000-25FFFF
32 088000-08FFFF 288000-28FFFF 32 250000-257FFF
32 080000-087FFF 280000-287FFF 32 248000-24FFFF
32 078000-07FFFF 278000-27FFFF 32 240000-247FFF
32 070000-077FFF 270000-277FFF 32 238000-23FFFF
32 068000-06FFFF 268000-26FFFF 32 230000-237FFF
32 060000-067FFF 260000-267FFF 32 228000-22FFFF
32 058000-05FFFF 258000-25FFFF 32 220000-227FFF
32 050000-057FFF 250000-257FFF 32 218000-21FFFF
32 048000-04FFFF 248000-24FFFF 32 210000-217FFF
32 040000-047FFF 240000-247FFF 32 208000-20FFFF
32 038000-03FFFF 238000-23FFFF 32 200000-207FFF
32 030000-037FFF 230000-237FFF 32 1F8000-1FFFFF 1F8000-1FFFFF
32 028000-02FFFF 228000-22FFFF 32 1F0000-1F7FFF 1F0000-1F7FFF
32 020000-027FFF 220000-227FFF 32 1E8000-1EFFFF 1E8000-1EFFFF
32 018000-01FFFF 218000-21FFFF 32 1E0000-1E7FFF 1E0000-1E7FFF
32 010000-017FFF 210000-217FFF 32 1D8000-1DFFFF 1D8000-1DFFFF
32 008000-00FFFF 208000-21FFFF 32 1D0000-1D7FFF 1D0000-1D7FFF
32 000000-007FFF 200000-207FFF 32 1C8000-1CFFFF 1C8000-1CFFFF
32 1F8000-1FFFFF 32 1C0000-1C7FFF 1C0000-1C7FFF
32 1F0000-1F7FFF 32 1B8000-1BFFFF 1B8000-1BFFFF
32 1E8000-1EFFFF 32 1B0000-1B7FFF 1B0000-1B7FFF
32 1E0000-1E7FFF 32 1A8000-1AFFFF 1A8000-1AFFFF
32 1D8000-1DFFFF 32 1A0000-1A7FFF 1A0000-1A7FFF
32 1D0000-1D7FFF 32 198000-19FFFF 198000-19FFFF
32 1C8000-1CFFFF 32 190000-197FFF 190000-197FFF
32 1C0000-1C7FFF 32 188000-18FFFF 188000-18FFFF
32 1B8000-1BFFFF 32 180000-187FFF 180000-187FFF
32 1B0000-1B7FFF 32 178000-17FFFF 178000-17FFFF
32 1A8000-1AFFFF 32 170000-177FFF 170000-177FFF
32 1A0000-1A7FFF 32 168000-16FFFF 168000-16FFFF
32 198000-19FFFF 32 160000-167FFF 160000-167FFF
32 190000-197FFF 32 158000-15FFFF 158000-15FFFF
32 188000-18FFFF 32 150000-157FFF 150000-157FFF
32 180000-187FFF 32 148000-14FFFF 148000-14FFFF
32 178000-17FFFF 32 140000-147FFF 140000-147FFF
32 170000-177FFF 32 138000-13FFFF 138000-13FFFF
32 168000-16FFFF 32 130000-137FFF 130000-137FFF
32 160000-167FFF 32 128000-12FFFF 128000-12FFFF
32 158000-15FFFF 32 120000-127FFF 120000-127FFF
32 150000-157FFF 32 118000-11FFFF 118000-11FFFF
32 148000-14FFFF 32 110000-117FFF 110000-117FFF
32 140000-147FFF 32 108000-10FFFF 108000-10FFFF
32 138000-13FFFF 32 100000-107FFF 100000-107FFF
32 130000-137FFF 32 F8000-FFFFF F8000-FFFFF F8000-FFFFF
32 128000-12FFFF 32 F0000-F7FFF F0000-F7FFF F0000-F7FFF
32 120000-127FFF 32 E8000-EFFFF E8000-EFFFF E8000-EFFFF
32 118000-11FFFF 32 E0000-E7FFF E0000-E7FFF E0000-E7FFF
32 110000-117FFF 32 D8000-DFFFF D8000-DFFFF D8000-DFFFF
32 108000-10FFFF 32 D0000-D7FFF D0000-D7FFF D0000-D7FFF
32 100000-107FFF 32 C8000-CFFFF C8000-CFFFF C8000-CFFFF
Thiscolumncontinuesonnextpage Thiscolumncontinuesonnextpage
28F008/800B3,28F016/160B3,28F320B3,28F640B3
52 Datasheet
16-Mbit,32-Mbit,and64-MbitWord-WideMemoryAddressing(Continued)
TopBoot BottomBoot
Size
(KW) 16Mbit 32Mbit 64Mbit Size
(KW) 16Mbit 32Mbit 64Mbit
32 0F8000-0FFFFF 32 C0000-C7FFF C0000-C7FFF C0000-C7FFF
32 0F0000-0F7FFF 32 B8000-BFFFF B8000-BFFFF B8000-BFFFF
32 0E8000-0EFFFF 32 B0000-B7FFF B0000-B7FFF B0000-B7FFF
32 0E0000-0E7FFF 32 A8000-AFFFF A8000-AFFFF A8000-AFFFF
32 0D8000-0DFFFF 32 A0000-A7FFF A0000-A7FFF A0000-A7FFF
32 0D0000-0D7FFF 32 98000-9FFFF 98000-9FFFF 98000-9FFFF
32 0C8000-0CFFFF 32 90000-97FFF 90000-97FFF 90000-97FFF
32 0C0000-0C7FFF 32 88000-8FFFF 88000-8FFFF 88000-8FFFF
32 0B8000-0BFFFF 32 80000-87FFF 80000-87FFF 80000-87FFF
32 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF 78000-7FFFF
32 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF 70000-77FFF
32 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF 68000-6FFFF
32 098000-09FFFF 32 60000-67FFF 60000-67FFF 60000-67FFF
32 090000-097FFF 32 58000-5FFFF 58000-5FFFF 58000-5FFFF
32 088000-08FFFF 32 50000-57FFF 50000-57FFF 50000-57FFF
32 080000-087FFF 32 48000-4FFFF 48000-4FFFF 48000-4FFFF
32 078000-07FFFF 32 40000-47FFF 40000-47FFF 40000-47FFF
32 070000-077FFF 32 38000-3FFFF 38000-3FFFF 38000-3FFFF
32 068000-06FFFF 32 30000-37FFF 30000-37FFF 30000-37FFF
32 060000-067FFF 32 28000-2FFFF 28000-2FFFF 28000-2FFFF
32 058000-05FFFF 32 20000-27FFF 20000-27FFF 20000-27FFF
32 050000-057FFF 32 18000-1FFFF 18000-1FFFF 18000-1FFFF
32 048000-04FFFF 32 10000-17FFF 10000-17FFF 10000-17FFF
32 040000-047FFF 32 08000-0FFFF 08000-0FFFF 08000-0FFFF
32 038000-03FFFF 4 07000-07FFF 07000-07FFF 07000-07FFF
32 030000-037FFF 4 06000-06FFF 06000-06FFF 06000-06FFF
32 028000-02FFFF 4 05000-05FFF 05000-05FFF 05000-05FFF
32 020000-027FFF 4 04000-04FFF 04000-04FFF 04000-04FFF
32 018000-01FFFF 4 03000-03FFF 03000-03FFF 03000-03FFF
32 010000-017FFF 4 02000-02FFF 02000-02FFF 02000-02FFF
32 008000-00FFFF 4 01000-01FFF 01000-01FFF 01000-01FFF
32 000000-007FFF 4 00000-00FFF 00000-00FFF 00000-00FFF
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 53
AppendixDByte-WideMemoryMapDiagrams
8-Mbitand16-MbitByte-WideByte-WideMemoryAddressing
TopBoot BottomBoot
Size(KB) 8Mbit 16Mbit Size(KB) 8Mbit 16Mbit
8 FE000-FFFFF 1FE000-1FFFFF 64
8 FC000-FDFFF 1FC000-1FDFFF 64
8 FA000-FBFFF 1FA000-1FBFFF 64
8 F8000-F9FFF 1F8000-1F9FFF 64
8 F6000-F7FFF 1F6000-1F7FFF 64
8 F4000-F5FFF 1F4000-1F5FFF 64
8 F2000-F3FFF 1F2000-1F3FFF 64
8 F0000-F1FFF 1F0000-1F1FFF 64
64 E0000-EFFFF 1E0000-1EFFFF 64
64 D0000-DFFFF 1D0000-1DFFFF 64
64 C0000-CFFFF 1C0000-1CFFFF 64
64 B0000-BFFFF 1B0000-1BFFFF 64
64 A0000-AFFFF 1A0000-1AFFFF 64
64 90000-9FFFF 190000-19FFFF 64
64 80000-8FFFF 180000-18FFFF 64
64 70000-7FFFF 170000-17FFFF 64
64 60000-6FFFF 160000-16FFFF 64
64 50000-5FFFF 150000-15FFFF 64
64 40000-4FFFF 140000-14FFFF 64
64 30000-3FFFF 130000-13FFFF 64
64 20000-2FFFF 120000-12FFFF 64
64 10000-1FFFF 110000-11FFFF 64
64 00000-0FFFF 100000-10FFFF 64
64 0F0000-0FFFFF 64
64 0E0000-0EFFFF 64
64 0D0000-0DFFFF 64
64 0C0000-0CFFFF 64
64 0B0000-0BFFFF 64
64 0A0000-0AFFFF 64
64 090000-09FFFF 64
64 080000-08FFFF 64
64 070000-07FFFF 64
64 060000-06FFFF 64 1F0000-1FFFFF
64 050000-05FFFF 64 1E0000-1EFFFF
64 040000-04FFFF 64 1D0000-1DFFFF
64 030000-03FFFF 64 1C0000-1CFFFF
64 020000-02FFFF 64 1B0000-1BFFFF
64 010000-01FFFF 64 1A0000-1AFFFF
64 000000-00FFFF 64 190000-19FFFF
Thiscolumncontinuesonnextpage Thiscolumncontinuesonnextpage
28F008/800B3,28F016/160B3,28F320B3,28F640B3
54 Datasheet
8-Mbitand16-MbitByte-WideMemoryAddressing(Continued)
TopBoot BottomBoot
Size(KB) 8Mbit 16Mbit Size(KB) 8Mbit 16Mbit
64 64 180000-18FFFF
64 64 170000-17FFFF
64 64 160000-16FFFF
64 64 150000-15FFFF
64 64 140000-14FFFF
64 64 130000-13FFFF
64 64 120000-12FFFF
64 64 110000-11FFFF
64 64 100000-10FFFF
64 64 F0000-FFFFF 0F0000-0FFFFF
64 64 E0000-EFFFF 0E0000-0EFFFF
64 64 D0000-DFFFF 0D0000-0DFFFF
64 64 C0000-CFFFF 0C0000-0CFFFF
64 64 B0000-BFFFF 0B0000-0BFFFF
64 64 A0000-AFFFF 0A0000-0AFFFF
64 64 90000-9FFFF 090000-09FFFF
64 64 80000-8FFFF 080000-08FFFF
64 64 70000-7FFFF 070000-07FFFF
64 64 60000-6FFFF 060000-06FFFF
64 64 50000-5FFFF 050000-05FFFF
64 64 40000-4FFFF 040000-04FFFF
64 64 30000-3FFFF 030000-03FFFF
64 64 20000-2FFFF 020000-02FFFF
64 64 10000-1FFFF 010000-01FFFF
64 8 0E000-0FFFF 00E000-00FFFF
64 8 0C000-0DFFF 00C000-00DFFF
64 8 0A000-0BFFF 00A000-00BFFF
64 8 08000-09FFF 008000-009FFF
64 8 06000-07FFF 006000-007FFF
64 8 04000-05FFF 004000-005FFF
64 8 02000-03FFF 002000-003FFF
64 8 00000-01FFF 000000-001FFF
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 55
4-MbitByte-WideMemoryAddressing
TopBoot BottomBoot
Size
(KB) 4Mbit Size
(KB) 4Mbit
8 7E000-7FFFF 64 70000-7FFFF
8 7C000-7DFFF 64 60000-6FFFF
8 7A000-7BFFF 64 50000-5FFFF
8 78000-79FFF 64 40000-4FFFF
8 76000-77FFF 64 30000-3FFFF
8 74000-75FFF 64 20000-2FFFF
8 72000-73FFF 64 10000-1FFFF
8 70000-71FFF 8 0E000-0FFFF
64 60000-6FFFF 8 0C000-0DFFF
64 50000-5FFFF 8 0A000-0BFFF
64 40000-4FFFF 8 08000-09FFF
64 30000-3FFFF 8 06000-07FFF
64 20000-2FFFF 8 04000-05FFF
64 10000-1FFFF 8 02000-03FFF
64 00000-0FFFF 8 00000-01FFF
28F008/800B3,28F016/160B3,28F320B3,28F640B3
56 Datasheet
AppendixEProgramandEraseFlowcharts
0580_E1
Figure13.ProgramFlowchart
Start
Write40H
ProgramAddress/Data
ReadStatusRegister
SR.7=1?
FullStatus
CheckifDesired
ProgramComplete
ReadStatusRegister
Data(SeeAbove)
V
PP
RangeError
ProgrammingError
AttemptedProgramto
LockedBlock-Aborted
ProgramSuccessful
SR.3=
SR.4=
SR.1=
FULLSTATUSCHECKPROCEDURE
BusOperation
Write
Write
Standby
Repeatforsubsequentprogrammingoperations.
SRFullStatusCheckcanbedoneaftereachprogramorafterasequenceof
programoperations.
WriteFFHafterthelastprogramoperationtoresetdevicetoreadarraymode.
BusOperation
Standby
Standby
SR.3MUSTbecleared,ifsetduringaprogramattempt,beforefurther
attemptsareallowedbytheWriteStateMachine.
SR.1,SR.3andSR.4areonlyclearedbytheClearStausRegisterCommand,
incaseswheremultiplebytesareprogrammedbeforefullstatusischecked.
Ifanerrorisdetected,clearthestatusregisterbeforeattemptingretryorother
errorrecovery.
No
Yes
1
0
1
0
1
0
Command
ProgramSetup
Program
Comments
Data=40H
Data=DatatoProgram
Addr=LocationtoProgram
CheckSR.7
1=WSMReady
0=WSMBusy
Command Comments
CheckSR.3
1=V
PP
LowDetect
CheckSR.1
1=AttemptedProgramto
LockedBlock-Program
Aborted
Read StatusRegisterDataToggle
CE#orOE#toUpdateStatus
RegisterData
Standby CheckSR.4
1=V
PP
ProgramError
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 57
0580_E2
Figure14.ProgramSuspend/ResumeFlowchart
Start
WriteB0H
ReadStatusRegister
No
Comments
Data=70H
Addr=X
Data=FFH
Addr=X
SR.7=
SR.2=
1
WriteFFH
ReadArrayData
ProgramCompleted
Done
Reading
Yes
WriteFFHWriteD0H
ProgramResumed ReadArrayData
0
1
Readarraydatafromblock
otherthantheonebeing
programmed.
StatusRegisterDataToggle
CE#orOE#toUpdateStatus
RegisterData
Addr=X
CheckSR.7
1=WSMReady
0=WSMBusy
CheckSR.2
1=ProgramSuspended
0=ProgramCompleted
Data=D0H
Addr=X
Bus
Operation
Write
Write
Read
Read
Standby
Standby
Write
Command
ReadStatus
ReadArray
Program
Resume
Write70H
0
Data=B0H
Addr=X
Write Program
Suspend
28F008/800B3,28F016/160B3,28F320B3,28F640B3
58 Datasheet
0580_E3
Figure15.BlockEraseFlowchart
Start
Write20H
WriteD0Hand
BlockAddress
ReadStatusRegister
SR.7=
FullStatus
CheckifDesired
BlockEraseComplete
FULLSTATUSCHECKPROCEDURE
BusOperation
Write
Write
Standby
Repeatforsubsequentblockerasures.
FullStatusCheckcanbedoneaftereachblockeraseorafterasequenceof
blockerasures.
WriteFFHafterthelastwriteoperationtoresetdevicetoreadarraymode.
BusOperation
Standby
SR.1and3MUSTbecleared,ifsetduringaneraseattempt,beforefurther
attemptsareallowedbytheWriteStateMachine.
SR.1,3,4,5areonlyclearedbytheClearStausRegisterCommand,incases
wheremultiplebytesareerasedbeforefullstatusischecked.
Ifanerrorisdetected,clearthestatusregisterbeforeattemptingretryorother
errorrecovery.
No Yes
SuspendErase
Suspend
EraseLoop
1
0
Standby
Command
EraseSetup
EraseConfirm
Comments
Data=20H
Addr=WithinBlocktoBe
Erased
Data=D0H
Addr=WithinBlocktoBe
Erased
CheckSR.7
1=WSMReady
0=WSMBusy
Command Comments
CheckSR.3
1=V
PP
LowDetect
CheckSR.4,5
Both1=CommandSequence
Error
ReadStatusRegister
Data(SeeAbove)
V
PP
RangeError
CommandSequence
Error
BlockErase
Successful
SR.3=
SR.4,5=
1
0
1
0
BlockEraseErrorSR.5=1
0
AttemptedEraseof
LockedBlock-Aborted
SR.1=1
0
Read StatusRegisterDataToggle
CE#orOE#toUpdateStatus
RegisterData
Standby CheckSR.5
1=BlockEraseError
Standby CheckSR.1
1=AttemptedEraseof
LockedBlock-EraseAborted
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 59
0580_E4
Figure16.EraseSuspend/ResumeFlowchart
Start
WriteB0H
ReadStatusRegister
BusOperation
Write
Write
No
Command
EraseSuspend
ReadArray
Comments
Data=B0H
Addr=X
Data=FFH
Addr=X
SR.7=
SR.6=
1
WriteFFH
ReadArrayData
EraseCompleted
Done
Reading
Yes
WriteFFHWriteD0H
EraseResumed ReadArrayData
0
1
0
Read Readarraydatafromblock
otherthantheonebeing
erased.
Read
StatusRegisterDataToggle
CE#orOE#toUpdateStatus
RegisterData
Addr=X
Standby CheckSR.7
1=WSMReady
0=WSMBusy
Standby CheckSR.6
1=EraseSuspended
0=EraseCompleted
Write EraseResume Data=D0H
Addr=X
Write ReadStatus Data=70H
Addr=X
Write70H
28F008/800B3,28F016/160B3,28F320B3,28F640B3
60 Datasheet
AppendixFMechanicalSpecifications
Figure17.µBGA*andVFBGAPackageDrawing&Dimensions
BottomView-Bumpsideup
e
b
S1
BallA1
Corner
TopView-BumpSidedown
BallA1
Corner
E
D
SideView
A
A2
A
1
Seating
Y
A
B
C
D
E
F
S2
Plan
123
4
5678
A
B
C
D
E
F
123
4
5678
Note:Drawingnottoscale
Millimeters Inches
Dimensions Symbol Min Nom Max Min Nom Max
PackageHeight A 1.000 0.0394
BallHeight A1 0.150 0.0059
PackageBodyThickness A2 0.665 0.0262
Ball(Lead)Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
PackageBodyLength8M(.25) D 7.810 7.910 8.010
PackageBodyLength16M(.25/.18/.13)32M(.25/.18/.13) D 7.186 7.286 7.386 0.2829 0.2868 0.2908
PackageBodyLength64M(.18) D 7.600 7.700 7.800 0.2992 0.3031 0.3071
PackageBodyWidth8M(.25) E 6.400 6.500 6.600 0.2520 0.2559 0.2598
PackageBodyWidth16M(.25/.18/.13)32M(.18/.13) E 6.864 6.964 7.064 0.2702 0.2742 0.2781
PackageBodyWidth32M(.25) E 10.750 10.850 10.860 0.4232 0.4272 0.4276
PackageBodyWidth64M(.18) E 8.900 9.000 9.100 0.3504 0.3543 0.3583
Pitch e 0.750 0.0295
Ball(Lead)Count8M,16M N 46 46
Ball(Lead)Count32M N 47 47
Ball(Lead)Count64M N 48 48
SeatingPlaneCoplanarity Y 0.100 0.0039
CornertoBallA1DistanceAlongD8M(.25) S1 1.230 1.330 1.430 0.0484 0.0524 0.0563
CornertoBallA1DistanceAlongD16M(.25/.18/.13)32M(.18/.13) S1 0.918 1.018 1.118 0.0361 0.0401 0.0440
CornertoBallA1DistanceAlongD64M(.18) S1 1.125 1.225 1.325 0.0443 0.0482 0.0522
CornertoBallA1DistanceAlongE8M(.25) S2 1.275 1.375 1.475 0.0502 0.0541 0.0581
CornertoBallA1DistanceAlongE16M(.25/.18/.13)32M(.18/.13)
S2 1.507 1.607 1.707 0.0593 0.0633 0.0672
CornertoBallA1DistanceAlongE32M(.25) S2 3.450 3.550 3.650 0.1358 0.1398 0.1437
CornertoBallA1DistanceAlongE64M(.18) S2 2.525 2.625 2.725 0.0994 0.1033 0.1073
R0
28F008/800B3,28F016/160B3,28F320B3,28F640B3
Datasheet 61
1. OnedimpleonpackagedenotesPin1.
2. Iftwodimples,thenthelargerdimpledenotesPin1.
3. Pin1willalwaysbeintheupperleftcornerofthepackage,inreferencetotheproductmark.
4. Pin1willalwayssupersedeabovepinonenotes.
Figure18.TSOPPackageDrawing&Dimensions
Dimensions
A5568-02
A
0
L
DetailA
Y
D
C
Z
Pin1
E
D
1
b
DetailB
SeeDetailA
e
SeeDetailB
A
1
A
2
Seating
Plane
SeeNotes1,2,3and4
Family:ThinSmallOut-LinePackage
Symbol Millimeters Inches
Min Nom Max Notes Min Nom Max Notes
PackageHeight A 1.200 0.047
Standoff A1 0.050 0.002
PackageBodyThickness A2 0.950 1.000 1.050 0.037 0.039 0.041
LeadWidth b 0.150 0.200 0.300 0.006 0.008 0.012
LeadThickness c 0.100 0.150 0.200 0.004 0.006 0.008
PlasticBodyLength D1 18.200 18.400 18.600 0.717 0.724 0.732
PackageBodyWidth E 11.800 12.000 12.200 0.465 0.472 0.480
LeadPitch e 0.500 0.0197
TerminalDimension D 19.800 20.000 20.200 0.780 0.787 0.795
LeadTipLength L 0.500 0.600 0.700 0.020 0.024 0.028
LeadCount N 48 48
LeadTipAngle Ø 0° 3° 5° 0° 3° 5°
SeatingPlaneCoplanarity Y 0.100 0.004
LeadtoPackageOffset Z 0.150 0.250 0.350 0.006 0.010 0.014
28F008/800B3,28F016/160B3,28F320B3,28F640B3
62 Datasheet
Figure19.EasyBGAPackageDrawing&Dimension
Millimeters Inches
Symbol Min Nom Max Notes Min Nom Max
PackageHeight A 1.200 0.0472
BallHeight A10.250 0.0098
PackageBodyThickness A20.780 0.0307
Ball(Lead)Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209
PackageBodyWidth D 9.900 10.000 10.100 1 0.3898 0.3937 0.3976
PackageBodyLength E 12.900 13.000 13.100 1 0.5079 0.5118 0.5157
Pitch [e] 1.000 0.0394
Ball(Lead)Count N 64 64
SeatingPlaneCoplanarity Y 0.100 0.0039
CornertoBallA1DistanceAlongDS
11.400 1.500 1.600 1 0.0551 0.0591 0.0630
CornertoBallA1DistanceAlongE S22.900 3.000 3.100 1 0.1142 0.1181 0.1220
DimensionsTable
Note:(1)Packagedimensionsareforreferenceonly.Thesedimensionsareestimatesbased
ondiesize,andaresub
ecttochan
e.
E
Seating
Plane
S1
S2
e
TopView -Ballsidedown Bottom View -BallSideUp
Y
A
A1
D
BallA1
Corner
A2
Note:Drawingnottoscale
A
B
C
D
E
F
G
H
8765432187654321
A
B
C
D
E
F
G
H
b
BallA1
Corner
SideView