SC1404 Mobile Multi-Output PWM Controller with Virtual Current Sense TM POWER MANAGEMENT Description PRELIMINARY Features The SC1404 is a multiple-output power supply controller designed to power battery operated systems. The SC1404 provides synchronous rectified buck converter control for two power supplies. An efficiency of 95% can be achieved. The SC1404 uses Semtech's proprietary Virtual Current SenseTM technology along with external error amplifier compensation to achieve enhanced stability and DC accuracy over a wide range of output filter components while maintaining fixed frequency operation. The SC1404 also provides two linear regulators for system housekeeping. The 5V linear regulator takes its input from the battery; for efficiency, the output is switched to the 5V output when available. The 12V linear regulator output is generated from a coupled inductor off the 5V switching regulator. 6.0 V to 30 V Input Range Operation Below 6V Possible 3.3 V and 5 V Dual Synchronous Outputs Fixed Frequency or PSAVE for Maximum Efficiency Over Wide Load Current Range 5 V / 50 mA Linear Regulator and 12V/200mA Linear Regulator TM Virtual Current Sense for Enhanced Stability Accurate Low Loss Current Limiting Out-of Phase Switching Reduces Input Capacitance External Compensation Supports Wide Range of Output Filter Components For Reduced Cost Programmable Power-Up Sequence Power Good Output Output Overvoltage & Overcurrent Protection with Output Undervoltage Shutdown 4 A Typical Shutdown Current 6 mW Typical Quiescent Power Control functions include: power up sequencing, soft start, power-good signaling, and frequency synchronization. Line and load regulation is to +/-1% of the output voltage. The internal oscillator can be adjusted to 200 kHz or 300 kHz or synchronized to an external clock. The MOSFET drivers provide >1A peak drive current for fast MOSFET switching. Applications The SC1404 includes a PSAVE# input to select pulse skipping mode for high efficiency at light load, or fixed frequency mode for low noise operation. Notebook and Subnotebook Computers Automotive Electronics Desktop DC-DC Converters Typical Application Circuit O N /O F F IN P U T + 6 V T O + 3 0 V + 10 4 .7 F + + +5V A LWAY S ON 0 .2 F + 23 S H DN 22 6 21 V + S Y NC V DD 3 0 .1 F 4 .7 F VL 5 +12V 12 C O M P3 C O M P5 + D1 0 .1 F 25 B S T3 B S T5 0 .1 F D2 18 5 4 .7 F 0 .1 F 0 .1 F 1 2 V O UT 27 + 3 .3 V O U T P U T DH5 16 L1 +5 V O UT P UT 26 24 + DH3 + 2 .2 F 1 N5 8 1 9 P H A S E3 P H A S E5 DL 3 DL 5 Q2 PGN D 1 2 CS H3 CS H5 CS L 5 CS L 5 17 T1 19 Q4 + 20 14 13 15 3 V O N /O F F 5 V O N /O F F 28 7 SEQ O N3 R EF O N5 PS A V E 10 Revision 1, May 2002 R ES E T GND 9 + 11 + 2 .5 V R E F 0 .1 F P O W E R-G O O D 8 1 www.semtech.com SC1404 POWER MANAGEMENT Absolute Maximum Ratings PRELIMINARY PAR AMETER DESCR IPTION MAXIMUM / UNITS VDD, V+, PHASE3, PHASE5 to GND Supply Voltage -0.3V to +30V BST3, BST5, DH3, DH5 to GND Boost voltages -0.3V, +36V PGND to GND 0.3V BST3 TO PHASE3 , BST5 TO PHASE5 , CSL5, CSH5, CSL3, CSH3 to GND -0.3V to +6V DC -2.0V to +7V Transient , 100nS REF, SYNC, SEQ, PSAVE#, ON5, RESET#, VL, COMP3, COMP5 to GND -0.3V to +6V ON3, SHDN# to GND -0.3V to (V+ + 0.3V) VL, REF Shor t to GND Continuous REF Current +5mA VL Current +50mA 12OUT to GND -0.3 to (VDD + 0.3V) 12OUT Shor t to GND Continuous 12OUT Current +200mA TJ j-a Thermal resistance Junction operating temperature Junction-to-ambient 150C 76 C/Watt TS Storage Temperature -65C to +200C TL Lead soldering temperature 300C, 10 seconds Electrical Characteristics Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to +85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit PAR AMETER CODE CONDITIONS MI N T YP MAX UNITS 30.0 V MAIN SMPS CONTR OLLER S Inp ut Voltage Range V IN 3V Outp ut Voltage V 3OUT V + = 6.0 to 30V, 3V load = 0A to current limit 3.23 3.3 3.37 V 5V Outp ut Voltage V 5OUT V + = 6.0 to 30V, 5V load = 0A to current limit 4.9 5.0 5.1 V Load Regulation V 3LDRG V 5LDRG Either SMPS, 0A to current limit, PSAV E = V L -0.4 % Line Regulation V 3LIRG V 5LIRG Either SMPS, 6.0 < V + < 30V, PSAV E 0.05 % /V May 2002 Semtech Corp. 6 2 = VL www.semtech.com SC1404 POWER MANAGEMENT Electrical Characteristics Cont. PRELIMINARY Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to +85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit PAR AMETER Current-Limit Thresholds CODE I3LIMP I5LIMP I3LIMN I5LIMN CONDITIONS CSHX - CSLX (p ositive current) MI N T YP MAX UNITS 40 50 70 mV CSHX - CSLX (negative current) -50 Zero Crossing Threshold CSHX - CSLX PSAVE# = 0V, not tested 5 mV Soft-Star t Ramp Time From enable to 95% full current limit, with resp ect to fOSC 512 clks Oscillator Frequency FOSCHI FOSCLO SYN C = VL SYN C = 0V 220 170 300 200 Maximum Duty Factor DF3MAX DF5MAX SYN C = VL SYN C = 0V 92 94 94 96 SYN C Inp ut High Pulse N ot tested 300 SYN C Inp ut Low Pulse Width N ot tested 300 SYN C Rise/Fall Time N ot tested SYN C Inp ut Frequency Range SYN CRG Current-Sense Inp ut Leakage Current ICSH3 ICSH5 380 230 kHz % ns 200 240 CSH3 = 3.3V, CSH5 = 5.0V 3 350 kHz 10 A ER R OR AMP DC Loop Gain DCG3, DCG5 From internal feedback node to COMP3/COMP5 Gain Bandwidth Product Outp ut Resistance RC3, RC5 Offset Voltage VOS3, VOS5 COMP3, COMP5 15 Internal feedback sense (resistor divider) - REF 18 V/V 8 MHz 25 35 2 Kohms mV INTER NAL R EGULATOR AND R EFER ENCE 5.2 VLOUT VL Undervoltage Lockout Fault Threshold V LU V Falling edge, hysteresis = 0.7V VL Switchover Lockout VLSW Switchover at star tup REF Outp ut Voltage REFOUT N o external load REF Load Regulation REFLD1 0A < ILOAD < 50A 12.5 REFLD2 0mA < ILOAD < 5mA 50 May 2002 Semtech Corp. SHDN # = V+; 6V < V+ <30V, 0mA <I <50mA, ON 3 = ON 5 = 0V 4.6 VL Outp ut Voltage 3 LOAD 3.5 3.7 V 4.0 4.5 2.45 2.5 2.55 mV www.semtech.com SC1404 POWER MANAGEMENT Electrical Characteristics Cont. PRELIMINARY Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to +85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit PAR AMETER CODE CONDITIONS MI N T YP REF Sink Current IREFSK REF Fault Lockout Voltage REFUV Falling edge V+ Op erating Sup p ly Current IVPOP VL switched over to VOUT5, 5V SMPS on, ILOAD5 = ILOAD3 = 0A 10 V+ Standby Sup p ly Current IVPSB V+ = 6V to 30V, SMPS off, includes current into SHDN # 200 V+ Shutdown Sup p ly Current IVPSD V+ = 6V to 30V, SHDN # = 0V 4 Quiescent Power Consump tion PQ SMPS enabled, N o Load on SMPS 6 MAX 10 1.8 UNITS A 2.2 V 50 A 10 mW FAULT DETECTION Overvoltage Trip Threshold V3OV, V5OV Overvoltage-Fault Prop agation Delay With resp ect to unloaded outp ut voltage Outp ut driven 2% above overvoltage trip V Outp ut Undervoltage Threshold V3UV, V5UV Outp ut Undervoltage Lockout Time V3UV TO V5UV TO Thermal Shutdown Threshold 7 From each SMPS enabled, with resp ect to f OSC 15 1.5 TH With resp ect to unloaded outp ut voltage 10 % s 68 75 82 % 5000 6144 7000 clks Typ ical hysteresis = +10C 150 C R ESET# RESET# Trip Threshold V3RST V5RST RESET# Prop agation Delay RESET# Delay Time With resp ect to unloaded outp ut voltage, falling edge; typ ical hysteresis = 1% -13 Falling edge, outp ut driven 2% below RESET# trip threshold T3RSDL T5RSDL With resp ect to fOSC -10 -7 1.5 27,000 32,000 % s 37,000 clks 0.6 V INPUTS AND OUTPUTS Logic Inp ut Low Voltage VIO3, VIOP, VIO5, VIOSD, VIOSN ON 3, PSAVE#, ON 5, SHDN #, SYN C (SEQ = REF) Logic Inp ut High Voltage VIH3, VIHP, VIH5, VIHSD, VIHSN ON 3, PSAVE#, ON 5, SHDN #, SYN C (SEQ = REF) May 2002 Semtech Corp. 4 2.4 V www.semtech.com SC1404 POWER MANAGEMENT Electrical Characteristics Cont. PRELIMINARY Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to +85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit PAR AMETER CODE CONDITIONS MI N T YP MAX UNITS -1 +1 A -10 +10 A 0.4 V Inp ut Leakage Current ON 3, PSAVE#, ON 5, SYN C IL3, ILP, IL5, ILSN SEQ = REF Inp ut Leakage Current SHDN # ILSD Logic Outp ut Low Voltage VORSTL RESET#, ISIN K = 4mA Logic Outp ut High Current IORSTH RESET# = 3.5V ON 5 Pull-down Resistance RON 5 ON 5, RUN /ON 3 = 0V, (SEQ = REF) 100 ohms Gate Driver Sink/Source Current IDL3, IDH3, IDL5, IDH5 DL3, DH3, DL5, DH5, forced to 2.5V 1 A Gate Driver On-Resistance RGBH3, RGHP3, RGBH5, RGHP5, RGVL3, RGLG3 RGVL5, RGLG5 BST3 to DH3, DH3 to PHASE3, BST5 to DH5, DH5 to PHASE5, VL to DL3, DL3 to PGN D, VL to DL5, DL5 to PGN D 1.5 PHASE3, PHASE5, DL3, or DL5 1.0 V DL3 falling edge to DH3 rising edge, DL5 falling edge to DH5 rising edge, 30 nsec SEQ = REF N on-Overlap Threshold Shoot-through Delay 1 mA 7 ohms FLYBACK CONTR OLLER VDD Shunt Threshold VDDSHN Rising edge, hysteresis = 1% 18 VDD Shunt Current IVDDST VDD = 20V 5 VDD Leakage Current IVDDLK VDD = 5V, Standby mode 10 20 V 30 mA 30 A 12.50 V 12VOUT LINEAR R EGULATION 12OUT Outp ut Voltage VOUT12 12OUT Current Limit ILIM12 12OUT Regulation Threshold V12THR Quiescent VDD Current I12Q 0mA < Load < 200mA 11.55 12.1 12OUT forced to 11V, VDD = 13V 200 300 mA Falling edge 11.9 V VDD = 18V, run mode, no 12OUT load 80 Note: (1) This device is ESD sensitive. May 2002 Semtech Corp. 100 A Use of standard ESD handling procedures required. 5 www.semtech.com SC1404 POWER MANAGEMENT Pin Descriptions Pi n # Pin N ame PRELIMINARY Pin Function 1 CSH3 Current limit sense inp ut for 3.3 V SMPS. Connect to the inductor side of a current sense resistor. 2 CSL3 Outp ut voltage sense inp ut for 3.3 V SMPS. Connect to the outp ut side of a current sense resistor. 3 COMP3 The outp ut of the error amp lifier for 3.3V SMPS. 4 12OUT 12V Internal Linear Regulator Oup ut. 5 VDD Sup p ly Voltage Inp ut for the 12OUT Linear regulator. Also connects to a 18V overvoltage shunt regulator clamp . 6 SYN C Oscillator Synchronization and Frequency Select. Tie to VL for 300 kHz op eration; tie to GN D for 200 kHz. Drive externally to synchronize to an external oscillator between 240 kHz and 350 kHz. 7 ON 5 5V ON /OFF Control Inp ut 8 GN D Low noise Analog Ground and Feedback reference p oint 9 REF 2.5 V Reference Voltage Outp ut. Byp ass to GN D with 1 F minimum 10 PSAVE# Logic Control Inp ut that disables PSAVE Mode when high. Connect to GN D for normal use 11 RESET# Active Low Timed Reset Outp ut. RESET# swings GN D to VL. Goes high after a fixed 32,000 clock cycle delay following p ower up 12 COMP5 The outp ut of the error amp lifier for 5V SMPS. 13 CSL5 Outp ut voltage sense inp ut for 5 V SMPS. Connect to the outp ut side of a current sense resistor. 14 CSH5 Current limit sense inp ut for 5 V SMPS. Connect to the inductor side of a current sense resistor. 15 SEQ Inp ut that selects SMPS sequence for RESET# 16 DH5 Gate Drive Outp ut for the 5 V, high side N -Channel switch 17 PHASE5 18 BST5 Boost cap acitor connection for high side gate drive 19 DL5 Gate Drive Outp ut for the low side synchronous rectifier MOSFET 20 PGN D 21 VL 5 V Internal Linear Regulator Outp ut 22 V+ Battery Voltage Inp ut 23 SHDN # 24 DL3 Gate Drive Outp ut for the low side synchronous rectifier MOSFET 25 BST3 Boost Cap acitor Connection for high side gate drive 26 PHASE3 27 DH3 28 ON 3 Switching N ode (inductor) connection Power Ground Shutdown Control Inp ut, active low Switching N ode (inductor) Connection Gate Drive Outp ut for the 3.3 V, high side N -Channel switch 3V ON /OFF Control Inp ut Note: All logic level inputs and outputs are open collector TTL compatible. May 2002 Semtech Corp. 6 www.semtech.com SC1404 POWER MANAGEMENT Block Diagram PRELIMINARY 200m A V+ V+ SYNC PSAV E VDD 12OUT + VL 12 V REG 5V REG VL 4.7 f + 2.2 f VL VIN BST3 BST5 EN VIN CSL5 DH3 LX3 DELAY HS DH5 VL +3.3V T1 LX5 +5V LS DL3 VL OSC LS DL5 1:3 PGND 50mV OC 7.5m V PS 2.5m V POL 3V CTL LOGIC PWM MODULATOR CSH3 5V CTL LOGIC OV FAULT OC 50mV PS 7.5m V POL 2.5m V PWM MODULATOR CSH5 CSL5 CSL3 +10% -25% COMP5 COMP3 UV FAULT DELAY REF 2.5V REF V+ CSL3 CSL5 TIMER BV CURRENT RAMP RESET SS 2.0 ON5 POW ER-ON SEQUENCE LOGIC SEQ 0.5 ON3 May 2002 Semtech Corp. 7 www.semtech.com SC1404 POWER MANAGEMENT Pin Configuration PRELIMINARY Ordering Information Top View C SH 3 C S L3 C OMP3 12OU T ON 5 GN D R EF PSAVE# R E S E T# C OMP5 C S L5 C SH 5 9 10 11 SC1404 VD D SYN C 1 2 3 4 5 6 7 8 12 13 14 28 27 26 25 24 23 SH D N # 22 V+ 21 20 19 18 17 VL ON 3 DEVICE PACKAGE TEMP. (TAMB) SC1404ITS TSSOP-28 -40 - +85C DH3 PH ASE3 Block Diagram B S T3 D L3 INPUT +5V 5V LINEAR 12V LINEAR 3.3V SMP S 5V SMP S POW ER-UP SEQU ENCE POW ERGOOD +12V PGN D D L5 B S T5 PH ASE5 16 DH5 15 SEQ +3.3V +5V TSSOP-28 ON/OFF May 2002 Semtech Corp. 8 RESET www.semtech.com SC1404 POWER MANAGEMENT Functional Information PRELIMINARY Detailed Description trip voltage set around the reference. When entering PSAVE mode, if the minimum (valley) inductor current measured across the CSH and CSL pins is below the PSAVE threshold for four switching cycles, the virtual current sensing circuitry is shutdown and PWM switches from forced continuous to hysteretic mode. If the minimum (valley) inductor current is above the threshold for four switching cycles, PWM control changes from hysteretic to forced continuous mode. The SC1404 provides built-in hysteresis to prevent chattering between the two modes of operation. The SC1404 is a versatile multiple-output power supply controller designed to power battery operated systems. Out of phase switching is adopted to improve signal quality and reduce input RMS current, thereby reducing the size of input filter capacitors(see Out-of-Phase Switching). The SC1404 provides synchronous rectified buck control in fixed-frequency forced-continuous mode and hysteretic PSAVE mode for two switching power supplies over a wide load range. The two switchers have on-chip preset output voltage of 5.0V and 3.3V. The control and fault monitoring circuitry associated with each PWM controller includes digital softstart, turn-on sequencing, voltage error amplifier with built-in slope compensation, pulse width modulator, power save, over-current, over-voltage and under-voltage fault protection. Two linear regulator and a precision reference voltage are also provided by the SC1404. The 5V/50mA linear regulator takes input from the battery to power the gate drivers, however to improve efficiency, the 5V switcher output is used instead when available. The 12V/ 200mA linear regulator is capable of supplying 200mA. Semtech's proprietary Virtual Current SenseTM provides greater advantages in stability and signal to noise ratio than the conventional current sense method. Gate Drive / Control The gate drivers on the SC1404 are designed to switch large MOSFETs up to 350KHz. The high-side gate driver is required to drive the gates of high-side MOSFETs above the V+ input. The supply for the gate drivers is generated by charging a boostrap capacitor from the VL supply when the low-side driver is on. Monitoring circuitry ensures that the bootstrap capacitor is charged when coming out of shutdown or fault conditions where the bootstrap capacitor may be depleted. In continuous conduction mode, the low-side driver output that controls the synchronous rectifier in the power stage is on when the high-side driver is off. Under light load conditions when PSAVE pin is low, the inductor ripple current will approach the point where it reverses polarity. This is detected by the low-side driver control and the synchronous rectifier is turned off before the current reverses, preventing energy drain from the output. The low-side driver operation is also affected by various fault conditions as described in the Fault Protection section. PWM control There are two separate PWM control blocks for the 3V and 5V switchers. They are switched out-of-phase with each other. The interleaved topology offers greater advantage over in-phase solutions. It reduces steady state input filter requirements by reducing current drawn from the filter capacitors. To avoid both switchers switching at the same instance, there is a built-in delay between the on-time of the 3.3V switcher and 5V switcher, the amount of which depends on the input voltage (see Out-of-Phase Switching). The PWM provides two modes of control over the entire load range. The SC1404 operates in forced continuous conduction mode as a fixed-frequency peak current mode controller with falling edge modulation. Current sense is done differently than that in the conventional peak current mode control. Semtech's proprietary Virtual Current SenseTM emulates the necessary inductor current information for proper functioning of the IC. External Compensation The COMP pin allows external compensation of the feedback loop. This allows greater flexibilty when choosing output filters, resulting in reduced cost and smaller size compared to a fixed compensation approach. A nominal gain of 18 for the error amplifier improves the system loop gain and output transient response. Internal Bias Supply The VL linear regulator provides a 5V output that powers the gate drivers, 2.5V reference, and internal controls of the SC1404. The VL supply is capable of supplying up to 50mA (including MOSFET gate charge current). The VL pin should be bypassed to GND with 4.7uF to supply the peak gate drive curents. The regulator receives input power from the V+ battery input. Efficiency is improved by providing a boot-strap for the VL bias. When the 5V SMPS output voltage reaches 5V, internal circuitry detects this condition and turns on a PMOS pass device between CSL5 and VL. The internal VL regulator is then disabled and the VL bias is provided by the high efficiency 5V switcher. When the switcher is operating in continuous conduction mode, the high-side MOSFET is turned on at the beginning of each switching cycle. It is turned off when the desired duty cycle is reached. Active shoot-through protection delays the turn-on of the lower MOSFET until the phase node drops below 1.0 V. The lowside MOSFET remains on until the beginning of the next switching cycle. Again, active shoot-through protection ensures that the gate to the low-side MOSFET has dropped low before the high-side MOSFET is turned on. Under light load conditions when the PSAVE pin is low, the SC1404 operates as a hysteretic controller in the discontinuous conduction mode to reduce its switching frequency and switching bias current. The switching of the output MOSFET does not depend on the oscillator frequency, but on the hysteretic May 2002 Semtech Corp. 9 www.semtech.com SC1404 POWER MANAGEMENT Functional Information PRELIMINARY The REF output is accurate to +/- 2% over temperature. It is capable of delivering 5mA max and should be bypassed with 1uF minimum. Loading the REF pin will reduce the REF voltage slightly. Loading Resistance (ohm) 511 2.67K 49.9K 255K 1Meg Deviation from Vref = 2.4920V 8.3mV 3.1mV 0.5mV 0.3mV 0mV SHDN # ON 3 ON 5 MODE DESCRIPTION Low X X Shutdown Minimum b ias current High Low Low Standb y VREF and VL regulator enab le High High High Ru n Mode Both SMPS Ru n n i n g Power up Controls and Soft Start Current Sense (CSH, CSL) The user has control of the SC1404 RESET# by setting the SEQ, ON3 and ON5 pins as described in the following table. The output current of the power supply is sensed as the voltage drop across an external resistor between the CSH and CSL pins. Overcurrent is detected when the current sense voltage exceeds +/- 50mV. A positive overcurrent will turn off the high-side driver; a negative overcurrent will turn off the low-side driver, each on a cycle-by-cycle basis. At startup, the RESET# pin is held low for 32K switching cycles. Another timer is used to enable the undervoltage protection. The undervoltage protection circuitry is enabled after 6144 switching cycles at which time the SMPS should be in regulation. Oscillator When SEQ is set to REF, the RESET# only monitors the 3.3V SMPS in regulation and the 5V SMPS is ignored. When the SYNC pin is set high the oscillator runs at 300KHz; when SYNC is set low the frequency is 200KHz. The oscillator can also be synchronized to the falling edge of a clock on the SYNC pin with a frequency between 240KHz and 350KHz. In general, 200KHz operation is used for highest efficiency, and the 300KHz for minimum output ripple and/or smaller filter components. Each SMPS contains its own counter and DAC to gradually increase the current limit at startup to prevent surge currents. The current limit is increased from 0, 20%, 40%, 60%, 80%, to 100% linearly over the course of 512 switching cycles. 12OUT Supply Fault Protection The 12OUT linear regulator is capable of supplying 200mA. The input voltage to the 12OUT regulator is generated by a secondary winding on the 5V SMPS inductor. In addition to cycle-by-cycle current limit, the SC1404 monitors over-temperature, and output overvoltage and undervoltage conditions. The overtemperature detection will shut the part down if the die temperature exceeds 150C with 10C of hysteresis. A heavy load on the 12OUT regulator when the 5V SMPS is in PSAVE will cause the VDD input to drop, browning out the regulator. If the output drops 0.8% from its nominal value, the 5V SMPS is forced out of PSAVE mode and into continuous conduction mode for several cycles. This recharges the bulk input capacitor on the VDD. The 12OUT linear regulator also has a current limit to prevent damage under short circuit conditions. If either SMPS output is more than 10% above its nominal value, both SMPS are latched off and synchronous rectifiers are latched on. To prevent the output from ringing too far below ground in a fault condition, a 1A Schottky diode should be placed across each output. Two different levels of undervoltage are detected. If the output falls 10% below its nominal output, the RESET# output is pulled low.If the output falls 25% below its nominal output following a start-up delay, both SMPS are latched off. Both of the latched fault modes persist until SHDN or ON3 is toggled or the V+ input is brought below 1V. Over-voltage protection is provided on the VDD input. If the VDD input is above 19V, an over-voltage is detected and a 10mA current shunt load is applied to VDD. The over-voltage threshold has a 0.5V hysteresis. Shutdown and Operating Modes Holding the SHDN pin low disables the SC1404, reducing the V+ input current to less than 10uA. When SHDN goes high, the part enters a standby mode where the VL regulator and VREF are enabled. Turning on either SMPS will put the SC1404 in run mode. May 2002 Semtech Corp. 10 www.semtech.com SC1404 POWER MANAGEMENT Functional Information SC1404 Startup Sequence Chart SEQ ON 3 ON 5 PRELIMINARY RESET# DESCRIPTION REF LOW LOW Follows 3.3V SMPS. Indep endant star t control mode. Both SMPSs off. REF LOW HIGH Low. 5V SMPS ON , 3.3V SMPS OFF. REF HIGH LOW Follows 3.3V SMPS. 3.3V SMPS ON , 5V SMPS OFF. REF HIGH HIGH Follows 3.3V SMPS. Both SMPSs on. GN D LOW X Low. Both SMPSs off. GN D HIGH HIGH/LOW High after both outp uts are in regulation. 5V star ts when ON 3 goes high. If ON 5= HIGH, 3V is on. IF ON 5 = LOW, 3V is off. VL LOW X Low. Both SMPSs off. VL HIGH HIGH/LOW High after both outp uts are in regulation. 3V star ts when ON 3 goes high. If ON 5 = HIGH, 5V is on. IF ON 5 = LOW, 5V is off. Applications Information maximum load. However, in order to speed up the output transient response, ripple current can be much higher. In this design, we are going to set the ripple current to be 40% of maximum load. So once the ripple voltage specification is determined, the capacitor ESR is chosen. The output ripple voltage is usually specified at +/ - 1% of the output voltage. Reference Circuit Design Introduction The SC1404 is a versatile dual switching regulator with fixed 5V and 3.3V outputs . In addition, there is an on-chip 5V linear regulator capable of supplying 50mAoutput current and a 12V linear regulator of 200mA. The SC1404 is designed for notebook applications but has applications where high efficiency, small package and low cost are required. For the reference circuit 3.3V switcher, we selected a maximum ripple voltage of 33mV. Choosing one 180uF, 4V Panasonic SP Polymer Aluminum Electrolytic Cap, of which ESR is 15 m , sets the maximum ripple current as follows: Design Guidelines IO = The schematic for the reference circuit is shown on page 22. The reference circuit is configured as follows: Switching Regulator 1 Switching Regulator 2 Linear Regulator 1 Linear Regulator 2 I O = 0.033 V = 2.2A 0.015 Checking to see if the maximum RMS current can be met by the SP cap. Vout1 = 3.3V @ 6A Vout2 = 5.0V @ 6A Vout3 = 12V, 200mA Vout3 = 5.0V @ 50mA IRMS = Designing the Output Filter I1 2 + I1 I2 + I2 2 3 I1 = - IO 2 I2 = + IO 2 Irms=0.635 A << Irms_rated=3.0A Before calculating the output filter inductance and output capacitance, an acceptable amount of output ripple current must be determined. The maximum allowable ripple current depends on the transient requirement of the power supply. Under normal situation, the ripple current is usually set around 10 to 20% of the May 2002 Semtech Corp. VO _ MAX ESR The output inductance can now be found by: LO = 11 (VIN _ NOM - VO) DNOM TS IO www.semtech.com SC1404 POWER MANAGEMENT Applications Information PRELIMINARY where Vin_nom=15V, Vo=3.3V, D=Vo/Vin_nom, Fs=300KHz, Ts=3.33uS and Io=2.2 A. Lo is then calculated to be 3.9uH. For the interest of this design, Lo is chosen to be 4.7uH for the 3.3V output. For the 5V output, a coupled inductor with 6.4uH primary (5V winding) inductance is used. Choosing Current Sense Resistor Since the SC1404 implements Virtual Current SenseTM, the external current sense resistor is not needed by the control loop. But it is required for cycle-by-cycle current limit. Cycle-by-cycle current limit is reached when the voltage across the current sense resistor exceeds 50mV nominal. Depending on the system requirement, this current limit can vary, it is usually 10 to 30% higher than the maximum load. Taking into consideration lower limit of the 50mV, the value of the current sense resistor can be calculated using the following equation: Vendor P/N VDS (V) ID ( A ) Rds(0n) @ 4.5V (ohm) Package Si4886DY 30 13 0.0135 so-8 IRF7413 30 13 0.011 so-8 FDS9412 30 7.9 0.036 so-8 STS12N F30L 30 12 0.0085 so-8 The following calculations are done to verify that the power dissipation of the main switch MOSFET is well within 1.86W, which is the maximum allowable power dissipation for the package. PTOTAL _ DISS = PCONDUCTION + PSWITCHING + PGATE PCONDUCTION = Rds ( on) IRMS 2 Dnom 40mV (min) RSENSE = IPK _ OC For a DC OC trip point between 8 to 12A, Rsense is chosen to be 5m . where Rds(on) = 0.01 @Tj=25 C and Vgs = 4.5V. In order to find Rds(on)@ Tj=100 C , use 1.40*Rds(on)@25 C . Therefore, Rds(on) @ Tj = 100 C is equal to 0.014 . Choosing the Main Switching MOSFET IRMS = ( Before choosing the main switch MOSFET, we need to know two critical parameters: voltage and current rating. In order to minimize the conduction loss, we recommend using the lowest Rds(on) for the same voltage and current rating. The maximum drain to source voltage of the switch MOSFET is mainly decided by the topology of the switcher. Since this is a buck topology, VDS _ MAX = VIN _ MAX = 21 V where IO _ MAX = 7.1A, I2 = IMAX - IO _ MAX = 4.9A and I1 = IMAX + 2 2 Dnom = PSWITCHING = 60mV = 11 A 5.5m According to the calculated voltage and current rating, Si4886DY, IRF7413, FDS9412 or STS12NF30L meets the requirement. The specs for these MOSFETs are listed in the table below. For the purpose of this exercise, STS12NF30L is chosen. Next step is to determine its power handling capability. Based on 85 C ambient temperature, 150 C junction temperature and 50 C /W thermal resistance, its power handling is calculated as follows: IPEAK = CRSS VIN 2 fS IOUT IG where Crss is the reverse transfer capacitance of the MOSFET; it is equal to 200pF for STS12NF30L, Ig is the gate driver current; it is equal to 1A for SC1404. And Vin_nom = 15V, fs = 300KHz. The switching loss is calculated to 81mW. And the gate loss is given by, PGATE = 1 CG V 2 fS 2 where Cg=11nF, V=5V and fs=300KHz. The gate loss is calculated to be 41mW. TJ = 150C; TA = 85C; JA= 50C/W So the total power dissipation is calculated to be 147mW and is well within the maximum power dissipation allowance of the MOSFET. No special heating sinking is required when laying out the MOSFET. TJ - TA 150 - 85 = = 1.30W JA 50 May 2002 Semtech Corp. VOUT VIN _ NOM The worst case conduction loss is calculated to be 25mW. And the switching loss of the MOSFET is given by, Applying a derating of 70%, a 30V MOSFET is used in the design. The peak current of the MOSFET is determined by PT = I 1 2 + I1 I 2 + I 2 2 ) Dnom 3 12 www.semtech.com SC1404 POWER MANAGEMENT Applications Information Information Applications PRELIMINARY 200 Designing the Loop 150 There are two aspects concerning the loop design. One is the power train design and the other is the external compensation design. A good loop design is a combination of the two. In the SC1404, the control-to-output/power train response is dominated by the load impedance, the effective current sense resistor, output capacitance, and the ESR of the output caps. The low frequency gain is dominated by the output load impedance and the effective current sense resistor. Inherent to Virtual Current SenseTM, there is one additional low frequency pole sitting between 100Hz and 1KHz and a zero between 15KHz and 25KHz. To compensate for the SC1404 is easy since the output of error amplifier COMP pin is available for external compensation. A traditional pole-zeropole compensation is not necessary in the design using SC1404. To ensure high phase margin at crossover frequency while minimizing the component count, a simple high frequency pole is usually sufficient. In the reference design below, single-pole compensation method is demonstrated. And the loop measurement results are compared to that obtained from the simulation model. Transient response is also done to validate the model. Also, to help speeding up the design process, a list of recommended output caps vs. compensation caps value is given in table I. 100 Phase (deg) 50 -50 -100 -150 -200 1.00E+02 1.00E+04 1.00E+05 Measured Control-to-Output gain & phase response (up to 100KHz) is plotted below. 50 40 30 Gain (dB) 20 10 0 -10 -20 -30 Given parameters: Vin = 19V, Vout = 3.3V @ 2.2A, Output impedance, Ro = 3.3V/2.2A = 1.5 , Panasonic SP cap, Co = 180uF, Resr = 15 m , Output inductor, Lo = 4.7uH Switching frequency, Fs = 300KHz -40 -50 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+04 1.00E+05 f (Hz) 200 150 Simulated Control-to-Output gain & phase response (up to 100KHz) is plotted below 100 50 Phase (deg) 50 40 Gain (dB) 1.00E+03 f (Hz) Single-Pole compensation Method . 0 0 30 -50 20 -100 10 -150 0 -200 -10 1.00E+02 1.00E+03 f (Hz) -20 -30 Single-pole compensation of the error amplifier is achieved by connecting a 100pF capacitor from the COMP pin of the SC1404 to ground. The simulated feedback gain & phase response (up to 100KHz) is plotted below. -40 -50 1.00E+02 1.00E+03 1.00E+04 1.00E+05 f (Hz) . May 2002 Semtech Corp. 13 www.semtech.com SC1404 POWER MANAGEMENT Applications Information PRELIMINARY 20 0 25 -20 20 -40 Phase (deg) 15 Gain (dB) 10 5 -60 -80 -100 -120 0 -140 -5 -160 -10 -180 1.00E+02 1.00E+03 -15 1.00E+02 1.00E+03 1.00E+04 1.00E+04 1.00E+05 Frequency (Hz) 1.00E+05 f (Hz) Simulated overall gain & phase responses (up to 100KHz) is plotted below. 0 -10 -20 80 60 -40 40 -50 20 -60 Gain (dB) Phase (deg) -30 -70 -80 0 -20 -90 -40 -100 1.00E+02 1.00E+03 1.00E+04 -60 1.00E+05 f (Hz) -80 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+04 1.00E+05 f (Hz) Measured feedback gain & phase responses (up to 100KHz) is plotted below. 180 25 160 20 140 15 120 Phase (deg) Gain (dB) 10 5 0 100 80 60 40 -5 20 -10 0 -15 -20 1.00E+02 1.00E+03 1.00E+04 1.00E+02 1.00E+05 f (Hz) f (Hz) May 2002 Semtech Corp. 1.00E+03 14 www.semtech.com SC1404 POWER MANAGEMENT Applications Information PRELIMINARY Table I. is useful only if the following ESR condition is satisfied. Measured overall gain & phase response of the single-pole compensation using SC1404 is plotted below. fO = fo > 50KHz 60 where Resr is the equivalent ESR of the total output caps. For instance, if two Panasonic SP cap 180uF, 15 m are used. The equivalent Resr = ESR(single)/2 = 7.5 m . Gain (dB) 25 The error amplifier compensation is set by the internal output resistance of the amplifier (25 Kohms typical) and the external impedance attached to the COMP pin. Connecting a single capacitor to the COMP pin places a R-C pole into the error amplifier. -10 -45 Transient response of the switcher using single-pole compensation is. shown below. The load steps from 0A to 3A and 3A to 0A. The applied di/dt is 0.3A/usec -80 1.00E+02 1 2 RESR C O 1.00E+03 1.00E+04 1.00E+05 1.00E+04 1.00E+05 f (Hz) 180 160 140 Phase (deg) 120 100 80 60 40 20 0 -20 1.00E+02 1.00E+03 f (Hz) Table I. R pensation cap ffor or dif Recommended compensation diffferent ecommended com output capacitance. Output Cap Recommended Compensation Cap Value <= 180uF 100pF >180uF & < 1000uF 200pF >1000uF 330pF May 2002 Semtech Corp. 15 www.semtech.com SC1404 POWER MANAGEMENT Applications Information PRELIMINARY Input Capacitor Selection/Out-of-phase Switching The SC1404 uses out-of-phase switching between the two converters to reduce input ripple current, enabling the use of smaller, cheaper input capacitors when compared to in-phase switching. The two approaches are shown in the following figures. As the input voltage is reduced, the duty cycle of both converters increases. For inputs less than 8.3 volts it is impossible to prevent overlap when producing 3.3V and 5V outputs, regardless of the phase relationship between the converters. This can be seen in the following figure. p e rio d p h a se le a d The first figure shows in-phase switching: I3in is the input current drawn by the 3.3V converter, I5in is the input current drawn by the 5V converter. The two converters start each switching cycle simultaneously, resulting in a significant amount of overlap. This overlap increases the peak current. The total input current to the converter is the third trace Iin, which shows how the two currents add together. The fourth trace shows the current flowing in and out of the input capacitors. I3 in I5 in Iin a ve ra g e In-phase Switching 0 I3 in 0 Ica p I5 in Iin From an input filter standpoint it is desirable to make the minimize the overlap, but it is also desirable to keep the turn-on and turn-off transitions of the two converters separated in time, otherwise the two converters may affect each other due to switching noise. The SC1404 implements this by changing the phase relationship between the converter depending on the input voltage. a ve ra g e 0 0 Icap Input voltage The next figure shows out-of-phase switching. Since the 3.3V and 5V converters are spaced apart, there is no resulting overlap. This results in a two benefits; the peak current is reduced and the frequency content is higher, both of which make filtering easier. The third trace shows the total input current, and the fourth trace shows the current in and out of the input capacitors. The RMS value of this current is significantly lower than the in-phase case and allows for smaller capacitors due to reduced RMS current ratings. Vin > 9.6 V 41% of switching period 9.6V > Vin > 6.7V 59% of switching period 6.7 > Vin 64% of switching period Vin > 9.6V: 3.3V turn-on leads 5V turn-on by 41% of the switching period. With Vin > 9.6V it is always possible to achieve no overlap, which minimizes the input ripple current. At Vin = 9.6V there is no overlap, but the 3.3V turn-on is nearing the 5V turn-off converter. Out-of-phase Switching I3 in 6.7 < Vin < 9.6V: 3.3V turn-on leads 5V turn-on by 59% of the period. To prevent the 3V turn-on from coinciding with the 5V turn-off (which could affect either output), the 5V pulse is delayed in time slightly such that the 3V turn-on occurs before the 5V turn-off. This creates a small overlap between the 3V turn-on and the 5V turn-off, with a resulting slight increase in RMS input ripple, but this is preferred since it greatly reduces noise problems caused by simultaneous transitions. Note that at Vin = 6.7, the 3V turn-off is nearing the 5V turn-on. I5 in a ve ra g e Iin Phase lead from 3V conver ter rising edge to 5V conver ter rising edge 0 0 Ica p May 2002 Semtech Corp. 16 www.semtech.com SC1404 POWER MANAGEMENT Typical Characteristics PRELIMINARY IF _ AVG = ILOAD where 100nsec is the estimated time between the MOSFET turning off and the Schottky diode taking over and Ts = 3.33uS. Therefore a Schottky diode with a forward current of 0.5A is sufficient for this design. Vin < 6.7 volts: 3.3V turn-on leads 5V turn-on by 64% of the period. The 5V turn-on is delayed slightly more to add separation between the 3V turn-off and 5V turn-on. This leads to more overlap, but at this point overlap is unavoidable. Operation below 6V input Input ripple current calculations: The following equations provide quick approximations for input ripple current: The SC1404 will operate below 6V input voltage with careful design, but there are limitations. The first limitation is the maximum available duty cycle from the SC1404, which limits the obtainable output voltage. The design should minimize all circuit losses through the system in order to deliver maximum power to the output. D3 = 3.3V duty cycle = 3.3/Vin D5 = 5V duty cycle = 5/Vin I3 = 3.3V load current I5 = 5V load current A second limitation with operation below 6V is transient response. When load current increases rapidly, the output voltage drops slightly; the feedback loop normally increases duty cycle briefly to bring the output voltage back up. If duty cycle is already near the maximum limit, the duty cycle cannot increase enough to meet the demand, and the output voltage sags more than normal. This problem can not be solved by changing the feedback compensation, it is a function of the input voltage, duty cycle, and inductor and capacitor values. Dovl = overlapping duty cycle of the 3V and 5V pulses, which varies according to input voltage: Vin > 9.6V: Dovl = 0 9.6V > Vin > 6.7V: Dovl = D5 - 0.41 6.7V > Vin Dovl = D5 - 0.36 Iin = D3 . I3 + D5 . I5 (average current drawn from Vin) Isw_rms = rms current flowing into 3V and 5V SMPS (Isw_rms)2 = Dovl . (I3 + I5)2 + (D3 - Dovl) . I32 + (D5 -Dovl) . I52 Irms_cap = 2 If an application requires 5V output from an input voltage below 6V, the following guidelines should be used: 2 1 - Set the switching frequency to 200 kHz (Tie SYNC to GND). This increases the maximum duty cycle compared to 300 kHz operation. Isw_rms + Iin The worst-case ripple current varies by application. For the case of I3 = I5 = 6A, the worst-case ripple occurs at Vin = 7.5V, at which point the rms capacitor ripple current is 4.2 amps. To handle this the reference design uses 4 paralleled ceramic capacitors, (Murata GRM32NF51E106Z, 10 uF 25V, size 1210). Each capacitor is rated at 2.2 Amps, allowing for derating at higher temperatures. 2 - Minimize the resistance in the power train. Select MOSFETs, inductor, and current sense resistor to provide the lowest resistance as is practical. 3 - Minimize the pcb resistance for all traces carrying high current. This includes traces to the input capacitors, MOSFETS and diodes, inductor, current sense resistor, and output capacitor. Choosing Synchronous MOSFET and Schottky diode Since this is a buck topology, the voltage and current ratings of the synchronous MOSFET are similar to the high-side MOSFET. It makes sense cost-volume-wise to use the same MOSFET for both the main switch and synchronous MOSFET. Therefore, STS12NF30L is used again in the design for synchronous MOSFET. To improve overall efficiency, an external schottky diode is used in parallel to the synchronous MOSFET. The freewheeling current goes into the schottky diode instead of the body diode of the synchronous MOSFET, which usually has very high forward drop and slow transient behavior. It is important when laying out the board to place both the synchronous MOSFET and Schottky diode close to each other to reduce the current ramp-up and ramp-down time due to parasitic inductance between the channel of the MOSFET and the Schottky diode. The current rating of the Schottky diode can be determined by the following equation. May 2002 Semtech Corp. 100n = 0.2A TS 4 - Minimize the resistance between the SC1404 circuit and the power source (battery, battery charger, AC adaptor). 5 - Use low ESR capacitors on the input to prevent the input voltage dropping during on-time. 6 - If large load transients are expected, high capacitance and low ESR capacitors should be used on both the input and output. 17 www.semtech.com SC1404 POWER MANAGEMENT PRELIMINARY 5V Start-up with slow Vin ramp. The following guidelines for 12V loading apply to the typical circuit, page 22. Proper startup of the 5V output can be hampered by slow dV/dt on the input. The SC1404 will power up and attempt to generate an output when the input voltage exceeds 4.5 volts. If the input has a slow dV/dt, the input voltage will not rise significantly during the start-up sequence, leading to two conditions. The VL supply can be hundreds of mV below 5V, since the input may not be above 5V. And, the duty cycle will be at maximum, leading to very small off-times. These two conditions tend to reduce the BOOST voltage; if continued indefinitely, the BOOST capacitor is unable to recharge fully, and eventually the high-side driver loses its BOOST bias. Vin range 12V load conditions >10V 12V load < 1/2 * 5V load 12V load = 200mA max 7V - 10V 12V load < 1/2 * 5V load Linearly derate 12V load: 200mA at 10V 100mA at 7V 6V - 7V 12V load < 1/2 * 5V load Linearly derate 12V load: 100mA at 10V 25mA at 7V To avoid this the following steps should be taken: 1. If possible the dV/dt of the input supply should exceed .02V/ usec. This dV/dt condition only applies when the input passes between 4 and 6 volts, the point at which the SC1404 begins a startup sequence. An alternative is to make sure the input voltage reaches 6 volts within 100 usec of SC1404 startup at approximately 4.2 volts. This is sufficiently fast to allow VL and duty cycle to achieve normal levels, which prevents the BOOST voltage from falling. PSAVE operation 2. If the dV/dt of the input cannot meet condition 1, the startup of the SC1404 should be delayed until the input voltage reaches 6V. This can be done using either the SHDN# or ON5 pin. If the dV/dt is moderate (slews from 4 to 6 volts in several msecs), an RC delay on either the SHDN# or ON5 pin should be enough to delay turn-on until the input reaches 6V. The SC1404 enters power-save operation if the load is sufficiently light, and if PSAVE is tied low. In PSAVE operation, the switching frequency is no longer fixed, and the converter operates as a hysteretic converter. This reduces gate drive losses and other switching losses to improve efficiency. Each converter willl enter or exit PSAVE operation independently, based on load current. The hysteresis on the 5V output is typically 70mV, and the 3V hysteresis is typically 35mV. 3. For slow dV/dt on the input (10's of msec), the SC1404 should be held off until the input reaches 6V. This can be done using a comparator or external logic to hold the SHDN# or ON5 pin low until the input reaches 6V. 12V Load Limitations The 12V regulator derives input power from a secondary winding on the 5V inductor. During the 5V off-time, the inductor transfers energy from the 5V winding to the secondary winding, thereby providing a crudely regulated 15V that feeds the 12V regulator. Note that duty cycle increases at low input voltages, and therefore the on-time decreases. At low input voltages, the duty cycle increases to maintain the 5V output. The off-time consequently decreases, which has two detrimental effects. It allows less time to recharge the raw 15V capacitor, and it also raises the peak 15V current required to maintain the average 12V load. The 15V winding needs higher peak current, delivered in less time. But the stray (leakage) inductance of the inductor resists rapid changes in winding current, and ultimately limits how much current can be drawn from 15V before the voltage falls. May 2002 Semtech Corp. 18 www.semtech.com SC1404 POWER MANAGEMENT PRELIMINARY Ov er age TTes es Over ervv olt oltage estt Measuring the overvoltage trip point can be problematic. Any buck converter with synchronous MOSFETS can act as a boost converter, sending energy from output to input. In some cases the energy sent to the input is enough to drive the input voltage beyond normal levels, causing input overvoltage. To prevent this, enable the SC1404 PSAVE# feature, which effectively disables the low side MOSFET drive so that little energy, if any, is transferred back to the input. SC1404 as replacement for MAX1632 The SC1404 can replace the MAX1632, if the pcb layout takes into account differences between the two parts. The SC1404 uses internal resistor dividers to set the output voltage rather than having dedicated feedback (FB) pins, as in the MAX1632, pins 3 and 12. The SC1404 then uses these pins as compensation pins for the feedback loop. This allows designers more freedom in selecting output filters. Semtech recommends the following circuit for measuring the overvoltage trip point. D1 prevents the output voltage from damaging lab supply 1. R1 limits the amount of energy that can be cycled from the output to the input. R2 absorbs the energy that might flow from output to input, and D2 protects lab supply from possible damage. The ON5 signal is monitored to indicate when overvoltage occurs. Pin 3, (FB3 of MAX1632) becomes COMP3 for the SC1404. Pin 12, (FB5 of MAX1632) becomes COMP5 for the SC1404. The same circuit is used to accomodate both pins. The circuit below applies to pin 3 (COMP3/FB3); the same circuit is used on pin 12 (COMP5/FB5), though the component values may differ. When using the SC1404, resistors R1 and R2 are not populated. COMP3 (pin 3) is a high-impedance circuit and can be affected by noise, so it is important to locate R1, R2, and C1 as close to the pin as possible, and to keep both the COMP3 and ground connections very short. If the MAX1632 is used in the adjustable output mode, R1 and R2 are installed and C1 is not populated. Normally only R2 or C1 would be populated, not both, so it is feasible to use only one pwb footprint to accomodate either component. If the MAX1632 is used in fixed-output mode, set a zero-ohm resistor in place of C1, and delete R1 and R2 from the design entirely. Initial conditions: Both lab supplies set to zero volts No load connected to 3V or 5V PSAVE# enabled (PSAVE# tied to GND) ON5 enabled ON3 enabled DVMs monitoring ON5 and the output under test. Oscilloscope probe connected to Phase Node of the output under test (not strictly required). Set lab supply 2 to provide 10V at the SC1404 input. The phase node of the output being tested should show some switching activity. The ON5 pin should be above 4V. Slowly increase lab supply 1 until the output under test rises slightly above it's normal DC level. As the input lab supply 1 increases, switching activity at the phase node will cease. The ON5 pin should remain above 4V. Increase lab supply 1 in very small increments, monitoring both ON5 and the output under test. The overvoltage trip point is the highest voltage seen at the output before ON5 pulls low (approximately 0.3V). Do not record the voltage seen at the output after ON5 has pulled low; when ON5 pulls low, the current flowing in D1 changes, corrupting the voltage seen at the output. D1 e.g. 1N4004 Lab Supply 2 R2 470 1/2W to DVM Output under test Vin SC1404 Evaluation Board D1 e.g. 1N4004 VL R1 75 1/2W 1K ON5 to DVM May 2002 Semtech Corp. Lab Supply 1 19 www.semtech.com SC1404 POWER MANAGEMENT Layout Guidelines PRELIMINARY Minimize the length of current sense signal trace. Keep it less than 15mm. Kevin connection should be used and try to keep the traces parallel to each other and have them close to each other as much as possible. Even though SC1404 implements Virtual Current Sense scheme, output signal is sampled by the SC1404 to determine the PSAVE threshold. See the following Fig. TBD for Kelvin connection for current sense signal hook up. As with any high frequency switching regulator design, a good PCB layout is very essential in order to achieve optimum noise, efficiency, and stability performance of the converter. Before starting to layout the PCB, a careful layout strategy is strongly recommended. See the PCB layout in the SC1404 Evaluation Kit manual for example. In most applications, we recommend to use FR4 with 4 or more layers and at least 2 oz copper (for output current up to 6A). Use at least one inner layer for ground connection. And it is always a good practice to tie signal ground and power ground at one single point so that the signal ground is not easily contaminated. Also be sure that high current paths have low inductance and resistance by making trace widths as wide as possible and lengths as short as possible. Properly decouple lines that pull large amounts of current in short periods of time. The following step by step layout strategy should be used in order to fully utilize the potential of SC1404. L1 SC1404 Step #1. Power train components placement. CSH CSL Rcs a. Power train arrangement. Place power train components first. Fig TBD. shows the recommended power train arrangement. Q1 is the main switching FET, Q2 is the synchronous Rectifier FET, D1 is the Schottky diode and L1 is the output inductor. The phase node, where the source of c. Gate Drive. SC1404 has built-in gate drivers capable of sinking/sourcing 1A pk-pk. Upper gate drive signals are noisier than the lower ones. Therefore, place them away from sensitive analog circuitries. Make sure the lower gate traces are as close as possible to the IC pins and both upper and lower gate traces as wide as possible. Q1 D1 Step #2: PWM controller placement (pins) and signal ground island. L1 Connect all analog grounds to a separate solid copper island plane, which connects to the SC1404's GND pin. This includes REF, COMP3, COMP5, SYNC, RUN/ON3, ON5, PSV# and RESET#. Q2 Step #3: Ground plane arrangement. There are several ways to tie the different grounds together. Analog Ground, Power Ground for the input side and Power Ground for the output side. Since this is a buck topology converter, the output is relatively quieter than the input side. That is where we choose to tie the analog ground to the power ground through a 0 resistor. The power ground for the input side and the power ground for the output side is the same ground and they can be tied together using internal planes. upper switching FET and the drain of the synchronous rectifier meets, since it switches at very high rate of speed, is generally the largest source of common-mode noise in the converter circuit. It should be kept to a minimum size consistent with its connectivity and current carrying requirements. Also place the Schottky diode as close to the phase node as possible to minimize the trace inductance, therefore reduce the efficiency loss due to the current ramp-up and down time. This becomes extremely important when converter needs to handle high di/dt requirement. b. Current Sense. May 2002 Semtech Corp. 20 www.semtech.com SC1404 POWER MANAGEMENT Typical Characteristics 3.3V Efficiency PRELIMINARY 6V 10V 19V Efficiency (%) 100 90 80 70 60 50 0.01 0.1 1 10 Load Current (A) 5V Efficiency 6V 10V 19V Efficiency (%) 100 95 90 85 80 0.01 0.1 1 10 Load Current (A) May 2002 Semtech Corp. 21 www.semtech.com SC1404 POWER MANAGEMENT Evaluation Board Schematic May 2002 Semtech Corp. PRELIMINARY 22 www.semtech.com SC1404 POWER MANAGEMENT Evaluation Board Bill of Materials PRELIMINARY IT E M QUAN TIT Y DESIGN ATION PART N UMBER DESCRIPTION MAN UFACTURER FORM FACTOR 1 4 C1,C2,C5,C6 GRM230Y5V106Z025 10uF, 25V 1210 2 1 C11 3 5 C10, C12, C21, C24, C29 ECJ-2YB1H104K 0.1uF,50V, X7R Panasonic 805 4 1 C9 Y475M250N 4.7uF, 25V N ovacap 1812 5 4 C3, C4, C15, C16 ECJ-2VF1H224Z 0.22uF,50V, Y5V Panasonic 805 6 2 C13, C14 ECJ1VC1H101K 100pF, 50V Panasonic 0603 7 3 C39, C40, C41 8 5 C27, C30, C31, C32, C33 ECJ1VB1C104K 0.01uF,50V Panasonic 0603 9 1 C28 ECJ3FB1C105 1uF, 16V Panasonic 1206 10 1 C17 EEF-UE0G181R 180uF, 4V Panasonic D_Case_7343 11 1 C19 EEF-UE0J151R 150uF, 6.3V Panasonic D_Case_7343 12 3 C34, C37, C38 ECJ2FB1A105K 1uF, 10V Panasonic 0805 13 1 D1 BAT54A 30V, 200ma, dual C_Anode Zetex SOT-23 14 4 D2,D3,D4,D5 MBRS140T3 40V, 1A Schottky Motorola SMB 15 7 D6, D7, D8, D9, D10, D11, D12 APTR3216 Sur face mount LED Kingbright 1206 May 2002 Semtech Corp. Murata 4.7uF, 20V B_case 10uF, 16V 23 1206 www.semtech.com SC1404 POWER MANAGEMENT PRELIMINARY IT E M QUAN TIT Y DESIGN ATION 16 8 JP1, JP2, JP3, JP4, JP5, JP6, JP7, JP8 2 Pin Berg Connector Berg 17 2 JP9, JP10 3Pin Berg Connector Berg 18 3 J1, J18, J19 Banana Jack Pair J2, J3, J4, J5, J9, J10, J11, J12, J13, J14, J15, J16, J17, J22, J23, J24 Test Points 19 PART N UMBER DESCRIPTION MAN UFACTURER FORM FACTOR 20 2 L1 SSLI306T-5R6M-S SMT Inductor 5.6uH Yageo/Act 21 4 Q1, Q2, Q3, Q4 IRF7413 30V N channel MOSFET International Rectifier SO8 22 6 Q5, Q6, Q7, Q8, Q9, Q10 MMBF170LT1 500mA, 60V N -channel FET On-Semiconductor SOT23 23 1 R1 Any 10ohm A ny 0603 24 2 R2, R3 WSL2512R010FB43 10mohm Vishay Dale 2512 25 2 R4, R5 Any 8.06Kohm A ny 0603 26 3 R6, R7, R31 Any 0ohm A ny 0603 27 2 R8, R9 WSL2512R005FB43 5mohm Vishay Dale 2512 28 5 R14, R15, R16, R17, R19 Any 2Megohm A ny 0603 29 1 R18 Any 1Kohm A ny 0603 30 31 32 May 2002 Semtech Corp. 24 www.semtech.com SC1404 POWER MANAGEMENT Evaluation Board Gerber Plots PRELIMINARY Inner2 To p Bottom Inner1 May 2002 Semtech Corp. 25 www.semtech.com SC1404 POWER MANAGEMENT Outline Drawing PRELIMINARY Land Pattern Contact Information Semtech Corporation Power Management Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 FAX (805)498-3804 May 2002 Semtech Corp. 26 www.semtech.com