MOTOROLA SEMICONDUCTOR TECHNICAL DATA High Slew Rate, Wide Bandwidth, Single Supply Operational Amplifiers Quality bipolar fabrication with innovative design concepts are employed for the MC33071/72/74, MC34071/72/74, MC35071/72/74 series of monolithic operational amplifiers. This series of operational amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/us slew rate and fast setting time without the use of JFET device technology. Although this series can be operated from split supplies, itis particularly suited for single supply operation, since the common mode input voltage range includes ground potential (VEE). With A Darlington input stage, this series exhibits high input resistance, low input offset voltage and high gain. The all NPN output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open-loop high frequency output impedance and symmetrical source/sink AC frequency response. The MC3307 1/72/74, MC3407 1/72/73, MC3507 1/72/74 series of devices are available in standard or prime performance (A Suffix) grades and are specified over the commercial, industrial/vehicular or military temperature ranges. The complete series of single, dual and quad operational amplifiers are available in the plastic, ceramic DIP and SOIC surface mount packages. Wide Bandwidth: 4.5 MHz High Slew Rate: 13 V/us Fast Settling Time: 1.1 us to 0.1% Wide Single Supply Operation: 3.0 V to 44 V Wide Input Common Mode Voltage Range: Includes Ground (Veg) Low Input Offset Voltage: 3.0 mV Maximum (A Suffix) Large Output Voltage Swing: -14.7 V to +14 V (with +15 V Supplies) Large Capacitance Drive Capability: 0 pF to 10,000 pF Low Total Harmonic Distortion: 0.02% Excellent Phase Margin: 60 Excellent Gain Margin: 12 dB Output Short Circuit Protection ESD Diodes/Clamps Provide Input Protection for Dual, and Quad ORDERING INFORMATION Op Amp Function Device Temperature Range Package Single MC34071P, AP Plastic DIP MC34071D, AD 0 to +70C SO-8 MC34071U, AU Ceramic DIP MC33071P, AP MC33071D, AD MC33071U, AU MC35071U, AU Dual MC34072P, AP Plastic DIP 40 to +85C SO-8 Ceramic DIP Ceramic DIP Plastic DIP SO-8 55 to +125C MC34072D, AD 0 to +70C MC34072U, AU Ceramic DIP MC33072P, AP Plastic DIP MC33072D, AD 40 to +85C So-8 MC33072U, AU Ceramic DIP MC35072U, AU 55 to +125C Ceramic DIP Quad MC34074P, AP Plastic DIP SO-14 MC34074D, AD 0 to +70C MC34074L, AL Ceramic DIP MC33074P, AP Plastic DIP MC33074D, AD 40 to +85C $0-14 MC33074L, AL MC35074L, AL Ceramic DIP Ceramic DIP 55 to +125C MC34071,2,4 MC35071,2,4 MC33071,2,4 1 1 P SUFFIX U SUFFIX PLASTIC PACKAGE CERAMIC PACKAGE CASE 626 CASE 693 D SUFFIX PLASTIC PACKAGE 1 CASE 751 (SO-8) PIN CONNECTIONS Offset Null [1] [8] NC (2] Voc Inputs { " b> 18] Output Vee [4] [5] Offset Null (Single, Top View) (Dual, Top View) Sen mn 14 1 1 P SUFFIX L SUFFIX PLASTIC PACKAGE CERAMIC PACKAGE CASE 646 CASE 632 D SUFFIX PLASTIC PACKAGE 14 CASE 751A (SO-14) PIN CONNECTIONS wi Output 1 [7] 114] Qutput 4 Ee | ha +e Inputs 1 (at Hy } inputs 4 Vec [4] 1] VEE Inputs 2 ao <s } Inputs 3 Output 2 [7] {8] Output 3 (Quad, Top View) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-284MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage (from Veg to Vcc) Vs +44 V Input Differential Voltage Range VIDR Note 1 Vv Input Voltage Range VIR Note 1 Vv Output Short Circuit Duration (Note 2) tsc Indefinite sec Operating Junction Temperature Ty C Ceramic Package +160 Plastic Package +150 Storage Temperature Range Tstg C Ceramic Package -65 to +160 Plastic Package 60 to +150 NOTES: 1. Either or both input voltages should not exceed the magnitude of Voc or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 1). Equivalent Circuit Schematic (Each Amplifier) e e e e e O Voc . 03 Q4 Q5 Qa a7 KO AOR an ey $a R6 | R7 4 Output at R8 C2 D3 }} aig Base 4013 Q14 Q15--~ Q16 Current Cancellation Q12 Current v DO mi RS Limit ; R3 R4 O I I Vee/Gnd Offset Null (MC33071, MC34071, MC35071 onty) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-285MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 ELECTRICAL CHARACTERISTICS (Vcc = +15 V, Veg =15 V, RL = connected to ground, unless otherwise noted. See [Note 3] for TA = Tiow to Thigh) A Suffix Non-Suffix Characteristics Symbol Min Typ Max Min Typ Max Unit Input Offset Voltage (Rg = 100 2, Voy =0V. Vo =0V) Vio _ mV Voc =+15V, Veg =-15 V. Ta = +25C a 0.5 3.0 _ 1.0 5.0 Voc = +5.0 V, Veg =O V. Ta = +25C 0.5 3.0 _ 15 5.0 Voc = +15 V, VEE =-15 V, Ta = Tiow 19 Thigh ~~ _ 5.0 _ 7.0 Average Temperature Coefficient of Input Offset Voltage | AV\Q/AT _ 10 _ _ 10 _ pvc Rg = 102, Vom=0V. Vo = OV, TA = Tiow t0 Thigh Input Bias Current (Von =0V. Vo = 0 V) lip nA Ta = +25C _ 100 500 _ 100 500 Ta = Tlow t0 Thigh _ 700 _ _ 700 Input Offset Current (Vc = 0 V. Vo = OV) re) nA Ta = +25C _ 6.0 50 _ 6.0 75 Ta = Tigw t0 Thigh _ _ 300 _ _ 300 Input Common Mode Voltage Range VICR Vv Ta = +25C VEE to (Voc -1.8) VEE to (Vcc ~1.8) TA = Tlow t0 Thigh VEE to (Vcc -2.2) VEE to (Vcc -2.2) Large Signal Voltage Gain (Vo = +10 V, RL = 2.0 kQ) AVOL VimV Ta = +25C 50 100 _ 25 100 _ Ta = Tlow to Thigh 25 _ _ 20 _ Output Voltage Swing (Vip = +1.0 V) VOH Vv Voc = +5.0 V, VEE = 0 V. RL = 2.0 kQ, Ta = +25C 3.7 4.0 _ 3.7 4.0 _ Voc = +15 V, Veg =-15 V, RL = 10 kQ, Ta = +25C 13.6 14 _ 13.6 44 _ Voc =+15 V, Veg =-15 V, RL = 2.0 kQ, 13.4 _ 13.4 _ TA = Tlow to Thigh Voc = +8.0 V. Veg = 0 V, RE = 2.0 kQ, Ta = +25C VOL _ 0.1 0.3 _ 0.1 0.3 v Veco = +15 V Veg =-15 V, RL = 10 kQ, Ta = +25C _ -14.7 | -14.3 _ 14.7 | -14.3 Voc = +15 V, Veg =-15 V, RL = 2.0 kQ, _ _ ~13.5 _ -13.5 Ta = Tlow t0 Thigh Output Short Circuit Current (Vip = 1.0 V. Vo =0V, Isc mA Ta = 25C) Source 10 30 _ 10 30 _ Sink 20 30 _ 20 30 _ Common Made Rejection CMR 80 97 _ 70 97 _ dB Rs = 100 kQ, Vom = Vicr. Ta = 25C Power Supply Rejection (Rg = 100 2) PSR 80 97 70 97 _ dB Voc/VEE = +16.5 V/-16.5 V to +13.5 V/-13.5 V, Ta = 25C Power Supply Current (Per Ampiifier, No Load) Ip mA Voc = +5.0 V, VEE = 0 V, Vo = +2.5 V, Ta = +25C 16 2.0 16 2.0 Voc = +15 V, Veg =-15 V, Vo = 0 V, Ta = +25C _ 19 25 _ 1.9 25 Voc =+15V. Veg =-15 V. Vo =O0V. _ _ 2.8 _ _ 2.8 Ta = Tow to Thigh NOTES: 3. Tigy = 55C for MC35071 2.4, /A = 40C for MC33071, 2. 4, /A = 0C for MC34071, 2, 4. /A Thigh = +125C tor MC35071. 2, 4, /A = +85C for MC33071, 2. 4, /A = +70C for MC34071, 2. 4, /A MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-286MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 AC ELECTRICAL CHARACTERISTICS (Vcc = +15 V, Veg =-15 V, RI = connected to ground Ta = +25C, unless otherwise noted.) A Suffix Non-Suffix Characteristics Symbol | Min Typ Max Min Typ | Max Unit Slew Rate (Vin = -10 V to +10 V, RL = 2.0 kQ, CL = 500 pF) SR Vins Ay = +1.0 8.0 10 | 80 10 Ay =-1.0 - 13 - 13 Setting Time (10 V Step, Ay =1.0) ts Hs To 0.1% (+1/2 LSB of 9-Bits) _ 1.1 _ ~~ 1.4 _ To 0.01% (+1/2 LSB of 12-Bits) _ 2.2 _ _ 2.2 _ Gain Bandwidth Product (f = 100 kHz) GBW 3.5 45 _ 3.5 45 _ MHz Power Bandwidth BW _ 160 _ - 160 _ kHz Ay = +1.0, Rl = 2.0 kQ, VQ = 20 Vp.p, THD = 5.0% Phase margin om Deg RL = 2.0 kQ 60 60 RL = 2.0 kQ, Cy = 300 pF 40 40 _ Gain Margin Am dB RL = 2.0 kQ 12 ~ 12 RL = 2.0 kQ, CL = 300 pF | 40 | | 40 | Equivaient Input Noise Voltage en _ 32 _ _ 32 _ nV/v Hz Rs = 100 Q f= 1.0 kHz Equivalent Input Noise Current in _ 0.22 _ _ 0.22 | pAHz f= 1.0 kHz Differential Input Resistance RIN _ 150 _ _ 150 _ MQ Vom =0V Differential Input Capacitance CIN _ 25 _ _- 2.5 _ pF Vom=0V Total Harmonic Distortion THD _ 0.02 _ - 0.02 _ % Ay = +10, RL = 2.0 kQ, 2.0 Vp-p <VQs20 Vp-p. f = 10 kHz Channel Separation (f = 10 kHz) _ _ 120 _ _ 120 _ dB Open-Loop Output Impedance (f = 1.0 MHz) IZol _ 30 _ _ 30 _ Q Figure 1. Power Supply Configurations Figure 2. Offset Null Circuit : : : Voc Singie Supply Split Supplies 3.0V 10 44V VoctVeEe|s44 V ] Vec h Vec Veo= a 1 ro o+f> 2> o 2 > bo L o+T> 3 > - of 3 >fe VEE 4>- VEE = ol 4 > bo Offset nulling range is approximately +80 mV with a 10 k L potentiometer (MC33071, MC34071, MC35071 onty). b VEE MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-287MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 Figure 3. Maximum Power Dissipation versus Temperature for Package Types 2400 2000 8 & 124 Pin Ceramic Pkg 1600 $0-14 Pkg 8 & 14 Pin Plastic Pkg 1200 $0-8 Pkg Pp, MAXIMUM POWER DISSIPATION (mW) 0 -55 -40 -20 0 20 40 60 80 100 120 140 160 Ta, AMBIENT TEMPERATURE (C) Figure 5. Input Common Mode Voltage Range versus Temperature Vcc Vcc = 41.5 V/-1.5 V to +22 V/ -22 V Voc -0.8 Voc -1.6 Voc -2.4 o.oo op Vee +0.01 VEE VEE y -55 -25 0 25 50 75 Ta, AMBIENT TEMPERATURE (C) 100 125 Figure 7. Normalized Input Bias Current versus Input Common Mode Voltage 1.4 Voc = +15V VEE =-15V Ta = 25C 1.2 1.0 0.8 ')p, INPUT BIAS CURRENT (NORMALIZED) 0.6 -12 -8.0 -4.0 0 40 8.0 Vic. INPUT COMMON MODE VOLTAGE (V) 12 ICR INPUT COMMON MODE VOLTAGE RANGE (V) > Figure 4. Input Offset Voltage versus Temperature for Representative Units Voc = +18 V Veg =-15V Vom =9 Vio, INPUT OFFSET VOLTAGE (mV) m m = o o o o I - a -25 0 25 50 75 Ta, AMBIENT TEMPERATURE (C) 100 125 Figure 6. Normalized Input Bias Current versus Temperature te Voc = +15V Veg=-15V Vem = 0 | jp. INPUT BIAS CURRENT (NORMALIZED) ee ts Ss Ny I n a -25 0 25 50 1 Ta, AMBIENT TEMPERATURE (C} 100 125 Figure 8. Split Supply Output Voltage Swing versus Supply Voltage 50 R,_ Connected to Ground Ta = 25C nN we a So So So Vo OUTPUT VOLTAGE SWING (Vp.p) o 0 5.0 10 15 Voc. Vee|, SUPPLY VOLTAGE (v) 20 25 MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-288MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 Figure 9. Split Supply Output Saturation Figure 10. Single Supply Output Saturation versus Load Current versus Load Resistance to Ground Vv r 1 r r + Vv ad KT voovee=150W/-50Vtow2vi-zv | = VOC T Ty = 25C = 8 3 < ~. < 5 Vcc -1LO SS Voc -20 > 2 Source = Z 2 Voc -2.0 2vcc -40 z [| J] Ij 4 = & Ee & VEE +2.0 GB 02 & Ee > 2 a oa 3 VEE +1.0 3 04 3 ee E > VEE > 0 0 5.0 10 15 20 100 1.0k 10k 100k IL, LOAD CURRENT (+mA) Ry, LOAD RESISTANCE TO GROUND (82) Figure 11. Single Supply Output Saturation Figure 12. Output Short Circuit Current versus Load Resistance to Vcc versus Temperature S 60 3 3 g eB ac 3 & E =< > nm a 5 5 20 p o Voc = +168 V 3 B 19 Vep=-15V = - RL S010 # AVin = 1.0 V > 0 100 1.0k 10k 100k -5 = -25 0 25 50 % 100 125 RL, LOAD RESISTANCE TO Voc (Q) Ta, AMBIENT TEMPERATURE (C) Figure 14. Output Voltage Swing Figure 13. Output Impedance versus Frequency versus Frequency 50 Voc = +15 V = _ cc=+ S Voc = +15V ee 40 = Veg =-15V to 3 Ay =+1.0 8 5 RL=2.0k S 30 H THD < 1.0% w w Ta = 25C 2 5 2 8 3 Ay = 100 Ay =10 Ay=1 5 & S 10 3 a 0 1.0k 10k 100 1.0M 10M 3.0k 10k 30k 100k 300k 10M 30M {, FREQUENCY (Hz) f, FREQUENCY (Hz) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-289MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 Figure 16. Output Distortion versus Figure 15. Output Distortion versus Frequency Output Voltage Swing Ay = 1000 _ Voc = +18 V z : g vee IY Z 03 5B 3.0 L=2 S 2 Ta = 25C & Voc = +15V x : Vea : a 02 RL=20k a z Ta = 25C = 2 3 2 04 es 1.0 2 = z= - 10 100 1.0k 10k 100k 0 4.0 8.0 12 16 20 f, FREQUENCY (Hz} Vg, OUTPUT VOLTAGE SWING (Vp_p) Figure 17. Open-Loop Voltage Gain Figure 18. Open-Loop Voltage Gain and versus Temperature Phase versus Frequency = a $ g = Voc = +t5V 2 a Be ver = -15V & iB wW Vo= -10V to +10 W 5S 5 108 | RL = t0k 5 o 2 t< 10Hz 2 wi o a 2 3 104 8 = 3 z Vec= +15V eB a Zz CC = 135 3 a a Veg = -15V g 100 o Vo=0V a S 3S Rp =2.0k tao > z Zz | T= 25C 96 55 = -25 0 25 50 75 100 125 10 10 100 10k 10k 100k 1.0M 10M 100M Ta, AMBIENT TEMPERATURE (C) t, FREQUENCY (Hz) Figure 19. Open-Loop Voltage Gain and Figure 20. Normalized Gain Bandwidth 9 Pp P ig Phase versus Frequency Produt versus Temperature a TTT B 1.15 T a 1 = = Se Phase 100 = = ~ Veco = +18V 2 ifs TS Margin = 60 z Vie e 1 v4 = 10 < = ei EE=-15 a 20IN Gain 4 120 i Zz Re =2.0k 2 4 Sty Margin = 12 dB __| = 5 105 MN 3 1408 3 a. -10 N PN w =F 40 9 1. Phase Ri = 2.0k EY SQ 1602 2 Zo 2. Phase RL = 2.0k, CL = 300 pF RK NSA a 5 KN G&G ~"| 3. Gain Ry = 2.0 k N VN 2 = 0.95 J 5 4, Gain RL = 2.0 k, CL = 300 pF TK 180 4 3 ~~ 3 -30| Voo=+18V N + _M aj S 09 < S| Vee=15V aN 6 2 Vg=0V Ta = 25C \ \ 3 08s "1.0 20 3.0 5.0 70 10 20 30 s 65-25 0 25 50 75 100 125 f, FREQUENCY (MHz) Tg, AMBIENT TEMPERATURE (C) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-290PERCENT OVERSHOOT Am, GAIN MARGIN (dB) Am, GAIN MARGIN (dB) MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 Figure 21. Percent Overshoot versus Load Capacitance Voc = +15 V Vee =-15V RL =2.0k Vo = -10V to +10 = 25C 10 100 1.0k C,, LOAD CAPACITANCE (pF} 10k Figure 23. Gain Margin versus Load Capacitance Voc = +15V Veg =-15V Ay =+1.0 Ri = 2.0 k to 9 Vo = -10 Vto +10 Ta = 25C 10 400 1.0k C1, LOAD CAPACITANCE (pF) 10k Figure 25. Gain Margin versus Temperature = +15V Cy = 10 pF Vee = -15V Ay=+1.0 RL =2.0k to 0 =-10Vto +10V = 100 pF CL = 10,000 pF C_ = 1,000 pF -55 -25 0 35 50 5 Ta, AMBIENT TEMPERATURE (C) 100 125 Figure 22. Phase Margin versus Load Capacitance ~ o Voc= +15V Veg = -15V Ay =+1.0 RL = 2.0k to 2 Vo = -10V to +10 Ta = 25C $m: PHASE MARGIN (DEGREES) 8s $s 8&8 & 8 = o o 10 400 C1, LOAD CAPACITANCE (pF) 1.0k 10k Figure 24. Phase Margin versus Temperature 80 a = 10F 60 Wu 2 5 Vv 15V oO CC= +t = 40 Veg = -15V = Ay=+1.0 Q Ry = 2.0 k to co Eo = 1,000 pF _ Vo =-10Vto +10 s Oy = 10,000 pF 0 -25 9 25 50 i) Ta, AMBIENT TEMPERATURE (C) 100 125 Figure 26. Phase Margin and Gain Margin versus Differential Source Resistance _ nN ~ So a 10 60 iB 80 h 50 z 1 V Qa Ss o z = 6.0 8 Re z 3 F Voc= +15V 30 - Veg =-15V 3 20 Rr = Ry + Re 20 = Ay = +100 = 0 10 @ Vo =0V Ta = 25C 1.0 10 Fry, DIFFERENTIAL SOURCE RESISTANCE (2) o 100 1.0k 10k 3 MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-291MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 Figure 27. Normalized Slew Rate versus Temperature 1.15 T ~ Voc = +15 V a 1A Vep=-15V 3 Ay =+1.0 RL = 2.0k = 5 105 ~~ CL = 500 pF wi 10 PNY & ac qj 0.95 > wn & 09 0.85 -55 -25 25 75 100125 Ta, AMBIENT TEMPERATURE (C) Figure 29. Smail Signal Transient Response = $ = Oo wo 2.0 us/DIV Figure 31. Common Mode Rejection versus Frequency _ 100 T T T gs LJ Ta = 125C Vec= +15V | z Ta = 25C oo VEE =-15V = 80 + Vom =0V 4 @ | _ Ta=-55C AVom=#1.5V _ | a = 60 fa) = z 3 \ Q X\ ~ NX = NM 6 XQ 01 10 10 100 10k 100k 1.0M 10M f, FREQUENCY (Hz) Figure 28. Output Settling Time = o gs oa A Vg , OUTPUT VOLTAGE SWING FROM 0 V (V) I S ~ Qo o 0.5 10 15 ts, SETTLIN Vec= +15V Vee =-15V Ay=-1.0 Ta = 25C Uncompensated ~ 2.0 25 3.0 3.5 G TIME (us) Figure 30. Large Signal Transient Reponse 1.0 ps/DIV Figure 32. Power Supply Rejection versus Frequency S So a IN Voc= +15V | = i! Vee =-15V 3 80 A Ta = 25C J 5 +PSR| | | % 60 (AVcc = +1.5 V) c O AV N 3 N a 40 0 NEE [AN \ \ A \ & | sPSR=20L0g | ANo/AoM N\ XX y \ Veo NOY & 20F / \ a? -PSR=20Log { SVO/ADM | -pse \ \ Eg \ AVEE / (AVeE = +15 7) XY 0 : 1 1 0.1 1.0 10 100 10k 10k 100k 10M 10M f, FREQUENCY (Hz) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-292MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 Figure 34. Power Supply Rejection Figure 33. Supply Current versus Supply Voltage versus Temperature 9.0 105 T T | _ = -PSR (AVER=+1.5V) Voo= +15V 80 3 A Po VEE=-15V - QO 95 i a ey ~~ J i rt A AV eo = +1.5 VY} DSS ce 70 / +PSR (AVcc = +1.5 Vy SN = > 5 = 95 5 a | I & 60 a AVo/ADM a c +PSR = 20 Log ( ) 3S = 75 AVEC O AVo 50 = AVoIAp - 5 M a ~PSR = 20 = O Vee | 2 29 ( AVEE ) | | 40 65 1 1. 1 1 0 5.0 10 15 20 25 55 = -25 0 25 50 75 100 125 Vcc; Vee}, SUPPLY VOLTAGE (V) Ta, AMBIENT TEMPERATURE (C) Figure 35. Channel Separation versus Frequency Figure 36. Input Noise versus Frequency 120 _ 2.8 2 = +15V in @& 100} Voc= +15V e 24 [5 2 VEE = -15V z a Ss = 25C wD 2.0 _ = 80 S 2 <x Ww Fs 5 16 = = 3 Se ty 60 = a a 2 1.2 w 2 40 zc Current 08 2 2 Bos ~ 20 2 o4 = = 0 0 10 20 30 50 70 100 200 300 10 100 1.0k 10k 100 k f, FREQUENCY (kHz) f, FREQUENCY (kHz) APPLICATIONS INFORMATION CIRCUIT DESCRIPTION/PERFORMANCE FEATURES Although the bandwidth, slew rate, and settling time of the maximum rating table. In practice, although not MC34071 amplifier series are similar to op amp products utilizing JFET input devices, these amplifiers offer other additional distinct advantages as a result of the PNP transistor differential input stage and an all NPN transistor output stage. Since the input common mode voltage range of this input stage includes the Veg potential, single supply operation is feasible to as low as 3.0 V with the common mode input voltage at ground potential. The input stage also allows differential input voltages up to +44 V, provided the maximum input voltage range is not exceeded. Specifically, the input voltages must range between VEE and Vcc supply voltages as shown by the recommended, the input voltages can exceed the Vcc voltage by approximately 3.0 V and decrease below the VEE voltage by 0.3 V without causing product damage, although output phase reversal may occur. !t is also possible to source up fo approximately 5.0 mA of current from VEE through either inputs clamping diode without damage or latching, although phase reversal may again occur. If one or both inputs exceed the upper common mode voltage limit the amplifier output is readily predictable and may be in a low or high state depending on the existing input bias conditions. MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-293MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 Since the input capacitance associated with the small geometry input device is substantially lower (2.5 pF) than the typical JFET input gate capacitance (5.0 pF), better frequency response for a given input source resistance can be achieved using the MC34071 series of amplifiers. This performance feature becomes evident, for example, in fast settling D-to-A current to voltage conversion applications where the feedback resistance can form an input pole with the input capacitance of the op amp. This input pole creates a 2nd order system with the single pole op amp and is therefore detrimental to its settling time. In this context, lower input capacitance is desirable especially for higher values of feedback resistances (lower current DACs). This input pole can be compensated for by creating a feedback zero with a capacitance across the feedback resistance, if necessary, to reduce overshoot. For 2.0 kQ of feedback resistance, the MC34071 series can settle to within 1/2 LSB of 8 bits in 1.0 ys, and within 1/2 LSB of 12-bits in 2.2 ys for a 10 V step. In a inverting unity gain fast settling configuration, the symmetrical slew rate is +13 V/us. In the classic noninverting unity gain configuration the output positive slew rate is +10 V/us, andthe corresponding negative slew rate will exceed the positive slew rate as a function of the fall time of the input waveform. Since the bipolar input device matching characteristics are superior to that of JFETs, a low untrimmed maximum offset voltage of 3.0 mV prime and 5.0 mV downgrade can be economically offered with high frequency performance characteristics. This combination is ideal for low cost precision, high speed quad op amp applications. The all NPN output stage, shown in its basic form on the equivalent circuit schematic, offers unique advantages over the more conventional NPN/PNP transistor Class AB output stage. A 10 kQ load resistance can swing within 1.0 V of the positive rail (Vcc), and within 0.3 V of the negative rail (VEE), providing a 28.7 Vp-p swing from +15 V supplies. This large output swing becomes most noticeable at lower supply voltages. The positive swing is limited by the saturation voltage of the current source transistor Q7, and VBE of the NPN pull up transistor Q17, and the voltage drop associated with the short circuit resistance, R7. The negative swing is limited by the saturation voltage of the pull-down transistor Q4g, the voltage drop ILRg, and the voltage drop associated with resistance R7, where I, is the sink load current. For smalt valued sink currents, the above voltage drops are negligible, allowing the negative swing voltage to approach within millivolts of Veg. For large valued sink currents (>5.0 mA), diode D3 clamps the voltage across Rg, thus limiting the negative swing to the Saturation voltage of Q16, plus the forward diode drop of D3 (VEE +1.0 V). Thus for a given supply voltage, unprecedented peak-to-peak output voltage swing is possible as indicated by the output swing specifications. If the load resistance is referenced to Vcc instead of ground for single supply applications, the maximum possible output swing can be achieved for a given supply voltage. For light load currents, the load resistance will pull the output to Voc during the positive swing and the output will pull the load resistance near ground during the negative swing. The load resistance value should be much less than that of the feedback resistance to maximize pull up capability. Because the PNP output emitter-follower transistor has been eliminated, the MC34071 series offers a20 mA minimum current sink capability, typically to an output voltage of (VEE +1.8 V). In single supply applications the output can directly source or sink base current from a common emitter NPN transistor for fast high current switching applications. In addition, the all NPN transistor output stage is inherently fast, contributing to the bipolar amplifiers high gain bandwidth product and fast settling capability. The associated high frequency low output impedance (30 Q typ @ 1.0 MHz) allows capacitive drive capability from 0 pF to 10,000 pF without oscillation in the unity closed-loop gain configuration. The 60 phase margin and 12 dB gain margin as well as the general gain and phase characteristics are virtually independent of the source/sink output swing conditions. This allows easier system phase compensation, since output swing will not be a phase consideration. The high frequency characteristics of the MC34071 series also allow excellent high frequency active filter capability, especially for low voltage single supply applications. Although the single supply specifications is defined at 5.0 V, these amplifiers are functional to 3.0 V @ 25C although slight changes in parametrics such as bandwidth, slew rate, and DC gain may occur. If power to this integrated circuit is applied in reverse polarity or if the IC is installed backwards in a socket, large unlimited current surges will occur through the device that may result in device destruction. Special static precautions are not necessary for these bipolar amplifiers since there are no MOS transistors on the die. As usual with most high frequency amplifiers, proper lead dress, component placement, and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted input-output coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole for optimum frequency response, but also minimizes extraneous pick up at this node. Supply decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. The output of any one amplifier is current limited and thus protected from a direct short to ground. However, under such conditions, it is important not to allow the device to exceed the maximum junction temperature rating. Typically for +15 V Supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating. MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-294MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 TYPICAL SINGLE SUPPLY APPLICATIONS Vcc = 5.0 V Figure 37. AC Coupled Noninverting Amplifer Figure 38. AC Coupled inverting Amplifier f 100k i , |____ 71 Mca4o Co Yo 68k MC34071 = cj Vo - Co Vin | 100k 10k 6, A Ri L Vin 370mVp.p 1 1.0k Ay = 101 Ay = 10BW (-3.0dB) = 450 kHz = _ BW(-3.0dB)=45kHz = Figure 39. DC Coupled Inverting Amplifer Maximum Output Swing | 2.5V MC54/74XX MC34071 0 0 to 10,000pF __, Figure 40. Unity Gain Buffer TTL Driver F 4.75Vp-p 0 Voc . _ Vin 91k f 51k Cable TTL Gate 4 RL 5.1k MC34071 = ANA PN] 100k f Vo 1.0M AWA Vj Ay = 10 = = = BW (-3.0dB} = 450 kHz f } Figure 42. Active Bandpass Filter Figure 41. Active High-Q Notch Filter Vin 2 0.2 Vde Mcs4071 Vo R R Vin 7 16k 16k Cc oor] Given fp = Center Frequency Ao = Gain at Center Frequency fo = 1.0 kHz Choose Value fo, Q, Ap, C ra= 7. pts SB pg. AUR gok 2 20R Then: ToC 2Ho 402R1-R3 1 L_ | o= GRAC For less than 10% error from operational amplifier Where fy and GBW are expressed in Hz. GBW = 4.5 MHz Typ. MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-295MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 Figure 43. Low Voltage Fast D/A Converter Figure 44. High Speed Low Voltage Comparator " : l, = 5 RF 5.0k 5.0k 5.0k MC34071 Vo 10k 10k 10k Vec wif f Switches | = 1 (R-2R) Ladder Net- a7 work fot Settling Time 1.08 (8-Bits, 1/2 LSB) Figure 45. LED Driver Figure 46. Transistor Driver Vcc Voc 47 ON Voc 14 Vin < Vref RL MC34071 Mc34071 MC34071 Vin br + ar ON (A) PNP (B) NPN cw Nin? Veet Figure 47. AC/DC Ground Current Monitor Figure 48. Photovoltaic Cell Amplifier lLoad Rr MC34071 MC34071 | + | 4 5 Vo call Vo Ground Cur- Rs (4) = rent Sense Resistor YR + R1\ Vell = OV =l ell L oe Load AST pp Vo = Ice RF For Vg > 0.1V Vo>01V R2 \ BW ( -3.0 dB) = caw one) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-296MC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 Figure 49. Low Input Voltage Comparator with Hysteresis Vo Hysteresis R2 A al Viet RY MC34071 Vou |- 7 + | VOL o - Vj n Vink VinH Vv Vink = So<n3 sR (VoL-Vretl+Vret ref Vin = py im (VoH-Vref)+Vret VH= = Ri Rien (VoH -Vou) Figure 51. High Imput Impedance Differential Amplifier Ri R2 1/2 MC34072 Vo ry. = ee {Critical to CMBR) R4 vont (v2 RE) (vew Bt ) For (V2 an V>0 Figure 53. Low Voltage Peak Detector Vin MC34071 Oo Vo = Vin (pk} > >_e"_0 osc = 2% RC Figure 50. High Compliance Voltage to Sink Current Converter | tout Vin MC34071 Figure 52. Bridge Current Amplifier +Vret Re MC34071 Vo Va=V AR Re O= Vref 2 AR<<R 2R Re >>R = (Vg 20.1V) Figure 54. High Frequency Pulse Width Modulation Vv +Aig + ~~ Ise v7 YP og t t - Base Charge Removal 85 Pulse Width = Control Group Comparator High Current Output 100k Vp MOTOROLA LINEAR/INTERFACE ICs DEVICE DATAMC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 GENERAL ADDITIONAL APPLICATIONS INFORMATION Vg = +15.0 V Figure 55. Second Order Low-Pass Active Filter iI ware 0.02 $v "+4 R2 Ri R3 5.6K 560 510 PN o fo = 1.0 kHz , | mc34071 Ho = 10 = = Choose: fp, Ho, C2 Then: Ct = 262 (Hp#t) V2 Ra at. F2 ~ ArigC2 RS = Ho#1 Ho Figure 57. Fast Settling Inverter BF | | Vo = 10V R Step $4 2.0k MC34071 q Lovo ! | = Uncompensated { tg= 10s fo 1/2 LSB (8-Bits) ts = 2.2 ps High Speed DAG Compensated *| 19 1/2 LSB (12-Bits) *Optional Compensation SR = 13 Vis Figure 59. Basic Noninverting Amplifier MC34071 PN Vin me WO _(1, f) = Vin R1 Ai | BW (-3.0 dB) = GBW l At A Figure 56. Second Order High-Pass Active Filter MC34071 Ci bo 1.0 Re fg = 100 Hz 11k Hy = 20 che { He Then: at = 0408 00S: Ty, 1 in: = one nigCtV2 pow ?2 2mtgC1 (WHy+2) c . & C= 4 Figure 58. Basic Inverting Amplifier MC34071 RD Yo RL Vin R2 = = Vo _ Re Rt Vin Rt BW (3048) = GBW Pa SR = 13 Vius Figure 60. Unity Gain Buffer (Ay = +1.0) MC34071 VinO + >_O Vo BWp = 200 kHz Vg =20 Vp-p SR = 10 Vis MOTOROLA LiINEAR/INTERFACE ICs DEVICE DATAMC34071, 34072, 34074/MC35071, 35072, 35074/MC33071, 33072, 33074 Figure 61. High Impedance Differential Amplifier MC34074 o+ a R R AW . MC34074 bn ton R + MC34074 | ORY Example: Let: R = Re = 12k R o+ R Then: Ay = 3.0 Aye} 142 BW = 1.5 MHz Figure 62. Dual Voltage Doubler +Vo MC34074 100k +10 MC34074 a L 220pF = T 100k = MC34074 RL +VO -Vo & 100 co | 18.93 | -18.78 1 10k 18 -18 Vg 5.0k 15.4 -15.4 MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 2-299