CY24130
HOTLink II™ SMPTE Receiver Training
Clock
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-07711 Rev. *A Revised May 22, 2008
Features
■Integrated phase-locked loop
■Low-jitter, high-accuracy outputs
■3.3V opera ti o n
Benefits
■Internal PLL with up to 400-MHz internal operation
■Meets critical timing requirements in complex system
designs
■Enables application compatibility
Table 1. Frequency table
Part Number Outputs Input Frequency Output Frequency Range
CY24130-1 2 27 MHz (Driven Reference) 1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
CY24130-2 2 27 MHz (Crystal Reference) 1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
XIN
XOUT
OUTPUT
MULTIPLEXER
AND
DIVIDERS
PLL
OSC.
CLKA
Q
P
VCO
VDDL AVSS
Φ
AVDD VSS
S0
S1
REFCLK
S2
VDD VSSL
Logic Block Diagram
Table 2. Frequency Select Options
S2 S1 S0 CLKA REFCLK Units
0 0 0 27 27 MHz
0 0 1 36 27 MHz
0 1 0 54 27 MHz
0 1 1 148.50 27 MHz
100 74.25 27MHz
1 0 1 OFF, pulled low 27 MHz
1 1 0 OFF, pulled low 27 MHz
1 1 1 OFF, pulled low 27 MHz
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CY24130
Document #: 38-07711 Rev. *A Page 2 of 6
Pin Configuration
Figure 1. CY24130-1, -2, 16-pin TSSOP
Table 3. Pin Definition
Name Pin Number Description
XIN 1 Reference Crystal Input.
VDD 2 Voltage Supply.
AVDD 3 Analog Voltage Supply.
S0 4 Frequency Select 0.
AVSS 5 Analog Ground.
VSSL 6 VDD L Ground.
N/C 7 No Connect.
CLKA 8 27-/36-/54-/148.50-/74.25-MHz Clock Output (frequency selectable).
N/C 9 No Connect.
S1 10 Frequency Select 1.
VDDL 11 Voltage Supply.
N/C 12 No Connect.
VSS 13 Ground.
REFCLK 14 Reference Clock Output.
S2 15 Frequency Select 2.
XOUT 16 Reference Crystal Output. Leave floating for -1.
Absolute Maximum Conditions
Parameter Description Min. Max. Unit
VDD, AVDD Supply Voltage –0.5 7.0 V
VDDL I/O Supply Voltage – 7.0 V
TJJunction Temperature – 125 °C
Digital Inputs AVSS – 0.3 AVDD + 0.3 V
Electro-Static Discharge 2 – kV
Recommended Operating Conditions
Parameter Description Min. Typ. Max. Unit
VDD/AVDDL/VDDL Operating Voltage 3.135 3.3 3.465 V
TAAmbient Temperature 0 – 70 °C
CLOAD Max. Load Capacitance – – 15 pF
fREF Reference Frequency – 27 – MHz
CLNOM Nominal Parallel Crystal Load
Capacitance for -2 –18
–pF
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VSS
VSSL
S1
XIN XOUT
VDD
S0
AVSS
N/C
S2
REFCLK
AVDD
VDDL
N/C
N/C
CLKA
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CY24130
Document #: 38-07711 Rev. *A Page 3 of 6
Figure 2. Test and Measurement Setup
Volt age and Timing Definitions
Figure 3. Duty Cycle Definitions
Note
1. Not 100% tested.
DC Electrical Specifications
Parameter[1] Name Description Min. Typ. Max. Unit
IOH Output High Current VOH = VDD – 0.5, VDD/VDDL = 3.3V 12 24 – mA
IOL Output Low Current VOL = 0.5, VDD/VDDL = 3.3V 12 24 – mA
IIH Input High Current VIH = VDD –510μA
IIL Input Low Current VIL = 0V – – 10 μA
VIH Input High Voltage CMOS levels, 70% of VDD 0.7 – – V
VIL Input Low Voltage CMOS levels, 30% of VDD ––0.3V
IVDD Supply Current AVDD/VDD Current –16–mA
IVDDL Supply Current VDDL Current – 14 – mA
AC Electrical Specifications
Parameter[1] Name Description Min. Typ. Max. Unit
DC Output Duty Cycle Duty Cycle is defined in Figure 3; t1/t2, 50% of
VDD 45 50 55 %
ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to
80% of VDD, CLOAD = 15 pF. See Figure 4.0.8 1.4 – V/ns
EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to
20% of VDD, CLOAD = 15 pF. See Figure 4.0.8 1.4 – V/ns
t9Clock Jitter CLKA Peak-Peak Period Jitter – 100 – ps
t10 PLL Lock Time – – 3 ms
0.1
μ
F
V
DDs
Outputs
C
LOAD
GND
DUT
Clock
Output
VDD
50% of VDD
0V
t1
t2
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CY24130
Document #: 38-07711 Rev. *A Page 4 of 6
Figure 4. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4
Ordering Information
Ordering Code Package Type Operating Range Operating Voltage
Pb-free
CY24130ZXC-1[2] 16-Pin TSSOP Commercial 3.3V
CY24130ZXC-1T[2] 16-Pin TSSOP – Tape and Reel Commercial 3.3V
CY24130ZXC-2[2] 16-Pin TSSOP Commercial 3.3V
CY24130ZXC-2T[2] 16-Pin TSSOP – Tape and Reel Commercial 3.3V
CY24130KZXC-1 16-Pin TSSOP Commercial 3.3V
CY24130KZXC-1T 16-Pin TSSOP – Tape and Reel Commercial 3.3V
Clock
Output
t3t4
VDD
80% of V DD
20% of VDD
0V
Note
2. Not recommended for new design.
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CY24130
Document #: 38-07711 Rev. *A Page 5 of 6
Package Drawing and Dimensions
Figure 5. 16-lead TSSOP 4.40 MM Body Z16.173
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Document #: 38-07711 Rev. *A Revised May 22, 2008 Page 6 of 6
MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY24130
© Cypress Semicondu ctor Corpor ation, 2005-2008. The informatio n contai ned herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre s s pro d ucts are n ot war ran ted no r int end ed to be us ed for
medical, life supp or t, l if e savin g, cr it ical control or safety ap pl i cat ions, unless pursuan t to a n exp re ss wr itten agreement with Cypress. Furthermore, Cyp ress doe s not auth ori ze i t s products for use as
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Document Title: CY24130 HOTLink II™ SMPTE Receiver Training Clock
Document Number: 38-07711
REV. ECN NO. Orig. of
Change Submission
Date Description of Change
** 314514 RGL See ECN New Data Sheet
*A 2442066 AESA See ECN Updated template. Added Note “Not recommended for new designs.”
Added part number CY24130KZXC-1, and CY24130KZXC-1T in ordering
information table.
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