128-Mbit 1.8 Volt Intel(R) Wireless Flash Memory (W18) + 32-Mbit PSRAM Stacked-CSP Family Datasheet Product Features Flash Architecture -- Flexible, Multiple-Partition, DualOperation: Read-While-Write / ReadWhile-Erase -- 32 Partitions, 4 Mbits each --31 Main Partitions, 8 Main Blocks each --1 Parameter Partition, 8 Parameter + 7 Main Blocks --32-Kword Main Blocks, 4-Kword Parameter Blocks -- Single flash die- Top or Bottom Parameter -- Dual flash die- Dual Parameter Flash Performance -- 65 ns Initial Access Speed -- 25 ns Async 4-Word Page-Mode Reads -- 14 ns Sync Burst-Read Speed -- 4-, 8-, 16-, Continuous-Word Burst Lengths -- Burst-/ Page-Mode Reads in all Blocks and across all partition boundaries -- Burst Suspend -- Programmable WAIT Configuration -- Enhanced Factory Programming Mode: 3.1s/Word -- Flash Protection Register --64 Unique Device Identifier Bits --64 User-Programmable OTP Bits Flash Automation Suspend Operations -- Erase Suspend to Program or Read -- Program Suspend to Read -- 5s (typ) Program/Erase Suspend Latency Flash Software -- Intel(R) Flash Data Integrator (FDI) Optimized -- Common Flash Interface (CFI) Flash Data Protection -- Absolute Protection with VPP and WP# -- Individual Dynamic Zero-Latency Block Locking -- Individual Block Lock-Down -- Erase/Program Lockout during Power Transitions Stacked-CSP Architecture -- Flash -- Flash + Flash -- Flash + PSRAM -- Flash + Flash + PSRAM -- Reduces Board Space Requirement -- Simplifies PCB Design Complexity -- Easy Migration to Future Stacked-CSP Devices Stacked-CSP Voltage -- 1.7 V to 1.95 V VCC -- 1.7 V to 2.24 V VCCQ (Flash only) -- 1.8 V to 1.95 V VCCQ (Flash + PSRAM) Stacked-CSP Packaging -- 0.8 mm Ball-Pitch Intel(R) Stacked-CSP -- Area: 8x10 mm, Height: 1.2mm and 1.4mm -- 88-Ball (8 x 10 Matrix): 80 Active Balls with 2 Support Balls at Each Corner PSRAM Architecture and Performance -- 1.8 V to 1.95 V P-VCC -- 85 ns Access Speed -- 8-Word Page Read -- 30 ns for Page Read Speed -- Low Power Mode Flash Quality and Reliability -- Extended Temperature: -25 C to +85 C -- Minimum 100K Block Erase Cycles -- 0.13 m ETOXTM VIII Process Versatile and compact Stacked Chip Scale Package (Stacked-CSP) solutions have been created by combining 128-Mbit 1.8 Volt Intel(R) Wireless Flash Memory (W18) with low-power 32-Mbit PSRAM. Ideal for high-performance, low-power, board-constrained memory applications, the W18 + 32-Mbit PSRAM Stacked-CSP family retains all of the features of the discrete 1.8 Volt Intel(R) Wireless Flash Memory (W18) device: flexible, multi-partition architecture for ReadWhile-Write / Read-While-Erase (RWW/RWE) dual operation and high performance asynchronous/ synchronous burst reads. Device upgrades and migrations are easy with a common package footprint and signal ballout for all Stacked-CSP combinations. Manufactured on Intel(R) 0.13 micron ETOXTM VIII process technology, W18 provides the highest levels of quality and reliability. Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. 252634-001 February 2003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. The 128-Mbit 1.8 Volt Intel(R) Wireless Flash Memory + 32-Mbit PSRAM Stacked-CSP family may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2003. *Other names and brands may be claimed as the property of others. 2 Datasheet Contents 1.0 Introduction ...............................................................................................................................7 1.1 1.2 Nomenclature .......................................................................................................................7 Conventions..........................................................................................................................7 2.0 Product Description ...............................................................................................................9 2.1 2.2 2.3 2.4 2.5 Product Overview .................................................................................................................9 Ballout Diagram ..................................................................................................................10 Signal Descriptions .............................................................................................................11 Block Diagram ....................................................................................................................13 Flash Memory Map and Partitioning ...................................................................................13 3.0 Device Operation ...................................................................................................................15 3.1 3.2 Bus Operations ...................................................................................................................15 Flash Command Definitions................................................................................................17 4.0 Flash Read Operations........................................................................................................17 5.0 Flash Program Operations ................................................................................................17 6.0 Flash Erase Operations ......................................................................................................17 7.0 Flash Security Modes ..........................................................................................................17 8.0 Flash Read Configuration Register ................................................................................17 9.0 Flash Power Consumption ................................................................................................17 10.0 Electrical Specifications .....................................................................................................18 10.1 10.2 10.3 10.4 Absolute Maximum Ratings ................................................................................................18 Operating Conditions ..........................................................................................................19 Capacitance ........................................................................................................................19 DC Characteristics..............................................................................................................20 11.0 AC Characteristics ................................................................................................................21 11.1 11.2 Flash AC Characteristics ....................................................................................................21 PSRAM AC Characteristics ................................................................................................22 12.0 PSRAM Operations ...............................................................................................................26 12.1 Power-up Sequence and Initialization ................................................................................26 12.2 Mode Register ....................................................................................................................26 12.2.1 Mode Register Setting ...................................................................................................27 12.2.2 Cautions for setting Mode Register ...............................................................................28 12.3 Low Power mode ................................................................................................................29 Appendix A Appendix B Appendix C Appendix D Datasheet Write State Machine .............................................................................................30 Common Flash Interface ....................................................................................30 Flash Flowcharts ...................................................................................................30 Mechanical Package Information ...................................................................31 3 Appendix E Additional Information ........................................................................................ 33 Appendix F Ordering Information............................................................................................ 34 4 Datasheet Revision History Datasheet Date of Revision Version 02/12/03 -001 Description Initial Release, Stacked Chip Scale Package 5 6 Datasheet 1.0 Introduction This document contains information pertaining to the 128-Mbit 1.8 Volt Intel(R) Wireless Flash Memory (W18) + 32-Mbit PSRAM Stacked-CSP family. The intent of this document is to provide information where this Stacked-CSP device differs from the discrete 1.8 Volt Intel(R) Wireless Flash Memory device. Refer to the latest revision 1.8 Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) for flash product details not included in this document. 1.1 Nomenclature 0x 0b Byte CUI DU ETOX k (noun) Kb KB Kword M (noun) Mb MB OTP PLR PR PRD RCR RFU Stacked-CSP SR SRD Word 1.2 Hexadecimal prefix Binary prefix 8 bits Command User Interface Do Not Use EPROM Tunnel Oxide 1 thousand 1024 bits 1024 bytes 1024 words 1 million 1,048,576 bits 1,048,576 bytes One Time Programmable Protection Lock Register Protection Register Protection Register Data Read Configuration Register Reserved for Future Use Stacked Chip Scale Package Status Register Status Register Data 16 bits Conventions Group Membership Brackets: Square brackets will be used to designate group membership or to define a group of signals with a similar function, such as A[21:1] and SR[4,1], for example. VCC vs. VCC: When referring to a signal or package-connection name, the notation used is VCC, etc. When referring to a timing or electrical level, the notation used is subscripted such as VCC, etc. Device: This term is used interchangeably throughout this document to denote either a particular die, or the combination of the triple-die. Datasheet 7 CE#[2:1], OE#[2:1]: This is the method used to refer to more than one chip-enable or output enable at the same time. When each is referred to individually, the reference will be CE#1 and OE#1 (for die #1), and CE#2 and OE#2 (for die #2). VCC, P-VCC, S-VCC: When referencing flash memory signals or timings, the notation used is VCC or VCC, respectively. When the reference is to PSRAM signals or timings, the notation is prefixed with "P-" (e.g., P-VCC, P-VCC). When referencing SRAM signals or timings, the notation is prefixed with "S-" (e.g., S-VCC or S-VCC). R-OE#, R-LB#, R-UB#, R-WE#: Used to identify OE#, LB#, UB#, WE# RAM signals, and are usually shared between 1 or 2 RAM die. 8 Datasheet 2.0 Product Description This section provides an overview of the features and capabilities of the 128-Mbit 1.8 Volt Intel(R) Wireless Flash Memory + 32-Mbit PSRAM Stacked-CSP family. 2.1 Product Overview The 128-Mbit 1.8 Volt Intel(R) Wireless Flash Memory + 32-Mbit PSRAM Stacked-CSP family encompasses multiple flash memory + 32-Mbit PSRAM die combinations. Products range from a flash-only, single-die device to a triple-die, dual flash + 32-Mbit PSRAM device. The user can choose 32-Mbit PSRAM combined with one or two flash memory dies, all offered in the same package footprint and signal ballout. Table 1 summarizes the 128-Mbit 1.8 Volt Intel(R) Wireless Flash Memory + 32-Mbit PSRAM Stacked-CSP family offerings. Table 1. Stacked-CSP Family Matrix Line Item Flash Die #1 Flash Die #2 RAM Die Package Size (mm) Notes 1 28F128W18T/B None None 8 x 10 x 1.2 1 2 28F128W18T/B None 32M PSRAM 8 x 10 x 1.2 1 3 28F128W18B 28F640W18T None 8 x 10 x 1.2 1,2 4 28F128W18B 28F640W18T 32M PSRAM 8 x 10 x 1.4 1,2 5 28F128W18B 28F128W18T None 8 x 10 x 1.2 1,2 6 28F128W18B 28F128W18T 32M PSRAM 8 x 10 x 1.4 1,2 NOTES: 1. W18 = 1.8 Volt Intel(R) Wireless Flash Memory. 2. T/B = Top or Bottom boot; B = Bottom boot (flash die#1); T = Top boot (flash die#2) Datasheet 9 2.2 Ballout Diagram The 1.8 Volt Intel(R) Wireless Flash Memory + 32-Mbit PSRAM Stacked-CSP family is available in an 88-ball (80-active ball) Stacked Chip-Scale Package (CSP) with a ball pitch of 0.8 mm. Figure 1 shows the ballout diagram for the 1.8 Volt Intel(R) Wireless Flash Memory + 32-Mbit PSRAM Stacked-CSP family devices. Figure 1. 88-Ball (80-Active Ball) Stacked-CSP Package Ballout A 1 2 3 4 5 DU DU A4 A18 A19 VSS VCC1 A5 R-LB# A23 VSS A3 A17 A24 A2 A7 A25 6 7 8 8 7 6 5 4 DU DU DU DU VCC2 A21 A11 A11 A21 VCC2 VCC1 VSS S-CS2 CLK A22 A12 A12 A22 CLK S-CS2 VPP, VPEN R-WE# P-CS# A9 A13 A13 A9 P-CS# R-WE# WP# ADV# A20 A10 A15 A15 A10 A20 ADV# 3 2 1 DU DU A19 A18 A4 VSS A23 R-LB# A5 VPP, VPEN A24 A17 A3 WP# A25 A7 A2 B B C C D D E E F F A1 A6 R-UB# RST# WE# A8 A14 A16 A16 A14 A8 WE# RST# R-UB# A6 A1 G G A0 D8 D2 D10 D5 D13 WAIT CE#2 CE#2 WAIT D13 D5 D10 D2 D8 A0 R-OE# D0 D1 D3 D12 D14 D7 OE#2 OE#2 D7 D14 D12 D3 D1 D0 R-OE# S-CS1# OE#1 D9 D11 D4 D6 D15 VCCQ VCCQ D15 D6 D4 D11 D9 OE#1 S-CS1# CE#1 RFU RFU S-VCC P-VCC VCC2 VCCQ P-Mode VCCQ VCC2 P-VCC S-VCC RFU RFU CE#1 VSS VSS VCCQ VCC1 VSS VSS VSS VSS VSS VSS VSS VSS VCC1 VCCQ VSS VSS DU DU DU DU DU DU DU DU H H J J K K P-Mode L M A L Top View - Ball Side Down M Bottom View - Ball Side Up NOTE: Solid balls are shown as ballout differences between various stacked combinations across the Stacked-CSP Family. See Signal Descriptions for details on the electrical connections per stacked combination. 10 Datasheet 2.3 Signal Descriptions Table 2 describes the active signals used on the 128-Mbit 1.8 Volt Intel(R) Wireless Flash Memory +32-Mbit PSRAM Stacked-CSP family. Table 2. Signal Descriptions (Sheet 1 of 2) Symbol Type Descriptions ADDRESS INPUTS for memory addresses of a SCSP device with: A[Max:0] D[15:0] CE#1 CE#2 Input Input/ Output Input * * * 32-Mbit density: A[Max]=A20 64-Mbit density: A[Max]=A21 128-Mbit density: A[Max]=A22 DATA INPUTS/OUTPUTS: Inputs data and commands during writing cycles, outputs data during memory, status register, protection register and configuration code reads. These signals float when the die or outputs are deselected. Data is internally latched during writes. FLASH CHIP ENABLE: CE#-low selects the flash component. When asserted, the flash internal control logic, input buffers, decoders, and sense amplifiers are activated. When deasserted, the flash die is deselected, power reduces to standby levels, and data and WAIT outputs are placed in high-Z state. CE#1 connects to flash die#1 Chip Enable while CE#2 connects to flash die#2 Chip Enable. CE#2 is only connected for stacked combinations with 2 flash dies. RST# OE#1 OE#2 WE# ADV# CLK Input Input Input FLASH RESET: RST#-low resets flash internal circuitry and inhibits write operations. This function may be employed to provide data protection during power transitions. After exiting the reset state (RST# returned to logic-high), the selected flash die resumes operation in asynchronous read-array mode. FLASH OUTPUT ENABLE: OE#-low activates device output through the flash data buffers during a flash read cycle. When deasserted, the flash outputs tri-state to high-Z. OE#1 connects to flash die#1 Output Enable while OE#2 connects to flash die#2 Output Enable. OE#2 is only connected for stacked combinations with 2 flash dies. FLASH WRITE ENABLE: WE# controls writes to the selected flash die. WE#-low allows input to the flash CUI, array, PR/PLR, RCR, or block lock bits. Addresses and data are latched on this signal's rising edge. Input FLASH ADDRESS VALID: ADV# indicates valid address presence on address inputs of the selected flash die. During synchronous read operations, all addresses are latched on ADV#'s rising edge or CLK's rising (or falling) edge, whichever occurs first. Input FLASH CLOCK: CLK synchronizes the selected flash die to the system bus frequency in synchronous-read configuration and increments an internal burst address generator. During synchronous read operations, addresses are latched on ADV#'s rising edge or CLK's rising (or falling) edge, whichever occurs first. CLK is only used for synchronous mode. Refer to flash product discrete datasheet for information how to use this signal in asynchronous mode. FLASH WAIT: Wait is driven when CE# is asserted. Flash RCR[10][WP] determines the WAIT asserted logic level. * WAIT Output In synchronous array read modes, WAIT indicates invalid data when asserted and valid data when de-asserted. * In synchronous non-array read modes, asynchronous page mode, and all write modes, WAIT is asserted. Refer to flash product discrete datasheet for more information. Datasheet 11 Table 2. Signal Descriptions (Sheet 2 of 2) Symbol Type WP# Input VPP Power VCC1 VCC2 Power Power VSS Power S-CS2 FLASH WRITE PROTECT: Enables/disables the lock-down mechanism of the selected flash die. When WP# is logic low, the lock-down mechanism is enabled and blocks marked lockdown can not be unlocked through software. FLASH PROGRAM / ERASE SUPPLY: Valid Vpp voltage on this ball allow block erase and program functions. Flash memory array contents cannot be altered when VPP<VPPLK. Block Erase and program at invalid VPP Voltage should not be attempted. FLASH POWER SUPPLY: Supplies power to the flash core. VCC1 connects to flash die#1 power supply while VCC2 connects to flash die#2 power supply. VCC2 is only connected for stacked combinations with 2 flash dies. VCCQ S-CS1# Descriptions Input OUTPUT BUFFER POWER SUPPLY: Supplies power for the input and output buffers. GROUND: Do not float any VSS connection. SRAM CHIP SELECTS: Activates the SRAM internal control logic, input buffers, decoders, and sense amplifiers. When either are deasserted (S-CS1# = VIH or S-CS2 = VIL), the SRAM is deselected and its power reduces to standby levels. S-CS1# and S-CS2 are only connected for stacked combinations with SRAM die. R-OE# Input RAM OUTPUT ENABLE: R-OE#-low activates device output through the selected RAM data buffers during a RAM read cycle. When deasserted, the selected RAM outputs tristate to high-Z. R-OE# is only connected for stacked combinations with 1 or more RAM die. R-WE# R-UB# R-LB# S-VCC P-CS# Input Input RAM WRITE ENABLE: R-WE#-low allows writes to the selected RAM array. R-WE# is only connected for stacked combinations with 1 or more RAM die. RAM UPPER / LOWER BYTE ENABLES: R-UB#-low enables the selected RAM highorder bytes (D[15:8]). R-LB#-low enables the selected RAM low-order bytes (D[7:0]). R-UB# and R-LB# are only connected for stacked combinations with 1 or more RAM die. Power Input SRAM POWER SUPPLY: Supplies power for SRAM operations. S-VCC is only connected for stacked combinations with SRAM die. PSRAM CHIP SELECT: Activates the PSRAM internal control logic, input buffers, decoders, and sense amplifiers. When deasserted, the PSRAM is deselected and its power reduces to standby levels. P-CS# is only connected for stacked combinations with PSRAM die. P-Mode Input PSRAM REFRESH: When deasserted, it enables PSRAM Lower Power Mode with partial array refresh or zero array refresh according to the Mode register setting. P-Mode is only connected for stacked combinations with PSRAM die. P-VCC 12 Power PSRAM POWER SUPPLY: Supplies power for PSRAM operations. P-VCC is only connected for stacked combinations with PSRAM die. RFU RESERVED for FUTURE USE: Do not drive RFU balls and leave them disconnected. Contact Intel regarding their future use. DU DO NOT USE: Do not connect to any other signal, or power supply; must be left floating. Datasheet 2.4 Block Diagram Figure 2 is a block diagram showing all internal package connections for the Stacked-CSP family with multiple dies. Refer to Table 1, "Stacked-CSP Family Matrix" on page 9 for valid combinations of flash and PSRAM die. Unused connections on combinations with less than triple die are reserved and should not be used. Figure 2. Block Diagram VCC2 CE#2 OE#2 Flash Die #2 WE# VPP VCCQ WAIT CLK ADV# WP# RST# OE#1 CE#1 VCC1 A[MAX:0] P-VCC P-CS# P-MODE R-OE# 2.5 Flash Die #1 VSS D[15:0] PSRAM Die R-WE# R-UB# R-LB# Flash Memory Map and Partitioning Consult the latest 1.8 Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) for individual flash die memory map and partitioning information. Refer to Table 1, "Stacked-CSP Family Matrix" on page 9 for valid configurations per stacked combination. Table 3 and Table 4 shows the Memory Map and Partitioning information for two flash memory die. Flash die#1(with CE#1 as its Chip Select) is configured to bottom boot while flash die#2(with CE#2 as its Chip Select) is configured to top boot. Datasheet 13 Table 3. 128W18B+128W18T Dual-Flash Die SCSP Memory Map and Partitioning Table 4. 128M-bit Main Partitions Main Partitions Parameter Partition One Partition Block Size (KW) Blk# Address Range 4 255-262 7F8000-7FFFFF 32 248-254 7C0000-7F7FFF One Partition 32 240-247 780000-7BFFFF One Partition 32 232-239 740000-77FFFF One Partition 32 224-231 700000-73FFFF Four Partitions 32 192-223 600000-6FFFFF Eight Partitions 32 128-191 400000-5FFFFF Sixteen Partitions 32 0-127 000000-3FFFFF Sixteen Partitions 32 135-262 400000-7FFFFF Eight Partitions 32 71-134 200000-3FFFFF Four Partitions 32 39-70 100000-1FFFFF One Partition 32 31-38 0C0000-0FFFFF One Partition 32 23-30 080000-0BFFFF One Partition 32 15-22 040000-07FFFF 32 8-14 008000-03FFFF 4 0-7 000000-007FFF One Partition 128W18B+64W18T Dual-Flash Die SCSP Memory Map and Partitioning Partitioning 64-Mbit Parameter Partition 128-Mbit Flash die #1(Bottom Boot) Flash die #2(Top Boot) Flash Die# 14 Partitioning Parameter Partition 128-Mbit Flash die #1(Bottom Boot) Flash die #2(Top Boot) Flash Die# Main Partitions Main Partitions Parameter Partition Block Size (KW) Blk # Address Range 4 127-134 3F8000-3FFFFF 32 120-126 3C0000-3F7FFF One Partition 32 112-119 380000-3BFFFF One Partition 32 104-111 340000-37FFFF One Partition One Partition 32 96-103 300000-33FFFF Four Partitions 32 64-95 200000-2FFFFF Eight Partitions 32 0-63 000000-1FFFFF Sixteen Partitions 32 135-262 400000-7FFFFF Eight Partitions 32 71-134 200000-3FFFFF Four Partitions 32 39-70 100000-1FFFFF One Partition 32 31-38 0C0000-0FFFFF One Partition 32 23-30 080000-0BFFFF One Partition 32 15-22 040000-07FFFF 32 8-14 008000-03FFFF 4 0-7 000000-007FFF One Partition Datasheet 3.0 Device Operation 3.1 Bus Operations Bus operations for the 128-Mbit 1.8 Volt Intel(R) Wireless Flash Memory + 32-Mbit PSRAM Stacked-CSP family involve the multiple control chip enable (CE#1 for flash die#1 and CE#2 for flash die#2) and output enable (OE#1 for flash die#1 and OE#2 for flash die#2) signals. All other control signals are shared between the two flash die. Table 5 to Table 6 explains the bus operations of products across this SCSP family. Refer to the W18 datasheet (order number 290701) for single flash die SCSP bus operations. CE#1 OE#1 WE# ADV VPP WAIT CE#2 OE#2 D[15:0] Sync Array Read H L L H L X Active H X Flash DOUT 2,3,4 All Async / Sync Non-Array Read H L L H X X Asserted H X Flash DOUT 1,3,4,5 Write H L H L X VPP1 or VPP2 Asserted H X Flash DIN 3,4,6 Output Disable H L H H X X Active X X Flash High-Z 4 Standby H H X X X X High-Z X X Flash High-Z 4 Reset L X X X X X High-Z X X Flash High-Z 4 Sync Array Read H H X H L X Active L L Flash DOUT 2,3,4 All Async / Sync Non-Array Read H H X H X X Asserted L L Flash DOUT 1,3,4,5 Write H H X L X VPP1 or VPP2 Asserted L H Flash DIN 3,4,6 Output Disable H X X H X X Active L H Flash High-Z 4 Standby H X X X X X High-Z H X Flash High-Z 4 Reset L X X X X X High-Z X X Flash High-Z 4 Notes Mode Device Flash Die#1 Enabled Flash Die#2 Enabled Flash Die#1 + Flash Die#2 Bus Operations RST# Table 5. NOTES: 1. For asynchronous read operation, both die may be simultaneously selected, but may not simultaneously drive the memory bus. See Section 3.2, "Flash Command Definitions" on page 17 for details regarding Flash selection overlap. 2. WAIT is only active during synchronous Flash reads. WAIT is driven if CE# is asserted. Refer to the 1.8-Volt Intel(R) Wireless Flash Memory datasheet (order number 290701) for further information regarding WAIT Signal. 3. For either Flash die, OE#1/OE#2 and WE# should never be asserted simultaneously. If done so on a particular flash die, OE#1/OE#2 will override WE#. 4. L means VIL while H means VIH. X can be VIL or VIH for inputs, VPP1, VPP2 or VPPLK for VPP. 5. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 6. Refer to W18 datasheet for valid DIN during Flash writes. Datasheet 15 Notes Flash High-Z 6 X X High-Z Flash High-Z 6 X X High-Z Flash High-Z 6 L H L X Active All Async/ Sync Nonarray Read H L L H X X Asserted Write H L H L L VPP1 or VPP2 Output Disable H L H H X Standby H H X X Reset L X X X Read R-UB#, R-LB# Active L R-WE# X H R-OE# 3,4,6, 8 Sync Array Read P-CS# Flash DIN WAIT Asserted VPP 1,2,3, 4,6,7 ADV# Flash DOUT WE# 1,2,3, 4,6 OE#X Flash DOUT Mode CE#X D[15:0] P-Mode Flash (Single Die/Dual Die) + PSRAM Bus Operations RST# Flash Die(#1 or #2) Enabled Device Table 6. PSRAM must be in High-Z Any PSRAM mode allowed L H L H L PSRAM DOUT 1,5 L H H L L PSRAM DIN 5 L H H H X PSRAM High-Z 6 H H X X X PSRAM High-Z 6 X L X X X PSRAM High-Z 6 PSRAM Enabled Flash must be in High-Z Write Output Disable Standby Low Power Mode Note 2 Any flash mode allowed NOTES: 1. For asynchronous read operation, all dies may be simultaneously selected, but may not simultaneously drive the memory bus. For synchronous burst-mode reads, only two die (one flash and the PSRAM) may be simultaneously selected. 2. WAIT is only valid during synchronous flash reads. Refer to the discrete datasheet for detailed Wait functionality. 3. CE#X is CE#1 for flash die#1, CE#2 for flash die#2. OE#X is OE#1 for flash die#1, OE#2 for flash die#2. 4. For either flash die, OE#X and WE# should never be asserted simultaneously. If done so on a particular flash die, OE#X will override WE#. 5. For PSRAM, R-OE# and R-WE# should never be asserted simultaneously. 6. X can be VIL or VIH for inputs, VPP1, VPP2 or VPPLK for VPP. 7. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 8. Refer to W18 datasheet for valid DIN during flash writes. 16 Datasheet 3.2 Flash Command Definitions Refer to the 1.8 Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) for information regarding Flash Command Definitions. 4.0 Flash Read Operations Refer to the 1.8 Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) for information regarding Flash Read Modes and Operations. 5.0 Flash Program Operations Refer to the 1.8 Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) for information regarding Flash Program Operations. 6.0 Flash Erase Operations Refer to the 1.8 Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) for information regarding Flash Erase Operations. 7.0 Flash Security Modes Refer to the 1.8 Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) for information regarding Flash Security Modes and Operations. 8.0 Flash Read Configuration Register Refer to the 1.8 Volt Intel(R) Wireless Flash Memory datasheet (order number 290701) for information regarding Flash Read Configuration Register (RCR) functions and programming. 9.0 Flash Power Consumption Refer to the 1.8 Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) for information regarding Flash Power Considerations and Consumption. Datasheet 17 10.0 Electrical Specifications 10.1 Absolute Maximum Ratings Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Table 7. Absolute Maximum Ratings Parameter Min Max Unit Temperature under Bias Expanded -25 +85 C Storage Temperature -55 +125 C Voltage On Any Signal (except VCC1, VCC2, VCCQ, VPP, and P-VCC) -0.5 +2.45 V 1 VCC1 and VCC2 Voltage -0.2 +2.45 V 1 VCCQ, and P-VCC Voltage -0.2 +2.45 V 1 VPP Voltage -0.2 +14.0 V 1,2,3 - 100 mA Ish Output Short Circuit Current Notes 4 NOTES: 1. All Specified voltages are relative to VSS. Minimum DC voltage is -0.5 V on input/output signals, -0.5 V on VCC and VPP signals. During transitions, this level may overshoot to -2.0 V for periods < 20 ns, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns. 3. VPP program voltage is normally VPP1. The maximum DC voltage on VPP may overshoot to +14 V for periods < 20 ns. VPP can be VPP2 for 1000 erase cycles on main blocks, 2500 cycles on parameter blocks. 4. Output shorted for no more than one second. No more than one output shorted at a time. 18 Datasheet Table 8. Operating Conditions Extended Temperature Operation Symbol TC VCC VCCQ P-VCC Flash/ Flash+Flash Parameter Flash+PSRAM/ Flash+Flash+PSRAM Unit 10.2 Min Max Min Max Operating Temperature -40 +85 -25 +85 C Flash Supply Voltage 1.7 1.95 1.7 1.95 V 1.7 2.24 1.8 1.95 V Flash I/O Voltage PSRAM Supply Voltage VPP1 Flash Program Logic Level 0.9 1.95 0.9 1.95 V VPP2 Flash Factory Program Voltage 11.4 12.6 11.4 12.6 V NOTE: VPP is normally VPP1. VPP can be connected to 11.4 V-12.6 V for 1000 cycles on main blocks for extended temperatures and 2500 cycles on parameter blocks at extended temperature. 10.3 Capacitance NOTICE: Refer to the 1.8-Volt Intel(R) Wireless Flash Memory datasheet (order number 290701) for flash capacitance details. For SCSP products with two flash die, flash capacitances for each of the flash die need to be considered accordingly. Table 9. Datasheet PSRAM Capacitance Symbol Parameter Max Unit CIN Input Capacitance 8 pF CI/O Input/Output Capacitance 10 pF Condition TC=25 C, f=1MHz, VIN=0V 19 10.4 DC Characteristics 32-Mbit PSRAM DC characteristics are shown in Table 10. Refer to the 1.8 Volt Intel(R) Wireless Flash Memory datasheet (order number 290701) for Flash DC Characteristics. NOTICE: DC Characteristics of all die in a SCSP device need to be considered accordingly, depending on the SCSP device operation. Table 10. PSRAM DC Characteristics Parameter Description P-VCC Voltage Range ICC Operating Current at Min cycle time ISB1 Standby Current ISB2 Low Power Mode Test Conditions Min Typ Max Unit 1.8 - 1.95 V II/O=0mA - - 35 mA P-CS#>P-VCC-0.2V, P-Mode > P-VCC-0.2V - 90 100 16 Mbits - 60 70 8 Mbits - 50 60 4 Mbits - 40 50 0 Mbits - 20 30 P-CS#>P-VCC-0.2V, PMode<0.2V A VOH Output High Voltage IOH = -0.5 mA 0.8P-Vcc - - V VOL Output Low Voltage IOL = 1 mA - - 0.2P-Vcc V VIH Input High Voltage 0.8P-Vcc - P-VCC + 0.3 V VIL Input Low Voltage -0.3 - 0.2P-VCC V *IIL Input Leakage Current VIN=0V to P-Vcc -1.0 - +1.0 *IOL Input/Output Leakage Current VI/O=0V to P-Vcc, P-CS#=VIH or R-WE#=VIH or R-OE#=VIH -1.0 - +1.0 A * VIN: Input voltage, VI/O: Input/Output voltage 20 Datasheet 11.0 AC Characteristics 11.1 Flash AC Characteristics Refer to the 1.8-Volt Intel(R) Wireless Flash Memory datasheet (order number 290701) for Flash AC Characteristics details not included in Table 11 below. Table 11. Flash AC Read Characteristics 128W18 Sym 64W18 Parameter Unit Min Max Min Max Asynchronous Specifications tAVAV Read Cycle Time 65 65 ns tAVQV Address to Output Delay 65 65 ns tELQV CE# Low to Output Delay 65 65 ns tVLQV ADV# Low to Output Delay 65 65 ns 25 25 ns 14 14 ns Latching Specifications tAPA Page Address Access Time Clock Specifications tCHQV Datasheet CLK to Output Delay 21 11.2 PSRAM AC Characteristics Table 12. PSRAM AC Characteristics--Read-Only Operations 32M # Symbol Parameter Unit Min Note Max Read Cycle R1 tRC Read Cycle Time 85 - ns R2 tAA Address access time - 85 ns R3 tCO P-CS# Low to Output Valid - 85 ns R4 tOE R-OE# Low to Output Valid - 65 ns R5 tBA R-UB#, R-LB# Low to Output Valid - 85 ns R6 tLZ P-CS# Low to Output in Low-Z 10 - ns R7 tOLZ R-OE# Low to Output in Low-Z 5 - ns R8 tHZ P-CS# High to Output in High-Z - 25 ns R9 tOHZ R-OE# High to Output in High-Z - 25 ns R10 tOH Output Hold from Address change 5 - ns R11 tBLZ R-UB#, R-LB# Low to Output in Low-Z 5 - ns R12 tBHZ R-UB#, R-LB# High to Output in High-Z - 25 ns R13 tASO Address set to R-OE# low level 0 - ns R14 tOHAH R-OE# high level to address hold -5 - ns R15 tCHAH P-CS# high level to address hold 0 - ns 1 R16 tBHAH R-LB#, R-UB# high level to address hold 0 - ns 1,2 R17 tCLOL P-CS# low level to R-OE# low level 0 10,000 ns 3 R18 tOLCH R-OE# low level to P-CS# high level 60 - ns R19 tCP P-CS# high level pulse width 10 - ns R20 tBP R-UB#, R-LB# high level pulse width 10 - ns R21 tOP R-OE# high level pulse width - 10,000 ns 1 3 Page Mode PR1 tPC Page Cycle Time 30 - ns PR2 tPA Page Mode Address Access Time - 30 ns 4 NOTE: 1. When R13>|R15|, |R16|. The minimum of R15 and R16 are -15 ns. (See Figure 3, "Conditions for Calculating R15 and R16 Minimum Values" on page 22.) 2. R16 is specified from when both R-LB# and R-UB# become high level. 3. R17 and R21(MAX) are applied while P-CS# is being hold at low level. 4. See Figure 5, "AC Waveform of PSRAM Read Operations" on page 24. Figure 3. Conditions for Calculating R15 and R16 Minimum Values R15, R16 Address R-UB#,R-LB#, P-CS# R-OE# 22 R13 Datasheet Table 13. PSRAM AC Characteristics--Write Operations 32M # Symbol Parameter Unit Min Max W1 tWC Write Cycle Time 85 - ns W2 tAS Address Setup Time 0 - ns W3 tWP Write Pulse Width 60 - ns W4 tDW Data valid to Write End 30 - ns W5 tAW Address valid to end of write 70 - ns W6 tCW P-CS# to end of write 70 - ns W7 tDH Data Hold time 0 - ns W8 tWR Write Recovery 0 - ns W9 tBW R-UB#, R-LB# Setup to end of Write 70 - ns W10 tCP P-CS# High level pulse width 10 - ns W11 tBP R-UB#, R-LB# High level pulse width 10 - ns Note W12 tWHP R-WE# High level pulse width 10 - ns W13 tOHAH R-OE# High level to address hold -5 - ns W14 tCHAH P-CS# High level to address hold 0 - ns 1 W15 tBHAH R-UB#, R-LB# High level to address hold 0 - ns 1,2 W16 tOES R-OE# High level to R-WE# set 0 10,000 ns W17 tOEH R-WE# High level to R-OE# set 10 10,000 ns 3 NOTES: 1. When W2 >|W14|, |W15| and W10>18ns, W14 and W15 (MIN) are -15 ns. (See Figure 4, "Conditions for Calculating W14 and W15 Minimum Values" on page 23.) 2. W15 is specified from when both R-LB# and R-UB# become high level. 3. W16 and W17(MAX) are applied while P-CS# is being hold at low level. 4. See Figure 7, "AC Waveform PSRAM Write Operation" . Figure 4. Conditions for Calculating W14 and W15 Minimum Values W14, W15 Address R-UB#,R-LB#, P-CS# R-WE# Datasheet W10 W2 23 Figure 5. AC Waveform of PSRAM Read Operations R1 Vih Address Vil R2 Vih P-CS# R3 Vil R8 Vih R-UB#, R-LB# R5 Vil R12 Vih R-OE# R4 Vil R9 R7 R11 R6 R10 Voh Data out High-Z Valid Output Vol High-Z NOTE: In read cycle, P-Mode and R-WE# should be fixed to high level Figure 6. AC Waveform of PSRAM 8-Word Page Read Operation R1 Vih A3-A MAX Vil Valid Address Vih A0,A1,A2 Vil P-CS# R-OE#, R-UB#, R-LB# 000 001 R2 R3 PR1 111 PR2 R4 R9 Voh Data out High-Z Vol Qn Qn+ 6 Qn+ 7 NOTE: In page read cycle, P-Mode and R-WE# should be fixed to high level, and R-UB#, R-LB# are low level. 24 Datasheet Figure 7. AC Waveform PSRAM Write Operation W1 Vih Address Vil W2 W8 Vih P-CS# W6 Vil W5 W9 Vih R-UB#, R-LB# Vil Vih R-WE# W3 Vil Voh Low-Z W4 High-Z Data I/O Valid Data In W7 High-Z Vol NOTES: 1. During address transition, at least one of pins P-CS#, R-WE#, or both of R-UB# and R-LB# pins should be inactivated. 2. Do not input data to the I/O pins while they are in the output state. 3. In write cycle, P-Mode and R-OE# should be fixed to high level. 4. Write operation is done during the overlap time of a low level P-CS#, R-WE#, R-LB# and/or R-UB#. Datasheet 25 12.0 PSRAM Operations 12.1 Power-up Sequence and Initialization The PSRAM functionality and reliability are independent of the power-up slew rate of the core PVCC. Any power-up slew rate is possible under use conditions. The following power up sequence and operation should be used before starting normal operation. The PSRAM power-up sequence is represented in Figure 8. Following power application, make PMode high level after fixing P-Mode to low level for the period of tVHMH. Make P-CS# high level before making P-Mode high level. Then, P-CS# and P-Mode are fixed to high level for the period of tMHCL. Normal Operation is possible once the power up sequence is complete. Figure 8. Timing Waveform for Power up sequence Initialization Normal Operation P-CS# tMHCL tCHMH P-Mode tVHMH P-Vcc Vcc (MIN) NOTES: 1. Make P-Mode low level when starting the power supply. 2. tVHMH is specified from when the power supply voltage reaches the prescribed minimum value (P-Vcc (MIN)) Table 14. Initialization timing Parameter 12.2 Symbol MIN MAX Unit Power application to P-Mode low level hold tVHMH 50 us P-CS# high level to P-Mode high level tCHMH 0 ns Following power application, P-Mode high level hold to P-CS# low level tMHCL 200 us Mode Register The PSRAM die has an internal register that helps control the Low Power mode of the PSRAM. This register is called the Mode register. The densities that can be selected for performing refresh are 16 Mbits, 8 Mbits, 4 Mbits and 0 Mbit. The density for performing refresh can be set with the Mode register. Once the refresh density has been set in the Mode register, these settings are retained until they are set again, while applying the power supply. However, the Mode register setting will become undefined if the power is turned off, so set the Mode register again after power application. 26 Datasheet 12.2.1 Mode Register Setting Since the initial value of the Mode register at power application is undefined, be sure to set the Mode register after initialization at power application. When setting the density of partial refresh, data before entering the Low Power Mode is not guaranteed.(This is the same for resetup) However, since Low Power Mode is not entered unless P-Mode=L, when partial refresh is not used, it is not necessary to set the Mode register. Moreover, when using page read without using partial refresh, it is not necessary to set the Mode register. The Mode register setting mode can be entered by successively writing two specific data after two continuous reads of the highest address. The Mode register setting is a continuous four-cycle operation - two read cycles and two writes cycles. See Table 15 for setting Mode register command sequence. Table 15. Setting Mode Register Command Sequence Command Sequence 1st Bus Cycle (Read Cycle) 2nd Bus Cycle (Read Cycle) 3rd Bus Cycle (Write Cycle) 4th Bus Cycle (Write Cycle) Partial refresh density Address Data Address Data Address Data Address Data 16 Mbits Highest Address _ Highest Address _ Highest Address 00H Highest Address 04H 8 Mbits Highest Address _ Highest Address _ Highest Address 00H Highest Address 05H 4 Mbits Highest Address _ Highest Address _ Highest Address 00H Highest Address 06H 0 Mbit Highest Address _ Highest Address _ Highest Address 00H Highest Address 07H For the timing chart and flow chart, refer to Figure 9 and Figure 10. register AMAX -A5, programming. a Figure 9. Mode Register Update--Timing Waveform Address R1 R1 W1 W1 Highest Address Highest Address Highest Address Highest Address Mode Register Setting P-CS# R-OE# W8 W3 W8 W3 R-WE# W7 W4 Data I/O W7 0000H W4 000XH R-UB#, R-LB# Datasheet 27 Figure 10. Mode Register Setting Flow Chart START Read Highest Address No by Toggling both P-CS# and R-OE# Read Highest Address No by Toggling both P-CS# and R-OE# No Write to Highest Address No Data=00H No Mode Register setting exit Fail Write to Highest Address No Data=xxH Begin Normal Operation NOTE: xxH=04H, 05H, 06H or 07H 12.2.2 Cautions for setting Mode Register Since, for the Mode register setting, the internal counter status is judged by toggling P-CS# and ROE#, toggle P-CS# at every cycle during entry (read cycle twice, write cycle twice), and toggle ROE# like P-CS# at the first and second read cycles. If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the Mode register is not performed correctly. When the highest address is read consecutively three or more times, the Mode register setting entries are not performed correctly. (Immediately after the highest address is read, the setting of the Mode register is not performed correctly.) Perform the setting of the Mode register after power application or after accessing other than the highest address. Once the refresh density has been set in the Mode register, these settings are retained until they are set again, while applying the power supply. However, the Mode register setting will become undefined if the power is turned off, so set the Mode register again after power application. 28 Datasheet 12.3 Low Power mode In addition to the regular Standby mode with a full density data hold, Low Power mode performs partial density data refresh or zero density data refresh. The Low Power mode allows customers to turn off sections of the PSRAM die to save refresh current. The PSRAM die is divided into four sections allowing certain sections to be refreshed with P-Mode tied Low. In regular Standby mode, both P-CS# and P-Mode are high level. But in Low Power mode, PMode is low level. In Low Power mode, if 0M bit is set as the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal operation from Low Power mode. Refer to Figure 8, "Timing Waveform for Power up sequence" on page 26 for timing charts. When the density has been to set to 16 Mbits, 8 Mbits, or 4 Mbits in Low Power mode, it is not necessary to perform initialization to return to normal operation from Low Power mode. For timing charts, refer to Figure 11, "Low Power mode -Entry/Exit (16/ 8/ 4/ 0 Mbits)" Figure 11. Low Power mode -Entry/Exit (16/ 8/ 4/ 0 Mbits) P-Mode Low Power Mode (Partial Array Refresh/Zero Refresh) tCHML tMHCL1/tMHCL2 P-CS# Table 16. Low Power mode-Entry/Exit Parameter Description Min Max Unit tCHML Low Power mode entry, P-CS# high level to P-Mode# Low level 0 - ns tMHCL1 Low Power mode(16/8/4 Mbits hold) exit to normal operation, P-Mode High level to P-CS# Low level 30 - ns tMHCL2 Low Power Mode(0 Mbit data hold) exit to normal operation, P-Mode High level to P-CS# Low level 200 - us NOTES: 1. tMHCL1 is the time it takes to return to normal operation from Low Power Mode (data hold: 16 /8 /4 Mbits). 2. tMHCL2 is the time it takes to return to normal operation from Low Power Mode (0 Mbits data hold). Datasheet 29 Appendix A Write State Machine Refer to the 1.8 Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) for the Write State Machine details. Appendix B Common Flash Interface Refer to the 1.8 Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) for the Common Flash Interface details. Appendix C Flash Flowcharts Refer to the 1.8 Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) for the Flash Flowchart details. 30 Datasheet Appendix D Mechanical Package Information Figure 12. 80-Active Ball Single or Double-Die Stacked-CSP Mechanical Specifications A1 Index Mark S1 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A A B B C C D D E E F D F G G H H J J K K L L M M e b E Top View - Ball Down Bottom View - Ball Up A2 A1 A Y Drawing not to scale. Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Datasheet Symbol A A1 A2 b D E e N Y S1 S2 Min Millimeters Nom Max 1.200 0.200 0.325 9.900 7.900 1.100 0.500 Notes Min Inches Nom Max 0.0472 0.0079 0.860 0.375 10.000 8.000 0.800 88 1.200 0.600 0.425 10.100 8.100 0.0128 0.3898 0.3110 0.100 1.300 0.700 0.0433 0.0197 0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236 0.0167 0.3976 0.3189 0.0039 0.0512 0.0276 31 Figure 13. 80-Active Ball Triple-Die Stacked-CSP Mechanical Specifications A1 Index Mark S1 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A A B B C C D D E E F D F G G H H J J K K L L M M e b E Top View - Ball Down Bottom View - Ball Up A2 A1 A Y Drawing not to scale. Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D 32 Symbol A A1 A2 b D E e N Y S1 S2 Min Millimeters Nom Max 1.400 0.200 0.325 9.900 7.900 1.100 0.500 Notes Min Inches Nom Max 0.0551 0.0079 1.070 0.375 10.000 8.000 0.800 88 1.200 0.600 0.425 10.100 8.100 0.0128 0.3898 0.3110 0.100 1.300 0.700 0.0433 0.0197 0.0421 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236 0.0167 0.3976 0.3189 0.0039 0.0512 0.0276 Datasheet Appendix E Additional Information : Order Number Document 290701 1.8 Volt Intel(R) Wireless Flash Memory (W18) Datasheet 251407 64-Mbit 1.8 Volt Intel(R) Wireless Flash Memory Stacked-CSP Family NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. For the most current information on Intel flash memory products, software and tools, visit our website at http://developer.intel.com/design/flash. S Datasheet 33 Appendix F Ordering Information F.1 128-Mbit W18 + 32-Mbit PSRAM Stacked-CSP Family Device Name Decoder Figure 14 shows the decoder for products in this SCSP family with both flash and PSRAM. Figure 15 shows the decoder for products in this SCSP family with flash die only (no RAM). Flash #2 Flash #1 RAM #2 RAM #1 Flash #2 Flash #1 Figure 14. Decoder for Flash+RAM SCSP Device Name R D 3 8 F 3 0 4 0 W 0 Y B Q 0 Package RD = Stacked-CSP Product Line Designator 38F = Stacked-CSP Intel(R) Flash Memory, Flash & RAM Flash Density Device Details 0 = Original version of the products: W18 Speed = 14 ns Sync/ 25 ns Page/65 ns Async Flash Process = 0.13 m RAM = 32 Mbit PSRAM PSRAM Speed = 30 ns Page/85ns Async Size=8x10x1.2mm/ 1.4mm 0 = No die 2 = 64 Mbit 3 = 128 Mbit Pinout Indicator Q= Quad ballout RAM Density 3 = 16 Mbit 4 = 32 Mbit 5 = 64 Mbit Product Family W = Intel(R) Wireless Flash Memory(Flash #1) 0 = No Die(Flash #2) 34 Parameter Location B = Bottom Parameter T = Top Parameter D = Flash Die#1 Bottom Parameter; Flash Die#2- Top Parameter pr Voltage Y = 1.8 Volt Core and I/O od uc t: Datasheet Flash Family Flash Family Flash #4 Flash #3 Flash #2 Flash #1 Figure 15. Decoder for Flash-Only SCSP Device Name R D 4 8 F 3 2 0 0 W 0 Y D Q 0 Package RD = Stacked-CSP Product Line Designator 48F = Intel(R) Flash Memory, Multiple Flash-only Die Flash Density 0 = No Die 2 = 64 Mbit 3 = 128 Mbit Device Details pro duc 0 = Original version of this t: product: W18 Speed = 14 ns Sync/ 25 ns Page/65 ns Async Flash Process = 0.13m Size = 8 x 10 x 1.2 mm Pinout Indicator Q = Quad Ballout Parameter Location B = Bottom Parameter T = Top Parameter D = Bottom Parameter for Flash Die#1, Top Parameter for Flash Die#2 Product Family Voltage W = Intel(R) Wireless memory 0 = No Die Y = 1.8V core and I/O Datasheet 35 F.2 128-Mbit W18 + 32-Mbit PSRAM Stacked-CSP Family Device Name List Table 17 shows the complete list of device names for products with single flash die in this SCSP family according to boot configuration. Table 18 shows the complete list of device names for products with double flash die. Flash die#1 is configured bottom parameter while flash die#2 is configured top parameter. See Section 2.5, "Flash Memory Map and Partitioning" on page 13 for flash memory map and partitioning details of devices with double flash dies. Table 17. Single Flash Die SCSP Device Name List Bottom Parameter Configuration Device Name Top Parameter Configuration Device Name 128W18 RD48F3000W0YBQ0 RD48F3000W0YTQ0 128W18+32PSRAM RD38F3040W0YBQ0 RD38F3040W0YTQ0 Product Table 18. Double Flash Die SCSP Device Name List Product 36 Device Name 128W18B+64W18T RD48F3200W0YDQ0 128W18B+64W18T+32PSRAM RD38F3240WWYDQ0 128W18B+128W18T RD48F3300W0YDQ0 128W18B+128W18T+32PSRAM RD38F3340WWYDQ0 Datasheet