128-Mbit1.8VoltIntel®WirelessFlash
Memory(W18)+32-MbitPSRAM
Stacked-CSPFamily
Datasheet
ProductFeatures
VersatileandcompactStackedChipScalePackage(Stacked-CSP)solutionshavebeencreated
bycombining128-Mbit1.8VoltIntel®WirelessFlashMemory(W18)withlow-power32-Mbit
PSRAM.Idealforhigh-performance,low-power,board-constrainedmemoryapplications,the
W18+32-MbitPSRAMStacked-CSPfamilyretainsallofthefeaturesofthediscrete1.8Volt
Intel®WirelessFlashMemory(W18)device:flexible,multi-partitionarchitectureforRead-
While-Write/Read-While-Erase(RWW/RWE)dualoperationandhighperformance
asynchronous/synchronousburstreads.Deviceupgradesandmigrationsareeasywitha
commonpackagefootprintandsignalballoutforallStacked-CSPcombinations.Manufactured
onIntel®0.13micronETOX™VIIIprocesstechnology,W18providesthehighestlevelsofquality
andreliability.
■FlashArchitecture
—Flexible,Multiple-Partition,Dual-
Operation:Read-While-Write/Read-
While-Erase
—32Partitions,4Mbitseach
—31MainPartitions,8MainBlockseach
—1ParameterPartition,8Parameter+7
MainBlocks
—32-KwordMainBlocks,4-Kword
ParameterBlocks
—Singleflashdie-ToporBottomParameter
—Dualflashdie-DualParameter
■FlashPerformance
—65nsInitialAccessSpeed
—25nsAsync4-WordPage-ModeReads
—14nsSyncBurst-ReadSpeed
—4-,8-,16-,Continuous-WordBurstLengths
—Burst-/Page-ModeReadsinallBlocksand
acrossallpartitionboundaries
—BurstSuspend
—ProgrammableWAITConfiguration
—EnhancedFactoryProgrammingMode:
3.1µs/Word
—FlashProtectionRegister
—64UniqueDeviceIdentifierBits
—64User-ProgrammableOTPBits
■FlashAutomationSuspendOperations
—EraseSuspendtoProgramorRead
—ProgramSuspendtoRead
—5µs(typ)Program/EraseSuspendLatency
■FlashSoftware
—Intel®FlashDataIntegrator(FDI)
Optimized
—CommonFlashInterface(CFI)
■FlashDataProtection
—AbsoluteProtectionwithVPPandWP#
—IndividualDynamicZero-LatencyBlock
Locking
—IndividualBlockLock-Down
—Erase/ProgramLockoutduringPower
Transitions
■Stacked-CSPArchitecture
—Flash
—Flash+Flash
—Flash+PSRAM
—Flash+Flash+PSRAM
—ReducesBoardSpaceRequirement
—SimplifiesPCBDesignComplexity
—EasyMigrationtoFutureStacked-CSP
Devices
■Stacked-CSPVoltage
—1.7Vto1.95VVCC
—1.7Vto2.24VVCCQ
(Flashonly)
—1.8Vto1.95VVCCQ
(Flash+PSRAM)
■Stacked-CSPPackaging
—0.8mmBall-PitchIntel®Stacked-CSP
—Area:8x10mm,Height:1.2mmand1.4mm
—88-Ball(8x10Matrix):80ActiveBalls
with2SupportBallsatEachCorner
■PSRAMArchitectureandPerformance
—1.8Vto1.95VP-VCC
—85nsAccessSpeed
—8-WordPageRead
—30nsforPageReadSpeed
—LowPowerMode
■FlashQualityandReliability
—ExtendedTemperature:–25°Cto+85°C
—Minimum100KBlockEraseCycles
—0.13µmETOX™VIIIProcess
252634-001
February2003
Notice:Thisdocumentcontainsinformationonnewproductsinproduction.Thespecifications
aresubjecttochangewithoutnotice.VerifywithyourlocalIntelsalesofficethatyouhavethelat-
estdatasheetbeforefinalizingadesign.
2Datasheet
INFORMATIONINTHISDOCUMENTISPROVIDEDINCONNECTIONWITHINTELPRODUCTS.NOLICENSE,EXPRESSORIMPLIED,BY
ESTOPPELOROTHERWISE,TOANYINTELLECTUALPROPERTYRIGHTSISGRANTEDBYTHISDOCUMENT.EXCEPTASPROVIDEDIN
INTEL'STERMSANDCONDITIONSOFSALEFORSUCHPRODUCTS,INTELASSUMESNOLIABILITYWHATSOEVER,ANDINTELDISCLAIMS
ANYEXPRESSORIMPLIEDWARRANTY,RELATINGTOSALEAND/ORUSEOFINTELPRODUCTSINCLUDINGLIABILITYORWARRANTIES
RELATINGTOFITNESSFORAPARTICULARPURPOSE,MERCHANTABILITY,ORINFRINGEMENTOFANYPATENT,COPYRIGHTOROTHER
INTELLECTUALPROPERTYRIGHT.Intelproductsarenotintendedforuseinmedical,lifesaving,orlifesustainingapplications.
Intelmaymakechangestospecificationsandproductdescriptionsatanytime,withoutnotice.
Thisdocumentcontainsinformationonproductsinthedesignphaseofdevelopment.Theinformationhereissubjecttochangewithoutnotice.Donot
finalizeadesignwiththisinformation.
The128-Mbit1.8VoltIntel®WirelessFlashMemory+32-MbitPSRAMStacked-CSPfamilymaycontaindesigndefectsorerrorsknownaserrata
whichmaycausetheproducttodeviatefrompublishedspecifications.Currentcharacterizederrataareavailableonrequest.
ContactyourlocalIntelsalesofficeoryourdistributortoobtainthelatestspecificationsandbeforeplacingyourproductorder.
Copiesofdocumentswhichhaveanorderingnumberandarereferencedinthisdocument,orotherIntelliteraturemaybeobtainedbycalling1-800-
548-4725orbyvisitingIntel'swebsiteathttp://www.intel.com.
Copyright©IntelCorporation,2003.
*Othernamesandbrandsmaybeclaimedasthepropertyofothers.
Datasheet 3
Contents
1.0 Introduction ...............................................................................................................................7
1.1 Nomenclature .......................................................................................................................7
1.2 Conventions..........................................................................................................................7
2.0 ProductDescription ...............................................................................................................9
2.1 ProductOverview .................................................................................................................9
2.2 BalloutDiagram..................................................................................................................10
2.3 SignalDescriptions.............................................................................................................11
2.4 BlockDiagram ....................................................................................................................13
2.5 FlashMemoryMapandPartitioning...................................................................................13
3.0 DeviceOperation...................................................................................................................15
3.1 BusOperations...................................................................................................................15
3.2 FlashCommandDefinitions................................................................................................17
4.0 FlashReadOperations........................................................................................................17
5.0 FlashProgramOperations ................................................................................................17
6.0 FlashEraseOperations ......................................................................................................17
7.0 FlashSecurityModes..........................................................................................................17
8.0 FlashReadConfigurationRegister................................................................................17
9.0 FlashPowerConsumption................................................................................................17
10.0 ElectricalSpecifications.....................................................................................................18
10.1 AbsoluteMaximumRatings................................................................................................18
10.2 OperatingConditions..........................................................................................................19
10.3 Capacitance........................................................................................................................19
10.4 DCCharacteristics..............................................................................................................20
11.0 ACCharacteristics................................................................................................................21
11.1 FlashACCharacteristics....................................................................................................21
11.2 PSRAMACCharacteristics ................................................................................................22
12.0 PSRAMOperations...............................................................................................................26
12.1 Power-upSequenceandInitialization ................................................................................26
12.2 ModeRegister ....................................................................................................................26
12.2.1 ModeRegisterSetting...................................................................................................27
12.2.2 CautionsforsettingModeRegister ...............................................................................28
12.3 LowPowermode................................................................................................................29
AppendixAWriteStateMachine .............................................................................................30
AppendixBCommonFlashInterface....................................................................................30
AppendixCFlashFlowcharts...................................................................................................30
AppendixDMechanicalPackageInformation ...................................................................31
4Datasheet
AppendixEAdditionalInformation ........................................................................................33
AppendixFOrderingInformation............................................................................................34
Datasheet 5
RevisionHistory
Dateof
Revision Version Description
02/12/03 -001 InitialRelease,StackedChipScalePackage
6Datasheet
Datasheet 7
1.0 Introduction
Thisdocumentcontainsinformationpertainingtothe128-Mbit1.8VoltIntel®WirelessFlash
Memory(W18)+32-MbitPSRAMStacked-CSPfamily.Theintentofthisdocumentistoprovide
informationwherethisStacked-CSPdevicediffersfromthediscrete1.8VoltIntel®WirelessFlash
Memorydevice.Refertothelatestrevision1.8VoltIntel®WirelessFlashMemoryDatasheet
(ordernumber290701)forflashproductdetailsnotincludedinthisdocument.
1.1 Nomenclature
0x Hexadecimalprefix
0b Binaryprefix
Byte 8bits
CUI CommandUserInterface
DU DoNotUse
ETOX EPROMTunnelOxide
k(noun) 1thousand
Kb 1024bits
KB 1024bytes
Kword 1024words
M(noun) 1million
Mb 1,048,576bits
MB 1,048,576bytes
OTP OneTimeProgrammable
PLR ProtectionLockRegister
PR ProtectionRegister
PRD ProtectionRegisterData
RCR ReadConfigurationRegister
RFU ReservedforFutureUse
Stacked-CSP StackedChipScalePackage
SR StatusRegister
SRD StatusRegisterData
Word 16bits
1.2 Conventions
GroupMembershipBrackets:Squarebracketswillbeusedtodesignategroupmembershiporto
defineagroupofsignalswithasimilarfunction,suchasA[21:1]andSR[4,1],for
example.
VCCvs.VCC:Whenreferringtoasignalorpackage-connectionname,thenotationusedisVCC,
etc.Whenreferringtoatimingorelectricallevel,thenotationusedissubscriptedsuchas
VCC,etc.
Device:Thistermisusedinterchangeablythroughoutthisdocumenttodenoteeitheraparticular
die,orthecombinationofthetriple-die.
8Datasheet
CE#[2:1],OE#[2:1]:Thisisthemethodusedtorefertomorethanonechip-enableoroutput
enableatthesametime.Wheneachisreferredtoindividually,thereferencewillbeCE#1
andOE#1(fordie#1),andCE#2andOE#2(fordie#2).
VCC,P-VCC,S-VCC:Whenreferencingflashmemorysignalsortimings,thenotationusedis
VCCorVCC,respectively.WhenthereferenceistoPSRAMsignalsortimings,the
notationisprefixedwith“P-”(e.g.,P-VCC,P-VCC).WhenreferencingSRAMsignalsor
timings,thenotationisprefixedwith“S-”(e.g.,S-VCCorS-VCC).
R-OE#,R-LB#,R-UB#,R-WE#:UsedtoidentifyOE#,LB#,UB#,WE#RAMsignals,andare
usuallysharedbetween1or2RAMdie.
Datasheet 9
2.0 ProductDescription
Thissectionprovidesanoverviewofthefeaturesandcapabilitiesofthe128-Mbit1.8VoltIntel®
WirelessFlashMemory+32-MbitPSRAMStacked-CSPfamily.
2.1 ProductOverview
The128-Mbit1.8VoltIntel®WirelessFlashMemory+32-MbitPSRAMStacked-CSPfamily
encompassesmultipleflashmemory+32-MbitPSRAMdiecombinations.Productsrangefroma
flash-only,single-diedevicetoatriple-die,dualflash+32-MbitPSRAMdevice.Theusercan
choose32-MbitPSRAMcombinedwithoneortwoflashmemorydies,allofferedinthesame
packagefootprintandsignalballout.
Table1summarizesthe128-Mbit1.8VoltIntel®WirelessFlashMemory+32-MbitPSRAM
Stacked-CSPfamilyofferings.
NOTES:
1. W18=1.8VoltIntel®WirelessFlashMemory.
2. T/B=ToporBottomboot;B=Bottomboot(flashdie#1);T=Topboot(flashdie#2)
Table1. Stacked-CSPFamilyMatrix
LineItem FlashDie#1 FlashDie#2 RAMDie PackageSize(mm) Notes
1 28F128W18T/B None None 8x10x1.2 1
2 28F128W18T/B None 32MPSRAM 8x10x1.2 1
3 28F128W18B 28F640W18T None 8x10x1.2 1,2
4 28F128W18B 28F640W18T 32MPSRAM 8x10x1.4 1,2
5 28F128W18B 28F128W18T None 8x10x1.2 1,2
6 28F128W18B 28F128W18T 32MPSRAM 8x10x1.4 1,2
10 Datasheet
2.2 BalloutDiagram
The1.8VoltIntel®WirelessFlashMemory+32-MbitPSRAMStacked-CSPfamilyisavailablein
an88-ball(80-activeball)StackedChip-ScalePackage(CSP)withaballpitchof0.8mm.Figure1
showstheballoutdiagramforthe1.8VoltIntel®WirelessFlashMemory+32-MbitPSRAM
Stacked-CSPfamilydevices.
Figure1.88-Ball(80-ActiveBall)Stacked-CSPPackageBallout
NOTE:Solidballsareshownasballoutdifferencesbetweenvariousstackedcombinations
acrosstheStacked-CSPFamily.SeeSignalDescriptionsfordetailsontheelectrical
connectionsperstackedcombination.
TopView-BallSideDown
87654321
A
B
C
D
E
F
G
H
J
K
L
M
DU
A4
DU DU DU
DUDUDU DU
A5
A3
A2 A7
A1 A6
A0
A18 A19 VSS
VSSA23
A24
A25
A17
VCC2
CLK
A21
A22 A12
A11
A13A9P-CS#
VPP,
VPEN
A20 A10 A15
WE# A8
D8 D2 D10 D5 D13 WAIT
A14 A16
CE#1 P-Mode
VSS VSS VSS
RFU
VCC1
VCC2 VCCQRFU
D0 D1
D9
D3
D4 D6
D7
D15D11
D12 D14
OE#1
OE#2
P-VCC
S-CS2
R-WE#
R-UB#
R-LB#
R-OE#
S-VCC
S-CS1#
VCC1
WP# ADV#
RST#
CE#2
VCCQ
VSS VSSVCCQ VSS
BottomView-BallSideUp
87654321
A
B
C
D
E
F
G
H
J
K
L
M
DU
A4
DUDUDU
DU DU DUDU
A5
A3
A2A7
A1A6
A0
A18A19VSS
VSS A23
A24
A25
A17
VCC2
CLK
A21
A22A12
A11
A13 A9 P-CS# VPP,
VPEN
A20A10A15
WE#A8
D8D2D10D5D13WAIT
A14A16
CE#1P-Mode
VSSVSSVSS
RFU
VCC1
VCC2VCCQ RFU
D0D1
D9
D3
D4D6
D7
D15 D11
D12D14
OE#1
OE#2
P-VCC
S-CS2
R-WE#
R-UB#
R-LB#
R-OE#
S-VCC
S-CS1#
VCC1
WP#ADV#
RST#
CE#2
VCCQ
VSSVSS VCCQVSS
Datasheet 11
2.3 SignalDescriptions
Table2describestheactivesignalsusedonthe128-Mbit1.8VoltIntel®WirelessFlashMemory
+32-MbitPSRAMStacked-CSPfamily.
Table2. SignalDescriptions(Sheet1of2)
Symbol Type Descriptions
A[Max:0] Input
ADDRESSINPUTSformemoryaddressesofaSCSPdevicewith:
•32-Mbitdensity:A[Max]=A20
•64-Mbitdensity:A[Max]=A21
•128-Mbitdensity:A[Max]=A22
D[15:0] Input/
Output
DATAINPUTS/OUTPUTS:Inputsdataandcommandsduringwritingcycles,outputsdata
duringmemory,statusregister,protectionregisterandconfigurationcodereads.These
signalsfloatwhenthedieoroutputsaredeselected.Dataisinternallylatchedduring
writes.
CE#1
CE#2 Input
FLASHCHIPENABLE:CE#-lowselectstheflashcomponent.Whenasserted,theflash
internalcontrollogic,inputbuffers,decoders,andsenseamplifiersareactivated.When
deasserted,theflashdieisdeselected,powerreducestostandbylevels,anddataand
WAIToutputsareplacedinhigh-Zstate.
CE#1connectstoflashdie#1ChipEnablewhileCE#2connectstoflashdie#2Chip
Enable.CE#2isonlyconnectedforstackedcombinationswith2flashdies.
RST# Input
FLASHRESET:RST#-lowresetsflashinternalcircuitryandinhibitswriteoperations.This
functionmaybeemployedtoprovidedataprotectionduringpowertransitions.After
exitingtheresetstate(RST#returnedtologic-high),theselectedflashdieresumes
operationinasynchronousread-arraymode.
OE#1
OE#2 Input
FLASHOUTPUTENABLE:OE#-lowactivatesdeviceoutputthroughtheflashdata
buffersduringaflashreadcycle.Whendeasserted,theflashoutputstri-statetohigh-Z.
OE#1connectstoflashdie#1OutputEnablewhileOE#2connectstoflashdie#2Output
Enable.OE#2isonlyconnectedforstackedcombinationswith2flashdies.
WE# Input FLASHWRITEENABLE:WE#controlswritestotheselectedflashdie.WE#-lowallows
inputtotheflashCUI,array,PR/PLR,RCR,orblocklockbits.Addressesanddataare
latchedonthissignal’srisingedge.
ADV# Input
FLASHADDRESSVALID:ADV#indicatesvalidaddresspresenceonaddressinputsof
theselectedflashdie.Duringsynchronousreadoperations,alladdressesarelatchedon
ADV#’srisingedgeorCLK’srising(orfalling)edge,whicheveroccursfirst.
CLK Input
FLASHCLOCK:CLKsynchronizestheselectedflashdietothesystembusfrequencyin
synchronous-readconfigurationandincrementsaninternalburstaddressgenerator.
Duringsynchronousreadoperations,addressesarelatchedonADV#’srisingedgeor
CLK’srising(orfalling)edge,whicheveroccursfirst.
CLKisonlyusedforsynchronousmode.Refertoflashproductdiscretedatasheetfor
informationhowtousethissignalinasynchronousmode.
WAIT Output
FLASHWAIT:WaitisdrivenwhenCE#isasserted.FlashRCR[10][WP]determinesthe
WAITassertedlogiclevel.
•Insynchronousarrayreadmodes,WAITindicatesinvaliddatawhenassertedand
validdatawhende-asserted.
•Insynchronousnon-arrayreadmodes,asynchronouspagemode,andallwrite
modes,WAITisasserted.
Refertoflashproductdiscretedatasheetformoreinformation.
12 Datasheet
WP# Input
FLASHWRITEPROTECT:Enables/disablesthelock-downmechanismoftheselected
flashdie.
WhenWP#islogiclow,thelock-downmechanismisenabledandblocksmarkedlock-
downcannotbeunlockedthroughsoftware.
VPP Power FLASHPROGRAM/ERASESUPPLY:ValidVppvoltageonthisballallowblockerase
andprogramfunctions.FlashmemoryarraycontentscannotbealteredwhenVPP<VPPLK.
BlockEraseandprogramatinvalidVPPVoltageshouldnotbeattempted.
VCC1
VCC2 Power FLASHPOWERSUPPLY:Suppliespowertotheflashcore.VCC1connectstoflash
die#1powersupplywhileVCC2connectstoflashdie#2powersupply.
VCC2isonlyconnectedforstackedcombinationswith2flashdies.
VCCQ Power OUTPUTBUFFERPOWERSUPPLY:Suppliespowerfortheinputandoutputbuffers.
VSS Power GROUND:DonotfloatanyVSSconnection.
S-CS1#
S-CS2 Input
SRAMCHIPSELECTS:ActivatestheSRAMinternalcontrollogic,inputbuffers,
decoders,andsenseamplifiers.Wheneitheraredeasserted(S-CS1#=VIHorS-CS2=
VIL),theSRAMisdeselectedanditspowerreducestostandbylevels.
S-CS1#andS-CS2areonlyconnectedforstackedcombinationswithSRAMdie.
R-OE# Input
RAMOUTPUTENABLE:R-OE#-lowactivatesdeviceoutputthroughtheselectedRAM
databuffersduringaRAMreadcycle.Whendeasserted,theselectedRAMoutputstri-
statetohigh-Z.
R-OE#isonlyconnectedforstackedcombinationswith1ormoreRAMdie.
R-WE# Input RAMWRITEENABLE:R-WE#-lowallowswritestotheselectedRAMarray.
R-WE#isonlyconnectedforstackedcombinationswith1ormoreRAMdie.
R-UB#
R-LB# Input RAMUPPER/LOWERBYTEENABLES:R-UB#-lowenablestheselectedRAMhigh-
orderbytes(D[15:8]).R-LB#-lowenablestheselectedRAMlow-orderbytes(D[7:0]).
R-UB#andR-LB#areonlyconnectedforstackedcombinationswith1ormoreRAMdie.
S-VCC Power SRAMPOWERSUPPLY:SuppliespowerforSRAMoperations.
S-VCCisonlyconnectedforstackedcombinationswithSRAMdie.
P-CS# Input
PSRAMCHIPSELECT:ActivatesthePSRAMinternalcontrollogic,inputbuffers,
decoders,andsenseamplifiers.Whendeasserted,thePSRAMisdeselectedandits
powerreducestostandbylevels.
P-CS#isonlyconnectedforstackedcombinationswithPSRAMdie.
P-Mode Input PSRAMREFRESH:Whendeasserted,itenablesPSRAMLowerPowerModewithpartial
arrayrefreshorzeroarrayrefreshaccordingtotheModeregistersetting.
P-ModeisonlyconnectedforstackedcombinationswithPSRAMdie.
P-VCC Power PSRAMPOWERSUPPLY:SuppliespowerforPSRAMoperations.
P-VCCisonlyconnectedforstackedcombinationswithPSRAMdie.
RFU RESERVEDforFUTUREUSE:DonotdriveRFUballsandleavethemdisconnected.
ContactIntelregardingtheirfutureuse.
DU DONOTUSE:Donotconnecttoanyothersignal,orpowersupply;mustbeleftfloating.
Table2. SignalDescriptions(Sheet2of2)
Symbol Type Descriptions
Datasheet 13
2.4 BlockDiagram
Figure2isablockdiagramshowingallinternalpackageconnectionsfortheStacked-CSPfamily
withmultipledies.RefertoTable 1,“Stacked-CSPFamilyMatrix”onpage 9forvalid
combinationsofflashandPSRAMdie.Unusedconnectionsoncombinationswithlessthantriple
diearereservedandshouldnotbeused.
2.5 FlashMemoryMapandPartitioning
Consultthelatest1.8VoltIntel®WirelessFlashMemoryDatasheet(ordernumber290701)for
individualflashdiememorymapandpartitioninginformation.
RefertoTable 1,“Stacked-CSPFamilyMatrix”onpage 9forvalidconfigurationsperstacked
combination.Table3andTable4showstheMemoryMapandPartitioninginformationfortwo
flashmemorydie.Flashdie#1(withCE#1asitsChipSelect)isconfiguredtobottombootwhile
flashdie#2(withCE#2asitsChipSelect)isconfiguredtotopboot.
Figure2.BlockDiagram
FlashDie#2
PSRAMDie
FlashDie#1
VCC2
P-VCC
CE#2
OE#2
R-WE#
R-UB#
R-LB#
P-MODE
VSS
VCC1
CE#1
OE#1
A[MAX:0]
P-CS#
R-OE#
A[MAX:0] D[15:0]
CLK
WP#
ADV#
RST#
WE#
VCCQ
VPP
WAIT
14 Datasheet
Table3. 128W18B+128W18TDual-FlashDieSCSPMemoryMapandPartitioning
Flash
Die# Partitioning BlockSize
(KW) Blk# AddressRange
Flashdie#2(TopBoot)
128M-bit
ParameterPartition OnePartition 4 255-262 7F8000-7FFFFF
32 248-254 7C0000-7F7FFF
MainPartitions
OnePartition 32 240-247 780000-7BFFFF
OnePartition 32 232-239 740000-77FFFF
OnePartition 32 224-231 700000-73FFFF
FourPartitions 32 192-223 600000-6FFFFF
EightPartitions 32 128-191 400000-5FFFFF
SixteenPartitions 32 0-127 000000-3FFFFF
Flashdie#1(BottomBoot)
128-Mbit
MainPartitions
SixteenPartitions 32 135-262 400000-7FFFFF
EightPartitions 32 71-134 200000-3FFFFF
FourPartitions 32 39-70 100000-1FFFFF
OnePartition 32 31-38 0C0000-0FFFFF
OnePartition 32 23-30 080000-0BFFFF
OnePartition 32 15-22 040000-07FFFF
ParameterPartition OnePartition 32 8-14 008000-03FFFF
4 0-7 000000-007FFF
Table4. 128W18B+64W18TDual-FlashDieSCSPMemoryMapandPartitioning
Flash
Die# Partitioning BlockSize
(KW) Blk# AddressRange
Flashdie#2(TopBoot)
64-Mbit
ParameterPartition OnePartition 4 127-134 3F8000-3FFFFF
32 120-126 3C0000-3F7FFF
MainPartitions
OnePartition 32 112-119 380000-3BFFFF
OnePartition 32 104-111 340000-37FFFF
OnePartition 32 96-103 300000-33FFFF
FourPartitions 32 64-95 200000-2FFFFF
EightPartitions 32 0-63 000000-1FFFFF
Flashdie#1(BottomBoot)
128-Mbit
MainPartitions
SixteenPartitions 32 135-262 400000-7FFFFF
EightPartitions 32 71-134 200000-3FFFFF
FourPartitions 32 39-70 100000-1FFFFF
OnePartition 32 31-38 0C0000-0FFFFF
OnePartition 32 23-30 080000-0BFFFF
OnePartition 32 15-22 040000-07FFFF
ParameterPartition OnePartition 32 8-14 008000-03FFFF
4 0-7 000000-007FFF
Datasheet 15
3.0 DeviceOperation
3.1 BusOperations
Busoperationsforthe128-Mbit1.8VoltIntel®WirelessFlashMemory+32-MbitPSRAM
Stacked-CSPfamilyinvolvethemultiplecontrolchipenable(CE#1forflashdie#1andCE#2for
flashdie#2)andoutputenable(OE#1forflashdie#1andOE#2forflashdie#2)signals.Allother
controlsignalsaresharedbetweenthetwoflashdie.Table5toTable6explainsthebusoperations
ofproductsacrossthisSCSPfamily.RefertotheW18datasheet(ordernumber290701)forsingle
flashdieSCSPbusoperations.
Table5. FlashDie#1+FlashDie#2BusOperations
Device
Mode
RST#
CE#1
OE#1
WE#
ADV
VPP
WAIT
CE#2
OE#2
D[15:0]
Notes
FlashDie#1Enabled
SyncArrayRead H L L H L X Active H X Flash
DOUT 2,3,4
AllAsync/
SyncNon-Array
Read HLLHX XAssertedH X Flash
DOUT 1,3,4,5
Write H L H L X VPP1
or
VPP2 Asserted H X Flash
DIN 3,4,6
OutputDisable H L H H X X Active X X Flash
High-Z 4
Standby H H X X X X High-Z X X Flash
High-Z 4
Reset L X X X X X High-Z X X Flash
High-Z 4
FlashDie#2Enabled
SyncArrayRead H H X H L X Active L L Flash
DOUT 2,3,4
AllAsync/
SyncNon-Array
Read HHXHX XAsserted L L Flash
DOUT 1,3,4,5
Write HHXLX
VPP1
or
VPP2 Asserted L H Flash
DIN 3,4,6
OutputDisable H X X H X X Active L H Flash
High-Z 4
Standby H X X X X X High-Z H X Flash
High-Z 4
Reset L X X X X X High-Z X X Flash
High-Z 4
NOTES:
1. Forasynchronousreadoperation,bothdiemaybesimultaneouslyselected,butmaynotsimultaneouslydrivethe
memorybus.SeeSection3.2,“FlashCommandDefinitions”onpage 17fordetailsregardingFlashselectionoverlap.
2. WAITisonlyactiveduringsynchronousFlashreads.WAITisdrivenifCE#isasserted.Refertothe1.8-VoltIntel®
WirelessFlashMemorydatasheet(ordernumber290701)forfurtherinformationregardingWAITSignal.
3. ForeitherFlashdie,OE#1/OE#2andWE#shouldneverbeassertedsimultaneously.Ifdonesoonaparticularflashdie,
OE#1/OE#2willoverrideWE#.
4. LmeansVIL
whileHmeansVIH.XcanbeVILorVIHforinputs,VPP1,VPP2orVPPLKforVPP.
5. FlashCFIqueryandstatusregisteraccessesuseD[7:0]only,allotherreadsuseD[15:0].
6. RefertoW18datasheetforvalidDINduringFlashwrites.
16 Datasheet
Table6. Flash(SingleDie/DualDie)+PSRAMBusOperations
Device
Mode
RST#
CE#X
OE#X
WE#
ADV#
VPP
WAIT
P-CS#
P-Mode
R-OE#
R-WE#
R-UB#,
R-LB#
D[15:0]
Notes
FlashDie(#1or#2)Enabled
SyncArray
Read HLLHL X Active
PSRAMmustbeinHigh-Z
Flash
DOUT 1,2,3,
4,6
AllAsync/
SyncNon-
array
Read H L L H X X Asserted Flash
DOUT 1,2,3,
4,6,7
Write H L H L L VPP1
or
VPP2 Asserted Flash
DIN 3,4,6,
8
Output
Disable HLHHX X Active
AnyPSRAMmodeallowed
Flash
High-Z 6
Standby H H X X X X High-Z Flash
High-Z 6
Reset LXXXX XHigh-Z Flash
High-Z 6
PSRAMEnabled
Read FlashmustbeinHigh-Z
Note2
LHLHL
PSRAM
DOUT 1,5
Write L H H L L PSRAM
DIN 5
Output
Disable
Anyflashmodeallowed
LHHHX
PSRAM
High-Z 6
Standby H H X X X PSRAM
High-Z 6
Low
Power
Mode XLXXX
PSRAM
High-Z 6
NOTES:
1. Forasynchronousreadoperation,alldiesmaybesimultaneouslyselected,butmaynotsimultaneouslydrivethe
memorybus.Forsynchronousburst-modereads,onlytwodie(oneflashandthePSRAM)maybesimultaneously
selected.
2. WAITisonlyvalidduringsynchronousflashreads.RefertothediscretedatasheetfordetailedWaitfunctionality.
3. CE#XisCE#1forflashdie#1,CE#2forflashdie#2.OE#XisOE#1forflashdie#1,OE#2forflashdie#2.
4. Foreitherflashdie,OE#XandWE#shouldneverbeassertedsimultaneously.Ifdonesoonaparticularflashdie,
OE#XwilloverrideWE#.
5. ForPSRAM,R-OE#andR-WE#shouldneverbeassertedsimultaneously.
6. XcanbeVILorVIHforinputs,VPP1,VPP2orVPPLKforVPP.
7. FlashCFIqueryandstatusregisteraccessesuseD[7:0]only,allotherreadsuseD[15:0].
8. RefertoW18datasheetforvalidDINduringflashwrites.
Datasheet 17
3.2 FlashCommandDefinitions
Refertothe1.8VoltIntel®WirelessFlashMemoryDatasheet(ordernumber290701)for
informationregardingFlashCommandDefinitions.
4.0 FlashReadOperations
Refertothe1.8VoltIntel®WirelessFlashMemoryDatasheet(ordernumber290701)for
informationregardingFlashReadModesandOperations.
5.0 FlashProgramOperations
Refertothe1.8VoltIntel®WirelessFlashMemoryDatasheet(ordernumber290701)for
informationregardingFlashProgramOperations.
6.0 FlashEraseOperations
Refertothe1.8VoltIntel®WirelessFlashMemoryDatasheet(ordernumber290701)for
informationregardingFlashEraseOperations.
7.0 FlashSecurityModes
Refertothe1.8VoltIntel®WirelessFlashMemoryDatasheet(ordernumber290701)for
informationregardingFlashSecurityModesandOperations.
8.0 FlashReadConfigurationRegister
Refertothe1.8VoltIntel®WirelessFlashMemorydatasheet(ordernumber290701)for
informationregardingFlashReadConfigurationRegister(RCR)functionsandprogramming.
9.0 FlashPowerConsumption
Refertothe1.8VoltIntel®WirelessFlashMemoryDatasheet(ordernumber290701)for
informationregardingFlashPowerConsiderationsandConsumption.
18 Datasheet
10.0 ElectricalSpecifications
10.1 AbsoluteMaximumRatings
Warning: Stressingthedevicebeyondthe“AbsoluteMaximumRatings”maycausepermanentdamage.
Thesearestressratingsonly.Operationbeyondthe“OperatingConditions”isnotrecommended
andextendedexposurebeyondthe“OperatingConditions”mayaffectdevicereliability.
NOTICE:Thisdocumentcontainsinformationavailableatthetimeofitsrelease.Thespecificationsare
subjecttochangewithoutnotice.VerifywithyourlocalIntelsalesofficethatyouhavethelatestdatasheet
beforefinalizingadesign.
Table7. AbsoluteMaximumRatings
Parameter Min Max Unit Notes
TemperatureunderBiasExpanded –25 +85 °C
StorageTemperature –55 +125 °C
VoltageOnAnySignal(exceptVCC1,VCC2,
VCCQ,
VPP,
andP-VCC) –0.5 +2.45 V 1
VCC1andVCC2
Voltage –0.2 +2.45 V 1
VCCQ,andP-VCCVoltage –0.2 +2.45 V 1
VPP
Voltage –0.2 +14.0 V 1,2,3
IshOutputShortCircuitCurrent – 100 mA 4
NOTES:
1. AllSpecifiedvoltagesarerelativetoVSS.MinimumDCvoltageis–0.5Voninput/outputsignals,–0.5V
onVCCandVPPsignals.Duringtransitions,thislevelmayovershootto–2.0Vforperiods<20ns,
duringtransitions,mayovershoottoVCC+2.0Vforperiods<20ns.
2. MaximumDCvoltageonVPPmayovershootto+14.0Vforperiods<20ns.
3. VPPprogramvoltageisnormallyVPP1.ThemaximumDCvoltageonVPPmayovershootto+14Vfor
periods<20ns.VPPcanbeVPP2for1000erasecyclesonmainblocks,2500cyclesonparameter
blocks.
4. Outputshortedfornomorethanonesecond.Nomorethanoneoutputshortedatatime.
Datasheet 19
10.2 OperatingConditions
10.3 Capacitance
Table8. ExtendedTemperatureOperation
Symbol Parameter
Flash/
Flash+Flash Flash+PSRAM/
Flash+Flash+PSRAM
Unit
Min Max Min Max
TCOperatingTemperature –40 +85 –25 +85 °C
VCC FlashSupplyVoltage 1.7 1.95 1.7 1.95 V
VCCQ
P-VCC
FlashI/OVoltage
PSRAMSupplyVoltage 1.7 2.24 1.8 1.95 V
VPP1 FlashProgramLogicLevel 0.9 1.95 0.9 1.95 V
VPP2 FlashFactoryProgram
Voltage 11.4 12.6 11.4 12.6 V
NOTE: VPPisnormallyVPP1.VPPcanbeconnectedto11.4V–12.6Vfor1000cyclesonmainblocksfor
extendedtemperaturesand2500cyclesonparameterblocksatextendedtemperature.
NOTICE:Refertothe1.8-VoltIntel®WirelessFlashMemorydatasheet(ordernumber290701)
forflashcapacitancedetails.ForSCSPproductswithtwoflashdie,flashcapacitancesfor
eachoftheflashdieneedtobeconsideredaccordingly.
Table9. PSRAMCapacitance
Symbol Parameter Max Unit Condition
CIN InputCapacitance 8 pF TC=25°C,f=1MHz,
VIN=0V
CI/O Input/OutputCapacitance 10 pF
20 Datasheet
10.4 DCCharacteristics
32-MbitPSRAMDCcharacteristicsareshowninTable10.Refertothe1.8VoltIntel®Wireless
FlashMemorydatasheet(ordernumber290701)forFlashDCCharacteristics.
NOTICE:DCCharacteristicsofalldieinaSCSPdeviceneedtobeconsideredaccordingly,
dependingontheSCSPdeviceoperation.
Table10.PSRAMDCCharacteristics
Parameter Description TestConditions Min Typ Max Unit
P-VCC VoltageRange 1.8 – 1.95 V
ICC Operating
CurrentatMin
cycletime II/O=0mA – – 35 mA
ISB1 StandbyCurrent P-CS#>P-VCC-0.2V,P-Mode>P-VCC-0.2V – 90 100
µA
ISB2 LowPowerMode P-CS#>P-VCC-0.2V,P-
Mode<0.2V
16Mbits – 60 70
8Mbits – 50 60
4Mbits – 40 50
0Mbits – 20 30
VOH OutputHigh
Voltage IOH
=-0.5mA 0.8P-Vcc – – V
VOL OutputLow
Voltage IOL
=1mA – – 0.2P-Vcc V
VIH InputHigh
Voltage 0.8P-Vcc – P-VCC+0.3 V
VIL InputLow
Voltage -0.3 – 0.2P-VCC V
*IIL InputLeakage
Current VIN=0VtoP-Vcc –1.0 – +1.0 µA
*IOL Input/Output
LeakageCurrent VI/O=0VtoP-Vcc,P-CS#=VIHorR-WE#=VIH
or
R-OE#=VIH –1.0 – +1.0
*VIN:Inputvoltage,VI/O:Input/Outputvoltage
Datasheet 21
11.0 ACCharacteristics
11.1 FlashACCharacteristics
Refertothe1.8-VoltIntel®WirelessFlashMemorydatasheet(ordernumber290701)forFlashAC
CharacteristicsdetailsnotincludedinTable11below.
Table11.FlashACReadCharacteristics
Sym Parameter 128W18 64W18 Unit
Min Max Min Max
AsynchronousSpecifications
tAVAV ReadCycleTime 65 65 ns
tAVQV AddresstoOutputDelay 65 65 ns
tELQV CE#LowtoOutputDelay 65 65 ns
tVLQV ADV#LowtoOutputDelay 65 65 ns
LatchingSpecifications
tAPA PageAddressAccessTime 25 25 ns
ClockSpecifications
tCHQV CLKtoOutputDelay 14 14 ns
22 Datasheet
11.2 PSRAMACCharacteristics
Table12.PSRAMACCharacteristics—Read-OnlyOperations
# Symbol Parameter 32M Unit Note
Min Max
ReadCycle
R1 tRC ReadCycleTime 85 – ns
R2 tAA Addressaccesstime – 85 ns
R3 tCO P-CS#LowtoOutputValid – 85 ns
R4 tOE R-OE#LowtoOutputValid – 65 ns
R5 tBA R-UB#,R-LB#LowtoOutputValid – 85 ns
R6 tLZ P-CS#LowtoOutputinLow-Z 10 – ns
R7 tOLZ R-OE#LowtoOutputinLow-Z 5 – ns
R8 tHZ P-CS#HightoOutputinHigh-Z – 25 ns
R9 tOHZ R-OE#HightoOutputinHigh-Z – 25 ns
R10 tOH OutputHoldfromAddresschange 5 – ns
R11 tBLZ R-UB#,R-LB#LowtoOutputinLow-Z 5 – ns
R12 tBHZ R-UB#,R-LB#HightoOutputinHigh-Z – 25 ns
R13 tASO AddresssettoR-OE#lowlevel 0 – ns 1
R14 tOHAH R-OE#highleveltoaddresshold -5 – ns
R15 tCHAH P-CS#highleveltoaddresshold 0 – ns 1
R16 tBHAH R-LB#,R-UB#highleveltoaddresshold 0 – ns 1,2
R17 tCLOL P-CS#lowleveltoR-OE#lowlevel 0 10,000 ns 3
R18 tOLCH R-OE#lowleveltoP-CS#highlevel 60 – ns
R19 tCP P-CS#highlevelpulsewidth 10 – ns
R20 tBP R-UB#,R-LB#highlevelpulsewidth 10 – ns
R21 tOP R-OE#highlevelpulsewidth – 10,000 ns 3
PageMode
PR1 tPC PageCycleTime 30 – ns 4
PR2 tPA PageModeAddressAccessTime – 30 ns
NOTE:
1. WhenR13>|R15|,|R16|.TheminimumofR15andR16are-15ns.(SeeFigure3,“Conditionsfor
CalculatingR15andR16MinimumValues”onpage 22.)
2. R16isspecifiedfromwhenbothR-LB#andR-UB#becomehighlevel.
3. R17andR21(MAX)areappliedwhileP-CS#isbeingholdatlowlevel.
4. SeeFigure5,“ACWaveformofPSRAMReadOperations”onpage 24.
Figure3.ConditionsforCalculatingR15andR16MinimumValues
Address
R-UB#,R-LB#,
P-CS#
R15,R16
R13R-OE#
Datasheet 23
Table13.PSRAMACCharacteristics—WriteOperations
# Symbol Parameter 32M Unit Note
Min Max
W1 tWC WriteCycleTime 85 – ns
W2 tAS AddressSetupTime 0 – ns
W3 tWP WritePulseWidth 60 – ns
W4 tDW DatavalidtoWriteEnd 30 – ns
W5 tAW Addressvalidtoendofwrite 70 – ns
W6 tCW P-CS#toendofwrite 70 – ns
W7 tDH DataHoldtime 0 – ns
W8 tWR WriteRecovery 0 – ns
W9 tBW R-UB#,R-LB#SetuptoendofWrite 70 – ns
W10 tCP P-CS#Highlevelpulsewidth 10 – ns
W11 tBP R-UB#,R-LB#Highlevelpulsewidth 10 – ns
W12 tWHP R-WE#Highlevelpulsewidth 10 – ns
W13 tOHAH R-OE#Highleveltoaddresshold -5 – ns
W14 tCHAH P-CS#Highleveltoaddresshold 0 – ns 1
W15 tBHAH R-UB#,R-LB#Highleveltoaddresshold 0 – ns 1,2
W16 tOES R-OE#HighleveltoR-WE#set 0 10,000 ns 3
W17 tOEH R-WE#HighleveltoR-OE#set 10 10,000 ns
NOTES:
1. WhenW2>|W14|,|W15|andW10>18ns,W14andW15(MIN)are-15ns.(SeeFigure4,
“ConditionsforCalculatingW14andW15MinimumValues”onpage 23.)
2. W15isspecifiedfromwhenbothR-LB#andR-UB#becomehighlevel.
3. W16andW17(MAX)areappliedwhileP-CS#isbeingholdatlowlevel.
4. SeeFigure7,“ACWaveformPSRAMWriteOperation”.
Figure4.ConditionsforCalculatingW14andW15MinimumValues
Address
R-UB#,R-LB#,
P-CS#
W14,W15
W2R-WE#
W10
24 Datasheet
NOTE: Inreadcycle,P-ModeandR-WE#shouldbefixedtohighlevel
NOTE: Inpagereadcycle,P-ModeandR-WE#shouldbefixedtohighlevel,andR-UB#,R-LB#arelowlevel.
Figure5.ACWaveformofPSRAMReadOperations
R1
Vih
Vil R2
Vih R3
Vil R8
Vih R5
Vil R12
Vih R4
Vil R9
R7
R11
R6 R10
Voh High-Z High-Z
Vol
Data
out Valid
Output
Address
P-CS#
R-UB#,
R-LB#
R-OE#
Figure6.ACWaveformofPSRAM8-WordPageReadOperation
Vih
A3-A
MAX
Valid
Vil Address
Vih
A0,A1,A2 Vil 000
R2 PR1
P-CS# R3
PR2R-OE#,
R-UB#,
R-LB# R4
R9
Voh High-Z Qn
Vol
Dataout Qn+
7
Qn+
6
001 111
R1
Datasheet 25
NOTES:
1. Duringaddresstransition,atleastoneofpinsP-CS#,R-WE#,orbothofR-UB#andR-LB#pinsshouldbe
inactivated.
2. DonotinputdatatotheI/Opinswhiletheyareintheoutputstate.
3. Inwritecycle,P-ModeandR-OE#shouldbefixedtohighlevel.
4. WriteoperationisdoneduringtheoverlaptimeofalowlevelP-CS#,R-WE#,R-LB#and/orR-UB#.
Figure7.ACWaveformPSRAMWriteOperation
W1
Vih
Vil W2 W8
Vih W6
Vil
W5
Vih W9
Vil
Vih W3
Vil
Voh W4 W7
High-Z High-Z
Vol
Address
P-CS#
R-UB#,
R-LB#
R-WE#
DataI/O ValidDataIn
Low-Z
26 Datasheet
12.0 PSRAMOperations
12.1 Power-upSequenceandInitialization
ThePSRAMfunctionalityandreliabilityareindependentofthepower-upslewrateofthecoreP-
VCC.Anypower-upslewrateispossibleunderuseconditions.
Thefollowingpowerupsequenceandoperationshouldbeusedbeforestartingnormaloperation.
ThePSRAMpower-upsequenceisrepresentedinFigure8.Followingpowerapplication,makeP-
ModehighlevelafterfixingP-ModetolowlevelfortheperiodoftVHMH.MakeP-CS#highlevel
beforemakingP-Modehighlevel.Then,P-CS#andP-Modearefixedtohighlevelfortheperiod
oftMHCL.
NormalOperationispossibleoncethepowerupsequenceiscomplete.
NOTES:
1. MakeP-Modelowlevelwhenstartingthepowersupply.
2. tVHMH
isspecifiedfromwhenthepowersupplyvoltagereachestheprescribedminimumvalue(P-Vcc
(MIN))
12.2 ModeRegister
ThePSRAMdiehasaninternalregisterthathelpscontroltheLowPowermodeofthePSRAM.
ThisregisteriscalledtheModeregister.Thedensitiesthatcanbeselectedforperformingrefresh
are16Mbits,8Mbits,4Mbitsand0Mbit.Thedensityforperformingrefreshcanbesetwiththe
Moderegister.OncetherefreshdensityhasbeensetintheModeregister,thesesettingsare
retaineduntiltheyaresetagain,whileapplyingthepowersupply.However,theModeregister
settingwillbecomeundefinedifthepoweristurnedoff,sosettheModeregisteragainafterpower
application.
Figure8.TimingWaveformforPowerupsequence
tVHMH
tMHCL
tCHMH
Initialization
Vcc(MIN)
NormalOperation
P-CS#
P-Mode
P-Vcc
Table14.Initializationtiming
Parameter Symbol MIN MAX Unit
PowerapplicationtoP-Modelowlevelhold tVHMH 50 us
P-CS#highleveltoP-Modehighlevel tCHMH 0ns
Followingpowerapplication,P-Modehighlevel
holdtoP-CS#lowlevel tMHCL 200 us
Datasheet 27
12.2.1 ModeRegisterSetting
SincetheinitialvalueoftheModeregisteratpowerapplicationisundefined,besuretosetthe
Moderegisterafterinitializationatpowerapplication.Whensettingthedensityofpartialrefresh,
databeforeenteringtheLowPowerModeisnotguaranteed.(Thisisthesameforresetup)
However,sinceLowPowerModeisnotenteredunlessP-Mode=L,whenpartialrefreshisnot
used,itisnotnecessarytosettheModeregister.Moreover,whenusingpagereadwithoutusing
partialrefresh,itisnotnecessarytosettheModeregister.
TheModeregistersettingmodecanbeenteredbysuccessivelywritingtwospecificdataaftertwo
continuousreadsofthehighestaddress.TheModeregistersettingisacontinuousfour-cycle
operation-tworeadcyclesandtwowritescycles.SeeTable15forsettingModeregistercommand
sequence.
Forthetimingchartandflowchart,refertoFigure9andFigure10.
AMAX-A5,aregisterprogramming.
Table15.SettingModeRegisterCommandSequence
Command
Sequence 1stBusCycle
(ReadCycle) 2ndBusCycle
(ReadCycle) 3rdBusCycle
(WriteCycle) 4thBusCycle
(WriteCycle)
Partialrefresh
density Address Data Address Data Address Data Address Data
16Mbits Highest
Address _Highest
Address _Highest
Address 00H Highest
Address 04H
8Mbits Highest
Address _Highest
Address _Highest
Address 00H Highest
Address 05H
4Mbits Highest
Address _Highest
Address _Highest
Address 00H Highest
Address 06H
0Mbit Highest
Address _Highest
Address _Highest
Address 00H Highest
Address 07H
Figure9.ModeRegisterUpdate--TimingWaveform
HighestAddress HighestAddress HighestAddress HighestAddress
0000H 000XH
W7
W4W7W4
W8
W3
W8
W3
ModeRegisterSetting
W1W1W1W1R1R1R1R1
Address
P-CS#
R-OE#
R-WE#
DataI/O
R-UB#,R-LB#
28 Datasheet
NOTE: xxH=04H,05H,06Hor07H
12.2.2 CautionsforsettingModeRegister
Since,fortheModeregistersetting,theinternalcounterstatusisjudgedbytogglingP-CS#andR-
OE#,toggleP-CS#ateverycycleduringentry(readcycletwice,writecycletwice),andtoggleR-
OE#likeP-CS#atthefirstandsecondreadcycles.Ifincorrectaddressesordataarewritten,orif
addressesordataarewrittenintheincorrectorder,thesettingoftheModeregisterisnotperformed
correctly.
Whenthehighestaddressisreadconsecutivelythreeormoretimes,theModeregistersetting
entriesarenotperformedcorrectly.(Immediatelyafterthehighestaddressisread,thesettingofthe
Moderegisterisnotperformedcorrectly.)PerformthesettingoftheModeregisterafterpower
applicationorafteraccessingotherthanthehighestaddress.
OncetherefreshdensityhasbeensetintheModeregister,thesesettingsareretaineduntiltheyare
setagain,whileapplyingthepowersupply.However,theModeregistersettingwillbecome
undefinedifthepoweristurnedoff,sosettheModeregisteragainafterpowerapplication.
Figure10.ModeRegisterSettingFlowChart
Data=00H
WritetoHighestAddress
Data=xxH
BeginNormal
Operation
ReadHighestAddress
byTogglingbothP-CS#
andR-OE#
START
WritetoHighestAddress
ReadHighestAddress
byTogglingbothP-CS#
andR-OE#
Fail
ModeRegister
settingexit
No
No
No
No
No
No
Datasheet 29
12.3 LowPowermode
InadditiontotheregularStandbymodewithafulldensitydatahold,LowPowermodeperforms
partialdensitydatarefreshorzerodensitydatarefresh.
TheLowPowermodeallowscustomerstoturnoffsectionsofthePSRAMdietosaverefresh
current.ThePSRAMdieisdividedintofoursectionsallowingcertainsectionstoberefreshedwith
P-ModetiedLow.
InregularStandbymode,bothP-CS#andP-Modearehighlevel.ButinLowPowermode,P-
Modeislowlevel.InLowPowermode,if0Mbitissetasthedensity,itisnecessarytoperform
initializationthesamewayasafterapplyingpower,inordertoreturntonormaloperationfrom
LowPowermode.RefertoFigure8,“TimingWaveformforPowerupsequence”onpage 26for
timingcharts.Whenthedensityhasbeentosetto16Mbits,8Mbits,or4MbitsinLowPower
mode,itisnotnecessarytoperforminitializationtoreturntonormaloperationfromLowPower
mode.Fortimingcharts,refertoFigure11,“LowPowermode-Entry/Exit(16/8/4/0Mbits)”
Figure11.LowPowermode-Entry/Exit(16/8/4/0Mbits)
Table16.LowPowermode-Entry/Exit
Parameter Description Min Max Unit
tCHML LowPowermodeentry,P-CS#highleveltoP-Mode#Lowlevel 0 - ns
tMHCL1 LowPowermode(16/8/4Mbitshold)exittonormaloperation,P-ModeHigh
leveltoP-CS#Lowlevel 30 - ns
tMHCL2 LowPowerMode(0Mbitdatahold)exittonormaloperation,P-ModeHigh
leveltoP-CS#Lowlevel 200 - us
NOTES:
1. tMHCL1
isthetimeittakestoreturntonormaloperationfromLowPowerMode(datahold:16/8/4Mbits).
2. tMHCL2
isthetimeittakestoreturntonormaloperationfromLowPowerMode(0Mbitsdatahold).
tMHCL1/tMHCL2
tCHML
LowPowerMode
(PartialArrayRefresh/ZeroRefresh)
P-Mode
P-CS#
30 Datasheet
AppendixAWriteStateMachine
Refertothe1.8VoltIntel®WirelessFlashMemoryDatasheet(ordernumber290701)fortheWrite
StateMachinedetails.
AppendixBCommonFlashInterface
Refertothe1.8VoltIntel®WirelessFlashMemoryDatasheet(ordernumber290701)forthe
CommonFlashInterfacedetails.
AppendixCFlashFlowcharts
Refertothe1.8VoltIntel®WirelessFlashMemoryDatasheet(ordernumber290701)fortheFlash
Flowchartdetails.
Datasheet 31
AppendixDMechanicalPackageInformation
Figure12.80-ActiveBallSingleorDouble-DieStacked-CSPMechanicalSpecifications
Millimeters Inches
Dimensions Symbol Min Nom Max Notes Min Nom Max
PackageHeight A 1.200 0.0472
BallHeight A1 0.200 0.0079
PackageBodyThickness A2 0.860 0.0339
Ball(Lead)Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
PackageBodyLength D 9.900 10.000 10.100 0.3898 0.3937 0.3976
PackageBodyWidth E 7.900 8.000 8.100 0.3110 0.3150 0.3189
Pitch e 0.800 0.0315
Ball(Lead)Count N 88 88
SeatingPlaneCoplanarity Y 0.100 0.0039
CornertoBallA1DistanceAlongE S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
CornertoBallA1DistanceAlongD S2 0.500 0.600 0.700 0.0197 0.0236 0.0276
TopView-BallDown BottomView-BallUp
A
A2
D
E
Y
A1
Drawingnottoscale.
S2
S1
A
C
B
E
D
G
F
J
H
K
L
M
e
1
2345678
b
A
C
B
E
D
G
F
J
H
K
L
M
A1Index
Mark
12345678
32 Datasheet
Figure13.80-ActiveBallTriple-DieStacked-CSPMechanicalSpecifications
Millimeters Inches
Dimens ions Symbol Min Nom Max Notes Min Nom Max
PackageHeight A 1.400 0.0551
BallHeight A1 0.200 0.0079
PackageBodyThickness A2 1.070 0.0421
Ball(Lead)Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
PackageBodyLength D 9.900 10.000 10.100 0.3898 0.3937 0.3976
PackageBodyWidth E 7.900 8.000 8.100 0.3110 0.3150 0.3189
Pitch e 0.800 0.0315
Ball(Lead)CountN8888
SeatingPlaneCoplanarity Y 0.100 0.0039
CornertoBallA1DistanceAlongE S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
CornertoBallA1DistanceAlongD S2 0.500 0.600 0.700 0.0197 0.0236 0.0276
TopView-BallDown BottomView-BallUp
A
A2
D
E
Y
A1
Drawingnottoscale.
S2
S1
A
C
B
E
D
G
F
J
H
K
L
M
e
12345678
b
A
C
B
E
D
G
F
J
H
K
L
M
A1
Index
Mark 12345678
Datasheet 33
AppendixEAdditionalInformation
:
S
OrderNumber Document
290701 1.8VoltIntel®
WirelessFlashMemory(W18)Datasheet
251407 64-Mbit1.8VoltIntel®
WirelessFlashMemoryStacked-CSPFamily
NOTES:
1. PleasecalltheIntelLiteratureCenterat(800)548-4725torequestInteldocumentation.International
customersshouldcontacttheirlocalIntelordistributionsalesoffice.
2. ForthemostcurrentinformationonIntelflashmemoryproducts,softwareandtools,visitourwebsiteat
http://developer.intel.com/design/flash.
34 Datasheet
AppendixFOrderingInformation
F.1 128-MbitW18+32-MbitPSRAMStacked-CSPFamilyDevice
NameDecoder
Figure14showsthedecoderforproductsinthisSCSPfamilywithbothflashandPSRAM.Figure
15showsthedecoderforproductsinthisSCSPfamilywithflashdieonly(noRAM).
Figure14.DecoderforFlash+RAMSCSPDeviceName
F 3 0 W 0 Y B Q8D 3R
Package
PinoutIndicator
ProductLineDesignator
FlashDensity
Voltage
ProductFamily
RD=Stacked-CSP
38F=Stacked-CSPIntel®
FlashMemory,Flash&RAM
0=Nodie
2=64Mbit
W=Intel®WirelessFlashMemory(Flash#1)
0=NoDie(Flash#2) Y=1.8VoltCoreandI/O
Q=Quadballout
4 0
RAMDensity
3=16Mbit
4=32Mbit
0
ParameterLocation
B=BottomParameter
T=TopParameter
DeviceDetails
0=Originalversionof
theproducts:
W18Speed=14nsSync/
25nsPage/65nsAsync
FlashProcess=0.13µm
Flash #1
Flash #2
Flash #1
Flash #2
RAM#2
RAM#1
3=128Mbit
5=64Mbit
RAM=32MbitPSRAM
pr od
uc
t:
D=FlashDie#1-
BottomParameter;
FlashDie#2-Top
Parameter
PSRAMSpeed=30ns
Page/85nsAsync
Size=8x10x1.2mm/
1.4mm
Datasheet 35
Figure15.DecoderforFlash-OnlySCSPDeviceName
F 3 2 W 0 Y D Q8D 4R
Package
PinoutIndicator
ProductLineDesignator
FlashDensity
VoltageProductFamily
RD=Stacked-CSP
48F=Intel®FlashMemory,Multiple
Flash-onlyDie
2=64Mbit
0=NoDie
W=Intel®Wirelessmemory
0=NoDie Y=1.8VcoreandI/O
Q=QuadBallout
0 0 0
ParameterLocation
D=BottomParameter
forFlashDie#1,
TopParameterforFlash
Die#2
DeviceDetails
0=Originalversionofthis
product:
FlashProcess=0.13µm
Size=8x10x1.2mm
Flash #1
Flash #2
Flash Family
Flash #4
Flash #3
Flash Family
3=128Mbit
W18Speed=14nsSync/
25nsPage/65nsAsync
pro
duc
t:
T=TopParameter
B=BottomParameter
36 Datasheet
F.2 128-MbitW18+32-MbitPSRAMStacked-CSPFamilyDevice
NameList
Table17showsthecompletelistofdevicenamesforproductswithsingleflashdieinthisSCSP
familyaccordingtobootconfiguration.
Table18showsthecompletelistofdevicenamesforproductswithdoubleflashdie.Flashdie#1is
configuredbottomparameterwhileflashdie#2isconfiguredtopparameter.SeeSection2.5,“Flash
MemoryMapandPartitioning”onpage 13forflashmemorymapandpartitioningdetailsof
deviceswithdoubleflashdies.
Table17.SingleFlashDieSCSPDeviceNameList
Product BottomParameterConfiguration
DeviceName TopParameterConfiguration
DeviceName
128W18 RD48F3000W0YBQ0 RD48F3000W0YTQ0
128W18+32PSRAM RD38F3040W0YBQ0 RD38F3040W0YTQ0
Table18.DoubleFlashDieSCSPDeviceNameList
Product DeviceName
128W18B+64W18T RD48F3200W0YDQ0
128W18B+64W18T+32PSRAM RD38F3240WWYDQ0
128W18B+128W18T RD48F3300W0YDQ0
128W18B+128W18T+32PSRAM RD38F3340WWYDQ0