W964A6BBN 1M WORD x 16 BIT LOW POWER PSEUDO SRAM Table of Contents1. GENERAL DESCRIPTION.................................................................................................................. 3 2. FEATURES ......................................................................................................................................... 3 3. PRODUCT OPTIONS ......................................................................................................................... 3 5. BALL DESCRIPTION .......................................................................................................................... 4 6. BLOCK DIAGRAM .............................................................................................................................. 5 7. FUNCTION TRUTH TABLE ................................................................................................................ 6 8. ELECTRICAL CHARACTERISTICS ................................................................................................... 7 Absolute Maximum Ratings .............................................................................................................. 7 Recommended Operation Conditions............................................................................................... 7 Capacitance ...................................................................................................................................... 8 DC Characteristics ............................................................................................................................ 8 AC Characteristics ............................................................................................................................ 9 Read Operation ..........................................................................................................................................9 Write Operation.........................................................................................................................................11 Power Down and Power Down Program Parameters ...............................................................................13 Other Timing Parameters .........................................................................................................................13 AC Test Conditions...................................................................................................................................13 9. TIMING WAVEFORMS ..................................................................................................................... 14 Read Timing #1 ( OE Control Access)............................................................................................ 14 Read Timing #2 ( CE1 Control Access) .......................................................................................... 15 Read Timing #3 (Address Access after OE Control Access) ........................................................ 16 Read Timing #4 (Address Access after CE1 Control Access) ....................................................... 17 Write Timing #1 ( CE1 Control) ....................................................................................................... 18 Write Timing #2-1 ( WE Control, Single Write Operation) .............................................................. 19 Write Timing #2 ( WE Control, Continuous Write Operation) ......................................................... 20 Read/Write Timing #1-1 ( CE1 Control)........................................................................................... 21 Read/Write Timing #1-2 ( CE1 Control)........................................................................................... 22 -1- Publication Release Date: March 20, 2003 Revision A1 W964A6BBN Read ( OE Control) / Write ( WE Control) Timing #2-1 .................................................................. 23 Read ( OE Control) / Write ( WE Control) Timing #2-2 .................................................................. 24 Power Down Program Timing ......................................................................................................... 25 Power Down Entry and Exit Timing................................................................................................. 25 Power-up Timing #1 ........................................................................................................................ 25 Power-up Timing #2 ........................................................................................................................ 26 Standby Entry Timing after Read or Write ...................................................................................... 26 10. PACKAGE DIMENSION.................................................................................................................. 27 TFBGA 48 Balls (6 x 8 mm^2, pitch 0.75 mm)................................................................................ 27 11. ORDERING INFORMATION........................................................................................................... 28 12. VERSION HISTORY ....................................................................................................................... 29 -2- W964A6BBN 1. GENERAL DESCRIPTION W964A6BBN is a 16M bits CMOS pseudo static random access memory (Pseudo SRAM), organized as 1M words x 16 bits. Using advanced single transistor DRAM architecture and 0.175 m process technology; W964A6BBN delivers fast access cycle time and low power consumption. It is suitable for mobile device application such as Cellular Phone and PDA, which high-density buffer is needed and power dissipation is most concerned 2. FEATURES * Asynchronous SRAM interface * Power supply: - VDD = +2.3V to +3.3V * Fast access cycle time: - tRC = 70 nS (-70), 80 nS (-80) * Temperature: - TA = 0C to +70C * Low power consumption: - IDDA1 = 20 mA Max. - TA = -25C to +85C (Extended temperature) - IDDS1 = 70 A Max. - TA = -40C to +85C (Industrial temperature) * Byte write control 3. PRODUCT OPTIONS PARAMETER W964A6BBN70 W964A6BBN80 tRC 70 nS Min. 80 nS Min. IDDS1 70 A Max. 70 A Max. IDDA1 20 mA 20 mA VDD 2.3V to 2.7V 2.3V to 3.3V -3- Publication Release Date: March 20, 2003 Revision A1 W964A6BBN 4. BALL CONFIGURATION Top view 1 2 3 4 5 6 A LB OE A0 A1 A2 CE2 B DQ9 UB A3 A4 CE1 DQ1 C DQ10 DQ11 A5 A6 DQ2 DQ3 D VSS DQ12 A17 A7 DQ4 VDD E VDD DQ13 NC A16 DQ5 VSS F DQ15 DQ14 A14 A15 DQ6 DQ7 G DQ16 A19 A12 A13 WE DQ8 H A18 A8 A9 A10 A11 NC ( FBGA48 , 6 x 8mm , pitch 0.75mm ) 5. BALL DESCRIPTION SYMBOL A0 - A19 DESCRIPTION Address Input CE1 Chip Enable Input 1, Low: Enable CE2 Chip Enable Input 2, High: Enable, Low: Enter Power Down Mode WE Write Enable Input OE Output Enable Input LB Lower Byte Write Control UB Upper Byte Write Control I/O0 - I/O15 Data Inputs/Outputs VDD Power Supply VSS Ground NC No Connection -4- W964A6BBN 6. BLOCK DIAGRAM VDD VSS A0 to A18 DQ1 to DQ8 DQ9 to DQ16 ADDRESS LATCH & BUFFER ROW DECODER MEMORY CELL ARRAY 33,554,432 bits INPUT / OUTPUT BUFFER INPUT DATA LATCH & CONTROL SENSE / SWITCH OUTPUT DATA CONTROL COLUMN / DECODER ADDRESS LATCH & BUFFER CE2 PE CE1 POWER CONTROL TIMING CONTROL WE LB UB OE -5- Publication Release Date: March 20, 2003 Revision A1 W964A6BBN 7. FUNCTION TRUTH TABLE MODE Standby (Deselect) Output Disable NOTE CE2 CE1 WE OE LB UB A0-18 DQ1-8 DQ9-16 IDD DATA RETENTION H X X X X X High-Z High-Z IDDS Yes H H X X *5 High-Z High-Z H H Valid High-Z High-Z H L Valid Output Valid IDDA Yes Invalid Output Valid Input Valid IDDP No/Yes *1 No Read *2 Read H L L Write (Upper Byte) L Write (Lower Byte) H Write (Word) Power Down *3 L *4 X X X H L Valid L H Valid L L Valid X X X Input Valid Input Valid High-Z Invalid Input Valid High-Z Notes: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High impedance, KEY = Key Address. *1: Output Disable mode should not be kept longer than 1 S. *2: Byte control at Read mode is not supported. *3: Power down mode can be entered from standby state and all DQ pins are in High-Z state. IDDP current and data retention depend on the selection of Power Down Program. *4: Either or both LB and UB must be Low for Read operation. *5: Can be either VIL or VIH but must be valid before Read or Write. -6- W964A6BBN 8. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings PARAMETER SYMBOL VALUE UNIT Voltage of VDD Supply Relative to VSS VDD -0.5 to +3.6 V VIN, VOUT -0.5 to +3.6 V Short Circuit Output Current IOUT 50 mA Storage Temperature TSTG -55 to +125 C Voltage at Any Pin Relative to VSS WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Recommended Operation Conditions (Reference to VSS) PARAMETER NOTES Supply Voltage SYMBOL MIN. MAX. UNIT VDD 2.3 3.3 V VSS 0 0 V High Level Input Voltage *1 VIH 2.2 VDD +0.3 V Low Level Input Voltage *2 VIL -0.3 0.5 V Ambient Temperature TA 0 70 C Ambient Temperature TA -25 85 C Ambient Temperature TA -40 85 C Notes: *1: Maximum DC voltage on input and I/O pins are VDD +0.3V. During voltage transitions, inputs may positive overshoot to VDD +1.0V for periods of up to 5 nS. *2: Minimum DC voltage on input and I/O pins are -0.3V. During voltage transitions, inputs may negative overshoot to 1.0V for periods of up to 5 nS. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users considering application outside the listed conditions are advised to contact their Winbond representative beforehand. -7- Publication Release Date: March 20, 2003 Revision A1 W964A6BBN Capacitance Test conditions: TA = 25C, f = 1.0 MHz SYMBOL DESCRIPTION TEST SETUP TYP. MAX. UNIT CIN1 Address Input Capacitance VIN = 0V - 5 pF CIN2 Control Input Capacitance VIN = 0V - 5 pF CIO Data Input/Output Capacitance VIO = 0V - 8 pF DC Characteristics (Under Recommended Operating Conditions unless otherwise noted) PARAMETER SYM. notes*1, *2, *3 TEST CONDITIONS MIN. MAX. UNIT Input Leakage Current ILI VIN = VSS to VDD -1.0 +1.0 A Output Leakage Current ILO VOUT = VSS to VDD, Output Disable -1.0 +1.0 A Output High Voltage Level VOH VDD = VDD, IOH = -0.5 mA 2.2 - V Output Low Voltage Level VOL IOL = 1 mA - 0.4 V IDDS VDD = VDD Max., VIN = VIH or VIL - 3 mA IDDS1 CE1 = CE2 = VIH VDD = VDD Max., VIN 0.2V or VIN VDD -0.2V, - 70 A (TTL) Standby Current (CMOS) CE1 = CE2 VDD -0.2V IDDA1 VDD = VDD Max., VIN = VIH or VIL, tRC / tWC = Minimum - 20 mA IDDA2 CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = 1 S - 3 mA Active Current Notes: *1: All voltages are reference to VSS. *2: DC Characteristics are measured after following POWER-UP timing. *3: IOUT depends on the output load conditions. -8- W964A6BBN AC Characteristics (Under Recommended Operating Conditions unless otherwise noted) Read Operation PARAMETER SYM. -70 -80 Min. Max. Min. Max. UNIT NOTES Read Cycle Time Chip Enable Access Time Output Enable Access Time Address Access Time Output Data Hold Time tRC tCE tOE tAA tOH 70 5 65 40 65 - 80 5 75 45 75 - nS nS nS nS nS *1, *3 *1 *1 *1 CE1 Low to Output Low-Z tCLZ 5 - 5 - nS *2 OE Low to Output Low-Z tOLZ 0 - 0 - nS *2 CE1 High to Output High-Z tCHZ - 20 - 25 nS *2 OE High to Output High-Z tOHZ - 20 - 25 nS *2 Address Setup Time to CE1 Low tASC -5 - -5 - nS *4 Address Setup Time to OE Low tASO tASO[ABS] 30 10 - 35 10 - nS nS *3, *5 *6 LB / UB Setup Time to CE1 Low tBSC -5 - -5 - nS LB / UB Setup Time to OE Low tBSO 10 - 10 - nS Address Invalid Time tAX - 5 - 5 nS Address Hold Time from CE1 Low tCLAH 70 - 80 - nS Address Hold Time from OE Low tOLAH 40 - 45 - nS Address Hold Time from CE1 High tCHAH -5 - -5 - nS Address Hold Time from OE High tOHAH -5 - -5 - nS LB / UB Hold Time from CE1 High tCHBH -5 - -5 - nS LB / UB Hold Time from OE High tOHBH -5 - -5 - nS CE1 Low to OE Low Delay Time tCLOL 25 1000 30 1000 nS *3, *5, *7, *8 OE Low to CE1 High Delay Time tOLCH 35 - 40 - nS *7 tCP 12 - 15 - nS tOP 25 12 1000 - 30 15 1000 - nS nS CE1 High Pulse Width OE High Pulse Width tOP[ABS] -9- *9 *5, *7, *8 *6 Publication Release Date: March 20, 2003 Revision A1 W964A6BBN Read Operation, Continued Notes: *1: The output load is 30 pF. *2: The output load is 5 pF. *3: The tCE is applicable if OE is brought to Low before CE1 goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. *4: Applicable if OE is brought to Low before CE1 goes Low. *5: The tASO, tCLOL(min.) and tOP(min.) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. For example, if actual tASO, tASO(actual), is shorter than specified minimum value, tASO(min), during OE control access (ie., CE1 stays Low), the tOE become tOE(max.) + tASO(min) - tASO(actual). *6: The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access. *7: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC(min.) tCLOL(actual) or tRC(min.) - tOP(actual). *8: Maximum value is applicable if CE1 is kept at low. - 10 - W964A6BBN AC Characteristics, Continued Write Operation PARAMETER SYMBOL -70 -80 Min. Max. Min. Max. UNIT NOTES Write Cycle Time tWC 70 - 80 - nS *1 Address Setup Time tAS 0 - 0 - nS *2 Address Hold Time tAH 35 - 40 - nS *2 CE1 Write Setup Time tCS 0 1000 0 1000 nS CE1 Write Hold Time tCH 0 1000 0 1000 nS WE Setup Time tWS 0 - 0 - nS WE Hold Time tWH 0 - 0 - nS LB and UB Setup Time tBS -5 - -5 - nS LB and UB Hold Time tBH -5 - -5 - nS OE Setup Time tOES 0 1000 0 1000 nS *3 tOEH 30 1000 35 1000 nS *3, *4 tOEH[ABS] 12 - 15 - nS *5 OE High to CE1 Low Setup Time tOHCL -5 - -5 - nS *6 OE High to Address Hold Time tOHAH -5 - -5 - nS *7 CE1 Write Pulse Width tCW 45 - 50 - nS *1, *8 WE Write Pulse Width TWP 45 - 50 - nS *1, *8 CE1 Write Recovery Time tWRC 10 - 15 - nS *1, *9 WE Write Recovery Time tWR 10 1000 15 1000 nS *1, *3, *9 Data Setup Time tDS 15 - 20 - nS Data Hold Time tDH 0 - 0 - nS CE1 High Pulse Width tCP 12 - 15 - nS OE Hold Time - 11 - *9 Publication Release Date: March 20, 2003 Revision A1 W964A6BBN Write Operation, Continued Notes: *1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR). *2: New write address is valid from either CE1 or WE is brought to High. *3: The tOEH is specified from end of tWC(min.). The tOEH(min.) is a reference value when the access time is determined by tOE. If actual value, tOEH(actual) is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. *4: The tOEH(max.) is applicable if CE1 is kept at Low and both WE and OE are kept at High. *5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 stays Low. *6: tOHCL(min.) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL(min.), WE Low must be asserted after tRC(min.) from CE1 Low. In other words, read operation is initiated if tOHCL(min.) is not satisfied. *7: Applicable if CE1 stays Low after read operation. *8: tCW and tWP is applicable if write operation is initiated by CE1 and WE , respectively. *9: tWRC and tWR is applicable if write operation is terminated by CE1 and WE , respectively. The tWR(min.) can be ignored if CE1 is brought to High together or after WE is brought to High. In such case, the tCP(min.) must be satisfied. - 12 - W964A6BBN AC Characteristics, Continued Power Down and Power Down Program Parameters PARAMETER SYM. -70 -80 Min. Max. Min. Max. UNIT NOTES CE2 Low Setup Time for Power Down Entry tCSP 10 - 10 - nS CE2 Low Hold Time after Power Down Entry tC2LP 70 - 80 - nS CE1 High Setup Time following CE2 High after Power Down Exit tCHS 10 - 10 - nS Other Timing Parameters PARAMETER SYM. CE1 High to OE Invalid Time for Standby Entry -70 -80 UNIT NOTES Min. Max. Min. Max. tCHOX 10 - 10 - nS CE1 High to WE Invalid Time for Standby Entry tCHWX 10 - 10 - nS *1 CE2 Low Hold Time after Power-up tC2LH 50 - 50 - S *2 CE2 High Hold Time after Power-up tC2HL 50 - 50 - S *3 CE1 High Hold Time following CE2 High after Power-up tCHH 350 - 350 - S *2 tT 1 25 1 25 nS *4 Input Transition Time Notes: *1: Some data might be written into any address location if tCHWX(min.) is not satisfied. *2: Must satisfy tCHH(min.) after tC2LH(min.). *3: Requires Power Down mode entry and exit after tC2HL. *4: The Input Transition Time (tT) at AC testing is 5ns as shown in below. If actual tT is longer than 5 nS, it may violate AC specified of some timing parameters. AC Test Conditions SYMBOL DESCRIPTION TEST SETUP VALUE UNIT VIH Input High Level VDD = 2.7V to 3.3V 2.3 V VIL Input Low Level VDD = 2.7V to 3.3V 0.5 V Input Timing Measurement Level VDD = 2.7V to 3.3V 1.3 V Between VIL and VIH 5 nS VREF TT Input Transition Time - 13 - NOTE Publication Release Date: March 20, 2003 Revision A1 W964A6BBN 9. TIMING WAVEFORMS Read Timing #1 ( OE Control Access) tRC ADDRESS tRC ADDRESS VALID ADDRESS VALID tCE tOHAH tASO tOHAH CE1 tOLCH tCLOL OE tOE tOP tOE tASO tBSO tOHBH tBSO tOHBH LB / UB tOHZ tOH tOLZ tOLZ tOHZ tOH DQ (Output) VALID DATA OUTPUT Note: CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 14 - VALID DATA OUTPUT W964A6BBN Timing Waveforms, Continued Read Timing #2 ( CE1 Control Access) tRC ADDRESS tRC ADDRESS VALID tASC tCE ADDRESS VALID tCHAH tASC tCE tCHAH CE1 tCP OE tBSC tCHBH tBSC tCHBH LB / UB tOLZ tCHZ tOH tCLZ tCHZ tOH DQ (Output) VALID DATA OUTPUT VALID DATA OUTPUT Note: CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 15 - Publication Release Date: March 20, 2003 Revision A1 W964A6BBN Timing Waveforms, Continued Read Timing #3 (Address Access after OE Control Access) ADDRESS tRC tRC ADDRESS VALID ADDRESS VALID tASO tOLAH tAX tAA tOHAH CE1 tOE tOHZ OE tOHBH tBSO LB / UB tOLZ tOH tOH DQ (Output) VALID DATA OUTPUT Note: CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 16 - VALID DATA OUTPUT W964A6BBN Timing Waveforms, Continued Read Timing #4 (Address Access after CE1 Control Access) ADDRESS tRC tRC ADDRESS VALID ADDRESS VALID tASC tCLAH tAX tAA tCHAH CE1 tCE tCHZ OE tCHBH tBSC LB / UB tCLZ tOH tOH DQ (Output) VALID DATA OUTPUT VALID DATA OUTPUT Note: CE2, PE and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1 and OE are Low. - 17 - Publication Release Date: March 20, 2003 Revision A1 W964A6BBN Timing Waveforms, Continued Write Timing #1 ( CE1 Control) tWC ADDRESS ADDRESS VALID tAS tAS tAH CE1 tWS tWC tWRC tWH tWS tBH tBS WE tBS LB / UB tOHCL OE tDS tDH DQ (Intput) VALID DATA INTPUT Note: CE2 and PE must be High for entire write cycle. - 18 - W964A6BBN Timing Waveforms, Continued Write Timing #2-1 ( WE Control, Single Write Operation) tWC ADDRESS tOHAH tAS ADDRESS VALID tAH tCS tWP tAS tCH CE1 tCP tOHCL tWR WE tBH tBS tBH LB / UB tOES OE tOHZ tDS tDH DQ (Intput) VALID DATA INTPUT Note: CE2 and PE must be High for entire write cycle. - 19 - Publication Release Date: March 20, 2003 Revision A1 W964A6BBN Timing Waveforms, Continued Write Timing #2 ( WE Control, Continuous Write Operation) tWC ADDRESS ADDRESS VALID tOHAH tAS tAH tAS CE1 tOHCL tCS tWP tWR WE tOHBH tBS tBH LB / UB tOES OE tOHZ tDS tDH DQ (Intput) VALID DATA INTPUT Note: CE2 and PE must be High for entire write cycle. - 20 - tBS W964A6BBN Timing Waveforms, Continued Read/Write Timing #1-1 ( CE1 Control) tWC ADDRESS ADDRESS VALID tCHAH tAS tAH tAS CE1 tCP tWH tCW tWRC tWS tWH tWS tCLOL WE tCHBH tBS tBH tBSO LB / UB tOHCL OE tCHZ tOH tDS tDH tOLZ DQ (Intput) VALID DATA INTPUT VALID DATA INTPUT Note: Write address is valid from either CE1 or WE of last falling edge. - 21 - Publication Release Date: March 20, 2003 Revision A1 W964A6BBN Timing Waveforms, Continued Read/Write Timing #1-2 ( CE1 Control) tRC ADDRESS ADDRESS VALID tWRC CE1 tASC WRITE ADDRESS tCHAH tWRC(min) tWH tWS tAS tCP tWS tWH WE tBH tBSC tOE tBS tCHBH LB / UB tOEH tOHCL OE tCHZ tDH tCLZ tOH DQ VALID DATA OUTPUT VALID DATA OUTPUT Note: The tOEH is specified from the time satisfied both tWRC and tWR(min.). - 22 - W964A6BBN Timing Waveforms, Continued Read ( OE Control) / Write ( WE Control) Timing #2-1 tWC ADDRESS WRITE ADDRESS tOHAH CE1 tAS READ ADDRESS tAH tASO Low tWP tWR tOEH WE tOHBH tBS tBH tOEH LB / UB tOES OE tOHZ tOH tDS tDH tOLZ DQ (Intput) VALID DATA INTPUT VALID DATA INTPUT Note: CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE . - 23 - Publication Release Date: March 20, 2003 Revision A1 W964A6BBN Timing Waveforms, Continued Read ( OE Control) / Write ( WE Control) Timing #2-2 tRC ADDRESS ADDRESS VALID tASO CE1 WRITE ADDRESS tOHAH tAS tOHBH tBS Low tWR tOEH WE tBH tBSO LB / UB tOE tOES OE tOHZ tDH tOLZ tOH DQ VALID DATA OUTPUT VALID DATA OUTPUT Note: CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE . - 24 - W964A6BBN Timing Waveforms, Continued Power Down Program Timing CE1 tEPS tEP tEPH PE tEAS ADDRESS (A20-16) tEAH KEY Note: CE2 must be High for Power Down Program operation. Any other inputs not specified above can be either High or Low. Power Down Entry and Exit Timing CE1 tCHS CE2 tCSP tC2LP tCHH (tCHHN) High-Z DQ Power Down Entry Power Down Mode Power Down Exit Note: This Power Down mode can be also used for Power-up #2 below except that tCHHN can not be used at Power-up timing. Power-up Timing #1 CE1 tCHS tC2LH tCHH CE2 VDD VDD min 0V Note: The tC2LH specifies after VDD reaches specified minimum level. - 25 - Publication Release Date: March 20, 2003 Revision A1 W964A6BBN Timing Waveforms, Continued Power-up Timing #2 CE1 tCHS tC2HL tCSP tC2LP tCHH CE2 tC2HL VDD VDD min 0V Note: The tC2HL specifies from CE2 low to High transition after VDD reaches specified minimum level. CE1 must be brought to High prior to or together with CE2 Low to High transition. Standby Entry Timing after Read or Write CE1 tCHOX tCHWX OE WE Active (Read) Standby Active (Write) Standby Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC(min.) period from either last address transition of A0, A1 and A2, or CE1 Low to High transition. - 26 - W964A6BBN 10. PACKAGE DIMENSION TFBGA 48 Balls (6 x 8 mm^2, pitch 0.75 mm) - 27 - Publication Release Date: March 20, 2003 Revision A1 W964A6BBN 11. ORDERING INFORMATION SPEED OPERATING TEMPERATURE PACKAGE W964A6BBN70 70 nS 0 to 70 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm W964A6BBN70E 70 nS -25 to 85 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm W964A6BBN70I 70 nS -40 to 85 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm W964A6BBN80 80 nS 0 to 70 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm W964A6BBN80E 80 nS -25 to 85 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm W964A6BBN80I 80 nS -40 to 85 TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm PART NO. Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 28 - W964A6BBN 12. VERSION HISTORY VERSION DATE PAGE A1 March 20, 2003 - DESCRIPTION Create new document Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 29 - Publication Release Date: March 20, 2003 Revision A1