LC2MOS 8-/16-Channel High Performance Analog Multiplexers ADG406/ADG407/ADG426 FUNCTIONAL BLOCK DIAGRAMS ADG406 S1 D S16 APPLICATIONS Audio and video routing Automatic test equipment Data acquisition systems Battery powered systems Sample hold systems Communication systems Avionics PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 7. Extended Signal Range. The ADG406/ADG407/ADG426 are fabricated on an enhanced LC2MOS process giving an increased signal range which extends to the supply rails. Low Power Dissipation. Low RON. Single/Dual Supply Operation. Single Supply Operation. For applications where the analog signal is unipolar, the ADG406/ADG407/ADG426 can be operated from a single rail power supply. The parts are fully specified with a single +12 V power supply and remain functional with single supplies as low as +5 V. 1 OF 16 DECODER A0 A1 A2 A3 EN 00026-001 44 V supply maximum ratings VSS to VDD analog signal range Low on resistance (80 maximum) Low power Fast switching tON < 160 ns tOFF < 150 ns Break-before-make switching action Figure 1. ADG407 S1A DA S8A S1B DB S8B 1 OF 8 DECODER A0 A1 A2 00026-002 FEATURES EN Figure 2. ADG426 S1 D S16 DECODER/ LATCHES A0 A1 A2 A3 EN RS 00026-003 WR Figure 3. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)1994-2010 Analog Devices, Inc. All rights reserved. ADG406/ADG407/ADG426 TABLE OF CONTENTS Features .............................................................................................. 1 ADG426 Timing Diagrams..........................................................7 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................8 Product Highlights ........................................................................... 1 ESD Caution...................................................................................8 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ............................9 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 12 General Description ......................................................................... 3 Test Circuits ..................................................................................... 15 Specifications..................................................................................... 4 Terminology .................................................................................... 18 Dual Supply ................................................................................... 4 Outline Dimensions ....................................................................... 19 Single Supply ................................................................................. 6 Ordering Guide .......................................................................... 20 REVISION HISTORY 5/10--Rev. A to Rev. B Changes to Ordering Guide .......................................................... 20 6/09--Rev. 0 to Rev. A Updated Format .................................................................. Universal Removed T Grade ............................................................... Universal Added Table 4.................................................................................... 9 Added Table 6.................................................................................. 10 Added Table 8.................................................................................. 11 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 4/94--Revision 0: Initial Version Rev. B | Page 2 of 20 ADG406/ADG407/ADG426 GENERAL DESCRIPTION The ADG406, ADG407, and ADG426 are monolithic CMOS analog multiplexers. The ADG406 and ADG426 switch one of sixteen inputs to a common output as determined by the 4-bit binary address lines: A0, A1, A2, and A3. The ADG426 has on-chip address and control latches that facilitate microprocessor interfacing. The ADG407 switches one of eight differential inputs to a common differential output as determined by the 3-bit binary address lines A0, A1 and A2. An EN input on all devices is used to enable or disable the device. When disabled, all channels are switched off. The ADG406/ADG407/ADG426 are designed on an enhanced LC2MOS process that provides low power dissipation yet gives high switching speed and low on resistance. These features make the parts suitable for high speed data acquisition systems and audio signal switching. Low power dissipation makes the parts suitable for battery powered systems. Each channel conducts equally well in both directions when on and has an input signal range which extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All channels exhibit breakbefore-make switching action preventing momentary shorting when switching channels. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. Rev. B | Page 3 of 20 ADG406/ADG407/ADG426 SPECIFICATIONS DUAL SUPPLY VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter 1 ANALOG SWITCH Analog Signal Range RON RON Match LEAKAGE CURRENTS Source Off Leakage IS (Off) Drain Off Leakage ID (Off ) ADG406, ADG426 ADG407 Channel On Leakage ID, IS (On) ADG406, ADG426 ADG407 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 2 tTRANSITION Break Before Make Delay, tOPEN tON (EN, WR) tOFF (EN, RS) +25C -40C to +85C Unit VSS to VDD V typ max typ Test Conditions/Comments 50 80 4 125 VD = 10 V, IS = -1 mA VDD = +13.5 V, VSS = -13.5 V VD = 0 V, IS = -1 mA VDD = +16.5 V, VSS = -16.5 V VD = 10 V, VS = +10 V, see Figure 26 VD = 10 V, VS = +10 V; see Figure 27 0.5 20 nA max 1 1 20 20 nA max nA max 1 1 20 20 nA max nA max 2.4 0.8 V min V max 1 A max pF typ VIN = 0 or VDD f = 1 MHz VS = VD = 10 V; see Figure 28 8 120 150 10 ns typ ns max ns min RL = 300 , CL = 35 pF; V1 = 10 V, V2 = +10 V; see Figure 29 250 10 120 160 110 150 175 225 130 180 ns typ ns max ns typ ns max RL = 300 , CL = 35 pF; VS = 5 V, see Figure 31 100 100 10 100 ADG426 Only tW, Write Pulse Width tS, Address, Enable Setup Time tH, Address, Enable Hold Time tRS, Reset Pulse Width Charge Injection 8 ns min ns min ns min ns min pC typ Off Isolation -75 dB typ Channel-to-Channel Crosstalk CS (Off ) CD (Off ) ADG406, ADG426 ADG407 CD, CS (On) ADG406, ADG426 ADG407 85 5 dB typ pF typ 50 25 pF typ pF typ 60 40 pF typ pF typ RL = 300 , CL = 35 pF; VS = +5 V, see Figure 30 RL = 300 , CL = 35 pF; VS = 5 V, see Figure 31 VS = +5 V VS = 0 V, RS = 0 , CL = 1 nF; See Figure 34 RL = 1 k , f = 100 kHz; VEN = 0 V, see Figure 35 RL = 1 k , f = 100 kHz, see Figure 36 f = 1 MHz f = 1 MHz f = 1 MHz Rev. B | Page 4 of 20 ADG406/ADG407/ADG426 Parameter 1 POWER REQUIREMENTS IDD +25C ISS IDD 100 200 ISS 1 2 -40C to +85C Unit 1 5 1 5 A typ A max A typ A max A typ A max A typ A max 500 1 5 Temperature ranges is -40C to +85C. Guaranteed by design, not subject to production test. Rev. B | Page 5 of 20 Test Conditions/Comments VDD = +16.5 V, VSS = -16.5 V VIN = 0 V, VEN = 0 V VIN = 0 V, VEN = 2.4 V ADG406/ADG407/ADG426 SINGLE SUPPLY VDD = +12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter 1 ANALOG SWITCH Analog Signal Range RON LEAKAGE CURRENTS Source Off Leakage IS (Off ) Drain Off Leakage ID (Off ) ADG406, ADG426 ADG407 Channel On Leakage ID, IS (On) ADG406, ADG426 ADG407 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 2 tTRANSITION Break Before Make Delay, tOPEN tON (EN, WR) tOFF (EN, RS) ADG426 Only tW, Write Pulse Width tS, Address, Enable Setup Time tH, Address, Enable Hold Time tRS, Reset Pulse Width Charge Injection Off Isolation Channel-to-Channel Crosstalk CS (Off ) CD (Off ) ADG406, ADG426 ADG407 CD, CS (On) ADG406, ADG426 ADG407 POWER REQUIREMENTS IDD IDD 1 2 +25C -40C to +85C Unit 0 to VDD Test Conditions/Comments 90 125 200 V typ max 0.5 20 nA max 1 1 20 20 nA max nA max 1 1 20 20 nA max nA max 2.4 0.8 V min V max 1 A max pF typ VIN = 0 or VDD f = 1 MHz ns typ ns max ns typ ns typ ns max ns typ ns max RL = 300 , CL = 35 pF; V1 = 8 V/0 V, V2 = 0 V/8 V; see Figure 29 VD = +3 V, +8.5 V, IS = -1 mA; VDD = +10.8 V VDD = +13.2 V VD = 8 V/0.1 V, VS = 0.1 V/8 V; see Figure 26 VD = 8 V/0.1 V, VS = 0.1 V/8 V; see Figure 27 VS = VD = 8 V/0.1 V, see Figure 28 8 180 220 10 180 240 135 180 350 350 220 100 100 10 100 5 -75 85 8 ns min ns min ns min ns min pC typ dB typ dB typ pF typ 80 40 pF typ pF typ 100 50 pF typ pF typ 1 5 100 200 500 A typ A max A typ A max Temperature range is -40C to +85C. Guaranteed by design, not subject to production test. Rev. B | Page 6 of 20 RL = 300 , CL = 35 pF; VS = 5 V, see Figure 30 RL = 300 , CL = 35 pF; VS = +5 V, see Figure 31 RL = 300 , CL = 35 pF; VS = 5 V, see Figure 31 VS = +5 V VS = 6 V, RS = 0 , CL = 1 nF; see Figure 34 RL = 1 k, f = 100 kHz; see Figure 35 RL = 1 k, f = 100 kHz; see Figure 36 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +13.2 V VIN = 0 V, VEN = 0 V VIN = 0 V, VEN = 2.4 V ADG406/ADG407/ADG426 ADG426 TIMING DIAGRAMS 3V 3V 0V A0, A1, A2, (A3) EN 0V 50% 0V tW tS 3V RS 50% tH 2V 0.8V 50% tW tOFF (RS) SWITCH OUTPUT 0.8V0 0V Figure 4. Timing Sequence for Latching the Switch Address and Enable Inputs Figure 4 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR. V0 00026-010 50% 00026-009 WR Figure 5. Reset Pulse Width and Reset Turn Off Time Figure 5 shows the reset pulse width, trs, and the reset turn off time, tOFF (RS). Note that all digital input signals rise and fall times are measured from 10% to 90% of 3 V; tR = tF = 20 ns. Rev. B | Page 7 of 20 ADG406/ADG407/ADG426 ABSOLUTE MAXIMUM RATINGS TA = 25C unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog, Digital Inputs1 Continuous Current, S or D Peak Current, S or D Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature Plastic Package JA, Thermal Impedance Lead Temperature, Soldering (10 sec) PLCC Package JA, Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) SSOP Package JA, Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) 1 Rating 44 V -0.3 V to +25 V +0.3 V to -25 V VSS - 2 V to VDD + 2 V or 20 mA, whichever occurs first 20 mA 40 mA (Pulsed at 1 ms, 10% duty cycle max) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION -40C to +85C -65C to +150C 150C 75C/W 260C 80C/W 215C 220C 122C/W 215C 220C Overvoltages at A, S, D, WR, or RS will be clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. B | Page 8 of 20 ADG406/ADG407/ADG426 S11 9 20 S2 S10 10 19 S1 S9 11 18 EN GND 12 17 A0 NC 13 16 A1 A3 14 15 A2 NC = NO CONNECT VDD D VSS S8 28 27 26 PIN 1 INDENTFIER S15 5 S14 6 S13 7 ADG406 23 S5 S12 8 TOP VIEW (Not to scale) 22 S4 S11 9 25 S7 24 S6 21 S3 S10 10 20 S2 S9 11 19 S1 12 13 14 15 16 17 18 00026-005 S13 7 1 EN S12 8 23 S5 TOP VIEW (Not to Scale) 22 S4 21 S3 S14 6 2 A0 24 S6 3 GND ADG406 00026-004 S15 5 4 A1 25 S7 NC S16 4 A2 26 S8 A3 27 VSS NC 3 NC 28 D NC 2 NC VDD 1 S16 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC = NO CONNECT Figure 6. 28-Lead PDIP Figure 7. 28-Lead PLCC Table 4. Pin Function Descriptions Pin No. 1 2, 3, 13 4 to 11 12 14 to 17 18 Mnemonic VDD NC S16 to S9 GND A3 to A0 EN 19 to 26 27 28 S1 to 8 VSS D Description Most Positive Power Supply Potential. No Connect. Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs. Ground (0 V) Reference. Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Drain Terminal. This pin can be an input or an output. Table 5. Truth Table (ADG406) A3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. B | Page 9 of 20 On Switch None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3B 9 20 S2A S2B 10 19 S1A S1B 11 18 EN GND 12 17 A0 NC 13 16 A1 NC 14 15 A2 NC = NO CONNECT VDD DA VSS S8A 28 27 26 S5B 7 S4B 8 S3B 9 25 S7A 24 S6A ADG407 23 S5A TOP VIEW (Not to scale) 22 S4A 21 S3A S2B 10 20 S2A S1B 11 19 S1A 12 00026-006 S5B 7 1 13 14 15 16 17 18 EN S4B 8 23 S5A TOP VIEW (Not to Scale) 22 S4A 21 S3A S6B 6 S6B 6 2 PIN 1 INDENTFIER 00026-007 24 S6A 3 A0 ADG407 4 GND S7B 5 S7B 5 A1 25 S7A DB S8B 4 A2 26 S8A NC 27 VSS NC 3 NC 28 DA DB 2 NC VDD 1 S8B ADG406/ADG407/ADG426 NC = NO CONNECT Figure 8. 28-Lead PDIP Figure 9. 28-Lead PLCC Table 6. Pin Function Descriptions Pin No. 1 2 3, 13, 14 4 to 11 12 15 to 17 18 Mnemonic VDD DB NC S8B to S1B GND A2 to A0 EN 19 to 26 27 28 S1A to S8A VSS DA Description Most Positive Power Supply Potential. Drain Terminal B. This pin can be an input or an output. No Connect. Source Terminal 8B to Source Terminal 1B. These pins can be inputs or outputs. Ground (0 V) Reference. Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. Source Terminal 1A to Source Terminal 8A. These pins can be inputs or outputs. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Drain Terminal A. This pin can be an input or an output. Table 7. Truth Table (ADG407) A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 On Switch Pair None 1 2 3 4 5 6 7 8 Rev. B | Page 10 of 20 ADG406/ADG407/ADG426 VDD 1 28 D NC 2 27 VSS RS 3 26 S8 S16 4 25 S7 S14 6 S13 7 S12 8 ADG426 TOP VIEW (Not to Scale) 24 S6 23 S5 22 S4 21 S3 S11 9 20 S2 S10 10 19 S1 S9 11 18 EN GND 12 17 A0 WR 13 16 A1 A3 14 15 A2 NC = NO CONNECT 00026-008 S15 5 Figure 10. 28-Lead PDIP/SSOP Table 8. Pin Function Descriptions Pin No. 1 2 3 Mnemonic VDD NC RS 4 to 11 12 13 S16 to S9 GND WR 14 to 17 18 A3 to A0 EN 19 to 26 27 28 S1 to S8 VSS D Description Most Positive Power Supply Potential. No Connect. Active Low Logic Input. When this pin is low, all switches are open, and address and enable latches registers are cleared to 0. Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs. Ground (0 V) Reference. The rising edge of the WR signal latches the state of the address control lines and the enable line. Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Drain Terminal. This pin can be an input or an output. Table 9. Truth Table (ADG426) A3 X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EN X X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 WR RS X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 On switch Retains previous switch condition None (address and enable latches cleared) None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Rev. B | Page 11 of 20 ADG406/ADG407/ADG426 TYPICAL PERFORMANCE CHARACTERISTICS 150 400 TA = 25C TA = 25C VDD = +5V VSS = -5V 90 VDD = +5V VSS = 0V 300 250 VDD = +10V VSS = -10V RON () RON () 120 350 60 200 VDD = +10V VSS = 0V 150 VDD = +12V VSS = 0V VDD = +15V VSS = -15V 0 -15 -10 VDD = +12V VSS = -12V -5 0 5 10 50 00026-011 30 VDD = +15V VSS = 0V 0 15 00026-014 100 0 2.5 5.0 VD (VS) (V) 7.5 10 Figure 11. RON as a Function of VD (VS): Dual Supplies 15 Figure 14. RON as a Function of VD (VS): Single Supplies 100 150 VDD = +15V VSS = -15V VDD = 12V VSS = 0V 80 120 125C 125C 60 RON () RON () 12.5 VD (VS) (V) 85C 40 90 85C 25C 60 25C 0 -15 -10 -5 0 5 10 0 15 00026-015 30 00026-012 20 0 2 4 VD (VS) (V) Figure 12. RON as a Function of VD (VS) for Different Temperatures 8 10 12 Figure 15. RON as a Function of VD (VS) for Different Temperatures 0.10 0.02 VDD = +12V VSS = 0V TA = +25C ID(ON) 0.06 0.04 ID(OFF) 0.02 0 -0.02 -15 -10 -5 0 5 00026-013 IS(OFF) 10 0.01 ID(OFF) VD (VS) (V) ID(ON) -0.01 -0.02 15 IS(OFF) 0 00026-016 LEAKAGE CURRENT (nA) VDD = +15V VSS = -15V TA = +25C 0.08 LEAKAGE CURRENT (nA) 6 VD (VS) (V) 0 2 4 6 8 10 VD (VS) (V) Figure 13. Leakage Currents as a Function of VD (VS) Figure 16. Leakage Currents as a Function of VD (VS) Rev. B | Page 12 of 20 12 ADG406/ADG407/ADG426 100 100 VDD = +15V VSS = -15V VDD = +15V VSS = -15V 10 1 EN = 2.4V ISS (mA) IDD (mA) 10 EN = 2.4V 0.1 EN = 0V 1 0.01 1k 10k 100k 00026-017 0.1 100 1M 00026-020 0.001 EN = 0V 0.0001 100 10M 1k 10k FREQUENCY (Hz) 100k 1M 10M FREQUENCY (Hz) Figure 17. Positive Supply Current vs. Switching Frequency Figure 20. Negative Supply Current vs. Switching Frequency 160 220 VDD = +15V VSS = -15V tON VDD = +12V VSS = 0V 200 140 tON tTRANSITION 180 tTRANSITION t (ns) t (ns) 120 100 160 140 120 tOFF 80 1 3 5 7 9 11 13 80 15 00026-021 60 100 00026-018 tOFF 2 4 6 VIN (V) 8 10 12 VIN (V) Figure 18. Switching Time vs. VIN (Bipolar Supply) Figure 21. Switching Time vs. VIN (Single Supply) 300 500 VIN = +5V VIN = +5V 400 tON 200 tTRANSITION t (ns) t (ns) 300 tON 200 tTRANSITION 100 tOFF tOFF 5 7 9 11 13 15 17 19 0 21 00026-022 0 00026-019 100 5 7 9 11 13 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 22. Switching Time vs. Single Supply Figure 19. Switching Time vs. Bipolar Supply Rev. B | Page 13 of 20 15 ADG406/ADG407/ADG426 140 140 VDD = +15V VSS = -15V VDD = +15V VSS = -15V CROSSTALK (dB) 120 100 80 40 100 100 80 60 1k 10k 100k 1M 40 100 10M FREQUENCY (Hz) 00026-024 60 00026-023 OFF ISOLATION (dB) 120 1k 10k 100k FREQUENCY (Hz) Figure 23. Off Isolation vs. Frequency Figure 24. Crosstalk vs. Frequency Rev. B | Page 14 of 20 1M 10M ADG406/ADG407/ADG426 TEST CIRCUITS IDS V1 S1 VDD VSS VDD VSS S2 S D ID (OFF) A D S16 00026-025 RON = V1/IDS S1 VDD VSS VDD VSS VDD VSS VDD VSS ID (ON) A S16 S16 EN VD +0.8V VD EN VS 00026-026 VS D S1 D S2 +2.4V 00026-028 A +0.8V Figure 27. ID (Off) Figure 25. On Resistance IS (OFF) VD EN VS 00026-027 VS Figure 28. ID (On) Figure 26. IS (Off) VDD VSS VDD A3 VSS 3V A2 50 S1 A1 A0 50% 50% V2 S16 ADG4261 EN 2.4V V1 S2 THRU S15 RS GND D RL 300 WR CL 35pF 90% VOUT VOUT 90% tTRANSITION tTRANSITION CONNECTION FOR ADG406/ADG407 Figure 29. Switching Time of Multiplexer, tTRANSITION VDD VSS VDD A3 VSS 3V VIN 50 A2 S1 S2 THRU S15 A1 A0 S16 ADG4261 RS 2.4V VS ADDRESS DRIVE (VIN) D EN GND WR VOUT RL 300 CL 35pF OUTPUT 80% 80% 0V tOPEN 1SIMILAR CONNECTION FOR ADG406/ADG407 Figure 30. Break-Before-Make Delay, tOPEN Rev. B | Page 15 of 20 00026-030 1SIMILAR 00026-029 VIN ADDRESS DRIVE (VIN) ADG406/ADG407/ADG426 VDD VSS VDD A3 VSS A2 3V S1 ENABLE DRIVE (VIN) VS S2 THRU S16 0V A1 tOFF (EN) ADG4261 VO RS VOUT D RL 300 EN VIN GND 50 WR 90% 90% OUTPUT CL 35pF 0V 00026-031 A0 2.4V 50% 50% tON (EN) 1SIMILAR CONNECTION FOR ADG406/ADG407 Figure 31. Enable Delay, tON (EN), tOFF (EN) VDD VSS VDD A3 VSS A2 S1 3V VS WR S2 THRU S16 A1 2.4V 0V ADG426 A0 V0 EN D RS WR RL 300 VOUT CL 35pF tON(WR) OUTPUT 0.2V0 0V GND 00026-032 VRS 50% VWR Figure 32. Write Turn-On Time, tON (WR) VSS VDD A3 VSS A2 S1 3V VS RS S2 THRU S16 A1 A0 2.4V tOFF(RS) D RS VIN 0V ADG426 EN GND WR 50% RL 300 VOUT CL 35pF V0 0.8V0 OUTPUT 0V Figure 33. Reset Turn-Off Time, tOFF (RS) Rev. B | Page 16 of 20 00026-033 VDD ADG406/ADG407/ADG426 VDD VSS VDD A3 VSS 2.4V RS A2 3V LOGIC INPUT (VIN) A1 RS VS ADG4261 D CL 1nF EN VIN 1SIMILAR GND VOUT VOUT WR VOUT QINJ = CL x VOUT 00026-034 A0 S CONNECTION FOR ADG406/ADG407. Figure 34. Charge Injection VDD VDD S16 VDD VDD 1k S1 A0 A2 S16 A1 2.4V A3 RS D EN GND WR VSS RL 1k VSS 1SIMILAR ADG4261 A2 ADG4261 CONNECTION FOR ADG406/ADG407. 2.4V VOUT EN RS GND 00026-035 A0 A1 VIN VOUT 1k S1 WR VSS VSS 1SIMILAR CONNECTION FOR ADG406/ADG407. Figure 35. Off Isolation Figure 36. Crosstalk Rev. B | Page 17 of 20 00026-036 A3 D S2 VIN ADG406/ADG407/ADG426 TERMINOLOGY VDD Most positive power supply potential. VSS Most negative power supply potential in dual supplies. In single supply applications, it may be connected to ground. GND Ground (0 V) reference. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. tOPEN Off time measured between 80% points of both switches when switching from one address state to another. RON Ohmic resistance between the D and S terminals. RON Match Difference between the RON of any two channels. VINL Maximum input voltage for Logic 0. IS (Off) Source leakage current when the switch is off. VINH Minimum input voltage for Logic 1. ID (Off) Drain leakage current when the switch is off. IINL (IINH) Input current of the digital input. ID, IS (On) Channel leakage current when the switch is on. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. VD (VS) Analog voltage on Terminal D, Terminal S. Off Isolation A measure of unwanted signal coupling through an off channel. CS (Off) Channel input capacitance for off condition. CD (Off) Channel output capacitance for off condition. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. CD, CS (ON) On switch capacitance. IDD Positive supply current. CIN Digital input capacitance. ISS Negative supply current. tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. Rev. B | Page 18 of 20 ADG406/ADG407/ADG426 OUTLINE DIMENSIONS 1.565 (39.75) 1.380 (35.05) 28 15 0.580 (14.73) 0.485 (12.31) 1 14 0.625 (15.88) 0.600 (15.24) 0.100 (2.54) BSC 0.250 (6.35) MAX 0.195 (4.95) 0.125 (3.17) 0.015 (0.38) GAUGE PLANE 0.015 (0.38) MIN 0.200 (5.08) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.014 (0.36) 0.700 (17.78) MAX 0.005 (0.13) MIN 0.015 (0.38) 0.008 (0.20) 0.070 (1.78) 0.050 (1.27) 071006-A COMPLIANT TO JEDEC STANDARDS MS-011 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS. Figure 37. 28-Lead Plastic Dual In-Line Package {PDIP} Wide Body (N-28-2) Dimensions shown in inches and (millimeters) 0.180 (4.57) 0.165 (4.19) 0.048 (1.22) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 4 5 PIN 1 IDENTIFIER 26 25 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC TOP VIEW (PINS DOWN) 11 12 0.020 (0.51) MIN 0.032 (0.81) 0.026 (0.66) 19 18 0.456 (11.582) SQ 0.450 (11.430) 0.495 (12.57) SQ 0.485 (12.32) 0.120 (3.04) 0.090 (2.29) 0.430 (10.92) 0.390 (9.91) BOTTOM VIEW (PINS UP) 0.045 (1.14) R 0.025 (0.64) COMPLIANT TO JEDEC STANDARDS MO-047-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 38. 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28) Dimensions shown in inches and (millimeters) Rev. B | Page 19 of 20 042508-A 0.048 (1.22) 0.042 (1.07) ADG406/ADG407/ADG426 10.50 10.20 9.90 15 28 5.60 5.30 5.00 1 8.20 7.80 7.40 14 0.65 BSC 0.38 0.22 SEATING PLANE 8 4 0 COMPLIANT TO JEDEC STANDARDS MO-150-AH 0.95 0.75 0.55 060106-A 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX Figure 39. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADG406BN ADG406BNZ ADG406BP ADG406BP-REEL ADG406BPZ ADG406BPZ-REEL ADG407BN ADG407BNZ ADG407BP ADG407BP-REEL ADG407BPZ ADG407BPZ-RL ADG407BCHIPS ADG426BN ADG426BNZ ADG426BRS ADG426BRS-REEL ADG426BRS-REEL7 ADG426BRSZ ADG426BRSZ-REEL 1 2 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 28-Lead PDIP 28-Lead PDIP 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PDIP 28-Lead PDIP 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PDIP 28-Lead PDIP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP Z = RoHS Compliant Part. N = Plastic DIP, P = Plastic Leaded Chip Carrier (PLCC), RS = Shrink Small Outline Package (SSOP). (c)1994-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00026-0-5/10(B) Rev. B | Page 20 of 20 Package Option 2 N-28-2 N-28-2 P-28 P-28 P-28 P-28 N-28-2 N-28-2 P-28 P-28 P-28 P-28 DIE N-28-2 N-28-2 RS-28 RS-28 RS-28 RS-28 RS-28