Y33A41235FPLFT - C & K COMPONENTS

1. General description

The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded

applications featuring a high level of integration and low power consumption. The ARM

Cortex-M3 is a next generation core that offers system enhancements such as enhanced

debug features and a higher level of support block integration.

The LPC1311/13/42/43 operate at CPU frequencies of up to 72 MHz. The ARM

Cortex-M3 CPU incorporates a 3-stage pi peline and uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals. The ARM

Cortex-M3 CPU also includes an internal prefetch unit that supports speculative

branching.

The peripheral comp lement of the LPC1311/13/42/43 includes up to 32 kB of flash

memory, up to 8 kB of data memor y, USB Device (LPC1342/43 only), one Fast-mode Plus

I2C-bus interface, one UART, four general purpose timers, and up to 42 general purpose

I/O pins.

2. Features and benefits

ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.

ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming

memory.

8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.

In-System Programming (ISP) and In- A pplication Programming (IAP) via on-chip

bootloader software.

Selectable boot-up: UART or USB (USB on LPC134x only).

On LPC134x: USB MSC and HID on-chip drivers.

Serial interfaces:

USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43

only).

UART with fractional baud rate generation, modem, internal FIFO, and

RS-485/EIA-485 support.

SSP controller with FIFO and multi-protocol capabilities.

I2C-bus interface supporting full I2C-bus specification and Fa st-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monitor mode.

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and

8 kB SRAM; USB device

Rev. 3 — 10 August 2010 Product data sheet

Product data sheet Rev. 3 — 10 August 2010 2 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Other periph er als :

Up to 42 General Purpose I/O (GPIO) pi ns with configurable pull-up/pull-down

resistors.

Four general pu rp os e co un te r/ tim er s w ith a to tal of four captu re inpu ts and 13

match outpu ts.

Programmable WatchDog Timer (WDT).

System tick timer.

Serial Wire Debug and Serial Wire Trace port.

High-current output driver (20 mA) on one pin.

High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.

Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

Single power supply (2.0 V to 3.6 V).

10-bit ADC with input multiplexing among 8 pins.

GPIO pins can be used as edge and level sensitive interrupt sources.

Clock output function with divider that can reflect the system oscillator clock, IRC

clock, CPU clock, or the watchdog clock.

Processor wake-u p from Deep-sleep mode via a dedicated star t logic using up to 40 of

the functional pins.

Brownout detect with four separate thresholds for interrupt and one threshold for

forced reset.

Power-On Reset (POR).

Integrated oscillator with an operating range of 1 MHz to 25 MHz.

12 MHz internal RC oscillator trimmed to 1 % accuracy over the entire temperature

and voltage range that can optionally be used as a system clock.

Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.

System PLL allows CPU operation up to the maximum CPU rate without the need fo r a

high-frequency crystal. May be run from the system oscillator or the internal RC

oscillator.

For USB (LPC1342/43), a second, dedicated PLL is provided.

Code Read Protection (CRP) with different security levels.

Unique device serial number for identification.

Availa ble as 48-pin LQFP package and 33-pin HVQFN package.

3. Applications

eMetering

Lighting

Alarm systems

White goods

Product data sheet Rev. 3 — 10 August 2010 3 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

4. Ordering information

4.1 Ordering options

Table 1. Ordering information

Type number Package

Name Description Version

LPC1311FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1313FBD48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

LPC1313FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1342FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 7 × 7 × 0.85 mm n/a

LPC1343FBD48 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

LPC1343FHN33 HVQFN33 HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 7 × 7 × 0.85 mm n/a

Tabl e 2. Ordering option s for LPC1311/13/42/43

Type number Flash Total

SRAM USB UART

RS-485 I2C/

Fast+ SSP ADC

channels Pins Package

LPC1311FHN33 8 kB 4 kB - 1 1 1 8 33 HVQFN33

LPC1313FBD48 32 kB 8 kB - 1 1 1 8 48 LQFP48

LPC1313FHN33 32 kB 8 kB - 1 1 1 8 33 HVQFN33

LPC1342FHN33 16 kB 4 kB Device 1 1 1 8 33 HVQFN33

LPC1343FBD48 32 kB 8 kB Device 1 1 1 8 48 LQFP48

LPC1343FHN33 32 kB 8 kB Device 1 1 1 8 33 HVQFN33

Product data sheet Rev. 3 — 10 August 2010 4 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

5. Block diagram

(1) LPC1342/43 only.

(2) LQFP48 package only.

Fig 1. Block diagram

SRAM

4/8 kB

ARM

CORTEX-M3

TEST/DEBUG

INTERFACE

FLASH

8/16/32 kB

USB DEVICE

CONTROLLER(1)

I-code

bus

D-code

bus

system

bus

AHB TO

APB

BRIDGE

HIGH-SPEED

GPIO

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

XTALOUT

RESET

clocks and

controls

SWD

USB PHY(1)

SSP

10-bit ADC

UART

32-bit COUNTER/TIMER 0

I2C-BUS

WDT

IOCONFIG

LPC1311/13/42/43

slave

002aae722

slaveslave slave

slave

ROM

slave

AHB-LITE BUS

GPIO ports

PIO0/1/2/3

CT32B0_MAT[3:0]

AD[7:0]

CT32B0_CAP0

SDA

SCL

RXD

TXD

DTR, DSR(2), CTS,

DCD(2), RI(2), RTS

SYSTEM CONTROL

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0]

CT32B1_CAP0

16-bit COUNTER/TIMER 1

CT16B1_MAT[1:0]

CT16B1_CAP0

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0]

CT16B0_CAP0

USB pins

SCK

SSEL

MISO

MOSI

CLKOUT

IRC

WDO

POR

Product data sheet Rev. 3 — 10 August 2010 5 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

6. Pinning information

6.1 Pinning

Fig 2. LPC1343 LQFP48 package

LPC1343FBD48

PIO2_6 PIO3_0

PIO2_0/DTR R/PIO1_2/AD3/CT32B1_MAT1

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE R/PIO1_0/AD1/CT32B1_CAP0

VSS R/PIO0_11/AD0/CT32B0_MAT3

XTALIN PIO2_11/SCK

XTALOUT PIO1_10/AD6/CT16B1_MAT1

VDD SWCLK/PIO0_10/SCK/CT16B0_MAT2

PIO1_8/CT16B1_CAP0 PIO0_9/MOSI/CT16B0_MAT1/SWO

PIO0_2/SSEL/CT16B0_CAP0 PIO0_8/MISO/CT16B0_MAT0

PIO2_7 PIO2_2/DCD

PIO2_8 PIO2_10

PIO2_1/DSR PIO3_3

PIO0_3/USB_VBUS PIO1_7/TXD/CT32B0_MAT1

PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0

PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0

PIO1_9/CT16B1_MAT0 VDD

PIO2_4 PIO3_2

USB_DM PIO1_11/AD7

USB_DP VSS

PIO2_5 PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO0_6/USB_CONNECT/SCK SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO0_7/CTS

PIO2_9

PIO2_3/RI

PIO3_1

002aae505

Product data sheet Rev. 3 — 10 August 2010 6 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Fig 3. LPC1342/43 HVQFN33 package

002aae516

LPC1342FHN33

LPC1343FHN33

Transparent top view

PIO0_8/MISO/CT16B0_MAT0

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL/CT16B0_CAP0

PIO0_9/MOSI/CT16B0_MAT1/SWO

VDD SWCLK/PIO0_10/SCK/CT16B0_MAT2

XTALOUT PIO1_10/AD6/CT16B1_MAT1

XTALIN R/PIO0_11/AD0/CT32B0_MAT3

PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE R/PIO1_0/AD1/CT32B1_CAP0

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO2_0/DTR R/PIO1_2/AD3/CT32B1_MAT1

PIO0_3/USB_VBUS

PIO0_4/SCL

PIO0_5/SDA

PIO1_9/CT16B1_MAT0

USB_DM

USB_DP

PIO0_6/USB_CONNECT/SCK

PIO0_7/CTS

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

PIO1_5/RTS/CT32B0_CAP0

VDD

PIO3_2

PIO1_11/AD7

PIO1_4/AD5/CT32B1_MAT3/WAKEUP

SWDIO/PIO1_3/AD4/CT32B1_MAT2

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

terminal 1

index area

33 VSS

Product data sheet Rev. 3 — 10 August 2010 7 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Fig 4. LPC1313 LQFP48 package

LPC1313FBD48

PIO2_6 PIO3_0

PIO2_0/DTR R/PIO1_2/AD3/CT32B1_MAT1

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

VSS R/PIO0_11/AD0/CT32B0_MAT3

XTALIN PIO2_11/SCK

XTALOUT PIO1_10/AD6/CT16B1_MAT1

VDD SWCLK/PIO0_10/SCK/CT16B0_MAT2

PIO1_8/CT16B1_CAP0 PIO0_9/MOSI/CT16B0_MAT1/SWO

PIO0_2/SSEL/CT16B0_CAP0 PIO0_8/MISO/CT16B0_MAT0

PIO2_7 PIO2_2/DCD

PIO2_8 PIO2_10

PIO2_1/DSR PIO3_3

PIO0_3 PIO1_7/TXD/CT32B0_MAT1

PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0

PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0

PIO1_9/CT16B1_MAT0 VDD

PIO3_4 PIO3_2

PIO2_4 PIO1_11/AD7

PIO2_5 VSS

PIO3_5 PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO0_6/SCK SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO0_7/CTS

PIO2_9

PIO2_3/RI

PIO3_1

002aae513

Product data sheet Rev. 3 — 10 August 2010 8 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Fig 5. LPC1311/13 HVQFN33 package

002aae517

LPC1311FHN33

LPC1313FHN33

Transparent top view

PIO0_8/MISO/CT16B0_MAT0

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL/CT16B0_CAP0

PIO0_9/MOSI/CT16B0_MAT1/SWO

VDD SWCLK/PIO0_10/SCK/CT16B0_MAT2

XTALOUT PIO1_10/AD6/CT16B1_MAT1

XTALIN R/PIO0_11/AD0/CT32B0_MAT3

PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO1_0/AD1/CT32B1_CAP0

RESET/PIO0_0 R/PIO1_1/AD2/CT32B1_MAT0

PIO2_0/DTR R/PIO1_2/AD3/CT32B1_MAT1

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

PIO1_9/CT16B1_MAT0

PIO3_4

PIO3_5

PIO0_6/SCK

PIO0_7/CTS

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

PIO1_5/RTS/CT32B0_CAP0

VDD

PIO3_2

PIO1_11/AD7

PIO1_4/AD5/CT32B1_MAT3/WAKEUP

SWDIO/PIO1_3/AD4/CT32B1_MAT2

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

terminal 1

index area

33 VSS

Product data sheet Rev. 3 — 10 August 2010 9 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

6.2 Pin description

Table 3. LPC1313/43 LQFP48 pin description table

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

RESET/PIO0_0 3[2] yes I I; PU RESET — External reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default states, and

processor execution to begin at address 0.

I/O - PIO0_0 — General purpose digital input/output pin.

PIO0_1/CLKOUT/

CT32B0_MAT2/

USB_FTOGGLE

4[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on

this pin during reset starts the ISP command handler or the USB device

enumeration (USB on LPC1343 only, see description of PIO0_3).

O- CLKOUT — Clockout pin.

O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

O- USB_FTOGGLE — USB 1 ms Start-of-Frame signal (LPC1343 only).

PIO0_2/SSEL/

CT16B0_CAP0 10[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.

I/O - SSEL — Slave select for SSP.

I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_3/USB_VBUS 14[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. LPC1343 only: A

LOW level on this pin during reset starts the ISP command handler, a

HIGH level starts the USB device enumeration.

I- USB_VBUS — Monitors the presence of USB bus power (LPC134 3

only).

PIO0_4/SCL 15[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain).

I/O - SCL — I2C-bus clock input/output (open-drain). High-current sink only

if I2C Fast-mode Plus is selected in the I/O configuration register.

PIO0_5/SDA 16[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain).

I/O - SDA — I2C-bus data input/output (open-drain). High-current sink only if

I2C Fast-mode Plus is selected in the I/O configurati on register.

PIO0_6/

USB_CONNECT/

SCK

22[3] yes I/O I; PU PIO0_6 — General purpose digi tal input/output pin.

O- USB_CONNECT — Signal used to switch an ex ternal 1.5 kΩ resistor

under software control. Used with the SoftConnect USB feature

(LPC1343 only).

I/O - SCK — Serial clock for SSP.

PIO0_7/CTS 23[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output

driver).

I- CTS — Clear To Send input for UART.

PIO0_8/MISO/

CT16B0_MAT0 27[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.

I/O - MISO — Master In Slave Out for SSP.

O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_9/MOSI/

CT16B0_MAT1/

SWO

28[3] yes I/O I; PU PIO0_9 — General purpose digi tal input/output pin.

I/O - MOSI — Master Out Slave In for SSP.

O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

O- SWO — Serial wire trace output.

Product data sheet Rev. 3 — 10 August 2010 10 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

SWCLK/PIO0_10/

SCK/CT16B0_MAT2 29[3] yes I I; PU SWCLK — Serial wire clock.

I/O - PIO0_10 — General purpose digital input/output pin.

I/OO - SCK — Serial clock for SSP.

O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

R/PIO0_11/

AD0/CT32B0_MAT3 32[5] yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO0_11 — General purpose digital input/output pin.

I- AD0 — A/D converter, inp ut 0.

O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

R/PIO1_0/

AD1/CT32B1_CAP0 33[5] yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_0 — General purpose digital input/output pin.

I- AD1 — A/D converter, inp ut 1.

I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

R/PIO1_1/

AD2/CT32B1_MAT0 34[5] yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_1 — General purpose digital input/output pin.

I- AD2 — A/D converter, inp ut 2.

O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R/PIO1_2/

AD3/CT32B1_MAT1 35[5] yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_2 — General purpose digital input/output pin.

I- AD3 — A/D converter, inp ut 3.

O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3/

AD4/

CT32B1_MAT2

39[5] yes I/O I; PU SWDIO — Serial wire debug input/output.

I/O - PIO1_3 — General purpose digital input/output pin.

I- AD4 — A/D converter, inp ut 4.

O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_4/AD5/

CT32B1_MAT3/

WAKEUP

40[5] yes I/O I; PU PIO1_4 — General purpose digi tal input/output pin.

I- AD5 — A/D converter, inp ut 5.

O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

I- WAKEUP — Deep power-down mode wake-up pin. This pin must be

pulled HIGH externally to enter Deep power-down mode and pulled

LOW to exit Deep power-down mode.

PIO1_5/RTS/

CT32B0_CAP0 45[3] yes I/O I; PU PIO1_5 — General purpose digital input/output pin.

O- RTS — Request To Send output for UART.

I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO1_6/RXD/

CT32B0_MAT0 46[3] yes I/O I; PU PIO1_6 — General purpose digital input/output pin.

I- RXD — Receiver input for UART.

O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

Table 3. LPC1313/43 LQFP48 pin description table …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 August 2010 11 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

PIO1_7/TXD/

CT32B0_MAT1 47[3] yes I/O I; PU PIO1_7 — General purpose digital input/output pin.

O- TXD — Transmitter output for UART.

O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8/CT16B1_C

AP0 9[3] yes I/O I; PU PIO1_8 — General purpose digital input/output pin.

I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

PIO1_9/CT16B1_M

AT0 17[3] yes I/O I; PU PIO1_9 — General purpose digital input/output pin.

O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

PIO1_10/AD6/

CT16B1_MAT1 30[5] yes I/O I; PU PIO1_10 — General purpose digital input/output pin.

I- AD6 — A/D converter, inp ut 6.

O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

PIO1_11/AD7 42[5] yes I/O I; PU PIO1_11 — General purpose digital input/output pi n.

I- AD7 — A/D converter, inp ut 7.

PIO2_0/DTR 2[3] yes I/O I; PU PIO2_0 — General purpose digital input/output pin .

O- DTR — Data Terminal Ready output for UART.

PIO2_1/DSR 13[3] yes I/O I; PU PIO2_1 — General purpose digi tal input/output pin.

I- DSR — Data Set Ready input for UART.

PIO2_2/DCD 26[3] yes I/O I; PU PIO2_2 — General purpose digi tal input/output pin.

I- DCD — Data Carrier Detect input for UART.

PIO2_3/RI 38[3] yes I/O I; PU PIO2_3 — General purpose digi tal input/output pin.

I- RI — Ring Indicator input for UART.

PIO2_4 18[3] yes I/O I; PU PIO2_4 — General purpose digi tal input/outpu t pin (LPC1343 only).

PIO2_4 19[3] yes I/O I; PU PIO2_4 — General purpose digi tal input/outpu t pin (LPC1313 only).

PIO2_5 21[3] yes I/O I; PU PIO2_5 — General purpose digi tal input/outpu t pin (LPC1343 only).

PIO2_5 20[3] yes I/O I; PU PIO2_5 — General purpose digi tal input/outpu t pin (LPC1313 only).

PIO2_6 1[3] yes I/O I; PU PIO2_6 — General purpose digital input/output pin.

PIO2_7 11[3] yes I/O I; PU PIO2_7 — General purpose digital input/output pin.

PIO2_8 12[3] yes I/O I; PU PIO2_8 — General purpose digi tal input/outpu t pin.

PIO2_9 24[3] yes I/O I; PU PIO2_9 — General purpose digi tal input/outpu t pin.

PIO2_10 25[3] yes I/O I; PU PIO2_10 — General purpose digital input/output pin.

PIO2_11/SCK 31[3] yes I/O I; PU PIO2_11 — General purpose digital input/output pi n.

I/O - SCK — Serial clock for SSP.

PIO3_0 36[3] yes I/O I; PU PIO3_0 — General purpose digi tal input/outpu t pin.

PIO3_1 37[3] yes I/O I; PU PIO3_1 — General purpose digi tal input/outpu t pin.

PIO3_2 43[3] yes I/O I; PU PIO3_2 — General purpose digi tal input/outpu t pin.

PIO3_3 48[3] yes I/O I; PU PIO3_3 — General purpose digi tal input/outpu t pin.

PIO3_4 18[3] no I/O I; PU PIO3_4 — General purpose digital input/output pin (LPC1313 only).

PIO3_5 21[3] no I/O I; PU PIO3_5 — General purpose digital input/output pin (LPC1313 only).

USB_DM 19[6] no I/O F USB_DM — USB bidirectional D− line (LPC1343 only).

USB_DP 20[6] no I/O F USB_DP — USB bidirectional D+ line (LPC1343 only).

Table 3. LPC1313/43 LQFP48 pin description table …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 August 2010 12 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;

F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.

[2] See Figure 31 for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset

the chip and wake up from Deep power-down mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 30).

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 30).

[6] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only).

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

VDD 8;

44 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the

ADC. Also used as the ADC reference voltage.

XTALIN 6[7] - I - Input to the oscillator circuit and internal clock generator circuits. Input

voltage must not exceed 1.8 V.

XTALOUT 7[7] - O - Output from the oscillator amplifier.

VSS 5;

41 - I - Ground.

Table 3. LPC1313/43 LQFP48 pin description table …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Table 4. LPC1311/13/42/43 HVQFN33 pin description table

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

RESET/PIO0_0 2[2] yes I I; PU RESET — External reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default states, and

processor execution to begin at address 0.

I/O - PIO0_0 — General purpose digital input/output pin.

PIO0_1/CLKOUT/

CT32B0_MAT2/

USB_FTOGGLE

3[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on this

pin during reset starts the ISP command handler or the USB device

enumeration (USB on LPC1342/43 only, see description of PIO0_3).

O- CLKOUT — Clock out pin.

O- CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

O- USB_FTOGGLE — USB 1 ms Start-of-Frame signal (LPC1342/43 only).

PIO0_2/SSEL/

CT16B0_CAP0 8[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin.

I/O - SSEL — Slave select for SSP.

I- CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO0_3/

USB_VBUS 9[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. LPC1342/43 only: A

LOW level on this pin during reset starts the ISP command handler, a

HIGH level starts the USB device enumeration.

I- USB_VBUS — Monitors the presence of USB bus power (LPC1342/43

only).

PIO0_4/SCL 10[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain).

I/O - SCL — I2C-bus clock input/output (open-drain). High-current sink only if

I2C Fast-mode Plus is selected in the I/O configuration register.

Product data sheet Rev. 3 — 10 August 2010 13 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

PIO0_5/SDA 11[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (op en-drain).

I/O - SDA — I2C-bus data input/output (open-drain). High-current sink only if

I2C Fast-mode Plus is selected in the I/O configuration register.

PIO0_6/

USB_CONNECT/

SCK

15[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin.

O- USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor

under software control. Used with the SoftConnect USB feature

(LPC1342/43 only).

I/O - SCK — Serial clock for SSP.

PIO0_7/CTS 16[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output

driver).

I- CTS — Clear To Send input for UART.

PIO0_8/MISO/

CT16B0_MAT0 17[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin.

I/O - MISO — Master In Slave Out for SSP.

O- CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO0_9/MOSI/

CT16B0_MAT1/

SWO

18[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin.

I/O - MOSI — Master Out Slave In for SSP.

O- CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

O- SWO — Serial wire trac e ou tp u t.

SWCLK/PIO0_10/

SCK/

CT16B0_MAT2

19[3] yes I I; PU SWCLK — Serial wire clock.

I/O - PIO0_10 — General purpose digital input/output pin.

O- SCK — Serial clock for SSP.

O- CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

R/PIO0_11/AD0/

CT32B0_MAT3 21[5] yes - I; PU R — Reserved. Configure for an alte rnate function in the IOCONFIG

block.

I/O - PIO0_11 — General purpose digital input/output pin.

I- AD0 — A/D converter, input 0.

O- CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

R/PIO1_0/AD1/

CT32B1_CAP0 22[5] yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG

block.

I/O - PIO1_0 — General purpose digital input/output pin.

I- AD1 — A/D converter, input 1.

I- CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

R/PIO1_1/AD2/

CT32B1_MAT0 23[5] yes - I; PU R — Reserved. Configure for an alte rnate function in the IOCONFIG

block.

I/O - PIO1_1 — General purpose digital input/output pin.

I- AD2 — A/D converter, input 2.

O- CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

Table 4. LPC1311/13/42/43 HVQFN33 pin description table …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 August 2010 14 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

R/PIO1_2/AD3/

CT32B1_MAT1 24[5] yes - I; PU R — Reserved. Configure for an alte rnate function in the IOCONFIG

block.

I/O - PIO1_2 — General purpose digital input/output pin.

I- AD3 — A/D converter, input 3.

O- CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3/

AD4/

CT32B1_MAT2

25[5] yes I/O I; PU SWDIO — Serial wire debug input/output.

I/O - PIO1_3 — General purpose digital input/output pin.

I- AD4 — A/D converter, input 4.

O- CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_4/AD5/

CT32B1_MAT3/WA

KEUP

26[5] yes I/O I; PU PIO1_4 — General purpose digital input/output pin.

I- AD5 — A/D converter, input 5.

O- CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

I- WAKEUP — Deep power-down mode wake-up pin. Th is pin must be

pulled HIGH externally to enter Deep power-down mode and pulled LOW

to exit Deep power-down mode.

PIO1_5/RTS/

CT32B0_CAP0 30[3] yes I/O I; PU PIO1_5 — General purpose digi tal input/output pin.

O- RTS — Request To Send output for UART.

I- CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO1_6/RXD/

CT32B0_MAT0 31[3] yes I/O I; PU PIO1_6 — General purpose digital input/output pin.

I- RXD — Receiver input for UART.

O- CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

PIO1_7/TXD/

CT32B0_MAT1 32[3] yes I/O I; PU PIO1_7 — General purpose digital input/output pin.

O- TXD — Transmitter output for UART.

O- CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8/

CT16B1_CAP0 7[3] yes I/O I; PU PIO1_8 — General purpose digital input/output pin.

I- CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

PIO1_9/

CT16B1_MAT0 12[3] yes I/O I; PU PIO1_9 — General purpose digital input/output pin.

O- CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

PIO1_10/AD6/

CT16B1_MAT1 20[5] yes I/O I; PU PIO1_10 — General purpose digital input/output pin.

I- AD6 — A/D converter, input 6.

O- CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

PIO1_11/AD7 27[5] yes I/O I; PU PIO1_11 — General purpose digital input/output pin.

I- AD7 — A/D converter, input 7.

PIO2_0/DTR 1[3] yes I/O I; PU PIO2_0 — General purpose digital input/output pin.

O- DTR — Data Terminal Ready output for UART.

PIO3_2 28[3] yes I/O I; PU PIO3_2 — General purpose digital input/output pin.

PIO3_4 13[3] no I/O I; PU PIO3_4 — General purpose digital input/output pin (LPC1311/13 only).

PIO3_5 14[3] no I/O I; PU PIO3_5 — General purpose digital input/output pin (LPC1311/13 only).

USB_DM 13[6] no I/O F USB_DM — USB bidirectional D− line (LPC1342/43 only).

USB_DP 14[6] no I/O F USB_DP — USB bidirectional D+ line (LPC1342/43 only).

Table 4. LPC1311/13/42/43 HVQFN33 pin description table …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 August 2010 15 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled.

F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.

[2] See Figure 31 for pad characteristics. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset

the chip and wake up from Deep power-down mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 30).

[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure 30).

[6] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only).

[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

VDD 6;

29 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the

ADC. Also used as the ADC refere nce voltage.

XTALIN 4[7] - I - Input to the oscillator circuit and internal clock generator circuits. Input

voltage must not exceed 1.8 V.

XTALOUT 5[7] - O - Output from the oscillator amplifier.

VSS 33 - - - Thermal pad. Connect to ground.

Table 4. LPC1311/13/42/43 HVQFN33 pin description table …continued

Symbol Pin Start

logic

input

Type Reset

state

[1]

Description

Product data sheet Rev. 3 — 10 August 2010 16 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7. Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus (s ee Figure 1). The I-code and D-code core buses are faster than the

system bus and are used similarly to TCM interfaces: one bus dedicated for instruction

fetch (I-code) and one bu s for data access (D-code ). The use of two core buses allo ws for

simultaneous operations if concurrent operations target diff erent devices.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,

interruptible/continuable multiple load and store instructions, automatic state save and

restore for interrupts, tightly integrated interrupt controller, and multiple core buses

capable of simultaneous accesses.

Pipeline techniques are em ployed so that all p arts of the processing and memory system s

can operate continuously. Typically, while one instruction is being executed, its successo r

is being decoded, and a thir d instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual which is available on the official ARM website.

7.3 On-chip flash program memory

The LPC1311/13/42/43 contain 32 kB (LPC1313 and LPC1343), 16 kB (LPC1342), or

8 kB (LPC1311) of on-chip flash memory.

7.4 On-chip SRAM

The LPC1311/13/42/43 cont ain a total of 8 kB (LPC1343 and LPC1313) or 4 kB (L PC1342

and LPC1311) on-chip static RAM memory.

7.5 Memory map

The LPC134x incorporates several distinct memory regions, shown in the following

figures. Figure 6 shows the overall map of the entire address spa ce from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.

The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the

address decoding for each peripheral.

Product data sheet Rev. 3 — 10 August 2010 17 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.6 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.6.1 Features

•Controls system exceptions and peripheral interrupts.

•On the LPC1311/13/42/43 , th e NVIC su pp o rts 16 vectored interrupts. In addition, up

to 40 of the individual GPIO inputs are NVIC-vector cap able.

Fig 6. LPC1311/13/42/43 memory map

0x5000 0000

0x5001 0000

0x5002 0000

0x5020 0000

AHB peripherals

16 - 127 reserved

GPIO PIO1

4-7

0x5003 0000

0x5004 0000

GPIO PIO2

GPIO PIO3

8-11

12-15

GPIO PIO0

0-3

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

WDT

32-bit counter/timer 0

32-bit counter/timer 1

ADC

UART

PMU

I2C-bus

10 - 13 reserved

reserved

19 - 31 reserved

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x0000 4000

0x0000 2000

0x1000 2000

0x1000 1000

0x1FFF 0000

0x1FFF 4000

0x2200 0000

0x2000 0000

0x2400 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5020 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

AHB SRAM bit-band alias addressing

8 kB SRAM (LPC1313/1343)

0x1000 0000

4 kB SRAM (LPC1311/1342)

LPC1311/13/42/43

16 kB on-chip flash (LPC1342)

8 kB on-chip flash (LPC1311)

0x0000 8000

32 kB on-chip flash (LPC1313/43)

16 kB boot ROM

0x0000 0000

0x0000 0400

active interrupt vectors

+ 256 words

I-code/D-code

memory space

002aae72

reserved

SSP

16-bit counter/timer 1

16-bit counter/timer 0

USB (LPC1342/43 only)

IOCONFIG

system control

flash controller

0xE000 0000

0xE010 0000

private peripheral bus

Product data sheet Rev. 3 — 10 August 2010 18 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

•8 programmable interrupt priority levels, with hardware priority level masking

•Relocatable vector table.

•Software interrupt generation .

7.6.2 Interrupt sources

Each peripheral devi ce has one interrupt line conne cted to the NVIC but may have several

interrupt flags. Individual interrup t flags may also represent more than one interrupt

source.

Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be

programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.7 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be conn ected to th e appro priate pins prior to being activated and prior

to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.8 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamica lly configured as input s or outputs. Multip le outputs

can be set or cleared in on e wr ite op e ra tio n.

LPC1311/13/42/43 use accelerated GPIO functions:

•GPIO block is a dedicated AHB peripheral so that the fastest possible I/O timing can

be achieved.

•Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be

programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.8.1 Features

•Bit level port registers allow a single instruction to set or clear any number of bits in

one write operation.

•Direction control of individual bits.

•All I/O default to inputs with pull-up resistors enabled after reset with the exception of

the I2C-bus pins PIO0_4 an d PIO0_5.

•Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG

block for each GPIO pin.

Product data sheet Rev. 3 — 10 August 2010 19 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.9 USB interface (LPC1342/43 only)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports

hot-plugging an d dynamic configuration of th e devices. All transactions are initiated by the

host controller.

The LPC1342/43 USB interface is a device controller with on-chip PHY for device

functions.

7.9.1 Full-speed USB device controller

The device controller enable s 12 Mbit/s data exchange with a USB Host controller. It

consists of a register interface, serial interface engine, and endpoint buffer memory. The

serial interface engine decod es the USB data stream and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

7.9.1.1 Features

•Dedicated USB PLL available.

•Fully compliant with USB 2.0 specification (full speed).

•Supports 10 physical (5 logical) endpoints with up to 64 bytes buffer RAM per

endpoint (see Table 5).

•Supports Control, Bulk, Isochronous, and Interrupt endpoints.

•Supports SoftConnect feature.

•Double buffer implementation for Bulk and Isochronous endpoints.

7.10 UART

The LPC1311/13/42/43 contains one UART.

Support for RS-4 85 /9 -b it mo d e allo ws bo th software addr ess detection and auto m at ic

address detection using 9-bit mode.

Table 5. USB device endpoint configuration

Logical

endpoint Physical

endpoint Endpoint type Direction Packet size

(byte) Double buffer

0 0 Control out 64 no

0 1 Control in 64 no

1 2 Interrupt/Bulk out 64 no

1 3 Interrupt/Bulk in 64 no

2 4 Interrupt/Bulk out 64 no

2 5 Interrupt/Bulk in 64 no

3 6 Interrupt/Bulk out 64 yes

3 7 Interrupt/Bulk in 64 yes

4 8 Isochronous out 512 yes

4 9 Isochronous in 512 yes

Product data sheet Rev. 3 — 10 August 2010 20 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.10.1 Features

•Maximum UART data bit rate of 4.5 MBit/s.

•16-byte receive and transmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud ra te generator covering wide range of baud rates without a

need for external crystals of particular values.

•Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

•Support for RS -485 /9 -b it mo d e.

•Support for modem control.

7.11 SSP serial I/O controller

The LPC1311/13/42/43 contain one SSP controller. The SSP controller is capable of

operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and

slaves on the bus. Only a single master and a single slave can communicate on the bus

during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits

to 16 bits of data flo wing from the ma ste r to the slave and from the slave to the master. In

practice, often only one of these data flows carries meaningful data.

7.11.1 Features

•Maximum SSP speed of 36 Mbit/s (master) or 6 Mbit/s (slave)

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

7.12 I2C-bus serial I/O controller

The LPC1311/13/42/43 contain one I2C-bus controller.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-only de vice ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on whe ther th e chip ha s

to initiate a data transfer or is only addressed. The I2C is a multi-master bus an d ca n be

controlled by more than one bus master connected to it.

Product data sheet Rev. 3 — 10 August 2010 21 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.12.1 Features

•The I2C-bus interface is a standard I2C-bus compliant interface with true open-drain

pins. The I2C-b us interface also su ppo rts Fast-mode Plus with bit rates up to 1 Mbit/s.

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake me chanism to suspend and

resume serial transfer.

•The I2C-bus can be used for test an d diagnostic purposes.

•The I2C-bus controller supports multiple address recognition and a bus mo nitor mode .

7.13 10-bit ADC

The LPC1311/13/42/43 contains one ADC. It is a single 10-bit successive approximation

ADC with eight channels.

7.13.1 Features

•10-bit successive approximation ADC.

•Input multiplexing among 8 pins.

•Power-down mode.

•Measurement range 0 V to VDD.

•10-bit conver sio n time ≥ 2.44 μs (up to 400 kSamples/s).

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition of input pin or timer match signal.

•Individual result registers for each ADC channel to reduce interrupt overhead.

7.14 General purpose external event counter/timers

The LPC1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counte r/timers.

The counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified tim er values, based on four

match registers. Each counter/timer also includes one capture input to trap the timer value

when an input signal transitions, optionally generating an interrupt.

7.14.1 Features

•A 32-bit/16-bit counter/timer with a programmable 32-bit/16-bit prescaler.

•Counter or time r op er a tion .

•One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

Product data sheet Rev. 3 — 10 August 2010 22 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

•Four match re gis ter s pe r tim er that allow :

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional inter rupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

7.15 System tick timer

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval, normally set to 10 ms.

7.16 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a selectable time

period. When enabled, the watchdog will generate a system reset if the user program fails

to ‘feed’ (or reload) the watchdog within a predetermined amou nt of time.

7.16.1 Features

•Internally resets chip if not periodically reloaded.

•Debug mode.

•Enabled by soft ware but requires a hardwar e reset or a watchdog reset/interrupt to be

disabled.

•Incorrect/incomplete feed sequence causes reset/interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 32-bit tim er with internal prescaler.

•Selectable time period from (Tcy(WDCLK) ×256 ×4) to (Tcy(WDCLK) ×232 ×4) in

multiples of Tcy(WDCLK) ×4.

•The W atchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC), the watchdog oscillator, or the main clock. This gives a wide range of potential

timing choices of watchdog operation unde r different power reduction conditions. It

also provides the ability to run the WDT from an entirely internal source that is not

dependent on an external crystal and its associated components and wiring for

increased reliability.

7.17 Clocking and power control

7.17.1 Integrated oscillators

The LPC1311/13/42/43 include three independent oscillators. These are the system

oscillator , the Internal RC oscillator (IRC), and the watchdog oscillator . Each oscillator can

be used for more than one purpose as required in a particular application.

Product data sheet Rev. 3 — 10 August 2010 23 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Following reset, the LPC1311/13/42/43 will operate from the internal RC oscillator until

switched by software. This allows systems to oper ate without any exte rnal cryst al and the

bootloader code to operate at a known frequency.

See Figure 7 for an overview of the LPC1311/13/42/43 clock generation.

The USB clock is available on LPC1342/43 only.

Fig 7. LPC1311/13/42/43 clocking generation block diagram

SYSTEM PLL

IRC oscillator

system oscillator

watchdog oscillator

IRC oscillator

watchdog oscillator

USB PLL

MAINCLKSEL

(main clock select)

SYSPLLCLKSEL

(system PLL clock select)

USBPLLCLKSEL

(USB clock select)

SYSTEM CLOCK

DIVIDER

AHBCLKCTRL

(AHB clock enable)

AHB clock 0

(system)

AHB clock 1

(ROM)

AHB clock 16

(IOCONFIG)

AHBCLKCTRL

SSP PERIPHERAL

CLOCK DIVIDER SSP

UART PERIPHERAL

CLOCK DIVIDER UART

SYSTICK TIMER

CLOCK DIVIDER

WDT CLOCK

DIVIDER

SYSTICK

timer

ARM TRACE

CLOCK DIVIDER

ARM

trace clock

WDT

WDTUEN

(WDT clock update enable)

USB 48 MHz CLOCK

DIVIDER USB

USBUEN

(USB clock update enable)

watchdog oscillator

IRC oscillator

system oscillator CLKOUT PIN CLOCK

DIVIDER CLKOUT pin

CLKOUTUEN

(CLKOUT update enable)

002aae859

main clock

system clock

IRC oscillator

AHB clocks

2 to 15

(memories

and peripherals)

Product data sheet Rev. 3 — 10 August 2010 24 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.17.1.1 Internal RC oscillator

The IRC may be used as th e clock source for th e WDT, and/or as the clock that drives the

system PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC

is trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up, any chip reset, or wake- up from Deep power-down mode, the

LPC1311/13/42/43 use the IRC as the clock source. Software may later switch to one of

the other availa ble clock sources.

7.17.1.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL. On the LPC134x, the system oscillator must be used to provide the clock source

to USB.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

7.17.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable between 7.8 kHz and 1.7 MHz. The frequency spread over p rocessing and

temperature is ±40 % (see also Table 14).

7.17.2 System PLL and USB PLL

The LPC134x cont ain a system PLL and a dedicate d PLL for g enerating the 48 MHz USB

clock. The LPC131x contain the system PLL only. The system and USB PLLs are

identical.

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce th e ou tp ut clock. Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must configure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is 100 μs.

7.17.3 Clock output

The LPC1311/13/42/43 features a clock output function that routes the IRC oscillator, the

system oscillator, the watchdog oscillator, or the main clock to an output pin.

7.17.4 Wake-up process

The LPC1311/13/42/43 begin op eration at power-up and when awakened from Deep

power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows

chip operation to resume quickly. If the main oscillator or the PLL is needed by the

application, software will need to enable these features and wait for them to stabilize

before they are used as a clock source.

Product data sheet Rev. 3 — 10 August 2010 25 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.17.5 Power control

The LPC1311/13/42/43 support a variety of power control features. There are three

special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep

power-down mode. The CPU clock rate may also be controlled as needed by changing

clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This

allows a trade-off of power versus processing speed based on application requirements.

In addition, a register is provided for shutting down the clocks to individual on-chip

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any periph era ls th at ar e no t req uir ed for the a pplica tion. Selected periph erals have

their own clock divide r wh ich pr ovides even better power control.

7.17.5.1 Sleep mode

When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep

mode does not need an y special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.17.5.2 Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in add ition all analo g blocks are sh ut

down. As an exception, the user has the option to keep the watchdog oscillator and the

BOD circuit running for se lf-timed wake- up and BOD protection. Dee p-sleep mod e allows

for additiona l powe r sa vin gs.

Up to 40 pins total can serve as external wake-up pins to the start logic to wake up the

chip from Deep-sleep mode (see Section 7.18.1).

Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source

should be switched to IRC before entering Deep-sleep mode, because the IRC can be

switched on and off glitch-free.

7.17.5.3 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The LPC1311/13/42/43 can wake up from Deep power-down mode via the

WAKEUP pin.

7.18 System control

7.18.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 3 and Table 4 as input to the start logic has an individual interrupt in the

NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when

the chip is running. In addition, an input signal on the start logic pins can wake up the chip

from Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

Product data sheet Rev. 3 — 10 August 2010 26 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.18.2 Reset

Reset has four sources on the LPC1311/13/42/43: the RESET pin, the Watchdog reset,

power-on reset (POR), and the Brown-Out Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage

attains a usable level, starts the IRC and initializes the fla sh co nt ro ller.

When the internal reset is removed, the processor begins executing at address 0, which is

initially the reset vector mapped from the boo t block. At that point, all of the pr ocessor and

peripheral registers have been initialized to predetermined values.

7.18.3 Brownout detection

The LPC1311/13/42/43 includes four levels for monitoring the voltage on the VDD pin. If

this voltage falls below on e of the four select ed levels, the BOD asserts an interrupt signal

to the NVIC. This signal can be enabled for interrupt in the Interr upt Enable Register in th e

NVIC in order to cause a CPU interrupt; if no t, software can monitor the signal by reading

a dedicated status register. An additional threshold level can be selected to cause a

forced reset of the chip.

7.18.4 Code security (Code Read Protection - CRP)

This feature of the LPC1311/13/42/43 allows user to enable different levels of security in

the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)

and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. In-Application

Programming (IAP) commands are not affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP (NO_ISP

mode). For details see the LPC13xx user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to chip via the SWD and allows partial fla sh update (e xcluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when

CRP is required and flash field update s are needed but all sectors can not be erased.

2. CRP2 disabl es ac ce ss to chip via th e SWD an d on ly allo ws fu ll flash era se and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to chip via

the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1

pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

UART0.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 3 — 10 August 2010 27 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.18.5 Boot loader

The boot loader controls initial operation after reset and also provides the means to

program the flash memory. This could be initial programming of a blank device, erasure

and re-programming of a previously programmed device, or programming of the flash

memory by the application program in a running system.

The boot loader code is executed every time the part is reset or powered up. The loader

can either execute th e ISP command handler or the user application code, or, on the

LPC134x, it can program the flash image via an attached MSC device through USB

(Windows operating system only). A LOW level during reset applied to the PIO0_1 pin is

considered as an exter nal hardware re quest to star t the ISP command handler or the USB

device enumeration. The st ate of PIO0_3 dete rmines whether the UAR T or USB interface

will be used (LPC134x only).

7.18.6 APB interface

The APB peripherals are located on one APB bus.

7.18.7 AHB-Lite

The AHB-Lite connect s the instruction ( I-code) a nd dat a (D-code) CPU bu ses of the ARM

Cortex-M3 to the flash memory, the main static RAM, and the boot ROM.

7.18.8 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as exte rn al in te r ru pts (see Section 7.18.1).

7.18.9 Memory mapping control

The Cortex-M3 incorp orates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address

space. The vector table must be located on a 256 word boundary.

7.19 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M3. Serial wire debug is supported.

Product data sheet Rev. 3 — 10 August 2010 28 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

8. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Dependent on package type.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD supply voltage (core and

external rail) 2.0 3.6 V

VIinput voltage 5 V tolerant I/O pins; only valid

when the VDD supply volt age is

present

[2] −0.5 +5.5 V

IDD supply current per supply pin [3] -100mA

ISS ground current per ground pin [3] -100mA

Ilatch I/O latch-up curre nt −(0.5VDD) < VI < (1.5VDD);

Tj < 125 °C-100mA

Tstg storage temperature [4] −65 +150 °C

Tj(max) maximum junction temperature - 150 °C

Ptot(pack) total power dissipation (per

package) based on package heat transfer, not

device po wer consumption -1.5W

VESD electrostatic discharge voltage human body model; all pins [5] −6500 +6500 V

Product data sheet Rev. 3 — 10 August 2010 29 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

9. Static characteristics

Table 7. Static characteristics

Tamb =−40 °C to +85 °C , unl ess oth erwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD supply voltage (core

and external rail) 2.0 3.3 3.6 V

IDD supply current Active mode; VDD =3.3V;

Tamb =25°C; code

while(1){}

executed from flash;

system clock = 12 MHz [2][3][4]

[5][6] -4-mA

system clock = 72 MHz [3][4][5]

[7][6] -17-mA

Sleep mode;

VDD = 3.3 V; Tamb =25°C;

system clock = 12 MHz

[2][3][4]

[5][6] -2-mA

Deep-sleep mode; VDD = 3.3 V ;

Tamb =25°C[3][8][6] -30-μA

Deep power-down mode;

VDD =3.3V; T

amb =25°C[9] - 220 - nA

Standard port pins and RESET pin; see Figure 16, Figure 17, Figure 18, Figure 19

IIL LOW-level input current VI= 0 V; on-chip pull-up resistor

disabled -0.510nA

IIH HIGH-level input

current VI=V

DD; on-chip pull-down resistor

disabled -0.510nA

IOZ OFF-state output

current VO=0V; V

O=V

DD; on-chip

pull-up/down resistors disabled -0.510nA

VIinput voltage pin configured to provide a digital

function [10][11]

[12] 0- 5.0V

VOoutput voltage output active 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage 0.4 - - V

VOH HIGH-level output

voltage IOH =−4 mA VDD − 0.4 - - V

VOL LOW-level output

voltage IOL =4 mA - - 0.4 V

IOH HIGH-level output

current VOH =V

DD −0.4 V −4- - mA

IOL LOW-level output

current VOL =0.4V 4 - - mA

IOHS HIGH-level short-circuit

output current VOH =0V [13] --−45 mA

IOLS LOW-level short-circuit

output current VOL =V

DD [13] --50mA

Product data sheet Rev. 3 — 10 August 2010 30 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Ipd pull-down current VI= 5 V 10 50 150 μA

Ipu pull-up current VI=0V −15 −50 −85 μA

VDD <V

I<5V 0 0 0 μA

High-drive output pin (PIO0_7); see Figure 14 and Figure 16

IIL LOW-level input current VI= 0 V; on-chip pull-up resistor

disabled -0.510nA

IIH HIGH-level input

current VI=V

DD; on-chip pull-down resistor

disabled -0.510nA

IOZ OFF-state output

current VO=0V; V

O=V

DD; on-chip

pull-up/down resistors disabled -0.510nA

VIinput voltage pin configured to provide a digital

function [10][11]

[12] 0- 5.0V

VOoutput voltage output active 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage 0.4 - - V

VOH HIGH-level output

voltage IOH =−20 mA VDD − 0.4 - - V

VOL LOW-level output

voltage IOL =4 mA - - 0.4 V

IOH HIGH-level output

current VOH =V

DD −0.4 V;

VDD ≥ 2.5 V 20 - - mA

IOL LOW-level output

current VOL =0.4V 4 - - mA

Ipd pull-down current VI= 5 V 10 50 150 μA

Ipu pull-up current VI=0V −15 −50 −85 μA

VDD <V

I<5V 0 0 0 μA

I2C-bus pins (PIO0_4 and PIO0_5); see Figure 15

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage - 0.5VDD -V

VOL LOW-level output

voltage IOLS = 20 mA - - 0.4 V

ILI input leakage current VI=V

DD [14] -24μA

VI= 5 V - 10 22 μA

Oscillator pins

Vi(xtal) crystal input voltage −0.5 +1.8 +1.95 V

Vo(xtal) crystal output voltage −0.5 +1.8 +1.95 V

USB pins (LPC1342/43 only)

IOZ OFF-state output

current 0V<V

I<3.3V - - ±10 μA

Table 7. Static characteristics …continued

Tamb =−40 °C to +85 °C , unl ess oth erwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 3 — 10 August 2010 31 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2] IRC enabled; system oscillator disabled; system PLL disabled.

[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[4] BOD disabled.

[5] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART, SSP, trace clock, and SysTick timer disabled in

the syscon block.

[6] For LPC134x: USB_DP and USB_DM pulled LOW exter nally.

[7] IRC disabled; system oscillator enabled; system PLL enabled.

[8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 0FFF.

[9] WAKEUP pin pulled HIGH externally.

[10] Including voltage on outputs in 3-state mode.

[11] VDD supply voltage must be present.

[12] 3-state outputs go into 3-state mode in Deep power-down mode.

[13] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[14] To VSS.

[15] Includes external resistors of 33 Ω±1 % on USB_DP and USB_DM.

VBUS bus supply voltage - - 5.25 V

VDI differential input

sensitivity voltage |(D+) −(D−)|0.2 - - V

VCM differential common

mode voltage range includes VDI range 0.8 - 2.5 V

Vth(rs)se singl e-ended receiver

switching threshold

voltage

0.8 - 2.0 V

VOL LOW-level output

voltage for low-/full-speed;

RL of 1.5 kΩ to 3.6 V - - 0.18 V

VOH HIGH-level output

voltage driven; for low-/full-speed;

RL of 15 kΩ to GN D 2.8 - 3.5 V

Ctrans transceiver capacitance pin to GND - - 20 pF

ZDRV driver output

impedance for driver

which is not high-speed

capable

with 33 Ω series resistor; steady state

drive [15] 36 - 44.1 Ω

Table 7. Static characteristics …continued

Tamb =−40 °C to +85 °C , unl ess oth erwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Table 8. ADC static characteristics

Tamb =−40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

VIA analog input voltage 0 - VDD V

Cia analog input capacitance - - 1 pF

EDdifferential linearity error [1][2] --±1LSB

EL(adj) integral non-linearity [3] --±1.5 LSB

EOoffset error [4] --±3.5 LSB

EGgain error [5] --0.6%

Product data sheet Rev. 3 — 10 August 2010 32 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 8.

[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 8.

[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 8.

[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 8.

[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 8.

[7] Tamb = 25 °C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 1 pF.

[8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs × Cia).

ETabsolute er ror [6] --±4LSB

Rvsi voltage source interface

resistance --40kΩ

Riinput resistance [7][8] --2.5MΩ

Table 8. ADC static characteristics …continued

Tamb =−40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 3 — 10 August 2010 33 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 8. ADC characteristics

002aaf426

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VDD − VSS

1024

offset

error

gain

error

offset error

VIA (LSBideal)

1 LSB =

Product data sheet Rev. 3 — 10 August 2010 34 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

9.1 BOD static characteristics

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx

user manual.

9.2 Power consumption

Power measurement s in Active, Sleep , and Deep-sleep modes wer e performed under the

following conditions (see LPC13xx user manual):

•Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.

•Configure GPIO pins as outputs using the GPIOnDIR registers.

•Write 0 to all GPIOnDATA registers to drive the outputs LOW.

Table 9. BOD static characteristics[1]

Tamb =25°C.

Symbol Parameter Conditions Min Typ Max Unit

Vth threshold voltage interrupt level 0

assertion - 1.69 - V

de-assertion - 1.84 - V

interrupt level 1

assertion - 2.29 - V

de-assertion - 2.44 - V

interrupt level 2

assertion - 2.59 - V

de-assertion - 2.74 - V

interrupt level 3

assertion - 2.87 - V

de-assertion - 2.98 - V

reset level 0

assertion - 1.49 - V

de-assertion - 1.64 - V

Product data sheet Rev. 3 — 10 August 2010 35 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Conditions: Tamb = 25 °C; active mode entered executing code

while(1){}

from flash;

internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled;

all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all

peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally (LPC134x).

Fig 9. Typical supply current versus regulator supply voltage VDD in active mode

Conditions: VDD = 3.3 V; Active mode entered executing code

while(1){}

from flash; internal

pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral

clocks disabled; USB_DP and USB_DM pulled LOW externally (LPC134x).

Fig 10. Typical supply current versus temperature in Active mode

VDD (V)

2.0 3.63.22.82.4

002aae993

IDD

(mA)

24 MHz

48 MHz

12 MHz

36 MHz

72 MHz

002aae994

temperature (°C)

−40 853510 60−15

IDD

(mA)

24 MHz

12 MHz

36 MHz

72 MHz

48 MHz

Product data sheet Rev. 3 — 10 August 2010 36 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Conditions: VDD = 3.3 V ; Sleep mode entered from flash; internal pull-up resistors disabled; system

oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; USB_DP

and USB_DM pulled LOW externally (LPC134x).

Fig 11. Typical supply current versus temperature in Sleep mode

Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG

(LPC134x).

Fig 12. Typical supply current versus temperature in Deep-sleep mode (analog blocks

disabled)

002aae995

temperature (°C)

−40 853510 60−15

IDD

(mA)

12 MHz

36 MHz

72 MHz

48 MHz

24 MHz

002aae998

temperature (°C)

−40 853510 60−15

IDD

(μA)

VDD = 3.6 V

3.3 V

2.0 V

Product data sheet Rev. 3 — 10 August 2010 37 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

9.3 Peripheral power consumption

The supply current p er peripheral is measured as the differ ence in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG or

PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers

and no code is executed. Measured on a typical sample at Tamb =25 °C. Unless noted

otherwise, the system oscillator and PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, and

72 MHz.

Fig 13. Typical supply current versus temperature in Deep power-down mode

002aae996

0.4

0.6

1.2

IDD

(μA)

temperature (°C)

−40 853510 60−15

VDD = 3.6 V

3.3 V

2.0 V

Table 10. Power consumption for individual analog and digital blocks

Peripheral Typical supply current in mA Notes

n/a 12 MHz 48 MHz 72 MHz

IRC 0.23 - - - System oscillator running; PLL off; independent of main clock

frequency.

System oscillator

at 12 MHz 0.23 - - - IRC running; PLL off; independent of main clock frequency.

Watchdog

oscillator at

500 kHz/2

0.002 - - - System oscillator running; PLL off; independent of main clock

frequency.

BOD 0.045 - - - Independent of main clock frequency.

Main or USB PLL - 0.26 0.34 0.48

ADC - 0.07 0.25 0.37

CLKOUT - 0.14 0 .56 0.82 Main clock divided by 4 in the CLKOUTD IV register.

CT16B0 - 0.010.050.08

CT16B1 - 0.010.040.06

CT32B0 - 0.010.050.07

CT32B1 - 0.010.040.06

Product data sheet Rev. 3 — 10 August 2010 38 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

9.4 Electrical pin characteristics

GPIO - 0.21 0.80 1.17 GPIO pins configured as outputs and set to LOW. Direction

and pin state are maintained if the GPIO is disabled in the

SYSAHBCLKCFG register.

IOCONFIG - 0.00 0.02 0.02

I2C - 0.03 0.12 0.17

ROM - 0.04 0.15 0.22

SSP - 0.11 0.41 0.60

UART - 0.200.761.11

WDT - 0.01 0.05 0.08 Main clock selected as clock source for the WD T.

USB - - 3.91 - Main clock selected as clock source for the USB. USB_DP

and USB_DM pulled LOW externally.

USB - 1.84 4.19 5.71 Dedicated USB PLL selected as cock source for the USB.

USB_DP and USB_DM pulled LOW externally.

Table 10. Power consumption for individual analog and digital blocks …continued

Peripheral Typical supply current in mA Notes

n/a 12 MHz 48 MHz 72 MHz

Conditions: VDD = 3.3 V; on pin PIO0_7.

Fig 14. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level

output current IOH.

IOH (mA)

0 60402010 5030

002aae990

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 3 — 10 August 2010 39 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.

Fig 15. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus

LOW-level output voltage VOL

Conditions: VDD = 3.3 V; standard port pins and PIO0_7.

Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL

VOL (V)

0 0.60.40.2

002aaf019

IOL

(mA)

T = 85 °C

25 °C

−40 °C

VOL (V)

0 0.60.40.2

002aae991

IOL

(mA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 3 — 10 August 2010 40 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Conditions: VDD = 3.3 V; standard port pins.

Fig 17. Typical HIGH-level output voltage VOH versus HIGH-level output source current

IOH

Conditions: VDD = 3.3 V; standard port pins.

Fig 18. Typical pull-up current Ipu versus input volt age Vi

IOH (mA)

0 24168

002aae992

2.8

2.4

3.2

3.6

VOH

(V)

T = 85 °C

25 °C

−40 °C

VI (V)

0 54231

002aae988

−30

−50

−10

Ipu

(μA)

−70

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 3 — 10 August 2010 41 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Conditions: VDD = 3.3 V; standard port pins.

Fig 19. Typical pull-down current Ipd versus input voltage Vi

VI (V)

0 54231

002aae989

Ipd

(μA)

T = 85 °C

25 °C

−40 °C

Product data sheet Rev. 3 — 10 August 2010 42 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

10. Dynamic characteristics

10.1 Flash memory

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.

10.2 External clock

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

Table 11. Flash characteristics

Tamb =−40 °C to +85 °C , unl ess oth erwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance [1] 10000 - - cycles

tret retention time powered 10 - - years

unpowered 20 - - years

ter erase time sector or multiple

consecutive sectors 95 100 105 ms

tprog programming time [2] 0.95 1 1.05 ms

Table 12 . Dynam ic characteristic: exte rnal clock

Tamb =−40 °C to +85 °C; VDD over specified ranges.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc oscillator frequency 1 - 25 MHz

Tcy(clk) clock cycle time 40 - 1000 ns

tCHCX clock HIGH time Tcy(clk) ×0.4 - - ns

tCLCX clock LOW time Tcy(clk) ×0.4 - - ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Fig 20. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

CHCL

CLCX

CHCX

cy(clk)

CLCH

002aaa90

Product data sheet Rev. 3 — 10 August 2010 43 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

10.3 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (Tamb = −40 °C to +85 °C) is ±40 %.

[3] See the LPC13xx user manual.

Table 13 . Dynamic characteristics: IRC

Tamb =−40 °C to +85 °C; 2.7 V ≤ VDD ≤ 3.6 V[1].

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz

Conditions: Frequency values are typical values. 12 MHz ± 1 % accuracy is guaranteed for

2.7 V ≤ VDD ≤ 3.6 V and Tamb =−40 °C to +85 °C. Variations between parts may cause the IRC to

fall outside the 12 MHz ± 1 % accuracy specification for voltages below 2.7 V.

Fig 21. Internal RC oscillator frequency f versus temperature

temperature (°C)

−40 853510 60−15

002aae987

11.95

12.05

12.15

(MHz)

11.85

VDD = 3.6 V

3.3 V

3.0 V

2.7 V

2.4 V

2.0 V

Table 14. Dynamic characteristics: Watchdog oscillator

Symbol Parameter Conditions Min Typ[1] Max Unit

fosc internal oscillator frequency DIVSEL = 0x1F, FREQSEL = 0x1 in the

WDTOSCCTRL register; [2][3] -7.8 - kHz

DIVSEL = 0x00, FREQSEL = 0xF in the

WDTOSCCTRL register [2][3] - 1700 - kHz

Product data sheet Rev. 3 — 10 August 2010 44 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

10.4 I/O pins

[1] Applies to standard port pins and RESET pin.

10.5 I2C-bus

[1] See the I2C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[5] Cb = total capacitance of one bus line in pF.

[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified tf.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

Table 15. Dynamic characteristics: I/O pins[1]

Tamb =−40 °C to +85 °C ; 3.0 V ≤ VDD ≤ 3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

trrise time pin configured as output 3.0 - 5.0 ns

tffall time pin configured as output 2.5 - 5.0 ns

Table 16. Dynamic characteristic: I2C-bus pins[1]

Tamb =−40 °C to +85 °C.[2]

Symbol Parameter Conditions Min Max Unit

fSCL SCL clock

frequency Standard-mode 0 100 kHz

Fast-mode 0 400 kHz

Fast-mode Plus 0 1 MHz

tffall time [4][5][6][7] of both SDA and SCL

signals

Standard-mode

-300ns

Fast-mode 20 + 0.1 × Cb300 ns

Fast-mode Plus - 120 ns

tLOW LOW period of the

SCL clock Standard-mode 4.7 - μs

Fast-mode 1.3 - μs

Fast-mode Plus 0.5 - μs

tHIGH HIGH period of the

SCL clock Standard-mode 4.0 - μs

Fast-mode 0.6 - μs

Fast-mode Plus 0.26 - μs

tHD;DAT data hold time [3][4][8] Standard-mode 0 - μs

Fast-mode 0 - μs

Fast-mode Plus 0 - μs

tSU;DAT data set-up time

[9][10] Standard-mode 250 - ns

Fast-mode 100 - ns

Fast-mode Plus 50 - ns

Product data sheet Rev. 3 — 10 August 2010 45 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

[8] The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or

tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the

SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

Fig 22. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

tHD;DAT

SCL

1 / fSCL

70 %

30 %

70 %

30 %

tVD;DAT

tHIGH

tLOW

tSU;DAT

Product data sheet Rev. 3 — 10 August 2010 46 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

10.6 SSP interface

[1] Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0

[2] Tamb = −40 °C to +85 °C.

[3] Tcy(clk) = 12 × Tcy(PCLK).

[4] Tamb = 25 °C; VDD = 3.3 V.

Table 17. Dynamic characteristics: SSP pins in SPI mode

Symbol Parameter Conditions Min Max Unit

SSP master

Tcy(clk) clock cycle time when only receiving [1] 40 - ns

when only tran smi tting [1] 27.8 - ns

tDS data set-up time in SPI mode;

2.4 V ≤ VDD ≤ 3.6 V

[2] 15 - ns

2.0 V ≤ VDD < 2.4 V [2] 20 - ns

tDH data hold time in SPI mode [2] 0- ns

tv(Q) data output valid time in SPI mode [2] -10ns

th(Q) data output hold time in SPI mode [2] 0- ns

SSP slave

Tcy(PCLK) PCLK cycle time 13.9 - ns

tDS data set-up time in SPI mode [3][4] 0- ns

tDH data hold time in SPI mode [3][4] 3 × Tcy(PCLK) + 4 - ns

tv(Q) data output valid time in SPI mode [3][4] -3 × Tcy(PCLK) + 11 ns

th(Q) data output hold time in SPI mode [3][4] -2 × Tcy(PCLK) + 5 ns

Product data sheet Rev. 3 — 10 August 2010 47 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Fig 23. SSP master timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk) tclk(H) tclk(L)

tDS tDH

tv(Q)

DATA VALID DATA VALID

th(Q)

SCK (CPOL = 1)

DATA VALID DATA VALID

MOSI

MISO

tDS tDH

DATA VALID DATA VALID

th(Q)

DATA VALID DATA VALID

tv(Q)

CPHA = 1

CPHA = 0

002aae82

Product data sheet Rev. 3 — 10 August 2010 48 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Fig 24. SSP slave timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk) tclk(H) tclk(L)

tDS tDH

tv(Q)

DATA VALID DATA VALID

th(Q)

SCK (CPOL = 1)

DATA VALID DATA VALID

MOSI

MISO

tDS tDH

tv(Q)

DATA VALID DATA VALID

th(Q)

DATA VALID DATA VALID

CPHA = 1

CPHA = 0

002aae83

Product data sheet Rev. 3 — 10 August 2010 49 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

10.7 USB interface (LPC1342/43 only)

[1] Characterized but not implemented as production test. Guaranteed by design.

Table 18 . Dynam ic characteristics: USB pins (full-speed)

CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

trrise time 10 % to 90 % 8.5 - 13.8 ns

tffall time 10 % to 90 % 7.7 - 13.7 ns

tFRFM differential rise and fall time

matching tr/t

f--109%

VCRS output signal crossover voltage 1.3 - 2.0 V

tFEOPT source SE0 interval of EOP see Figure 25 160 - 175 ns

tFDEOP source jitter for differential transition

to SE0 transition see Figure 25 −2-+5ns

tJR1 receiver jitter to next transition −18.5 - +18.5 ns

tJR2 receiver jitter for paired transitions 10 % to 90 % −9-+9ns

tEOPR1 EOP width at receiver must reject as

EOP; see

Figure 25

[1] 40 --ns

tEOPR2 EOP width at receiver must accept as

EOP; see

Figure 25

[1] 82 --ns

Fig 25. Differential data-to-EOP transition skew and EOP width

002aab561

TPERIOD

differential

data lines

crossover point

source EOP width: tFEOPT

receiver EOP width: tEOPR1, tEOPR2

crossover point

extended

differential data to

SE0/EOP skew

n × TPERIOD + tFDEOP

Product data sheet Rev. 3 — 10 August 2010 50 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

11. Application information

11.1 Suggested USB interface solutions (LPC1342/43 only)

11.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled th rough a cap acitor wi th

Ci = 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground Cg which attenuates the input volt age by a facto r Ci/(Ci + Cg). In slave

mode, a minimum of 200 mV(RMS) is needed.

Fig 26. LPC1342/43 USB interface on a self-powered device

LPC134x

USB-B

connector

USB_DP

USB_CONNECT

soft-connect switch

USB_DM

USB_VBUS

VSS

VDD

1.5 kΩ

RS = 33 Ω

002aae608

RS = 33 Ω

Fig 27. L PC1342/43 USB interface on a bus-powered device

LPC134x

VDD

1.5 kΩ

002aae609

USB-B

connector

USB_DP

USB_DM

USB_VBUS

VSS

RS = 33 Ω

Product data sheet Rev. 3 — 10 August 2010 51 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

In slave mode the input clock signal should be coup led by means of a cap acitor of 100 pF

(Figure 28), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 29 and in

Table 19 and Table 20. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances CX1 and CX2 need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, CL and

RS). Capacitance CP in Figure 29 represent s the p arallel p ackage cap acitance and should

not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal

manufacturer.

Fig 28. Slave mode operation of the on-chip oscillator

Fig 29. Oscillator modes and models: oscillation mode of operation and external crystal

model used for CX1/CX2 evaluation

LPC1xxx

XTALIN

100 pF

002aae78

002aaf42

LPC1xxx

XTALIN XTALOUT

CX2

CX1

XTAL

CLCP

Product data sheet Rev. 3 — 10 August 2010 52 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

11.3 XTAL Printed-Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors C x1, Cx2, and Cx3 in case o f

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be mad e as small as possible in

order to keep the noise coup le d in via the PCB as sm all as po ss ible . A lso parasitics

should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

Table 19. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

1 MHz - 5 MHz 10 pF < 300 Ω18 pF, 18 pF

20 pF < 300 Ω39 pF, 39 pF

30 pF < 300 Ω57 pF, 57 pF

5 MHz - 10 MHz 10 pF < 300 Ω18 pF, 18 pF

20 pF < 200 Ω39 pF, 39 pF

30 pF < 100 Ω57 pF, 57 pF

10 MHz - 15 MHz 10 pF < 160 Ω18 pF, 18 pF

20 pF < 60 Ω39 pF, 39 pF

15 MHz - 20 MHz 10 pF < 80 Ω18 pF, 18 pF

Table 20. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) hi gh frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

15 MHz - 20 MHz 10 pF < 180 Ω18 pF, 18 pF

20 pF < 100 Ω39 pF, 39 pF

20 MHz - 25 MHz 10 pF < 160 Ω18 pF, 18 pF

20 pF < 80 Ω39 pF, 39 pF

Product data sheet Rev. 3 — 10 August 2010 53 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

11.4 Standard I/O pad configuration

Figure 30 shows the possible pin modes for standard I/O pins with analog input function:

•Digital output driver

•Digital input: Pull-up enabled/disabled

•Digital input: Pull-down enabled/disabled

•Digital input: Repeater mode enabled/disabled

•Analog input

Fig 30. Standard I/O p ad configuration

VDD

ESD

VSS

ESD

VDD

weak

pull-up

weak

pull-down

output enable

repeater mode

enable

output

pull-up enable

pull-down enable

data input

analog input

select analog input

002aaf30

pin configured

as digital output

driver

pin configured

as digital input

pin configured

as analog input

Product data sheet Rev. 3 — 10 August 2010 54 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

11.5 Reset pad configuration

11.6 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy

environment beyond the ADC specifications listed in Table 8:

•The ADC input trace must be short and as cl ose as possible to the LPC131 1/13/42/43

chip.

•The ADC input traces must be shielded from fast switching digital signals and noisy

power supply lin e s.

•Because the ADC and the digital co re share the same power supply, the power supply

line must be adequately filtered.

•To improve the ADC performance in a very noisy environment, put the device in Sleep

mode during the ADC conversion.

Fig 31. Reset pad configuration

VSS

reset

002aaf27

VDD

Rpu ESD

ESD

20 ns RC

GLITCH FILTER PIN

Product data sheet Rev. 3 — 10 August 2010 55 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

12. Package outline

Fig 32. Package outline SOT313-2 (LQFP48)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05

1.45

1.35 0.25 0.27

0.17

0.18

0.12

7.1

6.9 0.5 9.15

8.85

0.95

0.55

0.12 0.10.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 00-01-19

03-02-25

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

QFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313

-2

Product data sheet Rev. 3 — 10 August 2010 56 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Fig 33. Package outline (HVQFN33)

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

- - -

hvqfn33_po

09-03-17

09-03-23

Unit

max

nom

min

1.00

0.85

0.80

0.05

0.02

0.00

0.2

7.1

7.0

6.9

4.85

4.70

4.55

7.1

7.0

6.9

0.65 4.55

0.75

0.60

0.45

0.1

A(1)

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

VQFN33: plastic thermal enhanced very thin quad flat package; no leads;

3 terminals; body 7 x 7 x 0.85 mm

A1b

0.35

0.28

0.23

(1) DhE(1) Eh

4.85

4.70

4.55

1e2

4.55

0.1

0.05

0.08

0 2.5 5 mm

scale

terminal 1

index area

detail X

AC B

terminal 1

index area Dh

9 16

Product data sheet Rev. 3 — 10 August 2010 57 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

13. Abbreviations

Table 21. Abbreviatio ns

Acronym Description

A/D Analog-to-Digital

ADC Analog-to-Digital Converter

AHB Advanced High-performance Bus

AMBA Advanced Microcontroller Bus Architecture

APB Advanced Peripheral Bus

BOD BrownOut Detection

EOP End Of Packet

ETM Embedded T race Macrocell

FIFO First-In, First-Out

GPIO General Purpose Input/Output

HID Human Inte rface Device

I/O Input/Output

LSB Least Significant Bit

MSC Mass Storage Class

PHY Physical Layer

PLL Phase-Locked Loop

SE0 Single Ended Zero

SPI Serial Peripheral Interface

SSI Serial Synchronous Interface

SSP Synchronous Serial Port

SoF Start-of-Frame

TCM Tightly-Coupled Memory

TTL Transistor-Transistor Logic

UART Universal Asynchron ous Receiver/Transmitter

USB Universal Serial Bus

Product data sheet Rev. 3 — 10 August 2010 58 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

14. Revision history

Table 22. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC1311_13_42_43 v.3 20100810 Product data sheet - LPC1311_13_42_43 v.2

Modifications: •VESD limit changed to −6500 V (min) /+6500 V (max) in Table 6.

•Reset state of pins and start logic functionality added in Table 3 to Table 4.

•Section 7.18.1 added.

•Table “Power consumption in Deep-sleep mode for individual analog blocks” removed.

•Deep-sleep mode functionality changed to allow BOD and watchdog oscillator as the

only analog blocks allowed to remain running in Deep-sleep mode (Section 7.17.5.2).

•VDD range changed to 3.0 ≤ VDD ≤ 3.6 V in Table 15.

•Tcy(CLK) conditions updated in Table 17.

•Size of GPIO registers updated in Figure 6.

•Editorial updates.

•Template updated.

LPC1311_13_42_43 v.2 20100506 Product data sheet - LPC1311_13_42_43 v.1

LPC1311_13_42_43 v.1 20091211 Product data sheet - -

Product data sheet Rev. 3 — 10 August 2010 59 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liabil i ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessar y

testing for the customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly object s to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property right s.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data fro m the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 3 — 10 August 2010 60 of 62

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors prod uct is automotive qualified,

the product is not suitable for automotive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 3 — 10 August 2010 61 of 62

continued >>

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

7 Functional description . . . . . . . . . . . . . . . . . . 16

7.1 Architectural overview . . . . . . . . . . . . . . . . . . 16

7.2 ARM Cortex-M3 processor. . . . . . . . . . . . . . . 16

7.3 On-chip flash program memory . . . . . . . . . . . 16

7.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 16

7.5 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.6 Nested Vectored Interrupt Controller

(NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.6.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 18

7.7 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 18

7.8 Fast general purpose parallel I/O . . . . . . . . . . 18

7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.9 USB interface (LPC1342/43 only) . . . . . . . . . 19

7.9.1 Full-speed USB device controller . . . . . . . . . . 19

7.9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.10 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.11 SSP serial I/O controller. . . . . . . . . . . . . . . . . 20

7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.12 I2C-bus serial I/O controller . . . . . . . . . . . . . . 20

7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.14 General purpose external event

counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 21

7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.15 System tick timer . . . . . . . . . . . . . . . . . . . . . . 22

7.16 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 22

7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.17 Clocking and power control . . . . . . . . . . . . . . 22

7.17.1 Integrated oscillators . . . . . . . . . . . . . . . . . . . 22

7.17.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 24

7.17.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 24

7.17.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 24

7.17.2 System PLL and USB PLL . . . . . . . . . . . . . . . 24

7.17.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.17.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 24

7.17.5 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 25

7.17.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.17.5.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 25

7.17.5.3 Deep power-down mode . . . . . . . . . . . . . . . . 25

7.18 System control. . . . . . . . . . . . . . . . . . . . . . . . 25

7.18.1 Start logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.18.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.18.3 Brownout detection . . . . . . . . . . . . . . . . . . . . 26

7.18.4 Code security

(Code Read Protection - CRP) . . . . . . . . . . . 26

7.18.5 Boot loader. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.18.6 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 27

7.18.7 AHB-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.18.8 External interrupt inputs. . . . . . . . . . . . . . . . . 27

7.18.9 Memory mapping control . . . . . . . . . . . . . . . . 27

7.19 Emulation and debugging . . . . . . . . . . . . . . . 27

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28

9 Static characteristics . . . . . . . . . . . . . . . . . . . 29

9.1 BOD static characteristics . . . . . . . . . . . . . . . 34

9.2 Power consumption . . . . . . . . . . . . . . . . . . . 34

9.3 Peripheral power consumption . . . . . . . . . . . 37

9.4 Electrical pin characteristics. . . . . . . . . . . . . . 38

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 42

10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 42

10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 42

10.3 Interna l oscillators . . . . . . . . . . . . . . . . . . . . . 43

10.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.5 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.6 SSP interface. . . . . . . . . . . . . . . . . . . . . . . . . 46

10.7 USB interface

(LPC1342/43 only). . . . . . . . . . . . . . . . . . . . . 49

11 Application information . . . . . . . . . . . . . . . . . 50

11.1 Suggested USB interface solutions

(LPC1342/43 only). . . . . . . . . . . . . . . . . . . . . 50

11.2 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11.3 XTAL Printed-Circuit Board

(PCB) layout guidelines . . . . . . . . . . . . . . . . . 52

11.4 Standard I/O pad configuration . . . . . . . . . . . 53

11.5 Reset pad configuration. . . . . . . . . . . . . . . . . 54

11.6 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 54

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 55

13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 57

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 58

15 Legal information . . . . . . . . . . . . . . . . . . . . . . 59

15.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 59

15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

NXP Semiconductors LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 August 2010

Document identifier: LPC1311_13_42_43

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 59

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 60

16 Contact information. . . . . . . . . . . . . . . . . . . . . 60

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61