830154BGI-09LFT - Integrated Device Technology

DATA SHEET

Over-Voltage 1.5V Tolerant,1:4 Fanout Buffer ICS830154I-09

CLK_IN

nOE

GND

VDD

General Description

The ICS830154I-09 is an LVCMOS 1.5V supply, over-voltage tolerant

clock fanout buffer targeted for clock generation in high-performance

telecommunication, networking and computing applications. The

device is optimized for low-skew clock distribution in low-voltage

applications. The input over-voltage tolerance enables using this

device in mixed-mode voltage applications. An output enable pin

controls whether the outputs are in the active or high impedance

state. Guaranteed output and part-to-part skew characteristics make

the ICS830154I-09 ideal for those applications demanding well

defined performance and repeatability. The ICS830154I-09 is

packaged in a small 8-TSSOP and in an 8-SOIC package.

Features

•Low-skew 1:4 fanout buffer

•Supports 1.5V and 1.8V power supply

•LVCMOS input and output levels

•3.6V Over-voltage tolerance at the clock and control input

•Support clock frequencies up to 150MHz

•LVCMOS compatible control input for output disable

•Output disabled to a high-impedance state

•Additive Phase Jitter, RMS: 0.24ps (typical), 1.5V output

•-40°C to 85°C ambient operating temperature

•Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages (8-TSSOP, 8-SOIC)

CLK_IN

nOE

Q3 ICS830154I-09

8-TSSOP

4.4mm x 3.0mm x 0.925mm package body

G-Package

Top View

ICS830154I-09

8-SOIC, 150mil

3.9mm x 4.9mm x 1.375mm package body

M-Package

Top View

Pin Assignments

Block Diagram

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Table 1. Pin Descriptions

NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Function Table

Table 3. nOE Configuration Table

Number Name Type Description

1 CLK_IN Input Pulldown Single-ended clock input. LVCMOS interface levels.

DD Power Power supply pin.

3 nOE Input Pulldown Output enable pin. See Table 3. LVCMOS interface levels.

4 GND Power Power supply ground.

5 Q3 Output Single-ended clock output. LVCMOS interface levels.

6 Q2 Output Single-ended clock output. LVCMOS interface levels.

7 Q1 Output Single-ended clock output. LVCMOS interface levels.

8 Q0 Output Single-ended clock output. LVCMOS interface levels.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4pF

CPD Power Dissipation Capacitance VDD = 1.95V 13 pF

VDD = 1.6V 12 pF

RPULLDOWN Input Pulldown Resistor 51 kΩ

ROUT Output Impedance VDD = 1.8V ± 0.15V 12 Ω

VDD = 1.5 ± 0.1V 15 Ω

Input

OperationnOE

0 (default) Q[3:0] are active.

1 Q[3:0] disabled in high-impedance state

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VDD = 1.5V ± 0.1V, TA = -40°C to 85°C

Table 4B. Power Supply DC Characteristics, VDD = 1.8V ± 0.15V, TA = -40°C to 85°C

Table 4C. LVCMOS DC Characteristics, VDD = 1.5V ± 0.1V, TA = -40°C to 85°C

Item Rating

Supply Voltage, VDD 4.6V

Inputs, VI3.6V

Outputs, VO -0.5V to VDD + 0.5V

Package Thermal Impedance, θJA

8 Lead TSSOP

8 Lead SOIC

121.5°C/W (0 mps)

103.0°C/W (0 mps)

Storage Temperature, TSTG -65°C to 150°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 1.4 1.5 1.6 V

IDDQ Quiescent Power Supply Current Inputs Open, Outputs Unloaded 1 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 1.65 1.8 1.95 V

IDDQ Quiescent Power Supply Current Inputs Open, Outputs Unloaded 1 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage 0.65 * VDD 3.6V V

VIL Input Low Voltage -0.3 0.35 * VDD V

IIH Input High Current CLK_IN, nOE VDD = VIN = 1.6V 150 µA

IIL Input Low Current CLK_IN, nOE VDD = 1.6V, VIN = 0V -5 µA

VOH Output High Voltage Q[3:0] IOH = -4mA 0.75 * VDD V

VOL Output Low Voltage Q[3:0] IOL = 4mA 0.25 * VDD V

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Table 4D. LVCMOS DC Characteristics, VDD = 1.8V ± 0.15V, TA = -40°C to 85°C

AC Electrical Characteristics

Table 5A. AC Characteristics, VDD = 1.5V ± 0.1V, TA = -40°C to +85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2.

NOTE 4: Characterized using a 33Ω series terminated 5” transmission line to a 5pF capacitor to GND in parallel with 500Ω (450Ω resistor +

50Ω scope) to GND.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage 0.65 * VDD 3.6V V

VIL Input Low Voltage -0.3 0.35 * VDD V

IIH Input High Current CLK_IN, nOE VDD = VIN = 1.95V 150 µA

IIL Input Low Current CLK_IN, nOE VDD = 1.95V, VIN = 0V -5 µA

VOH Output High Voltage Q[3:0] IOH = -6mA VDD – 0.45 V

VOL Output Low Voltage Q[3:0] IOL = 6mA 0.45 V

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fIN Input Reference Frequency 150 MHz

tpLH

Propagation Delay

(low to high transition) 1.9 4.1 ns

tpHL

Propagation Delay

(high to low transition) 1.9 4.1 ns

tPLZ, tPHZ

Disable Time

(active to high-impedance) 10 ns

tPZL, tPZH

Enable Time

(high-impedance to disable) 10 ns

tsk(o) Output Skew; NOTE 1, 2 40 ps

tsk(pp) Part-to-Part Skew; NOTE 2, 3 1.25 ns

tjit Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

25MHz, Integration Range:

12kHz - 5MHz 0.241 ps

tR / tFOutput Rise/Fall Time; NOTE 4 0.525V to 0.975V 0.14 0.64 ns

odc Output Duty Cycle 45 55 %

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Table 5B. AC Characteristics, VDD = 1.8V ± 0.15V, TA = -40°C to +85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2.

NOTE 4: Characterized using a 33Ω series terminated 5” transmission line to a 5pF capacitor to GND in parallel with 500Ω (450Ω resistor +

50Ω scope) to GND.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fIN Input Reference Frequency 150 MHz

tpLH

Propagation Delay

(low to high transition) 1.5 3.2 ns

tpHL

Propagation Delay

(high to low transition) 1.5 3.2 ns

tPLZ, tPHZ

Disable Time

(active to high-impedance) 10 ns

tPZL, tPZH

Enable Time

(high-impedance to disable) 10 ns

tsk(o) Output Skew; NOTE 1, 2 40 ps

tsk(pp) Part-to-Part Skew; NOTE 2, 3 1.25 ns

tjit Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

25MHz, Integration Range:

12kHz - 5MHz 0.187 ps

tR / tFOutput Rise/Fall Time; NOTE 4 0.63V to 1.17V 0.15 0.6 ns

odc Output Duty Cycle 45 55 %

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

The source generator "IFR2042 10kHz – 56.4GHz Low Noise Signal

Generator as external input to an Agilent 8133A 3GHz Pulse

Generator".

Additive Phase Jitter @ 25MHz

12kHz to 5MHz = 0.241ps (typical)

SSB Phase Noise dBc/Hz

Offset from Carrier Frequency (Hz)

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Parameter Measurement Information

1.5V Output Load AC Test Circuit

Output Skew

Output Duty Cycle/Pulse Width/Period

1.8V Output Load AC Test Circuit

Part-to-Part Skew

Propagation Delay

SCOPE

LVCMOS

GND

VDD

0.75V±0.05V

-0.75V±0.05V

tsk(o)

tPERIOD

tPW

tPERIOD

odc =

x 100%

tPW

Q0:Q3

SCOPE

LVCMOS

GND

VDD

0.9V±0.075V

-0.9V±0.075V

tsk(pp)

Part 1

Part 2

Q0:Q3

CLK_IN

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Parameter Measurement Information

1.5V Output Rise/Fall Time (Characterized using a 33Ω series

terminated 5” transmission line to a 5pF capacitor to GND in parallel

with 500Ω (450Ω resistor + 50Ω scope) to GND.)

1.8V Output Rise/Fall Time (Characterized using a 33Ω series

terminated 5” transmission line to a 5pF capacitor to GND in parallel

with 500Ω (450Ω resistor + 50Ω scope) to GND.)

Applications Information

Recommendations for Unused Output Pins

OUTputs:

LVCMOS Outputs

All unused LVCMOS output can be left floating. There should be no

trace attached.

0.525V

0.975V 0.975V

0.525V

tRtF

Q0:Q3 0.63V

1.17V 1.17V

0.63V

tRtF

Q0:Q3

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS830154I-09.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for theICS830154I-09 is the sum of the core power plus the power dissipation in the load(s). The following is the

power dissipation for VDD = 1.8V + 0.15V = 1.95V, which gives worst case results.

Power (core)MAX = VDD_MAX * IDD_MAX = 1.95V *1mA = 1.95mW

Total Static Power:

= Power (core)MAX = 1.95mW

Dynamic Power Dissipation at FOUT_MAX (150MHz)

Total Power (150MHz) = [(CPD * N) * Frequency * (VDDO)2] = [(13pF *4) * 150MHz * (1.95V)2] = 29.7mW

N = number of outputs

Total Power

= Static Power + Dynamic Power Dissipation

= 1.95mW + 29.7mW

= 31.65mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 121.5°C/W per Table 6A below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.032W *121.5°C/W = 88.9°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 6A. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection

Table 6B. Thermal Resistance θJA for 8 Lead SOIC, Forced Convection

θJA by Velocity

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 121.5°C/W 117.3°C/W 115.3°C/W

θJA by Velocity

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 103°C/W 94°C/W 89°C/W

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Reliability Information

Table 7A. θJA vs. Air Flow Table for a 8 Lead TSSOP

Table 7B. θJA vs. Air Flow Table for a 8 Lead SOIC

Transistor Count

The transistor count for ICS830154I-09 is: 169

θJA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 121.5°C/W 117.3°C/W 115.3°C/W

θJA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 103°C/W 94°C/W 89°C/W

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Package Outline and Package Dimensions

Package Outline - G Suffix for 8 Lead TSSOP

Table 8A. Package Dimensions for 8 Lead TSSOP

Reference Document: JEDEC Publication 95, MO-153

Package Outline - M Suffix for 8 Lead SOIC

Table 8B. Package Dimensions for 8 Lead SOIC

Reference Document: JEDEC Publication 95, MS-012

All Dimensions in Millimeters

Symbol Minimum Maximum

A1.20

A1 0.5 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D2.90 3.10

E6.40 Basic

E1 4.30 4.50

e0.65 Basic

L0.45 0.75

α0° 8°

aaa 0.10

All Dimensions in Millimeters

Symbol Minimum Maximum

A1.35 1.75

A1 0.10 0.25

B0.33 0.51

C0.19 0.25

D4.80 5.00

E3.80 4.00

e1.27 Basic

H5.80 6.20

h0.25 0.50

L0.40 1.27

α0° 8°

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Ordering Information

Table 9. Ordering Information

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Part/Order Number Marking Package Shipping Packaging Temperature

830154BGI-09 4BI09 8 Lead TSSOP Tube -40°C to 85°C

830154BGI-09T 4BI09 8 Lead TSSOP 2500 Tape & Reel -40°C to 85°C

830154BGI-09LF BI09L Lead-Free, 8 Lead TSSOP Tube -40°C to 85°C

830154BGI-09LFT BI09L Lead-Free, 8 Lead TSSOP 2500 Tape & Reel -40°C to 85°C

830154BMI-09 0154BI09 8 Lead SOIC Tube -40°C to 85°C

830154BMI-09T 0154BI09 8 Lead SOIC 2500 Tape & Reel -40°C to 85°C

830154BMI-09LF 154BI09L Lead-Free, 8 Lead SOIC Tube -40°C to 85°C

830154BMI-09LFT 154BI09L Lead-Free, 8 Lead SOIC 2500 Tape & Reel -40°C to 85°C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without

additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support

devices or critical medical instruments.

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

Revision History Sheet

Rev Table Page Description of Change Date

A 1 Pin Assignments - corrected part numbers. 6/9/10

ICS830154I-09 Data Sheet OVER-VOLTAGE 1.5V TOLERANT, 1:4 FANOUT BUFFER

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including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

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