1
UT54ACS165E
8-Bit Parallel Shift Registers
October 2008
www.aeroflex.com/Logic
FEATURES
• Complementary outputs
• Direct overriding load (data) inputs
• Gated clock inputs
• Parallel-to-serial data conversions
• 0.6μm CRH CMOS Process
- Latchup immune
• High speed
• Low power consumption
• Wide operating power supply from 3.0V to 5.5V
• Available QML Q or V processes
• 16-lead flatpack
DESCRIPTION
The UT54ACS165E is an 8-bit serial shift register that, when clocked,
shifts the data toward serial output QH. Parallel-in access to each stage
is provided by eight individual data inputs that are enabled by a low
level at the SH/L D input. The devices feature a clock inhibit functio n
and a complemented serial output QH .
Clocking is accomplished by a low-to-high transition of the CLK input
while SH/LD is held high and CLK INH is held low . The functio ns of
the CLK and CLK INH (clock inhibit) inputs are interchangeable.
Since a low CLK input and a low-to-high tra nsition of CLK INH will
also accomplish cl ocking, CLK INH should be changed to the high
level only while the CLK input is high. Parallel loading is disabled
when SH/LD is held high. Parallel inputs to the registers are enabled
while SH/L D is low independently of the levels of CLK, CLK INH or
SER inputs.
The device is characterized over the full HiRel temperature range of
-55°C to +125°C.
PINOUT
16-Lead Flatpack
Top View
FUNCTION TABLE
Note:
1. Qn = The state of the referenced output one setup time prior to the Low-to-
High clock transition.
LOGIC SYMBOL
1
2
3
4
5
7
6
16
15
14
13
12
10
11
VDD
89
SH/LD
CLK
E
F
G
H
QH
CLK INH
D
C
B
A
SER
VSS QH
INPUTS INTERNAL
OUTPUTS OUTPUTS
SH/
LD CLK
INH CLK SER PARALLEL
A . . . H QAQBQHQH
L X X X a . . . h a b h h
H L L X X QAQBQHQH
H L ↑H X H QAQGQG
H L ↑L X L QAQGQG
H H X X X QAQBQHQH
(1)
SH/LD (15)
CLK INH C2/
C1 (LOAD)
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
(10)
SER (11)
A
SRG8
(9) QH
(7) QH
≥1
(2)
CLK
2D
1D
(12)
B(13)
C(14)
D(3)
E(4)
F(5)
G(6)
H
1D
1D
2
LOGIC DIAGRAM
OPERATIONAL ENVIRONMENT 1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Threshold 280 MeV-cm2/mg
SEL Threshold 120 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
ABCDEFGH
(11)(12) (13) (14) (4) (5) (6)
(3)
S
C
D
R
(1)
(15)
(2)
(10)
CLK INH
CLK
SER QCQDQEQF QG
SH/LD
(9)
(7)
QH
QH
S
C
D
R
S
C
D
R
S
C
D
R
S
C
D
R
S
C
D
R
S
C
D
R
QA
S
C
D
R
QH
QB
3
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these
or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage -0.3 to 7.0 V
VI/O Voltage any pin -.3 to VDD + .3 V
TSTG Storage Temperature range -65 to +150 °C
TJMaximum junction temperature +175 °C
TLS Lead temperature (soldering 5 seconds) +300 °C
ΘJC Thermal resistance junction to case 20 °C/W
IIDC input current ±10 mA
PDMaximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 3.0 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTemperature range -55 to + 125 °C
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DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS165E7
( VDD = 3.0V to 5.5V; VSS = 0V6; -55°C < TC < +125°C)
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second .
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
8. Power dissipation specified per switching output.
9. This value is guaranteed based on characterization data, but not tested.
SYMBOL Description CONDITION VDD MIN MAX UNIT
VIL Low-level input voltage 13.0V 0.9 V
5.5V 1.65
VIH High-level input voltage 13.0V 2.1 V
5.5V 3.85
IIN Input leakage current VIN = VDD or VSS 5.5V -1 1μA
VOL Low-level output voltage 3IOL = 100μA3.0V 0.25 V
4.5V 0.25
VOH High-level output voltage 3IOH = -100μA3.0V 2.75 V
4.5V 4.25
IOS Short-circuit output current 2 ,4 VO = VDD and VSS 3.0V -100 100 mA
5.5V -200 200
IOL Low level output current9VIN = VDD or VSS
VOL = 0.4V
3.0V 6mA
5.5V 8
IOH High level output current9VIN = VDD or VSS
VOH = VDD-0.4V
3.0V -6 mA
5.5V -8
Ptotal Power dissipatio n 2, 8 CL = 50pF 5.5V
3.0V
2.9
1.16 mW/
MHz
IDDQ Quiescent Supply Current VIN = VDD or VSS 5.5V 10 μA
CIN Input capacitance 5ƒ = 1MHz 0V 15 pF
COUT Output capacitance 5 ƒ = 1MHz 0V 15 pF
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AC ELECTRICAL CHARACTERIST ICS FOR THE UT54 ACS165 E 2
(VDD = 3.0V to 5.5V; VSS = 0V 1, -55°C < TC < +125°C)
SYMBOL PARAMETER CONDITION VDD MINIMUM MAXIMUM UNIT
tPLH1 CLK or CLKINH to QH or QHCL = 30pF 3.0V & 3.6V 2 18 ns
4.5V & 5.5V 2 14
CL = 50pF 3.0V & 3.6 V 2 22 ns
4.5V & 5.5V 2 18
tPHL1 CLK or CLKINH to QH or QHCL = 30pF 3.0V & 3.6V 2 21 ns
4.5V & 5.5V 2 17
CL = 50pF 3.0V & 3.6 V 2 25 ns
4.5V & 5.5V 2 21
tPLH2 SH/LD to QH or QHCL = 30pF 3.0V & 3.6V 2 18 ns
4.5V & 5.5V 2 14
CL = 50pF 3.0V & 3.6 V 2 22 ns
4.5V & 5.5V 2 18
tPHL2 SH/LD to QH or QHCL = 30pF 3.0V & 3.6V 2 21 ns
4.5V & 5.5V 2 17
CL = 50pF 3.0V & 3.6 V 2 25 ns
4.5V & 5.5V 2 21
tPLH3 H to QHCL = 30pF 3.0V & 3.6V 2 17 ns
4.5V & 5.5V 2 13
CL = 50pF 3.0V & 3.6 V 2 21 ns
4.5V & 5.5V 2 17
tPHL3 H to QHCL = 30pF 3.0V & 3.6V 2 21 ns
4.5V & 5.5V 2 17
CL = 50pF 3.0V & 3.6 V 2 25 ns
4.5V & 5.5V 2 21
tPLH4 H to QHCL = 30pF 3.0V & 3.6V 2 18 ns
4.5V & 5.5V 2 14
CL = 50pF 3.0V & 3.6 V 2 22 ns
4.5V & 5.5V 2 18
tPLH4 H to QHCL = 30pF 3.0V & 3.6V 2 20 ns
4.5V & 5.5V 2 16
CL = 50pF 3.0V & 3.6 V 2 24 ns
4.5V & 5.5V 2 20
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Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
3. Based on characterization, hold time (tH3) of 0ns for data pins A-H, can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested.
SYMBOL PARAMETER CONDITION VDD MINIMUM MAXIMUM UNIT
fMAX Maximum clock frequency CL = 50pF 3.0V, 4.5V, and
5.5V 71 MHz
tSU1 SER, SH/LD, CLKINH or CLK
Setup time before CLK↑ or
CLKINH↑
CL = 50pF 3.0V, 4.5V, and
5.5V 7ns
tSU2 Data setup time before SH/LD CL = 50pF 3.0V, 4.5V, and
5.5V 7ns
tH1 SER hold time after CLK or
CLKINH↑CL = 50pF 3.0V, 4.5V, and
5.5V 2ns
tH2 CLKINH↑ hold time after CLK CL = 50pF 3.0V, 4.5V, and
5.5V 2ns
tH33Hold time for any input after
SH/LD CL = 50pF 3.0V, 4.5V, and
5.5V 2ns
tWMinimum pulse width
CLK or CLKINH high
CLK or CLKINH low
SH/LD
CL = 50pF 3.0V, 4.5V, and
5.5V 7ns
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Packaging
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Ordering Information: UT54ACS165E: SMD
Drawing Number:
96558 = UT54ACS165E
Device Type:
02 = 1 rad(Si)/sec
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
5962 ***** ** * * **
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
03 = 50 to 300 rads(Si)/sec
Class Designator:
Q = QML Class Q
V = QML Class V
Notes:
1. Lead fini sh (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For proto type inquiries, contact
factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test
Method 1019 Condition A and section 3.11.2. Device type 03 is o nly offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5
rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A.
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced HiRel
