Product Folder Order Now Technical Documents Support & Community Tools & Software SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 SN65DSI85 MIPI(R) DSI Bridge to FlatLinkTM LVDS Dual Channel DSI to Dual-Link LVDS Bridge 1 Features * 1 * * * * * * * * * * * * * * * 3 Description (R) Implements MIPI D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00 Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane Supports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats Suitable for 60 fps WQXGA 2560 x 1600 Resolution at 18-bpp and 24-bpp Color, and WUXGA 1920 x 1200 Resolution with 3D Graphics at 60 fps (120 fps Equivalent) MIPI(R) Front-End Configurable for Single-Channel or Dual-Channel DSI Configurations FlatLinkTM Output Configurable for Single-Link or Dual-Link LVDS Supports Dual-Channel DSI ODD or EVEN and LEFT or RIGHT Operating Modes Supports Two Single-Channel DSI to Two SingleLink LVDS Operating Mode LVDS Output Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Mode LVDS Pixel Clock May be Sourced from FreeRunning Continuous D-PHY Clock or External Reference Clock (REFCLK) 1.8-V Main VCC Power Supply Low-Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI(R) Ultra-Low Power State (ULPS) Support LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing ESD Rating 2 kV (HBM) Packaged in 64-pin 5 mm x 5 mm BGA MICROSTAR JUNIOR (ZQE) Temperature Range: -40C to 85C The SN65DSI85 DSI to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link. The SN65DSI85 is well suited for WQXGA (2560 x 1600) at 60 frames per second, as well as 3D Graphics at WUXGA and True HD (1920 x 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces. Designed with industry-compliant interface technology, the SN65DSI85 is compatible with a wide range of micro-processors, and is designed with a range of power management features including lowswing LVDS outputs, and the MIPI(R) defined ultra-low power state (ULPS) support. The SN65DSI85 is implemented in a small outline 5mm x 5-mm PBGA at 0.5-mm pitch package, and operates across a temperature range from -40C to 85C. Device Information(1) PART NUMBER SN65DSI85 PACKAGE BGA MICROSTAR JUNIOR (64) BODY SIZE (NOM) 5.00 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application 2 Applications * * Tablet PC, Notebook PC, Netbooks Mobile Internet Devices 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 7 8 1 1 1 2 4 7 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 7 Electrical Characteristics.......................................... 8 Switching Characteristics....................................... 10 Parameter Measurement Information ................ 11 Detailed Description ............................................ 13 8.1 8.2 8.3 8.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 13 13 14 16 8.5 Programming........................................................... 24 8.6 Register Maps ......................................................... 25 9 Application and Implementation ........................ 37 9.1 Application Information............................................ 37 9.2 Typical Applications ................................................ 38 10 Power Supply Recommendations ..................... 44 10.1 VCC Power Supply................................................. 44 10.2 VCORE Power Supply .......................................... 44 11 Layout................................................................... 44 11.1 Layout Guidelines ................................................. 44 11.2 Layout Example .................................................... 45 12 Device and Documentation Support ................. 46 12.1 12.2 12.3 12.4 12.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 46 46 46 46 46 13 Mechanical, Packaging, and Orderable Information ........................................................... 46 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (August 2015) to Revision F Page * Deleted figure RESET and Initialization Timing Definition While VCC is High ...................................................................... 12 * Changed the paragraph following Figure 8 ......................................................................................................................... 17 * Changed Recommended Initialization Sequence To: Initialization Sequence ..................................................................... 17 * Changed Table 5 .................................................................................................................................................................. 17 * Changed item 3 in Video Stop and Restart Sequence From: Drive all DSI input lanes including DSI CLK lane to LP11. To: Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS. ............................................................... 37 Changes from Revision D (September 2013) to Revision E Page * Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 * Changed item 3 of the ULPS sequence list for clarification. ............................................................................................... 14 * Changed description of the Init seq 7 - Recommended Initialization Sequence for clarification. ....................................... 17 * Changed description of Address 0x0A, Bit 7 in Table 8, CSR Bit Field Definitions - Reset and Clock Registers .............. 25 * Changed Address 0x18, Bits 3 and 2 Description, Address 0x18, Bit 1 Description, and Address 0x18, Bit 0 Description in Table 10 for clarification. ............................................................................................................................... 28 * Changed Video STOP and Restart Sequence, step 1 of the STOP sequence from " ...0(CSR 0x0A.7)" to "....0(CSR 0x0D.0)" and step 3 of the Restart sequence from "Wait for the PLL_LOCK bit to be set(CSR 0x0A.7)." to "Wait for a minimum of 3 ms." ............................................................................................................................................................ 37 2 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 Changes from Original (August 2012) to Revision A Page * Changed the tsetup and thold NOM value of 1.5 to a MIN value of 1.5...................................................................................... 7 * Changed the value of VOH From: 1.3 MIN To: 1.25 MIN ........................................................................................................ 8 * Changed the ICC TYP value From: 125 To: 127 and MAX value From: 200 To: 212 ........................................................... 8 * Added a TYP value of 7.7 to IULPS .......................................................................................................................................... 8 * Changed the IRST TYP value From: 0.05 To: 0.04 and MAX value From: 0.2 To: 0.06 ......................................................... 8 * Added table note 2 ................................................................................................................................................................. 8 * changed the values of |VOD|.................................................................................................................................................. 9 * changed the values of |VOD|.................................................................................................................................................. 9 * Changed the values of VOC(SS) for test conditions CSR 0x19.6 = 0 and, or CSR 0x19.4 = 0 ................................................ 9 * Added table note 3 ................................................................................................................................................................. 9 * Changed the SWITCHING CHARACTERISTICS table........................................................................................................ 10 * Changed the description of CHA_LVDS_VOD_SWING....................................................................................................... 28 * Changed the description of CHB_LVDS_VOD_SWING....................................................................................................... 28 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 3 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com 5 Pin Configuration and Functions ZQE Package 64-Pin BGA MICROSTAR JUNIOR (Top View) A B C D E F G H J 9 VCC GND A_Y0N A_Y1N A_Y2N A_CLKN A_Y3N GND IRQ 8 GND VCC A_Y0P A_Y1P A_Y2P A_CLKP A_Y3P RSVD1 VCORE 7 B_Y3N B_Y3P DA3P DA3N 6 B_CLKN B_CLKP VCC VCC VCC DA2P DA2N 5 B_Y2N B_Y2P GND VCC GND DACP DACN 4 B_Y1N B_Y1P GND GND DA1P DA1N 3 B_Y0N B_Y0P DA0P DA0N 2 GND RSVD2 DB0P DB1P DBCP DB2P DB3P REFCLK VCC 1 ADDR EN DB0N DB1N DBCN DB2N DB3N SCL SDA Not to scale To minimize the power supply noise floor, provide good decoupling near the SN65DSI85 power pins. The use of four ceramic capacitors (2x 0.1 F and 2x 0.01 F) provides good performance. At the least, it is recommended to install one 0.1 F and one 0.01 F capacitor near the SN65DSI85. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and device power inputs pins must be minimized. Placing the capacitor underneath the SN65DSI85 on the bottom of the PCB is often a good choice. 4 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 Pin Functions PIN NAME NO. ADDR A1 A_Y0N C9 A_Y0P C8 A_Y1N D9 A_Y1P D8 A_Y2N E9 A_Y2P E8 A_Y3N G9 A_Y3P G8 A_CLKN F9 A_CLKP F8 B_Y0N A3 B_Y0P B3 B_Y1N A4 B_Y1P B4 B_Y2N A5 B_Y2P B5 B_Y3N A7 B_Y3P B7 B_CLKN A6 B_CLKP B6 DA0N J3 DA0P H3 DA1N J4 DA1P H4 DA2N J6 DA2P H6 DA3N J7 DA3P H7 I/O DESCRIPTION CMOS Input/Output Local I2C Interface Target Address Select. See Table 6. In normal operation this pin is an input. When the ADDR pin is programmed high, it should be tied to the same 1.8 V power rails where the SN65DSI85 VCC 1.8 V power rail is connected. FlatLinkTM Channel A LVDS Data Output 0. FlatLinkTM Channel A LVDS Data Output 1. FlatLinkTM Channel A LVDS Data Output 2. FlatLinkTM Channel A LVDS Data Output 3. A_Y3P and A_Y3N shall be left NC for 18 bpp panels. FlatLinkTM Channel A LVDS Clock LVDS Output FlatLinkTM Channel B LVDS Data Output 0. FlatLinkTM Channel B LVDS Data Output 1. FlatLinkTM Channel B LVDS Data Output 2. FlatLinkTM Channel B LVDS Data Output 3. B_Y3P and B_Y3N shall be left NC for 18 bpp panels. FlatLinkTM Channel B LVDS Clock. MIPI(R) D-PHY Channel A Data Lane 0; data rate up to 1 Gbps. MIPI(R) D-PHY Channel A Data Lane 1; data rate up to 1 Gbps. MIPI(R) D-PHY Channel A Data Lane 2; data rate up to 1 Gbps. MIPI(R) D-PHY Channel A Data Lane 3; data rate up to 1 Gbps. DACN J5 DACP H5 DB0N C1 DB0P C2 DB1N D1 DB1P D2 DB2N F1 DB2P F2 DB3N G1 DB3P G2 DBCN E1 DBCP E2 EN B1 CMOS Input with pullup (Failsafe) GND A2, A8, B9, D5, E4, F4, F5, H9 Power Supply Reference Ground. IRQ J9 CMOS Output Interrupt Signal. RSVD1 H8 CMOS Input/Output with pulldown Reserved. This pin should be left unconnected for normal operation. RSVD2 B2 CMOS Input with pulldown Reserved. This pin should be left unconnected for normal operation. LVDS Input (HS) CMOS Input (LS) (Failsafe) MIPI(R) D-PHY Channel A Clock Lane; operates up to 500 MHz. MIPI(R) D-PHY Channel B Data Lane 0; data rate up to 1 Gbps. MIPI(R) D-PHY Channel B Data Lane 1; data rate up to 1 Gbps. MIPI(R) D-PHY Channel B Data Lane 2; data rate up to 1 Gbps. MIPI(R) D-PHY Channel B Data Lane 3; data rate up to 1 Gbps. MIPI(R) D-PHY Channel B Clock Lane; operates up to 500 MHz. Chip Enable and Reset. Device is reset (shutdown) when EN is low. Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 5 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com Pin Functions (continued) PIN NAME NO. REFCLK H2 SCL H1 SDA J1 VCC A9, B8, D6, E5, E6, F6, J2 VCORE 6 J8 I/O DESCRIPTION CMOS Input (Failsafe) Optional External Reference Clock for LVDS Pixel Clock. If an External Reference Clock is not used, this pin should be pulled to GND with an external resistor. The source of the reference clock should be placed as close as possible with a series resistor near the source to reduce EMI. Local I2C Interface Clock. Open Drain Input/Output (Failsafe) Local I2C Interface Bi-directional Data Signal. 1.8 V Power Supply. Power Supply 1.1 V Output from Voltage Regulator. This pin must have a 1 F external capacitor to GND. Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Supply Voltage Input Voltage MIN MAX UNIT VCC -0.3 2.175 V CMOS Input Terminals -0.5 2.175 V DSI Input Terminals (DA x P/N, DB x P/N) -0.4 1.4 V -65 105 C Storage Temperature, TS (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC VCC Power supply MIN NOM MAX UNIT 1.65 1.8 1.95 V f(noise) > 1MHz 0.05 V -40 85 C 92.2 C -50 1350 mV 400 kHz VPSN Supply noise on any VCC pin TA Operating free-air temperature TCASE Case temperature VDSI_PIN DSI input pin voltage range f(I2C) Local I2C input frequency fHS_CLK DSI HS clock input frequency tsetup DSI HS data to clock setup time 0.15 UI (1) thold DSI HS data to clock hold time; see Figure 5 0.15 UI (1) ZL LVDS output differential impedance (1) 40 500 90 132 MHz The unit interval (UI) is one half of the period of the HS clock; at 500 MHz the minimum setup and hold time is 150 ps 6.4 Thermal Information SN65DSI85 THERMAL METRIC (1) ZQE (BGA MICROSTAR JUNIOR) UNIT 64 PINS RJA Junction-to-ambient thermal resistance 72.1 C/W RJC(top) Junction-to-case (top) thermal resistance 35.7 C/W RJB Junction-to-board thermal resistance 35.2 C/W JT Junction-to-top characterization parameter 1.2 C/W JB Junction-to-board characterization parameter 36.1 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 7 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 6.5 www.ti.com Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 0.3 x VCC UNIT VIL Low-level control signal input voltage VIH High-level control signal input voltage VOH High-level output voltage IOH = -4 mA VOL Low-level output voltage IOL = 4 mA 0.4 V ILKG Input failsafe leakage current VCC = 0; VCC(PIN) = 1.8 V 30 A IIH High level input current Any input terminal 30 A IIL Low level input current Any input terminal 30 A IOZ High-impedance output current Any output terminal 10 A IOS Short-circuit output current Any output driving GND short 20 mA ICC Device active current See 127 212 mA IULPS Device standby current All data and clock lanes are in ultra-low power state (ULPS) 7.7 10 mA IRST Shutdown current EN = 0 0.04 0.06 mA REN EN control input resistor 0.7 x VCC V 1.25 (2) V V 200 k MIPI DSI INTERFACE VIH-LP LP receiver input high threshold See Figure 1 VIL-LP LP receiver input low threshold See Figure 1 |VID| HS differential input voltage |VIDT| HS differential input voltage threshold VIL-ULPS LP receiver input low threshold; ultra-low power state (ULPS) VCM-HS HS common mode voltage; steady-state VCM-HS HS common mode peak-to-peak variation including symbol delta and interference VIH-HS HS single-ended input high voltage See Figure 1 VIL-HS HS single-ended input low voltage See Figure 1 VTERM-EN HS termination enable; single-ended input Termination is switched simultaneous for voltage (both Dp AND Dn apply to Dn and Dp enable) RDIFF-HS HS mode differential input impedance (1) (2) 8 880 70 70 mV 550 mV 270 mV 50 mV 300 mV 330 mV 100 mV 460 mV -40 80 mV 450 mV 125 All typical values are at VCC = 1.8V and TA = 25C SN65DSI85: DUAL Channel DSI to DUAL Channel LVDS, 1920 x 1200 (a) number of LVDS lanes = 2x(3 data lanes + 1 CLK lane) (b) number of DSI lanes = 2x(4 data lanes + 1 CLK lane (c) LVDS CLK OUT = 81.6M (d) DSI CLK = 490M (e) RGB888, LVDS18bpp Maximum values are at VCC = 1.95 V and TA = 85C Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 100 near end termination 180 245 313 CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 100 near end termination 215 293 372 CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 100 near end termination 250 341 430 CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 100 near end termination 290 389 488 CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 200 near end termination 150 204 261 CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 200 near end termination 200 271 346 CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 200 near end termination 250 337 428 CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 200 near end termination 300 402 511 CSR 0x19.3:2=00 and/or CSR 0x19.1:0=00 near end termination 140 191 244 CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 100 near end termination 168 229 290 CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 100 near end termination 195 266 335 CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 100 near end termination 226 303 381 CSR 0x19.3:2=00 and, or CSR 0x19.1:0=00 200 near end termination 117 159 204 CSR 0x19.3:2=01 and, or CSR 0x19.1:0=01 200 near end termination 156 211 270 CSR 0x19.3:2=10 and, or CSR 0x19.1:0=10 200 near end termination 195 263 334 CSR 0x19.3:2=11 and, or CSR 0x19.1:0=11 200 near end termination 234 314 399 UNIT FLATLINK LVDS OUTPUT |VOD| |VOD| |VOD| VOC(SS) Steady-state differential output voltage A_Y x P/N and B_Y x P/N Steady-state differential output voltage for A_CLKP/N and B_CLKP/N Change in steady-state differential output voltage between opposite binary states Steady state common-mode output voltage (3) VOC(PP) Peak-to-peak common-mode output voltage RLVDS_DIS Pull-down resistance for disabled LVDS outputs (3) mV mV RL = 100 CSR 0x19.6 = 1 and CSR 0x1B.6 = 1; and, or CSR 0x19.4 = 1 and CSR 0x1B.4 = 1; see Figure 2 CSR 0x19.6 = 0 and, or CSR 0x19.4 = 0; see Figure 2 35 0.8 0.9 1 1.15 1.25 1.35 mV V see Figure 2 35 1 mV k Tested at VCC = 1.8V , TA = -40C for MIN, TA = 25C for TYP, TA = 85C for MAX. Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 9 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 6.6 www.ti.com Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT 300 ps 40 ns DSI tGS DSI LP glitch suppression pulse width tSK Skew time from DSI Channel A to Channel B in dual DSI operation See Figure 17 LVDS tc Output clock period tw High-level output clock (CLK) pulse duration 6.49 t0 Delay time, CLK to 1st serial bit position t1 4/7 tc ns -0.15 0.15 ns Delay time, CLK to 2nd serial bit position 1/7 tc - 0.15 1/7 tc + 0.15 ns t2 Delay time, CLK to 3rd serial bit position 2/7 tc - 0.15 2/7 tc + 0.15 ns t3 Delay time, CLK to 4th serial bit position 3/7 tc - 0.15 3/7 tc + 0.15 ns t4 Delay time, CLK to 5th serial bit position 4/7 tc - 0.15 4/7 tc + 0.15 ns t5 Delay time, CLK to 6th serial bit position 5/7 tc - 0.15 5/7 tc + 0.15 ns t6 Delay time, CLK to 7th serial bit position 6/7 tc - 0.15 6/7 tc + 0.15 ns tr Differential output rise-time tf Differential output fall-time 180 500 ps -10 10 ps tc = 6.49 ns; Input clock jitter < 25 ps (REFCLK) see Figure 3 LVDS CLK A to CLK B skew EN, ULPS, RESET ten Enable time from EN or ULPS tc(o) = 12.9 ns 1 ms tdis Disable time to standby tc(o) = 12.9 ns 0.1 ms treset Reset Time 10 FREFCLK REFCLK Freqeuncy. Supported frequencies: 25 MHz - 15 4MHz 25 154 tr, tf REFCLK rise and fall time 100ps 1ns s tpj REFCLK Peak-to-Peak Phase Jitter 50 ps Duty REFCLK Duty Cycle ms REFCLK 40% 50% 60% 0.5% 1% 2% MHz REFCLK or DSI CLK (DACP/N, DBCP/N) SSC_CLKIN (1) (2) SSC enabled Input CLK center spread depth (2) Modulation Frequency Range 30 60 kHz All typical values are at VCC = 1.8 V and TA = 25C For EMI reduction purpose, SN65DSI85 supports the center spreading of the LVDS CLK output through the REFCLK or DSI CLK input. The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP/N and/or B_CLKP/N. 1.3V LP-RX Input HIGH VIH-LP VIL-LP VIH-HS VID LP-RX Input LOW VCM-HS(MAX) HS-RX Common Mode Range VCM-HS(MIN) GND VIL-HS Low Power (LP) Mode Receiver High Speed (HS) Mode Receiver Figure 1. DSI Receiver Voltage Definitions 10 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 49.9 ? 1% (2 PLCS) A/B_YnP VOD VOC A/B_YnN 100 % 80% VOD(H) 0V VOD(L) 20% 0% tf tr VOC(PP) VOC(SS) VOC(SS) 0V Figure 2. Test Load and Voltage Definitions for FlatLinkTM Outputs 7 Parameter Measurement Information CLK t6 t5 t4 t3 t2 t1 t0 Yn VOD(H) 0.00V VOD(L) t0-6 Figure 3. SN65DSI85 FlatLinkTM Timing Definitions Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 11 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com Parameter Measurement Information (continued) ULPS (LP00) State DSI lane ten tdis A_CLKP/N (LVDS_CHA_CLK) (1) See the ULPS section of the data sheet for the ULPS entry and exit sequence. (2) ULPS entry and exit protocol and timing requirements must be met per MIPI(R) DPHY specification. Figure 4. ULPS Timing Definition Figure 5. DSI HS Mode Receiver Timing Definitions 12 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 8 Detailed Description 8.1 Overview The SN65DSI85 to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating a 1 Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18bpp RGB666 and 24 bpp RGB8888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link. 8.2 Functional Block Diagram AVCC AGND DSI PACKET PROCESSORS VCC ULPS GND ERR LANE MERGE LPRX PACKET HEADERS (ODD ) 18 8 DA0P LVDS SERIALIZER ERR HSRX DA0N LONG PACKETS DATA LANE 0 7-BIT SHIFT REGISTER (EVEN ) 18 EOT DA1P DA1N DA2P DA2N DA3P DA3N SOT DATA LANE 1 (Circuit same as DATA LANE 0) 8 DATA LANE 2 (Circuit same as DATA LANE 0) 8 Timers 32 SHORT PACKETS DE VS DATA LANE 3 (Circuit same as DATA LANE 0) HS 8 DSI CHANNEL MERGING CHANNEL FORMATTER EOT SOT ULPS 32 PARTIAL LINE BUFFER LPRX LVDSPLL DACP PLL Lock HSRX DACN CLOCK CIRCUITS CLK LANE DB0P DB0N DB1P DB1N DB2P DB2N DB3P DB3N DBCP DBCN PIXEL CLOCK 8 LANE MERGE 2 8 B_Y0P B_Y0N B_Y1P B_Y1N B_Y2P B_Y2N B_CLKP B_CLKN B_Y3P B_Y3N SCL CSR HS Clock Sourced M /N Pixel Clock PLL A_Y0P A_Y0N A_Y1P A_Y1N A_Y2P A_Y2N A_CLKP A_CLKN A_Y3P A_Y3N LOCAL I C CSR READ SDA IRQ CSR WRITE Channel B 8 ADDR Clock Dividers (Circuit same as Channel A) 8 Reset SN65DSI85 REFCLK EN RSVD1 RSVD2 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 13 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com 8.3 Feature Description 8.3.1 Clock Configurations and Multipliers The FlatLinkTM LVDS clock may be derived from the DSI channel A clock, or from an external reference clock source. When the MIPI(R) D-PHY channel A HS clock is used as the LVDS clock source, the D-PHY clock lane must operate in HS free-running (continuous) mode; this feature eliminates the need for an external reference clock reducing system costs The reference clock source is selected by HS_CLK_SRC (CSR 0x0A.0) programmed through the local I2C interface. If an external reference clock is selected, it is multiplied by the factor in REFCLK_MULTIPLIER (CSR 0x0B.1:0) to generate the FlatLinkTM LVDS output clock. When an external reference clock is selected, it must be between 25 MHz and 154 MHz. If the DSI channel A clock is selected, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the FlatLinkTM LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12) must be set to the frequency range of the FlatLinkTM LVDS output clock and DSI Channel A input clock respectively for the internal PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0x0D.0) must be set to enable the internal PLL. 8.3.2 ULPS The SN65DSI85 supports the MIPI(R) defined ultra-low power state (ULPS). While the device is in the ULPS, the CSR registers are accessible via I2C interface. ULPS sequence should be issued to all active DSI CLK and/or DSI data lanes of the enabled DSI Channels for the SN65DSI85 enter the ULPS. The Following sequence should be followed to enter and exit the ULPS. 1. Host issues a ULPS entry sequence to all DSI CLK and data lanes enabled. 2. When host is ready to exit the ULPS mode, host issues a ULPS exit sequence to all DSI CLK and data lanes that need to be active in normal operation. 3. Wait for a minimum of 3 ms. 4. Set the SOFT_RESET bit (CSR 0x09.0). 5. Device resumes normal operation.(i.e video streaming resumes on the panel). 8.3.3 LVDS Pattern Generation The SN65DSI85 supports a pattern generation feature on LVDS Channels. This feature can be used to test the LVDS output path and LVDS panels in a system platform. The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C. No DSI data is received while the pattern generation feature is enabled. There are three modes available for LVDS test pattern generation. The mode of test pattern generation is determined by register configuration as shown in the tables below. Table 1. Test Pattern Generation Test Pattern Generation Mode Register Configurations Single LVDS configuration mode LVDS_LINK_CFG(CSR 0x18.4) = 1b DSI_CH_MODE(CSR 0x10.6:5) = XXb CHA_TEST_PATTERN(CSR 0x3C.4) = 1b CHB_TEST_PATTERN(CSR 0x3C.0) = 0b Dual LVDS configuration mode LVDS_LINK_CFG(CSR 0x18.4) = 0b DSI_CH_MODE(CSR 0x10.6:5) = 0Xb CHA_TEST_PATTERN(CSR 0x3C.4) = 1b CHB_TEST_PATTERN(CSR 0x3C.0) = 0b Two independent LVDS configuration mode LVDS_LINK_CFG(CSR 0x18.4) = 0b DSI_CH_MODE(CSR 0x10.6:5) = 10b CHA_TEST_PATTERN(CSR 0x3C.4) = 1b CHB_TEST_PATTERN(CSR 0x3C.0) = 1b The following tables show lists of video registers that need to be configured for test pattern generation video parameters. 1. Single LVDS configuration 14 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 Table 2. Video Registers Bit Address Register Name 0x20.7:0 CHA_ACTIVE_LINE_LENGTH_LOW 0x21.3:0 CHA_ACTIVE_LINE_LENGTH_HIGH 0x24.7:0 CHA_VERTICAL_DISPLAY_SIZE_LOW 0x25.3:0 CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x2C.7:0 CHA_HSYNC_PULSE_WIDTH_LOW 0x2D.1:0 CHA_HSYNC_PULSE_WIDTH_HIGH 0x30.7:0 CHA_VSYNC_PULSE_WIDTH_LOW 0x31.1:0 CHA_VSYNC_PULSE_WIDTH_HIGH 0x34.7:0 CHA_HORIZONTAL_BACK_PORCH 0x36.7:0 CHA_VERTICAL_BACK_PORCH 0x38.7:0 CHA_HORIZONTAL_FRONT_PORCH 0x3A.7:0 CHA_VERTICAL_FRONT_PORCH 2. Dual LVDS configuration - Same set of video registers are used as in single LVDS configuration. 3. Two independent LVDS configuration mode. Both Channel A and Channel B register parameters need to be configured. Table 3. Channel A and B Registers Bit Address Register Name Channel A 0x20.7:0 CHA_ACTIVE_LINE_LENGTH_LOW 0x21.3:0 CHA_ACTIVE_LINE_LENGTH_HIGH 0x24.7:0 CHA_VERTICAL_DISPLAY_SIZE_LOW 0x25.3:0 CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x2C.7:0 CHA_HSYNC_PULSE_WIDTH_LOW 0x2D.1:0 CHA_HSYNC_PULSE_WIDTH_HIGH 0x30.7:0 CHA_VSYNC_PULSE_WIDTH_LOW 0x31.1:0 CHA_VSYNC_PULSE_WIDTH_HIGH 0x34.7:0 CHA_HORIZONTAL_BACK_PORCH 0x36.7:0 CHA_VERTICAL_BACK_PORCH 0x38.7:0 CHA_HORIZONTAL_FRONT_PORCH 0x3A.7:0 CHA_VERTICAL_FRONT_PORCH 0x22.7:0 CHB_ACTIVE_LINE_LENGTH_LOW 0x23.3:0 CHB_ACTIVE_LINE_LENGTH_HIGH 0x26.7:0 CHB_VERTICAL_DISPLAY_SIZE_LOW 0x27.3:0 CHB_VERTICAL_DISPLAY_SIZE_HIGH 0x2E.7:0 CHB_HSYNC_PULSE_WIDTH_LOW 0x2F.1:0 CHB_HSYNC_PULSE_WIDTH_HIGH 0x32.7:0 CHB_VSYNC_PULSE_WIDTH_LOW 0x33.1:0 CHB_VSYNC_PULSE_WIDTH_HIGH 0x35.7:0 CHB_HORIZONTAL_BACK_PORCH 0x37.7:0 CHB_VERTICAL_BACK_PORCH 0x39.7:0 CHB_HORIZONTAL_FRONT_PORCH 0x3B.7:0 CHB_VERTICAL_FRONT_PORCH Channel B Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 15 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com 8.4 Device Functional Modes 8.4.1 Operating Modes The SN65DSI85 can be configured for several different operating modes via LVDS_LINK_CFG (CSR 0x18.4), LEFT_RIGHT_PIXELS (CSR 0x10.7), and DSI_CHANNEL_MODE (CSR 0x10.6:5). These modes are summarized in Table 4. In each of the modes, video data can be 18 bpp or 24 bpp. Table 4. SN65DSI85 Operating Modes CSR 0x18.4 CSR 0x10.7 CSR 0x10.6:5 LVDS_LINK_CFG LEFT_RIGHT_PIXES DSI_CH_MODE Single DSI Input to Single-Link LVDS 1 N/A 01 Single DSI Input on Channel A to Single-Link LVDS output on Channel A. Single DSI Input to Dual-Link LVDS 0 N/A 01 Single DSI Input on Channel A to Dual-Link LVDS output with Odd pixels on Channel A and Even pixels on Channel B. Dual DSI Input (Odd/Even) to SingleLink LVDS (1) 1 0 00 Dual DSI Input with Odd pixels received on Channel A and Even pixels received on Channel B. Data is output to Single-Link LVDS on Channel A. Dual DSI Input (Odd/Even) to Dual-Link LVDS (1) 0 0 00 Dual DSI Input with Odd pixels received on Channel A and Even pixels received on Channel B. Data is output to Dual-Link LVDS with Odd pixels on Channel A and Even pixels on Channel B. Dual DSI Input (Left/Right) to SingleLink LVDS (2) 1 1 00 Dual DSI Input with Left pixels received on Channel A and Right pixels received on Channel B. Data is output to Single-Link LVDS on Channel A. Dual DSI Input (Left/Right) to Dual-Link LVDS (2) 0 1 00 Dual DSI Input with Left pixels received on Channel A and Right pixels received on Channel B. Data is output to Dual-Link LVDS with Odd pixels on Channel A and Even pixels on Channel B. Dual DSI Inputs (two streams) to two Single-Link LVDS (3) 0 N/A 10 One video stream input on DSI Channel A and output to Single-Link LVDS on Channel A. Another video stream input on DSI Channel B and output to Single-Link LVDS on Channel B. MODE (1) (2) (3) DESCRIPTION In these modes, DSI Channel A and DSI Channel B must be set to have the same number of data lanes enabled and the data format must be the same for both lanes. In these modes, DSI Channel A and DSI Channel B can each have a different number of data lanes enabled, but the data format must be the same for both lanes. In this mode, DSI Channel A and DSI Channel B can each have a different number of data lanes enabled, and the data format for each Channel can be different. 8.4.2 Reset Implementation When EN is de-asserted (low), the SN65DSI85 is in SHUTDOWN or RESET state. In this state, CMOS inputs are ignored, the MIPI(R) D-PHY inputs are disabled and outputs are high impedance. It is critical to transition the EN input from a low to a high level after the VCC supply has reached the minimum operating voltage as shown in Figure 6. This is achieved by a control signal to the EN input, or by an external capacitor connected between EN and GND. VCC 1.65V EN tVCC ten Figure 6. Cold Start VCC Ramp up to EN 16 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the VCC supply, where a slower ramp-up results in a larger value external capacitor. See the latest reference schematic for the SN65DSI85 device and, or consider approximately 200 nF capacitor as a reasonable first estimate for the size of the external capacitor. Both EN implementations are shown in Figure 7 and Figure 8. VCC GPO EN C EN REN =200 k C SN65DSI85 controller SN65DSI85 Figure 7. External Capacitor Controlled EN Figure 8. EN Input from Active Controller When the SN65DSI85 is reset while VCC is high, the EN pin must be held low for at least 10 ms before being asserted high as described in Table 5 to be sure that the device is properly reset. The DSI CLK lane MUST be in HS and the DSI data lanes MUST be driven to LP11 while the device is in reset before the EN pin is asserted per the timing described in Table 5. 8.4.3 Initialization Sequence Use the following initialization sequence to setup the SN65DSI85. This sequence is required for proper operation of the device. Steps 9 through 11 in the sequence are optional. Table 5. Initialization Sequence INITIALIZATION SEQUENCE NUMBER INITIALIZATION SEQUENCE DESCRIPTION Init seq 1 Power on Init seq 2 After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven to LP11 state Init seq 3 Set EN pin to Low Wait 10 ms (1) Init seq 4 Tie EN pin to High Wait 10 ms (1) Init seq 5 Initialize all CSR registers to their appropriate values based on the implementation (The SN65DSI8x is not functional until the CSR registers are initialized) Init seq 6 Set the PLL_EN bit (CSR 0x0D.0) Wait 10 ms (1) Init seq 7 Set the SOFT_RESET bit (CSR 0x09.0) Wait 10 ms (1) Init seq 8 Wait 5 ms Change DSI data lanes to HS state and start DSI video stream (1) Init seq 9 Read back all resisters and confirm they were correctly written Init seq 10 Wait 1 ms Init seq 11 (1) Write 0xFF to CSR 0xE5 and CSR 0xE6 to clear the error registers (1) Read CSR 0xE5 and CSR 0xE6. If CSR 0xE5 and CSR 0xE6 != 0x00, then go back to step #2 and re-initialize Minimum recommended delay. It is fine to exceed these. Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 17 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com 8.4.4 LVDS Output Formats The SN65DSI85 processes DSI packets and produces video data driven to the FlatLinkTM LVDS interface in an industry standard format. Single-Link LVDS and Dual-Link LVDS are supported by the SN65DSI85; when the FlatLinkTM output is implemented in a Dual-Link configuration, channel A carries the odd pixel data, and channel B carries the even pixel data. During conditions such as the default condition, and some video synchronization periods, where no video stream data is passing from the DSI input to the LVDS output, the SN65DSI85 transmits zero value pixel data on the LVDS outputs while maintaining transmission of the vertical sync and horizontal sync status. Figure 9 illustrates a Single-Link LVDS 18 bpp application. Figure 10 illustrates a Dual-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two MSB per color are transferred on the Y3P/N LVDS lane. Figure 11 illustrates a 24 bpp Single-Link application using Format 1. In data Format 1, the two LSB per color are transferred on the Y3P/N LVDS lane. Figure 12 illustrates a Single-Link LVDS application where 24 bpp data is received from DSI and converted to 18 bpp data for transmission to an 18 bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0x18.1) to 1 and CHA_24BPP_MODE (CSR 0x18.3) to 0. In this configuration, the SN65DSI85 will not transmit the 2 LSB per color since the Y3P/N LVDS lane is disabled. NOTE Note: Figure 9, Figure 10, Figure 11, and Figure 12 only illustrate a few example applications for the SN65DSI85. Other applications are also supported. A_CLKP/N B_CLKP/N cycle `n-1' cycle `n' A_Y0P/N G0 R5 R4 R3 R2 R1 R0 A_Y1P/N B1 B0 G5 G4 G3 G2 G1 A_Y2P/N DE VS HS B5 B4 B3 B2 A_Y3P/N B_YxP/N DE = Data Enable; Channel B Clock, Channel B Data, and A_Y3P/N are Output Low Figure 9. FlatLinkTM Output Data; Single-Link 18 bpp 18 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 A_CLKP/N B_CLKP/N cycle `n-1' cycle `n' A_Y0P/N G0 (o) R5 (o) R4 (o) R3 (o) R2 (o) R1 (o) R0 (o) A_Y1P/N B1 (o) B0 (o) G5 (o) G4 (o) G3 (o) G2 (o) G1 (o) A_Y2P/N DE (o) VS (o) HS (o) B5 (o) B4 (o) B3 (o) B2 (o) A_Y3P/N 0 (o) B7 (o) B6 (o) G7 (o) G6 (o) R7 (o) R6 (o) B_Y0P/N G0 (e) R5 (e) R4 (e) R3 (e) R2 (e) R1 (e) R0 (e) B_Y1P/N B1 (e) B0 (e) G5 (e) G4 (e) G3 (e) G2 (e) G1 (e) B_Y2P/N DE (e) VS (e) HS (e) B5 (e) B4 (e) B3 (e) B2 (e) B_Y3P/N 0 (e) B7 (e) B6 (e) G7 (e) G6 (e) R7 (e) R6 (e) DE = Data Enable; (o) = Odd Pixels; (e) = Even Pixels Figure 10. FlatLinkTM Output Data (Format 2); Dual-Link 24 bpp A_CLKP/N B_CLKP/N cycle `n-1' cycle `n' A_Y0P/N G2 R7 R6 R5 R4 R3 R2 A_Y1P/N B3 B2 G7 G6 G5 G4 G3 A_Y2P/N DE VS HS B7 B6 B5 B4 A_Y3P/N 0 B1 B0 G1 G0 R1 R0 B_YxP/N DE = Data Enable; Channel B Clock and Data are Output Low Figure 11. FlatLinkTM Output Data (Format 1); Single-Link 24 bpp A_CLKP/N B_CLKP/N cycle `n-1' cycle `n' A_Y0P/N G2 R7 R6 R5 R4 R3 R2 A_Y1P/N B3 B2 G7 G6 G5 G4 G3 A_Y2P/N DE VS HS B7 B6 B5 B4 A_Y3P/N B_YxP/N DE = Data Enable; Channel B Clock, Channel B Data, and A_Y3P/N are Output Low; Channel B Clock, Channel B Data, and A_Y3P/N are Output Low Figure 12. FlatLinkTM Output Data (Format 1); 24 bpp to Single-Link 18 bpp Conversion Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 19 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com 8.4.5 DSI Lane Merging The SN65DSI85 supports four DSI data lanes per input channel, and may be configured to support one, two, or three DSI data lanes per channel. Unused DSI input pins on the SN65DSI85 should be left unconnected or driven to LP11 state.The bytes received from the data lanes are merged in HS mode to form packets that carry the video stream. DSI data lanes are bit and byte aligned. Figure 13 illustrates the lane merging function for each channel; 4-Lane, 3-Lane, and 2-Lane modes are shown. HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 3 HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 4 LANE 0 SOT BYTE 0 BYTE 4 BYTE 8 BYTE n-4 EOT LANE 0 SOT BYTE 0 BYTE 3 BYTE 6 BYTE n-3 EOT LANE 1 SOT BYTE 1 BYTE 5 BYTE 9 BYTE n-3 EOT LANE 1 SOT BYTE 1 BYTE 4 BYTE 7 BYTE n-2 EOT LANE 2 SOT BYTE 2 BYTE 6 BYTE 10 BYTE n-2 EOT LANE 2 SOT BYTE 2 BYTE 5 BYTE 8 BYTE n-1 EOT LANE 3 SOT BYTE 3 BYTE 7 BYTE 11 BYTE n-1 EOT HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 3 HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 4 LANE 0 SOT BYTE 0 BYTE 4 BYTE 8 BYTE n-3 EOT LANE 1 SOT BYTE 1 BYTE 5 BYTE 9 BYTE n-2 EOT LANE 2 SOT BYTE 2 BYTE 6 BYTE 10 BYTE n-1 LANE 3 SOT BYTE 3 BYTE 7 BYTE 11 EOT SOT BYTE 0 BYTE 4 BYTE 8 BYTE n-2 LANE 1 SOT BYTE 1 BYTE 5 BYTE 9 BYTE n-1 LANE 2 SOT BYTE 2 BYTE 6 BYTE 10 EOT LANE 3 SOT BYTE 3 BYTE 7 BYTE 11 EOT BYTE 0 BYTE 3 BYTE 6 BYTE n-2 EOT LANE 1 SOT BYTE 1 BYTE 4 BYTE 7 BYTE n-1 EOT LANE 2 SOT BYTE 2 BYTE 5 BYTE 8 EOT EOT HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 3 HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 4 LANE 0 SOT LANE 0 SOT BYTE 0 BYTE 3 BYTE 6 LANE 1 SOT BYTE 1 BYTE 4 BYTE 7 EOT LANE 2 SOT BYTE 2 BYTE 5 BYTE 8 EOT LANE 0 SOT BYTE 0 BYTE 4 BYTE 8 BYTE n-1 LANE 1 SOT BYTE 1 BYTE 5 BYTE 9 EOT LANE 2 SOT BYTE 2 BYTE 6 BYTE 10 EOT LANE 3 SOT BYTE 3 BYTE 7 BYTE 11 EOT 4 DSI Data Lane Configuration (default) EOT EOT EOT 3 DSI Data Lane Configuration HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 2 HS BYTES TRANSMITTED (n) IS 3 LESS THAN INTEGER MULTIPLE OF 4 LANE 0 BYTE n-1 EOT LANE 0 SOT BYTE 0 BYTE 2 BYTE 4 BYTE n-2 EOT LANE 1 SOT BYTE 1 BYTE 3 BYTE 5 BYTE n-1 EOT HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 2 LANE 0 SOT BYTE 0 BYTE 2 BYTE 4 BYTE n-1 LANE 1 SOT BYTE 1 BYTE 3 BYTE 5 EOT EOT 2 DSI Data Lane Configuration Figure 13. SN65DSI85 DSI Lane Merging Illustration 20 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 8.4.6 DSI Pixel Stream Packets The SN65DSI85 processes 18 bpp (RGB666) and 24 bpp (RGB888) DSI packets on each channel as shown in Figure 14, Figure 15, and Figure 16. 2 Bytes DATA TYPE (0x2E) VIRTUAL CHANNEL 1 Byte 1 Byte WORD COUNT WORD COUNT Bytes 18 bpp Loosely Packed Pixel Stream ECC CRC CHECKSUM (Variable Size Payload) Packet Payload Packet Header 1 Byte 01 2 Bytes 1 Byte 1 Byte 1 Byte 1 Byte Packet Footer 1 Byte 1 Byte 1 Byte 1 Byte 2 7 2 7 2 7 2 7 2 7 2 7 2 7 2 7 2 7 R0 R5 G0 G5 B0 B5 R0 R5 G0 G5 B0 B5 R0 R5 G0 G5 B0 B5 6-bits RED 6-bits GREEN 6-bits BLUE 6-bits RED 6-bits GREEN First Pixel in Packet 6-bits BLUE 6-bits RED 6-bits GREEN Second Pixel in Packet 6-bits BLUE Third Pixel in Packet Variable Size Payload (Three Pixels Per Nine Bytes of Payload) Figure 14. 18 bpp (Loosely Packed) DSI Packet Structure 2 Bytes DATA TYPE (0x1E) VIRTUAL CHANNEL 1 Byte 1 Byte WORD COUNT WORD COUNT Bytes 18 bpp Packed Pixel Stream ECC Packet Payload Packet Header 5 R0 1 Byte 6 7 0 R5 G0 6-bits RED CRC CHECKSUM (Variable Size Payload) 1 Byte 0 2 Bytes 3 1 Byte 4 7 01 6-bits GREEN 2 7 B 5 R0 G5 B 0 1 Byte 6-bits BLUE 0 5 R5 G0 6-bits RED First Pixel in Packet 1 Byte 6 7 0 G5 B 0 6-bits GREEN 3 4 7 01 B 5 R0 6-bits BLUE Packet Footer 1 Byte 2 7 R5 G0 6-bits RED Second Pixel in Packet 1 Byte 0 5 G5 B 0 6-bits GREEN 1 Byte 6 7 0 3 B 5 R0 6-bits BLUE 1 Byte 4 7 01 R5 G0 6-bits RED Third Pixel in Packet 2 7 G5 B 0 6-bits GREEN B5 6-bits BLUE Fourth Pixel in Packet Variable Size Payload (Four Pixels Per Nine Bytes of Payload) Figure 15. 18 bpp (Tightly Packed) DSI Packet Structure 2 Bytes VIRTUAL CHANNEL DATA TYPE (0x3E) 1 Byte 1 Byte WORD COUNT WORD COUNT Bytes 24 bpp Packed Pixel Stream ECC CRC CHECKSUM (Variable Size Payload) Packet Payload Packet Header 1 Byte 1 Byte 0 7 0 R0 R7 G0 8-bits RED 2 Bytes 1 Byte 7 0 7 G 7 B0 8-bits GREEN 1 Byte B7 8-bits BLUE First Pixel in Packet 1 Byte 0 7 0 R0 R7 G0 8-bits RED Packet Footer 1 Byte 7 0 7 G 7 B0 8-bits GREEN 1 Byte B7 0 7 R0 8-bits BLUE Second Pixel in Packet 1 Byte R7 1 Byte 0 7 G0 G7 B 0 8-bits RED 0 8-bits GREEN 7 B7 8-bits BLUE Third Pixel in Packet Variable Size Payload (Three Pixels Per Nine Bytes of Payload) Figure 16. 24 bpp DSI Packet Structure Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 21 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com 8.4.7 DSI Video Transmission Specifications The SN65DSI85 supports burst video mode and non-burst video mode with sync events or with sync pulses packet transmission as described in the DSI specification. The burst mode supports time-compressed pixel stream packets that leave added time per scan line for power savings LP mode. The SN65DSI85 requires a transition to LP mode once per frame to enable PHY synchronization with the DSI host processor; however, for a robust and low-power implementation, the transition to LP mode is recommended on every video line. Figure 17 illustrates the DSI video transmission applied to SN65DSI85 applications. In all applications, the LVDS output rate must be less than or equal to the DSI input rate. The first line of a video frame shall start with a VSS packet, and all other lines start with VSE or HSS. The position of the synchronization packets in time is of utmost importance since this has a direct impact on the visual performance of the display panel; that is, these packets generate the HS and VS (horizontal and vertical sync) signals on the LVDS interface after the delay programmed into CHA_SYNC_DELAY_LOW/HIGH (CSR 0x28.7:0 and 0x29.3:0) and/or CHB_SYNC_DELAY_LOW/HIGH (CSR 0x2A.7:0 and 0x2B.3:0). When configured for dual DSI channels, the SN65DSI85 uses the VSS, VSE, and HSS packets from channel A to generate the HS and VS (horizontal and vertical sync) signals on the LVDS interface, and the VSS, VSE, and HSS packets from channel B are ignored. As required in the DSI specification, the SN65DSI85 requires that pixel stream packets contain an integer number of pixels (i.e. end on a pixel boundary); it is recommended to transmit an entire scan line on one pixel stream packet. When a scan line is broken in to multiple packets, inter-packet latency shall be considered such that the video pipeline (ie. pixel queue or partial line buffer) does not run empty (i.e. under-run); during scan line processing, if the pixel queue runs empty, the SN65DSI85 transmits zero data (18'b0 or 24'b0) on the LVDS interface. When configured for dual DSI channels, the SN65DSI85 supports ODD/EVEN configurations and LEFT/RIGHT configurations. In the ODD/EVEN configuration, the odd pixels for each scan line are received on channel A, and the even pixels are received on channel B. In LEFT/RIGHT mode, the LEFT portion of the line is received on channel A, and the right portion of the line is received on channel B. Neither the channel A LEFT portion input or the channel B RIGHT portion input per line shall exceed 1408 pixels, which is defined as 1/2 of the maximum line size (2560 pixels in WQXGA 2560x1600 mode) plus 10% headroom. The pixels received on channel B in LEFT/RIGHT mode are buffered during the LEFT side transmission to LVDS, and begin transmission to LVDS when the LEFT-side input buffer runs empty. When configured for two single DSI channels, the SN65DSI85 requires that the LVDS output clocks for both video data streams be the same. NOTE When the HS clock is used as a source for the LVDS pixel clock, the LP mode transitions apply only to the data lanes, and the DSI clock lane remains in the HS mode during the entire video transmission. The DSI85 does not support the DSI Virtual Channel capability or reverse direction (peripheral to processor) transmissions. 22 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 One Video Frame Vertical sync / blanking RGB NOP/ LP Active Lines NOP/ LP t LINE ... HSS NOP/ ... LP RGB t LINE HSS NOP/ LP t LINE HSS NOP/ LP ... NOP/ LP NOP/ LP t LINE HSS NOP/ LP t LINE HSS DSI Channel A t LINE HSS VSS t LINE NOP/ LP Vertical sync / blanking t SK (A_B) light shaded NOP/LP are optional; represents horizontal back porch (max value is 256 HS Clocks) RGB NOP/ LP NOP/ LP HSS* NOP/ ... LP HSS* RGB HSS* NOP/ LP NOP/ LP NOP/ LP ... HSS* NOP/ LP HSS* NOP/ LP HSS* DSI Channel B VSS* * VSS and HSS packets are required for DSI Channel B, although LVDS video sync signals are derived from DSI Channel A VSS and HSS packets ... NOP/ LP dark shaded NOP/LP represents horizontal front porch; a transition to LP mode is recommended here (if HS_CLK is free-running to source the LVDS clock , then only data lanes shall transition to LP mode It is recommended to have tSK(A_B) < 9 DSI HS Clock cycles or less than 3 Pixels data sample time. More delay between DSI Channel A and B can be tolerated by SN65DSI85, contact Texas Instruments for SN65DSI8X device configuration information that would allow longer delay between DSI Channel A and B. Vertical Blanking Period LVDS Transfer Function t W (HS ) HS (1) DSI Channel(s) t PD ... HS (1) t PD VS (2) VS DE (3) DE (3) DE (3) 0x000 NOP/ LP t W(HS) HS (1) VS (2) DATA RGB HSS NOP/ LP NOP/ LP DSI Channel A HSS NOP/ LP t LINE t LINE HSS DSI Channel A VSS t LINE Active Video Line LVDS Transfer Function DATA 0x000 DATA (1) The assertion of HS is delayed (t PD) by a programmable number of pixel clocks from the last bit of VSS/HSS packet received on DSI. The HS pulse width (tW(HS) ) is also programmable. The illustration shows HS active low. (2) VS is signaled for a programmable number of lines (tLINE ) and is asserted when HS is asserted for the first line of the frame . VS is de -asserted when HS is asserted after the number of lines programmed has been reached. The illustration shows VS active low (2) 0x000 PixelStream Data 0x000 (4) LEGEND VSS DSI Sync Event Packet: V Sync Start HSS DSI Sync Event Packet: H Sync Start RGB A sequence of DSI Pixel Stream Packets and Null Packets NOP/LP DSI Null Packet , Blanking Packet , or a transition to LP Mode (3) DE is asserted when active pixel data is transmitted on LVDS , and polarity is set independent to HS/VS. The illustration shows DE active high (4) After the last pixel in an active line is output to LVDS, the LVDS data is output zero Figure 17. DSI Channel Transmission and Transfer Function Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 23 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com 8.5 Programming 8.5.1 Local I2C Interface Overview The SN65DSI85 local I2C interface is enabled when EN is input high, access to the CSR registers is supported during ultra-low power state (ULPS). The SCL and SDA terminals are used for I2C clock and I2C data respectively. The SN65DSI85 I2C interface conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000), and supports fast mode transfers up to 400 kbps. The device address byte is the first byte received following the START condition from the master device. The 7 bit device address for SN65DSI85 is factory preset to 010110X with the least significant bit being determined by the ADDR control input. Table 6 clarifies the SN65DSI85 target address. Table 6. SN65DSI85 I2C Target Address Description (1) (2) SN65DSI85 I2C TARGET ADDRESS BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (W/R) 0 1 0 1 1 0 ADDR 0/1 (1) (2) When ADDR=1, Address Cycle is 0x5A (Write) and 0x5B (Read) When ADDR=0, Address Cycle is 0x58 (Write) and 0x59 (Read) The following procedure is followed to write to the SN65DSI85 I2C registers. 1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI85 7-bit address and a zero-value "W/R" bit to indicate a write cycle. 2. The SN65DSI85 acknowledges the address cycle. 3. The master presents the sub-address (I2C register within SN65DSI85) to be written, consisting of one byte of data, MSB-first. 4. The SN65DSI85 acknowledges the sub-address cycle. 5. The master presents the first byte of data to be written to the I2C register. 6. The SN65DSI85 acknowledges the byte transfer. 7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the SN65DSI85. 8. The master terminates the write operation by generating a stop condition (P). The following procedure is followed to read the SN65DSI85 I2C registers: 1. The master initiates a read operation by generating a start condition (S), followed by the SN65DSI85 7-bit address and a one-value "W/R" bit to indicate a read cycle. 2. The SN65DSI85 acknowledges the address cycle. 3. The SN65DSI85 transmit the contents of the memory registers MSB-first starting at register 00h. If a write to the SN65DSI85 I2C register occurred prior to the read, then the SN65DSI85 will start at the sub-address specified in the write. 4. The SN65DSI85 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer. 5. If an ACK is received, the SN65DSI85 transmits the next byte of data. 6. The master terminates the read operation by generating a stop condition (P). The following procedure is followed for setting a starting sub-address for I2C reads: 1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI85 7-bit address and a zero-value "W/R" bit to indicate a write cycle 2. The SN65DSI85 acknowledges the address cycle. 3. The master presents the sub-address (I2C register within SN65DSI85) to be written, consisting of one byte of data, MSB-first. 4. The SN65DSI85 acknowledges the sub-address cycle. 5. The master terminates the write operation by generating a stop condition (P). 24 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 8.6 Register Maps 8.6.1 Control and Status Registers Overview Many of the SN65DSI85 functions are controlled by the Control and Status Registers (CSR). All CSR registers are accessible through the local I2C interface. See the following tables for the SN65DSI85 CSR descriptions. Reserved or undefined bit fields should not be modified. Otherwise, the device may operate incorrectly. Table 7. CSR Bit Field Definitions - ID Registers ADDRESS BIT(S) 0x00 - 0x08 7:0 (1) DESCRIPTION Reserved Addresses 0x08 - 0x00 = {0x01, 0x20, 0x20, 0x20, 0x44, 0x53, 0x49, 0x38, 0x35} DEFAULT ACCESS (1) Reserved RO RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values) Table 8. CSR Bit Field Definitions - Reset and Clock Registers ADDRESS 0x09 0x0A BIT(S) DESCRIPTION DEFAULT 0 SOFT_RESET This bit automatically clears when set to 1 and returns zeros when read. This bit must be set after the CSR's are updated. This bit must also be set after making any changes to the DSI clock rate or after changing between DSI burst and non-burst modes. 0 - No action (default) 1 - Reset device to default condition excluding the CSR bits. 0 WO 7 PLL_EN_STAT After PLL_EN_STAT = 1, wait at least 3 ms for PLL to lock. 0 - PLL not enabled (default) 1 - PLL enabled 0 RO 101 RW 0 RW 3:1 0 (1) LVDS_CLK_RANGE This field selects the frequency range of the LVDS output clock. 000 - 25 MHz LVDS_CLK < 37.5 MHz 001 - 37.5 MHz LVDS_CLK < 62.5 MHz 010 - 62.5 MHz LVDS_CLK < 87.5 MHz 011 - 87.5 MHz LVDS_CLK < 112.5 MHz 100 - 112.5 MHz LVDS_CLK < 137.5 MHz 101 - 137.5 MHz LVDS_CLK 154 MHz (default) 110 - Reserved 111 - Reserved HS_CLK_SRC 0 - LVDS pixel clock derived from input REFCLK (default) 1 - LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock ACCESS (1) RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values) Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 25 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com Table 8. CSR Bit Field Definitions - Reset and Clock Registers (continued) ADDRESS BIT(S) DEFAULT 7:3 DSI_CLK_DIVIDER When CSR 0x0A.0 = 1, this field controls the divider used to generate the LVDS output clock from the MIPI D-PHY Channel A HS continuous clock. When CSR 0x0A.0 = 0, this field must be programmed to 00000. 00000 - LVDS clock = source clock (default) 00001 - Divide by 2 00010 - Divide by 3 00011 - Divide by 4 * * * 10111 - Divide by 24 11000 - Divide by 25 11001 through 11111 - Reserved ACCESS 00000 RW 1:0 REFCLK_MULTIPLIER When CSR 0x0A.0 = 0, this field controls the multiplier used to generate the LVDS output clock from the input REFCLK. When CSR 0x0A.0 = 1, this field must be programmed to 00. 00 - LVDS clock = source clock (default) 01 - Multiply by 2 10 - Multiply by 3 11 - Multiply by 4 00 RW 0 PLL_EN When this bit is set, the PLL is enabled with the settings programmed into CSR 0x0A and CSR 0x0B. The PLL should be disabled before changing any of the settings in CSR 0x0A and CSR 0x0B. The input clock source must be active and stable before the PLL is enabled. 0 - PLL disabled (default) 1 - PLL enabled 0 RW 0x0B 0x0D DESCRIPTION (1) Table 9. CSR Bit Field Definitions - DSI Registers ADDRESS BIT(S) 26 ACCESS 0 RW 6:5 DSI_CHANNEL_MODE 00 - Dual-channel DSI receiver 01 - Single channel DSI receiver (default) 10 - Two single channel DSI receivers 11 - Reserved 01 RW 4:3 CHA_DSI_LANES This field controls the number of lanes that are enabled for DSI Channel A. 00 - Four lanes are enabled 01 - Three lanes are enabled 10 - Two lanes are enabled 11 - One lane is enabled (default) Note: Unused DSI input pins on the SN65DSI85 should be left unconnected. 11 RW 2:1 CHB_DSI_LANES This field controls the number of lanes that are enabled for DSI Channel B. 00 - Four lanes are enabled 01 - Three lanes are enabled 10 - Two lanes are enabled 11 - One lane is enabled (default) Note: Unused DSI input pins on the SN65DSI85 should be left unconnected. 11 RW SOT_ERR_TOL_DIS 0 - Single bit errors are tolerated for the start of transaction SoT leader sequence (default) 1 - No SoT bit errors are tolerated 0 RW 0 (1) DEFAULT LEFT_RIGHT_PIXELS This bit selects the pixel arrangement in dual channel DSI implementations. 0 - DSI channel A receives ODD pixels and channel B receives EVEN (default) 1 - DSI channel A receives LEFT image pixels and channel B receives RIGHT image pixels 7 0x10 DESCRIPTION (1) RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values) Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 Table 9. CSR Bit Field Definitions - DSI Registers (continued) ADDRESS BIT(S) 0x13 DEFAULT ACCESS 7:6 CHA_DSI_DATA_EQ This field controls the equalization for the DSI Channel A Data Lanes 00 - No equalization (default) 01 - 1 dB equalization 10 - Reserved 11 - 2 dB equalization 00 RW 5:4 CHB_DSI_DATA_EQ This field controls the equalization for the DSI Channel B Data Lanes 00 - No equalization (default) 01 - 1 dB equalization 10 - Reserved 11 - 2 dB equalization 00 RW 3:2 CHA_DSI_CLK_EQ This field controls the equalization for the DSI Channel A Clock 00 - No equalization (default) 01 - 1 dB equalization 10 - Reserved 11 - 2 dB equalization 00 RW 1:0 CHB_DSI_CLK_EQ This field controls the equalization for the DSI Channel A Clock 00 - No equalization (default) 01 - 1 dB equalization 10 - Reserved 11 - 2 dB equalization 00 RW 7:0 CHA_DSI_CLK_RANGE This field specifies the DSI Clock frequency range in 5 MHz increments for the DSI Channel A Clock 0x00 through 0x07 - Reserved 0x08 - 40 frequency < 45 MHz 0x09 - 45 frequency < 50 MHz * * * 0x63 - 495 frequency < 500 MHz 0x64 - 500 MHz 0x65 through 0xFF - Reserved 0 RW 7:0 CHB_DSI_CLK_RANGE This field specifies the DSI Clock frequency range in 5 MHz increments for the DSI Channel B Clock 0x00 through 0x07 - Reserved 0x08 - 40 frequency < 45 MHz 0x09 - 45 frequency < 50 MHz * * * 0x63 - 495 frequency < 500 MHz 0x64 - 500 MHz 0x65 through 0xFF - Reserved 0 RW 0x11 0x12 DESCRIPTION Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 (1) 27 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com Table 10. CSR Bit Field Definitions - LVDS Registers ADDRESS BIT(S) DESCRIPTION DEFAULT ACCESS 7 DE_NEG_POLARITY 0 - DE is positive polarity driven 1 during active pixel transmission on LVDS (default) 1 - DE is negative polarity driven 0 during active pixel transmission on LVDS 0 RW 6 HS_NEG_POLARITY 0 - HS is positive polarity driven 1 during corresponding sync conditions 1 - HS is negative polarity driven 0 during corresponding sync (default) 1 RW 5 VS_NEG_POLARITY 0 - VS is positive polarity driven 1 during corresponding sync conditions 1 - VS is negative polarity driven 0 during corresponding sync (default) 1 RW 1 RW (1) LVDS_LINK_CFG 0 - LVDS Channel A and Channel B outputs enabled 4 When CSR 0x10.6:5 = 00 or 01, the LVDS is in Dual-Link configuration When CSR 0x10.6:5 = 10, the LVDS is in two Single-Link configuration 1 - LVDS Single-Link configuration; Channel A output enabled and Channel B output disabled (default) 0x18 3 CHA_24BPP_MODE 0 - Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled (default) 1 - Force 24bpp; LVDS channel A lane 4 (B_Y3P/N) is enabled 0 RW 2 CHB_24BPP_MODE 0 - Force 18bpp; LVDS channel B lane 4 (A_Y3P/N) is disabled (default) 1 - Force 24bpp; LVDS channel B lane 4 (B_Y3P/N) is enabled 0 RW 1 CHA_24BPP_FORMAT1 This field selects the 24bpp data format 0 - LVDS channel A lane A_Y3P/N transmits the 2 most significant bits (MSB) per color; Format 2 (default) 1 - LVDS channel B lane A_Y3P/N transmits the 2 least significant bits (LSB) per color; Format 1 Note1: This field must be 0 when 18bpp data is received from DSI. Note2: If this field is set to 1 and CHA_24BPP_MODE is 0, the SN65DSI85 will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In this configuration, the SN65DSI85 will not transmit the 2 LSB per color on LVDS channel A, since LVDS channel A lane A_Y3P/N is disabled. 0 RW 0 CHB_24BPP_FORMAT1 This field selects the 24bpp data format 0 - LVDS channel B lane B_Y3P/N transmits the 2 most significant bits (MSB) per color; Format 2 (default) 1 - LVDS channel B lane B_Y3P/N transmits the 2 least significant bits (LSB) per color; Format 1 Note1: This field must be 0 when 18bpp data is received from DSI. Note2: If this field is set to 1 and CHB_24BPP_MODE is 0, the SN65DSI85 will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In this configuration, the SN65DSI85 will not transmit the 2 LSB per color on LVDS channel B, since LVDS channel B lane B_Y3P/N is disabled. 0 RW 6 CHA_LVDS_VOCM This field controls the common mode output voltage for LVDS Channel A 0 - 1.2V (default) 1 - 0.9V (CSR 0x1B.5:4 CHA_LVDS_CM_ADJUST must be set to 01b) 0 RW 4 CHB_LVDS_VOCM This field controls the common mode output voltage for LVDS Channel B 0 - 1.2V (default) 1 - 0.9V (CSR 0x1B.1:0 CHB_LVDS_CM_ADJUST must be set to 01b) 0 RW 3:2 CHA_LVDS_VOD_SWING This field controls the differential output voltage for LVDS Channel A. See the Electrical Characteristics for |VOD| for each setting: 00, 01 (default), 10, 11 01 RW 1:0 CHB_LVDS_VOD_SWING This field controls the differential output voltage for LVDS Channel B. See the Electrical Characteristics for |VOD| for each setting: 00, 01 (default), 10, 11 01 RW 0x19 (1) 28 RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values) Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 Table 10. CSR Bit Field Definitions - LVDS Registers (continued) ADDRESS BIT(S) 6 DESCRIPTION DEFAULT EVEN_ODD_SWAP 0 - Odd pixels routed to LVDS Channel A and Even pixels routed to LVDS Channel B (default) 1 - Odd pixels routed to LVDS Channel B and Even pixels routed to LVDS Channel A Note: When the SN65DSI85 is in two stream mode (CSR 0x10.6:5 = 10), setting this bit to 1 will cause the video stream from DSI Channel A to be routed to LVDS Channel B and the video stream from DSI Channel B to be routed to LVDS Channel A. ACCESS 0 RW 0 RW 0 RW 1 CHA_LVDS_TERM This bit controls the near end differential termination for LVDS Channel A. This bit also affects the output voltage for LVDS Channel A. 0 - 100 differential termination 1 - 200 differential termination (default) 1 RW 0 CHB_LVDS_TERM This bit controls the near end differential termination for LVDS Channel B. This bit also affects the output voltage for LVDS Channel B. 0 - 100 differential termination 1 - 200 differential termination (default) 1 RW (1) CHA_REVERSE_LVDS This bit controls the order of the LVDS pins for Channel A. 0 - Normal LVDS Channel A pin order. LVDS Channel A pin order is the same as listed in the Terminal Assignments Section. (default) 1 - Reversed LVDS Channel A pin order. LVDS Channel A pin order is remapped as follows: 5 * * * * * * * * * * A_Y0P A_Y3P A_Y0N A_Y3N A_Y1P A_CLKP A_Y1N A_CLKN A_Y2P A_Y2P A_Y2N A_Y2N A_CLKP A_Y1P A_CLKN A_Y1N A_Y3P A_Y0P A_Y3N A_Y0N CHB_REVERSE_LVDS This bit controls the order of the LVDS pins for Channel B. 0 - Normal LVDS Channel B pin order. LVDS Channel B pin order is the same as listed in the Terminal Assignments Section. (default) 0x1A 1 - Reversed LVDS Channel B pin order. LVDS Channel B pin order is remapped as follows: 4 * * * * * * * * * * B_Y0P B_Y3P B_Y0N B_Y3N B_Y1P B_CLKP B_Y1N B_CLKN B_Y2P B_Y2P B_Y2N B_Y2N B_CLKP B_Y1P B_CLKN B_Y1N B_Y3P B_Y0P B_Y3N B_Y0N Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 29 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com Table 10. CSR Bit Field Definitions - LVDS Registers (continued) ADDRESS BIT(S) DESCRIPTION DEFAULT ACCESS 5:4 CHA_LVDS_CM_ADJUST This field can be used to adjust the common mode output voltage for LVDS Channel A. 00 - No change to common mode voltage (default) 01 - Adjust common mode voltage down 3% 10 - Adjust common mode voltage up 3% 11 - Adjust common mode voltage up 6% 00 RW 1:0 CHB_LVDS_CM_ADJUST This field can be used to adjust the common mode output voltage for LVDS Channel B. 00 - No change to common mode voltage (default) 01 - Adjust common mode voltage down 3% 10 - Adjust common mode voltage up 3% 11 - Adjust common mode voltage up 6% 00 RW 0x1B (1) Notes: 1. TEST PATTERN GENERATION PURPOSE ONLY registers are for test pattern generation use only. Others are for normal operation unless the test pattern generation feature is enabled. CHB* registers are used only when the device is configured for two stream mode -both LVDS output channels are enabled(CSR 0x18.4=0) and DSI channel mode configured as two stream(CSR 0x10.6:5 = 0X10b). CH*_SYNC_DELAY_HIGH/LOW registers are not used for test pattern generation. In all other configurations, CHA* registers are used for test pattern generation. 2. The CHB* register fields with a note "This field is only applicable when CSR 0x10.6:5 = 10." are used only when the device is configured as two stream mode with CSR 0x18.4='0' and CSR 0x10.6:5 = 10. Table 11. CSR Bit Field Definitions - Video Registers ADDRESS 0x20 (1) 30 BIT(S) DESCRIPTION DEFAULT 7:0 CHA_ACTIVE_LINE_LENGTH_LOW When the SN65DSI85 is configured for a single DSI input, this field controls the length in pixels of the active horizontal line. When configured for Dual DSI inputs in Odd/Even mode, this field controls the number of odd pixels in the active horizontal line that are received on DSI Channel A and output to LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5) . When configured for Dual DSI inputs in Left/Right mode, this field controls the number of left pixels in the active horizontal line that are received on DSI Channel A and output to LVDS Channel A. When configured for Dual DSI inputs in two stream mode, this field controls the number of pixels in the active horizontal line for the video stream received on DSI Channel A and output to LVDS Channel A. The value in this field is the lower 8 bits of the 12-bit value for the horizontal line length. Note: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and LEFT_CROP field is programmed to a value other than 0x00, the CHA_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Left portion of the line after LEFT_CROP has been applied. 0 ACCESS (1) RW RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values) Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 Table 11. CSR Bit Field Definitions - Video Registers (continued) ADDRESS 0x21 0x22 0x23 0x24 0x25 BIT(S) DESCRIPTION DEFAULT ACCESS 3:0 CHA_ACTIVE_LINE_LENGTH_HIGH When the SN65DSI85 is configured for a single DSI input, this field controls the length in pixels of the active horizontal line. When configured for Dual DSI inputs in Odd/Even mode, this field controls the number of odd pixels in the active horizontal line that are received on DSI Channel A and output to LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). When configured for Dual DSI inputs in Left/Right mode, this field controls the number of left pixels in the active horizontal line that are received on DSI Channel A and output to LVDS Channel A. When configured for Dual DSI inputs in two stream mode, this field controls the number of pixels in the active horizontal line for the video stream received on DSI Channel A and output to LVDS Channel A. The value in this field is the upper 4 bits of the 12-bit value for the horizontal line length. Note: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and LEFT_CROP field is programmed to a value other than 0x00, the CHA_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Left portion of the line after LEFT_CROP has been applied. 0 RW 7:0 CHB_ACTIVE_LINE_LENGTH_LOW When the SN65DSI85 is configured for a single DSI input, this field is not applicable. When configured for Dual DSI inputs in Odd/Even mode, this field controls the number of even pixels in the active horizontal line that are received on DSI Channel B. When configured for Dual DSI inputs in Left/Right mode, this field controls the number of right pixels in the active horizontal line that are received on DSI Channel B and output to LVDS Channel B. When configured for Dual DSI inputs in two stream mode, this field controls the number of pixels in the active horizontal line for the video stream received on DSI Channel B and output to LVDS Channel B. The value in this field is the lower 8 bits of the 12-bit value for the horizontal line length. Note: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and RIGHT_CROP field is programmed to a value other than 0x00, the CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Right portion of the line after RIGHT_CROP has been applied. 0 RW 3:0 CHB_ACTIVE_LINE_LENGTH_HIGH When the SN65DSI85 is configured for a single DSI input, this field is not applicable. When configured for Dual DSI inputs in Odd/Even mode, this field controls the number of even pixels in the active horizontal line that are received on DSI Channel B. When configured for Dual DSI inputs in Left/Right mode, this field controls the number of right pixels in the active horizontal line that are received on DSI Channel B and output to LVDS Channel B. When configured for Dual DSI inputs in two stream mode, this field controls the number of pixels in the active horizontal line for the video stream received on DSI Channel B and output to LVDS Channel B. The value in this field is the upper 4 bits of the 12-bit value for the horizontal line length. Note: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and RIGHT_CROP field is programmed to a value other than 0x00, the CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Right portion of the line after RIGHT_CROP has been applied 0 RW 7:0 CHA_VERTICAL_DISPLAY_SIZE_LOW TEST PATTERN GENERATION PURPOSE ONLY This field controls the vertical display size in lines for LVDS Channel A/B test pattern generation. The value in this field is the lower 8 bits of the 12-bit value for the vertical display size. 0 RW 3:0 CHA_VERTICAL_DISPLAY_SIZE_HIGH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the vertical display size in lines forLVDS Channel A/B test pattern generation. The value in this field is the upper 4 bits of the 12-bit value for the vertical display size 0 RW Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 (1) 31 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com Table 11. CSR Bit Field Definitions - Video Registers (continued) ADDRESS 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 32 BIT(S) DESCRIPTION DEFAULT ACCESS 7:0 CHB_VERTICAL_DISPLAY_SIZE_LOW TEST PATTERN GENERATION PURPOSE ONLY. This field controls the vertical display size in lines for LVDS Channel B test pattern generation. The value in this field is the lower 8 bits of the 12-bit value for the vertical display size. This field is only applicable when CSR 0x10.6:5 = 10 0 RW 3:0 CHB_VERTICAL_DISPLAY_SIZE_HIGH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the vertical display size in lines for LVDS Channel B test pattern generation. The value in this field is the upper 4 bits of the 12-bit value for the vertical display size. This field is only applicable when CSR 0x10.6:5 = 10 . 0 RW 7:0 CHA_SYNC_DELAY_LOW This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5).. The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI85. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the lower 8 bits of the 12-bit value for the Sync delay. 0 RW 3:0 CHA_SYNC_DELAY_HIGH This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5).. The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI85. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the upper 4 bits of the 12-bit value for the Sync delay. 0 RW 7:0 CHB_SYNC_DELAY_LOW This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel B when the SN65DSI85 is configured as two single stream mode with CSR 0x18.4=0 and CSR 0x10.6:5 = 10. The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI85. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the lower 8 bits of the 12-bit value for the Sync delay 0 RW 3:0 CHB_SYNC_DELAY_HIGH This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel B when the SN65DSI85 is configured as two single stream mode with CSR 0x18.4=0 and CSR 0x10.6:5 = 10. The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI85. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the upper 4 bits of the 12-bit value for the Sync delay. 0 RW 7:0 CHA_HSYNC_PULSE_WIDTH_LOW This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). The value in this field is the lower 8 bits of the 10-bit value for the HSync Pulse Width. 0 RW 1:0 CHA_HSYNC_PULSE_WIDTH_HIGH This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). The value in this field is the upper 2 bits of the 10-bit value for the HSync Pulse Width. 0 RW Submit Documentation Feedback (1) Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 Table 11. CSR Bit Field Definitions - Video Registers (continued) ADDRESS BIT(S) DESCRIPTION DEFAULT 7:0 CHB_HSYNC_PULSE_WIDTH_LOW This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel B. The value in this field is the lower 8 bits of the 10-bit value for the HSync Pulse Width. This field is only applicable when CSR 0x10.6:5 = 10. 0 RW 1:0 CHB_HSYNC_PULSE_WIDTH_HIGH This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel B. The value in this field is the upper 2 bits of the 10-bit value for the HSync Pulse Width. This field is only applicable when CSR 0x10.6:5 = 10. 0 RW 7:0 CHA_VSYNC_PULSE_WIDTH_LOW This field controls the length in lines of the VSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). The value in this field is the lower 8 bits of the 10bit value for the VSync Pulse Width. 0 RW 1:0 CHA_VSYNC_PULSE_WIDTH_HIGH This field controls the length in lines of the VSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). The value in this field is the upper 2 bits of the 10-bit value for the VSync Pulse Width. 0 RW 7:0 CHB_VSYNC_PULSE_WIDTH_LOW This field controls the length in lines of the VSync Pulse Width for LVDS Channel B. The value in this field is the lower 8 bits of the 10-bit value for the VSync Pulse Width. This field is only applicable when CSR 0x10.6:5 = 10. 0 RW 1:0 CHB_VSYNC_PULSE_WIDTH_HIGH This field controls the length in lines of the VSync Pulse Width for LVDS Channel B. The value in this field is the upper 2 bits of the 10-bit value for the VSync Pulse Width. This field is only applicable when CSR 0x10.6:5 = 10. 0 RW 0x34 7:0 CHA_HORIZONTAL_BACK_PORCH This field controls the time in pixel clocks between the end of the HSync Pulse and the start of the active video data for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0) with DSI_CHANNEL_MODE set to 01 or 00(CSR 0x10.6:5). 0 RW 0x35 7:0 CHB_HORIZONTAL_BACK_PORCH This field controls the time in pixel clocks between the end of the HSync Pulse and the start of the active video data for LVDS Channel B. This field is only applicable when CSR 0x10.6:5 = 10. 0 RW 0x36 7:0 CHA_VERTICAL_BACK_PORCH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the number of lines between the end of the VSync Pulse and the start of the active video data for Channel A/B. 0 RW 7:0 CHB_VERTICAL_BACK_PORCH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the number of lines between the end of the VSync Pulse and the start of the active video data for Channel B. This field is only applicable when CSR 0x10.6:5 = 10 . 0 RW 7:0 CHA_HORIZONTAL_FRONT_PORCH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the time in pixel clocks between the end of the active video data and the start of the HSync Pulse for Channel A/B. 0 RW 0x39 7:0 CHB_HORIZONTAL_FRONT_PORCH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the time in pixel clocks between the end of the active video data and the start of the HSync Pulse for Channel B. This field is only applicable when CSR 0x10.6:5 = 10. 0 RW 0x3A 7:0 CHA_VERTICAL_FRONT_PORCH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the number of lines between the end of the active video data and the start of the VSync Pulse for Channel A/B. 0 RW 0x2E 0x2F 0x30 0x31 0x32 0x33 0x37 0x38 ACCESS Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 (1) 33 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com Table 11. CSR Bit Field Definitions - Video Registers (continued) ADDRESS 0x3B BIT(S) 0x3E 34 DEFAULT ACCESS 7:0 CHB_VERTICAL_FRONT_PORCH TEST PATTERN GENERATION PURPOSE ONLY. This field controls the number of lines between the end of the active video data and the start of the VSync Pulse for Channel B. This field is only applicable when CSR 0x10.6:5 = 10. 0 RW 4 CHA_TEST_PATTERN TEST PATTERN GENERATION PURPOSE ONLY. When this bit is set, the SN65DSI85 will generate a video test pattern for Channel A based on the values programmed into the Video Registers for Channel A 0 RW 0 CHB_TEST_PATTERN TEST PATTERN GENERATION PURPOSE ONLY. When this bit is set, the SN65DSI85 will generate a video test pattern for Channel B based on the values programmed into the Video Registers for Channel B. This field is only applicable when CSR 0x10.6:5 = 10 0 RW 7:0 RIGHT_CROP This field controls the number of pixels removed from the beginning of the active video line for DSI Channel B. This field only has meaning if LEFT_RIGHT_PIXELS = 1. This field defaults to 0x00. Note1: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and this field is programmed to a value other than 0x00, the CHB_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Right portion of the line after RIGHT_CROP has been applied. 0 RW 7:0 LEFT_CROP This field controls the number of pixels removed from the end of the active video line for DSI Channel A. This field only has meaning if LEFT_RIGHT_PIXELS = 1. This field defaults to 0x00. Note1: When the SN65DSI85 is configured for dual DSI inputs in Left/Right mode and this field is programmed to a value other than 0x00, the CHA_ACTIVE_LINE_LENGTH_LOW/HIGH registers must be programmed to the number of active pixels in the Left portion of the line after LEFT_CROP has been applied. 0 RW 0x3C 0x3D DESCRIPTION Submit Documentation Feedback (1) Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 Table 12. CSR Bit Field Definitions - IRQ Registers ADDRESS 0xE0 0xE1 BIT(S) DEFAULT ACCESS 0 IRQ_EN When enabled by this field, the IRQ output is driven high to communicate IRQ events. 0 - IRQ output is high-impedance (default) 1 - IRQ output is driven high when a bit is set in registers 0xE5 or 0xE6 that also has the corresponding IRQ_EN bit set to enable the interrupt condition 0 RW 7 CHA_SYNCH_ERR_EN 0 - CHA_SYNCH_ERR is masked 1 - CHA_SYNCH_ERR is enabled to generate IRQ events 0 RW 6 CHA_CRC_ERR_EN 0 - CHA_CRC_ERR is masked 1 - CHA_CRC_ERR is enabled to generate IRQ events 0 RW 5 CHA_UNC_ECC_ERR_EN 0 - CHA_UNC_ECC_ERR is masked 1 - CHA_UNC_ECC_ERR is enabled to generate IRQ events 0 RW 4 CHA_COR_ECC_ERR_EN 0 - CHA_COR_ECC_ERR is masked 1 - CHA_COR_ECC_ERR is enabled to generate IRQ events 0 RW 3 CHA_LLP_ERR_EN 0 - CHA_LLP_ERR is masked 1 - CHA_ LLP_ERR is enabled to generate IRQ events 0 RW 2 CHA_SOT_BIT_ERR_EN 0 - CHA_SOT_BIT_ERR is masked 1 - CHA_SOT_BIT_ERR is enabled to generate IRQ events 0 RW 0 PLL_UNLOCK_EN 0 - PLL_UNLOCK is masked 1 - PLL_UNLOCK is enabled to generate IRQ events 0 RW 7 CHB_SYNCH_ERR_EN 0 - CHB_SYNCH_ERR is masked 1 - CHB_SYNCH_ERR is enabled to generate IRQ events 0 RW 6 CHB_CRC_ERR_EN 0 - CHB_CRC_ERR is masked 1 - CHB_CRC_ERR is enabled to generate IRQ events 0 RW 5 CHB_UNC_ECC_ERR_EN 0 - CHB_UNC_ECC_ERR is masked 1 - CHB_UNC_ECC_ERR is enabled to generate IRQ events 0 RW 4 CHB_COR_ECC_ERR_EN 0 - CHB_COR_ECC_ERR is masked 1 - CHB_COR_ECC_ERR is enabled to generate IRQ events 0 RW 3 CHB_LLP_ERR_EN 0 - CHB_LLP_ERR is masked 1 - CHB_ LLP_ERR is enabled to generate IRQ events 0 RW 2 CHB_SOT_BIT_ERR_EN 0 - CHB_SOT_BIT_ERR is masked 1 - CHB_SOT_BIT_ERR is enabled to generate IRQ events 0 RW 0xE2 (1) DESCRIPTION (1) RO = Read Only; RW = Read/Write; RW1C = Read/Write 1 to Clear; WO = Write Only (reads return undetermined values) Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 35 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com Table 12. CSR Bit Field Definitions - IRQ Registers (continued) ADDRESS BIT(S) 36 DEFAULT ACCESS 7 CHA_SYNCH_ERR When the DSI channel A packet processor detects an HS or VS synchronization error, that is, an unexpected sync packet; this bit is set; this bit is cleared by writing a 1 value. 0 RW1C 6 CHA_CRC_ERR When the DSI channel A packet processor detects a data stream CRC error, this bit is set; this bit is cleared by writing a 1 value. 0 RW1C 5 CHA_UNC_ECC_ERR When the DSI channel A packet processor detects an uncorrectable ECC error, this bit is set; this bit is cleared by writing a 1 value. 0 RW1C 4 CHA_COR_ECC_ERR When the DSI channel A packet processor detects a correctable ECC error, this bit is set; this bit is cleared by writing a 1 value. 0 RW1C 3 CHA_LLP_ERR When the DSI channel A packet processor detects a low level protocol error, this bit is set; this bit is cleared by writing a 1 value. Low level protocol errors include SoT and EoT sync errors, Escape Mode entry command errors, LP transmission sync errors, and false control errors. Lane merge errors are reported by this status condition. 0 RW1C 2 CHA_SOT_BIT_ERR When the DSI channel A packet processor detects an SoT leader sequence bit error, this bit is set; this bit is cleared by writing a 1 value. 0 RW1C 0 PLL_UNLOCK This bit is set whenever the PLL Lock status transitions from LOCK to UNLOCK. 1 RW1C 7 CHB_SYNCH_ERR When the DSI channel B packet processor detects an HS or VS synchronization error, that is, an unexpected sync packet; this bit is set; this bit is cleared by writing a 1 value. 0 RW1C 6 CHB_CRC_ERR When the DSI channel B packet processor detects a data stream CRC error, this bit is set; this bit is cleared by writing a 1 value. 0 RW1C 5 CHB_UNC_ECC_ERR When the DSI channel B packet processor detects an uncorrectable ECC error, this bit is set; this bit is cleared by writing a 1 value. 0 RW1C 4 CHB_COR_ECC_ERR When the DSI channel B packet processor detects a correctable ECC error, this bit is set; this bit is cleared by writing a 1 value. 0 RW1C 3 CHB_LLP_ERR When the DSI channel B packet processor detects a low level protocol error, this bit is set; this bit is cleared by writing a 1 value. Low level protocol errors include SoT and EoT sync errors, Escape Mode entry command errors, LP transmission sync errors, and false control errors. Lane merge errors are reported by this status condition. 0 RW1C 2 CHB_SOT_BIT_ERR When the DSI channel B packet processor detects an SoT leader sequence bit error, this bit is set; this bit is cleared by writing a 1 value. 0 RW1C 0xE5 0xE6 DESCRIPTION Submit Documentation Feedback (1) Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Video STOP and Restart Sequence When the system requires to stop outputting video to the display, it is recommended to use the following sequence for the SN65DSI85: 1. Clear the PLL_EN bit to 0 (CSR 0x0D.0) 2. Stop video streaming on DSI inputs 3. Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS. When the system is ready to restart the video streaming. 1. Start video streaming on DSI inputs. 2. Set the PLL_EN bit to 1 (CSR 0x0D.0). 3. Wait for a minimum of 3 ms. 4. Set the SOFT_RESET bit (0x09.0). 9.1.2 Reverse LVDS Pin Order Option For ease of PCB routing, the SN65DSI85 supports swapping/reversing the channel or pin order via configuration register programming. The order of the LVDS pin for LVDS Channel A or Channel B can be reversed by setting the address 0x1A bit 5 CHA_REVERSE_LVDS or bit 4 CHB_REVERSE_LVDS. The LVDS Channel A and Channel B can be swapped by setting the 0x1A.6 EVEN_ODD_SWAP bit. See the corresponding register bit definition for details. 9.1.3 IRQ Usage The SN65DSI85 provides an IRQ pin that can be used to indicate when certain errors occur on DSI. The IRQ output is enabled through the IRQ_EN bit (CSR 0xE0.0). Individual error conditions for DSI Channel A are enabled through the Channel A Error Enable bits (CSR 0xE1.7:2). Individual error conditions for DSI Channel B are enabled through the Channel B Error Enable bits (CSR 0xE2.7:2). The IRQ pin will be asserted when an error occurs on DSI, the corresponding error enable bit is set, and the IRQ_EN bit is set. An error is cleared by writing a 1 to the corresponding error status bit. NOTE If the SOFT_RESET bit is set while the DSI video stream is active, some of the error status bits may be set. If the DSI video stream is stopped, some of the error status bits may be set. These error status bits should be cleared before restarting the video stream. If the DSI video stream starts before the device is configured, some of the error status bits may be set. It is recommended to start streaming after the device is correctly configured as recommended in the initialization sequence in the Recommended Initialization Sequence section. Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 37 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com 9.2 Typical Applications 9.2.1 Typical WUXGA 18-bpp Application Figure 18 illustrates a typical application using the SN65DSI85 configured for a single channel DSI receiver to interface a single-channel DSI application processor to an LVDS Dual-Link 18 bit-per-pixel panel supporting 1920 x 1200 WUXGA resolutions at 60 frames per second. 100 DA0P DA0N A_Y1N A_Y1P 100 A_Y2N A_Y2P 100 A_CLKN A_CLKP 100 DA1P DA1N DA2P DA2N DA3P DA3N DACP DACN SCL SDA A_Y3N A_Y3P B_Y0N B_Y0P 100 IRQ EN B_Y1N B_Y1P 100 ADDR REFCLK GND B_Y2N B_Y2P 100 B_CLKN B_CLKP 100 1.8V VCC to odd pixel row and column drivers 18bpp TCON A_Y0N A_Y0P FPC Application Processor SN65DSI85 to even pixel row and column drivers B_Y3N B_Y3P C1 Figure 18. Typical WUXGA 18-bpp Panel Application 9.2.1.1 Design Requirements Table 13 lists the design parameters for SN65DSI85. Table 13. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VCC 1.8 V (5%) CLOCK DSIA_CLK REFCKL Frequency N/A DSIA Clock Frequency 490 MHz PANEL INFORMATION LVDS Output Clock Frequency 81 MHz Resolution 1920 x 1200 Horizontal Active (pixels) 960 Horizontal Blanking (pixels) 144 Vertical Active (Lines) 1200 Vertical Blanking (lines) 20 Horizontal Sync Offset (pixels) 50 38 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 Typical Applications (continued) Table 13. Design Parameters (continued) DESIGN PARAMETER EXAMPLE VALUE Horizontal Sync Pulse Width (pixels) 50 Vertical Sync Offset (lines) 1 Vertical Sync Pulse Width (lines) 5 Horizontal Sync Pulse Polarity Negative Vertical Sync Pulse Polarity Negative Color Bit Depth (6 bpc or 8 bpc) 6-bit Number of LVDS Lanes 2 x [3 Data lanes + 1 Clock lane] DSI INFORMATION Number of DSI Lanes 1 x [4 Data Lanes + 1 Clock Lane] DSI Input Clock Frequency 490 MHz Dual DSI Configuration (Odd/Even or Left/Right) N/A 9.2.1.2 Detailed Design Procedure The video resolution parameters required by the panel need to be programmed into the SN65DSI84. For this example, the parameters programmed would be the following: Horizontal active = 1920 or 0x780 CHA_ACTIVE_LINE_LENGTH_LOW = 0X80 CHA_ACTIVE_LINE_LENGTH_HIGH = 0x07 Horizontal pulse Width = 50 or 0x32 CHA_HSYNC_PULSE_WIDTH_LOW = 0x32 CHA_HSYNC_PULSE_WIDTH_HIGH= 0x00 Horizontal back porch = Horizontal blanking - (Horizontal sync offset + Horizontal sync pulse width) Horizontal back porch = 144- (50 + 50) Horizontal back porch = 44 or 0x2C CHA_HORIZONTAL_BACK_PORCH = 0x2C Vertical pulse width = 5 CHA_VSYNC_PULSE_WIDTH_LOW = 0x05 CHA_VSYNC_PULSE_WIDTH_HIGH= 0x00 The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C and configuring the following TEST PATTERN GENERATION PURPOSE ONLY registers. Vertical active = 1200 or 0x4B0 CHA_VERTICAL_DISPLAY_SIZE_LOW = 0xB0 CHA_VERTICAL_DISPLAY_SIZE_HIGH = 0x04 Vertical back porch = Vertical blanking - (Vertical sync offset +Vertical sync pulse width) Vertical back porch = 20 - (1 + 5) Vertical back porch = 14 or 0x0E CHA_VERTICAL_BACK_PORCH = 0x0E Horizontal front porch = Horizontal sync offset Horizontal front porch = 50 or 0x32 CHA_HORIZONTAL_FRONT_PORCH = 0x32 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 39 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com Vertical front porch = Vertical sync offset Vertical front porch =1 CHA_VERTICAL_FRONT_PORCH = 0x01 In this example, the clock source for the SN65DSI84 is the DSI clock. When the MIPI D-PHY clock is used as the LVDS clock source, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the FlatLink LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12) must be set to the frequency range of the FlatLink LVDS output clock and DSI Channel A input clock respectively for the internal PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0x0D.0) should be set to enable the internal PLL. LVDS_CLK)RANGE = 010b - 62.5 MHz LVDS_CLK < 87.5 MHz HS_CLK_SRC = 1 - LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock DSI_CLK_DIVIDER = 00101b - Divide by 6 CHA_DSI_LANES = 00 - Four lanes are enabled CHA_DSI_CLK_RANGE = 0x62 - 490 MHz frequency < 495 MHz 9.2.1.2.1 Example Script <aardvark> <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="1" /> <i2c_bitrate khz="100" /> =====SOFTRESET======= <i2c_write addr="0x2D" count="1" radix="16">09 01</i2c_write> <sleep ms="10" /> ======ADDR 0D======= ======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured====== <i2c_write addr="0x2D" count="1" radix="16">0D 00</i2c_write> <sleep ms="10" /> ======ADDR 0A======= ======HS_CLK_SRC bit0=== ======LVDS_CLK_Range bit 3:1====== <i2c_write addr="0x2D" count="1" radix="16">0A 05</i2c_write> <sleep ms="10" /> ======ADDR 0B======= ======DSI_CLK_DIVIDER bit7:3===== ======RefCLK multiplier(bit1:0)====== ======00 LVDSclk=source clk, 01 - x2, 10 -x3, 11 - x4====== <i2c_write addr="0x2D" count="1" radix="16">0B 28</i2c_write> <sleep ms="10" /> ======ADDR 10======= ======DSI Ch Confg Left_Right Pixels(bit7 0 for A ODD, B EVEN, 1 for the other config)====== ======DSI Ch Mode(bit6:5) 00 - Dual, 01 single, 10 - two single ======= ======CHA_DSI_Lanes(bit4:3), CHB_DSI_Lanes(bit2:1), 00 - 4, 01 3, 10 - 2, 11 - 1 ======SOT_ERR_TOL_DIS(bit0)======= <i2c_write addr="0x2D" count="1" radix="16">10 26</i2c_write> <sleep ms="10" /> ======ADDR 12======= <i2c_write addr="0x2D" count="1" radix="16">12 62</i2c_write> <sleep ms="10" /> ======ADDR 18======= ======bit7: DE_Pol, bit6:HS_Pol, bit5:VS_Pol, bit4: LVDS Link Cfg, bit3:CHA 24bpp, bit2: CHB 24bpp, bit1: CHA 24bpp fmt1, bit0: CHB 24bpp fmt1====== <i2c_write addr="0x2D" count="1" radix="16">18 63</i2c_write> <sleep ms="10" /> ======ADDR 19======= <i2c_write addr="0x2D" count="1" radix="16">19 00</i2c_write> <sleep ms="10" /> ======ADDR 1A======= <i2c_write addr="0x2D" count="1" radix="16">1A 03</i2c_write> <sleep ms="10" /> ======ADDR 20======= ======CHA_LINE_LENGTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16">20 80</i2c_write> <sleep ms="10" /> ======ADDR 21======= ======CHA_LINE_LENGTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16">21 07</i2c_write> <sleep ms="10" /> ======ADDR 22======= ======CHB_LINE_LENGTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16">22 00</i2c_write> <sleep ms="10" /> ======ADDR 23======= ======CHB_LINE_LENGTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16">23 00</i2c_write> <sleep ms="10" /> ======ADDR 24======= ======CHA_VERTICAL_DISPLAY_SIZE_LOW======== 40 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 <i2c_write addr="0x2D" count="1" radix="16">24 00</i2c_write> <sleep ms="10" /> ======ADDR 25======= ======CHA_VERTICAL_DISPLAY_SIZE_HIGH======== <i2c_write addr="0x2D" count="1" radix="16">25 00</i2c_write> <sleep ms="10" /> ======ADDR 26======= ======CHB_VERTICAL_DISPLAY_SIZE_LOW======== <i2c_write addr="0x2D" count="1" radix="16">26 00</i2c_write> <sleep ms="10" /> ======ADDR 27======= ======CHB_VERTICAL_DISPLAY_SIZE_HIGH======== <i2c_write addr="0x2D" count="1" radix="16">27 00</i2c_write> <sleep ms="10" /> ======ADDR 28======= ======CHA_SYNC_DELAY_LOW======== <i2c_write addr="0x2D" count="1" radix="16">28 20</i2c_write> <sleep ms="10" /> ======ADDR 29======= ======CHA_SYNC_DELAY_HIGH======== <i2c_write addr="0x2D" count="1" radix="16">29 00</i2c_write> <sleep ms="10" /> ======ADDR 2A======= ======CHB_SYNC_DELAY_LOW======== <i2c_write addr="0x2D" count="1" radix="16">2A 00</i2c_write> <sleep ms="10" /> ======ADDR 2B======= ======CHB_SYNC_DELAY_HIGH======== <i2c_write addr="0x2D" count="1" radix="16">2B 00</i2c_write> <sleep ms="10" /> ======ADDR 2C======= ======CHA_HSYNC_PULSE_WIDTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16">2C 32</i2c_write> <sleep ms="10" /> ======ADDR 2D======= ======CHA_HSYNC_PULSE_WIDTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16">2D 00</i2c_write> <sleep ms="10" /> ======ADDR 2E======= ======CHB_HSYNC_PULSE_WIDTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16">2E 00</i2c_write> <sleep ms="10" /> ======ADDR 2F======= ======CHB_HSYNC_PULSE_WIDTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16">2F 00</i2c_write> <sleep ms="10" /> ======ADDR 30======= ======CHA_VSYNC_PULSE_WIDTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16">30 05</i2c_write> <sleep ms="10" /> ======ADDR 31======= ======CHA_VSYNC_PULSE_WIDTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16">31 00</i2c_write> <sleep ms="10" /> ======ADDR 32======= ======CHB_VSYNC_PULSE_WIDTH_LOW======== <i2c_write addr="0x2D" count="1" radix="16">32 00</i2c_write> <sleep ms="10" /> ======ADDR 33======= ======CHB_VSYNC_PULSE_WIDTH_HIGH======== <i2c_write addr="0x2D" count="1" radix="16">33 00</i2c_write> <sleep ms="10" /> ======ADDR 34======= ======CHA_HOR_BACK_PORCH======== <i2c_write addr="0x2D" count="1" radix="16">34 2C</i2c_write> <sleep ms="10" /> ======ADDR 35======= ======CHB_HOR_BACK_PORCH======== <i2c_write addr="0x2D" count="1" radix="16">35 00</i2c_write> <sleep ms="10" /> ======ADDR 36======= ======CHA_VER_BACK_PORCH======== <i2c_write addr="0x2D" count="1" radix="16">36 00</i2c_write> <sleep ms="10" /> ======ADDR 37======= ======CHB_VER_BACK_PORCH======== <i2c_write addr="0x2D" count="1" radix="16">37 00</i2c_write> <sleep ms="10" /> ======ADDR 38======= ======CHA_HOR_FRONT_PORCH======== <i2c_write addr="0x2D" count="1" radix="16">38 00</i2c_write> <sleep ms="10" /> ======ADDR 39======= ======CHB_HOR_FRONT_PORCH======== <i2c_write addr="0x2D" count="1" radix="16">39 00</i2c_write> <sleep ms="10" /> ======ADDR 3A======= ======CHA_VER_FRONT_PORCH======== <i2c_write addr="0x2D" count="1" radix="16">3A 00</i2c_write> <sleep ms="10" /> ======ADDR 3B======= ======CHB_VER_FRONT_PORCH======== <i2c_write addr="0x2D" count="1" radix="16">3B 00</i2c_write> <sleep ms="10" /> ======ADDR 3C======= ======CHA/CHB TEST PATTERN(bit4 CHA, bit0 CHB)======== <i2c_write addr="0x2D" count="1" radix="16">3C 00</i2c_write> Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 41 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com <sleep ms="10" /> =======ADDR 0D======= ======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured====== <i2c_write addr="0x2D" count="1" radix="16">0D 01</i2c_write> <sleep ms="10" /> =====SOFTRESET======= <i2c_write addr="0x2D" count="1" radix="16">09 00</i2c_write> <sleep ms="10" /> ======write====== <i2c_write addr="0x2D" count="196" radix="16">00</i2c_write> <sleep ms="10" /> ======Read====== <i2c_read addr="0x2D" count="256" radix="16">00</i2c_read> <sleep ms="10" /> </aardvark 9.2.1.3 Application Curve SN65DSI85: SINGLE Channel DSI to DUAL Channel LVDS, 1440 x 1200 132 Supply Current, I (mA) Unit 1 Unit 2 130 Unit 3 128 126 124 122 40 20 0 20 40 60 Temperature (C) 80 C001 Figure 19. Supply Current vs Temperature 42 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 9.2.2 Typical WQXGA 24-bpp Application Figure 20 illustrates a typical application using the SN65DSI85 configured for a dual-channel DSI receiver to interface a dual-channel DSI application processor to an LVDS Dual-Link 24 bit-per-pixel panel supporting 2560x1600 WQXGA resolutions at 60 frames per second. Application Processor DACP DACN DB[3: 0]P DB[3: 0]N DBCP DBCN SCL SDA IRQ EN ADDR REFCLK GND 1.8V VCC 100 A_Y1N A_Y1P 100 A_Y2N A_Y2P 100 A_CLKN A_CLKP 100 A_Y3N A_Y3P 100 B_Y0N B_Y0P 100 B_Y1N B_Y1P 100 B_Y2N B_Y2P 100 B_CLKN B_CLKP 100 B_Y3N B_Y3P 100 to odd pixel row and column drivers 24bpp TCON DA[3: 0]P DA[3: 0]N A_Y0N A_Y0P FPC SN65DSI85 to even pixel row and column drivers C1 Figure 20. Typical WQXGA 24-bpp Panel Application 9.2.2.1 Design Requirements Table 14 lists the design parameters for SN65DSI85. Table 14. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VCC 1.8 V (5%) PANEL INFORMATION LVDS Output Clock Frequency 154 MHz Resolution 2560 x 1600 Color Bit Depth (6 bpc or 8 bpc) Number of LVDS Lanes 8-bit 2 x [4 Data lanes + 1 Clock lane] DSI INFORMATION Number of DSI Lanes 2 x [4 Data Lanes + 1 Clock Lane] DSI Input Clock Frequency 500 MHz Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 43 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com 10 Power Supply Recommendations 10.1 VCC Power Supply Each VCC power supply pin must have a 100-nF capacitor to ground connected as close as possible to the SN65DSI85 device. It is recommended to have one bulk capacitor (1 F to 10 F) on it. It is also recommended to have the pins connected to a solid power plane. 10.2 VCORE Power Supply This pin must have a 100-nF capacitor to ground connected as close as possible to the SN65DSI85 device. It is recommended to have one bulk capacitor (1 F to 10 F) on it. It is also recommended to have the pins connected to a solid power plane. 11 Layout 11.1 Layout Guidelines 11.1.1 Package Specific For the ZQE package, to minimize the power supply noise floor, provide good decoupling near the SN65DSI85 device power pins. The use of four ceramic capacitors (2 x 0.1 F and 2 x 0.01 F) provides good performance. At the least, TI recommends to install one 0.1-F and one 0.01-F capacitor near the SN65DSI85 device. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and device power inputs pins must be minimized. Placing the capacitor underneath the SN65DSI85 device on the bottom of the PCB is often a good choice. 11.1.2 Differential pairs * * * * * * * * * * * Differential pairs must be routed with controlled 100- differential impedance (20%) or 50- single-ended impedance (15%). Keep away from other high speed signals. Keep lengths to within 5 mils of each other. Length matching must be near the location of mismatch. Each pair must be separated at least by 3 times the signal trace width. The use of bends in differential traces must be kept to a minimum. When bends are used, the number of left and right bends must be as equal as possible and the angle of the bend must be 135 degrees. This arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on EMI. Route all differential pairs on the same of layer. The number of vias must be kept to a minimum. It is recommended to keep the via count to 2 or less. Keep traces on layers adjacent to ground plane. Do NOT route differential pairs over any plane split. Adding Test points will cause impedance discontinuity and will therefore negatively impact signal performance. If test points are used, they must be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair. 11.1.3 Ground TI recommends that only one board ground plane be used in the design. This provides the best image plane for signal traces running above the plane. The thermal pad of the SN65DSI85 must be connected to this plane with vias. 44 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 SN65DSI85 www.ti.com SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 11.2 Layout Example Purple traces on this side are LVDS ChB signals. Purple traces on this side are DSI ChA signals. Green traces on this side are LVDS ChA signals. Green traces on this side are LVDS ChB signals. Green - Top Layer, Purple - Layer 3, Blue - Bottom Layer Figure 21. SN65DSI85 Layout Example Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 45 SN65DSI85 SLLSEB9F - SEPTEMBER 2012 - REVISED JUNE 2018 www.ti.com 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks FlatLink, E2E are trademarks of Texas Instruments. MIPI is a registered trademark of Arasan Chip Systems, Inc. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 46 Submit Documentation Feedback Copyright (c) 2012-2018, Texas Instruments Incorporated Product Folder Links: SN65DSI85 PACKAGE OPTION ADDENDUM www.ti.com 11-Jun-2018 PACKAGING INFORMATION Orderable Device Status (1) SN65DSI85ZQER ACTIVE Package Type Package Pins Package Drawing Qty BGA MICROSTAR JUNIOR ZQE 64 2500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR Op Temp (C) Device Marking (4/5) -40 to 85 DSI85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Jun-2018 OTHER QUALIFIED VERSIONS OF SN65DSI85 : * Automotive: SN65DSI85-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 12-Jun-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65DSI85ZQER Package Package Pins Type Drawing BGA MI CROSTA R JUNI OR ZQE 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 5.3 1.5 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Jun-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65DSI85ZQER BGA MICROSTAR JUNIOR ZQE 64 2500 336.6 336.6 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, "Designers") understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers' applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI's provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, "TI Resources") are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer's company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI's provision of TI Resources does not expand or otherwise alter TI's applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2018, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: SN65DSI85ZQER