RT8070ZSP - Richtek - Product.Network

RT8070

DS8070-06 July 2012 www.richtek.com

Applications

zLCD TV and Monitor

zNotebook Computers

zDistributed Power Systems

zIP Phones

zDigital Ca meras

General Description

The RT8070 is a high efficiency synchronous, step-down

DC/DC converter . Its in put voltage ra nge is from 2.7V to

5.5V and provides a n adjustable regulated output voltage

from 0.8V to 5V while delivering up to 4A of output current.

The internal synchronous low on-resistance power

switches increase efficiency and eliminate the need for

an external Schottky diode. The default switching

frequency is set at 2MHz, if the RT pin is left open. It can

also be varied from 200kHz to 2MHz by adding an external

resistor. Current mode operation with external

compensation allows the transient response to be

optimized over a wide range of loads and output capacitors.

Ordering Information

4A, 2MHz, Synchronous Step-Down Converter

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Features

zHigh Efficiency : Up to 95%

zAdjustable Frequency : 200kHz to 2MHz

zNo Schottky Diode Required

z0.8V Reference Allows Low Output Voltage

zLow Dropout Operation : 100% Duty Cycle

zEnable Function

zExternal Soft-Start

zPower Good Function

zRoHS Compliant and Halogen Free

RT8070ZSP : Product Number

YMDNN : Date Code

RT8070ZSP

Marking Information

RT8070

ZSPYMDNN

25 YM

DNN

RT8070ZQW

25 : Product Code

YMDNN : Date Code

Package Type

SP : SOP-8 (Exposed Pad-Option 2)

QW : WDFN-8L 3x3 (W-Type)

RT8070

Lead Plating System

Z : ECO (Ecological Element with

Halogen Free and Pb free)

RT8070

2DS8070-06 July 2012www.richtek.com

Typical Application Circuit

Table 1. Recommended Components Selection for fSW = 1MHz

VOUT (V) R1 (kΩ) R2 (kΩ) RCOMP (kΩ) CCOMP (pF ) L ( μH) COUT (μF)

3.3 75 24 33 560 2 22

2.5 51 24 22 560 2 22

1.8 30 24 15 560 1.5 22

1.5 21 24 13 560 1.5 22

1.2 12 24 11 560 1.5 22

1 6 24 8.2 560 1.5 22

VIN

RT8070

VIN

2.7V to 5.5V

COMP

GND

ROSC

COUT

RCOMP

VOUT

CIN

10µF

CCOMP

SS CSS

10nF

Chip Enable

100k

PGOOD PGOOD

9 (Exposed Pad)

Pin Configurations (TOP VIEW)

SOP-8 (Exposed Pad)

COMP

VIN

PGOOD

GND

COMP

VIN

PGOOD

EN 7

GND

WDFN-8L 3x3

RT8070

DS8070-06 July 2012 www.richtek.com

Function Block Diagram

Functional Pin Description

Pin No.

SOP-8

(Expose d Pad) WDFN -8L 3x3 Pin Name Pin Func tion

1 1 COMP

Error Amplifier Compensation Point. The current comparator

threshold increases with this control voltage. Connect external

compensation elem ents to this pin to stabiliz e the control loop.

2 2 SS

S of t-S tart Cont ro l I nput . Connect a ca pac itor from SS to GND to

set the soft-start period. A 10nF capacitor sets the soft-start

period to 800μs (typ.).

3 3 EN

Enable C ontrol Input. Float or connec t this pin to logic high for

enable. Connect to GND for disable.

4 4 VIN Po wer Input Supply. Decouple this pin to GND with a ca pacitor.

5 5 LX

Internal Power MOSFET Switches Output. Connect this pin to

the inductor.

6 6 RT

Oscillator Resistor Input. Connect a resistor from this pin to

GND sets the switching frequency. If this pin is floating, the

frequency will be set at 2MHz internally.

7 7 FB

Feedback. Receives the feedback voltage from a resistive

divider connected across the output.

8 8 PGOOD

Power Good Indicator. This pin is an open drain logic output

that is pulled to ground when the output voltage is not within

±12.5% of regulation point.

(Exposed Pad) 9

(Exposed Pad) GND G rou nd. T he ex pos ed pa d mu st be s olde red t o a l ar ge PC B and

connected to GN D for maximum power dissipation.

Driver

NISEN

Control

Logic

N-MOSFET ILIM

0.7V

0.4V

ISEN

Slope

Com

OSC

Output

Clamp

0.8V

Enable OTP

COMP

VIN

GND

P-G

Hiccup

Limit

10µA

PGOOD

RT8070

4DS8070-06 July 2012www.richtek.com

Absolute Maximum Ratings (Note 1)

zSupply Input Voltage, VIN ----------------------------------------------------------------------------------------- −0.3V to 6V

zLX Pin Switch Voltage--------------------------------------------------------------------------------------------- −0.3V to (VIN + 0.3V)

<200ns ---------------------------------------------------------------------------------------------------------------- −5V to 7.5V

zOther I/O Pin Voltages -------------------------------------------------------------------------------------------- −0.3V to (VIN + 0.3V)

zLX Pin Switch Current --------------------------------------------------------------------------------------------- 5A

zPower Dissipation, PD @ TA = 25°C

SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------------- 1.333W

WDFN-8L 3x3 ------------------------------------------------------------------------------------------------------- 1.429W

zPa ckage Thermal Re sistance (Note 2)

SOP-8 (Exposed Pad), θJA --------------------------------------------------------------------------------------- 75°C/W

SOP-8 (Exposed Pad), θJC -------------------------------------------------------------------------------------- 15°C/W

W DFN-8L 3x3, θJA -------------------------------------------------------------------------------------------------- 70°C/W

WDFN-8L 3x3, θJC-------------------------------------------------------------------------------------------------- 8.2°C/W

zJunction T emperature---------------------------------------------------------------------------------------------- 150°C

zLead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------ 260°C

zStorage T emperature Range ------------------------------------------------------------------------------------- −65°C to 150°C

zESD Susceptibility (Note 3)

HBM (Human Body Model)--------------------------------------------------------------------------------------- 2kV

Electrical Characteristics

(VIN = 3.3V, TA = 25°C, unless otherwise specified)

Recommended Operating Conditions (Note 4)

zSupply Input Voltage, VIN ----------------------------------------------------------------------------------------- 2.7V to 5.5V

zJunction T emperature Range------------------------------------------------------------------------------------- −40°C to 125°C

zAmbient T emperature Range------------------------------------------------------------------------------------- −40°C to 85°C

Parameter Symbol Test Conditions Min Typ Max Unit

Feedback Reference

Voltage VREF 0.784 0.8 0.816 V

Active, VFB = 0.78V, Not Switching -- 460 --

DC Bi as Curr ent Shutdown -- -- 10

μA

Output Voltage Line

Regulation V

IN = 2.7V to 5.5V -- 0.1 -- %/V

Output Voltage Load

Regulation 0A < ILOAD < 4 A -- 0.25 -- %

Error Amplifier

Trans-conductance gm -- 400 -- μA/V

Current Sense

Trans-resistance RT -- 0.3 -- Ω

RT8070

DS8070-06 July 2012 www.richtek.com

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Parameter Symbol Test Conditions Min Typ Max Unit

OSC = 300k 0.8 1 1.2

Switching Frequency Switching 0.2 -- 2 MHz

VIH EN Rising 1.6 -- --

EN Threshold Voltage VIL EN Falling -- -- 0.4 V

Switch On-Resistanc e, H igh RDS(ON)_P I

LX = 0.5A -- 110 180 mΩ

Switch On-Resistance, Low RDS(ON)_N I

LX = 0.5A -- 70 120 mΩ

P eak C urrent Limit ILIM 4.7 5.8 -- A

IN Ris ing -- 2.4 --

Under Voltage Lockout

Threshold V

IN Falling -- 2.2 -- V

RT Shutdown Threshold VRT V

RT Risi ng -- VIN − 0.7 V IN − 0.4 V

Sof t -Start Peri od tSS C

SS = 10nF -- 80 0 -- μs

PGOOD Trip Thres h old -- 87.5 -- % VOUT

RT8070

6DS8070-06 July 2012www.richtek.com

Typical Operating Characteristics

Switching Frequency vs. Temperature

0.94

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

-50 -25 0 25 50 75 100 125

Temperature (°C)

Switchi ng Frequency (M H z) 1

VIN = 5V, VOUT = 1.1V, IOUT = 0.6A,

RRT = 330kΩ

Output Voltage vs. Output Current

1.070

1.075

1.080

1.085

1.090

1.095

1.100

1.105

1.110

1.115

1.120

1.125

1.130

0 0.5 1 1.5 2 2.5 3 3.5 4

Output Current (A)

Output Voltage (V)

VIN = 5V, VOUT = 1.1V, IOUT = 0A to 4A

Efficiency vs. Output Current

100

00.511.522.533.54

Output Current (A)

Effici en cy (%)

VIN = 5V, VOUT = 1.1V, IOUT = 0A to 4A

Reference Voltage vs. Temperature

0.76

0.77

0.78

0.79

0.80

0.81

0.82

0.83

0.84

-50-25 0 25 50 75100125

Temperature (°C)

Reference Volt age (V)

VIN = 5V, VOUT = 1.1V

VIN UVLO vs. Temperature

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

-50 -25 0 25 50 75 100 125

Temper ature (°C)

VIN UVLO (V)

Rising

Falling

Enable Voltage vs. Temperature

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

-50 -25 0 25 50 75 100 125

Temperature (°C)

Enable Voltage (V)

Rising

Falling

RT8070

DS8070-06 July 2012 www.richtek.com

Switching

Time (500ns/Div)

VIN = 5V, VOUT = 1.1V, IOUT = 4A

VLX

(5V/Div)

VOUT

(10mV/Div)

Power On from EN

Time (500μs/Div)

VEN

(5V/Div)

VOUT

(1V/Div)

IOUT

(5A/Div)

VPGOOD

(5V/Div)

VIN = 5V, VOUT = 1.1V, IOUT = 4A

Power Off from EN

Time (250μs/Div)

VEN

(5V/Div)

VOUT

(1V/Div)

IOUT

(5A/Div)

VPGOOD

(5V/Div)

VIN = 5V, VOUT = 1.1V, IOUT = 4A

Load Transient Response

Time (100μs/Div)

VIN = 5V, VOUT = 1.1V, IOUT = 1A to 4A,

RCOMP = 10kΩ, CCOMP = 560pF

VOUT

(200mV/Div)

IOUT

(2A/Div)

Power Off from VIN

Time (5ms/Div)

VIN

(5V/Div)

VOUT

(1V/Div)

IOUT

(5A/Div)

VPGOOD

(5V/Div)

VIN = 5V, VOUT = 1.1V, IOUT = 4A, EN = High

VIN

(5V/Div)

VOUT

(1V/Div)

IOUT

(5A/Div)

VPGOOD

(5V/Div)

Power On from VIN

Time (2.5ms/Div)

VIN = 5V, VOUT = 1.1V, IOUT = 4A, EN = High

RT8070

8DS8070-06 July 2012www.richtek.com

Application Information

The basic IC application circuit is shown in Typical

Application Circuit. External component selection is

determined by the maximum load current and begins with

the selection of the inductor value and operating frequency

followed by CIN and COUT.

Main Control Loop

During normal operation, the internal upper power switch

(P-MOSFET) is turned on at the beginning of ea ch clock

cycle. Current in the inductor increases until the peak

inductor current rea ches the value defined by the output

voltage (VCOMP) of the error a mplifier. The error amplifier

adjusts its output voltage by comparing the feedback signal

from a resistive voltage-divider on the FB pin with an

internal 0.8V reference. When the load current increa ses,

it causes a reduction in the feedback voltage relative to

the reference. The error amplifier increases its output

voltage until the average inductor current matches the new

load current. When the upper power MOSFET shuts off,

the lower synchronous power switch (N-MOSFET) turns

on until the beginning of the next clock cycle.

Output Voltage Setting

The output voltage is set by an external resistive voltage-

divider a ccording to the following equation :

OUT REF R1

V = V (1+)

where VREF equals to 0.8V typical.

The resistive voltage-divider allows the FB pin to sense a

fra ction of the output voltage a s shown in Figure 1.

Figure 1. Setting the Output Voltage

Soft-Start

The IC contains an external soft-start cla mp that gradually

raises the output voltage. The soft-start timing is

programmed by the external capacitor between SS pin

and GND. The chip provides an internal 10μA charge current

for the extern al ca pa citor . If 10nF ca pa citor is used to set

the soft-start, the period will be 800μs (typ.).

Power Good Output

The power good output is an open-drain output and requires

a pull up resistor. When the output voltage is 12.5% above

or 12.5% below its set voltage, PGOOD will be pulled

low . It is held low until the output voltage returns to within

the allowed tolerances once more. During soft-start,

PGOOD is actively held low and is only allowed to transition

high when soft-start is over and the output voltage reaches

87.5% of its set voltage.

Operating Frequency

Selection of the operating frequency is a tradeoff between

efficiency and component size. Higher frequency operation

allows the use of smaller inductor and capacitor values.

Lower frequency operation improves efficiency by reducing

internal gate charge and switching losses but requires

larger inductance and/or capacitance to maintain low output

ripple voltage.

The operating frequency of the IC is determined by an

external resistor , ROSC, that is connected between the

RT pin and ground. The value of the resistor sets the ra mp

current that is used to charge and discharge an internal

timing ca pacitor within the oscillator. The practical switching

frequency ranges from 200kHz to 2MHz. However , when

the RT pin is floating, the internal frequency is set at 2MHz.

Determine the RT resistor value by examining the curve

below. Plea se notice the minimum on time is about 90ns.

GND

RT8070

VOUT

RT8070

DS8070-06 July 2012 www.richtek.com

Figure 2. Switching Frequency vs. RRT Resistor

Inductor Selection

For a given input and output voltage, the inductor value

and operating frequency determine the ripple current. The

ripple current, DIL, increa ses with higher VIN and decrea ses

with higher inductance

OUT OUT

LIN

I = 1

fL V

⎡⎤

Δ−

⎢⎥

⎣⎦

Having a lower ripple current reduces not only the ESR

losses in the output ca pacitors but also the output voltage

ripple. Highest efficiency operation is achieved by reducing

ripple current at low frequency, but attaining this goal

requires a large inductor .

For the ripple current selection, the value of ΔIL = 0.4(IMAX)

is a reasonable starting point. The largest ripple current

occurs at the highest VIN. To guarantee that the ripple

current stays below a specified maximum value, the

inductor value needs to be chosen according to the following

equation :

OUT OUT

L(MAX) IN(MAX)

L = 1

fI V

⎡⎤⎡ ⎤

−

⎢⎥⎢ ⎥

×Δ

⎢⎥⎢ ⎥

⎣⎦⎣ ⎦

Using Ceramic In put and Output Cap acitors

Higher values, lower cost ceramic capacitors are now

becoming available in smaller ca se sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. However , care must

be taken when these ca pacitors are used at the input and

output. When a ceramic capacitor is used at the input

a nd the power is supplied by a wall ada pter through long

wires, a load step at the output can induce ringing at the

input. At best, this ringing can couple to the output and

be mista ken a s loop instability . At worst, a sudden inrush

of current through the long wires ca n potentially cause a

voltage spike at VIN large enough to da mage the part.

Slope Compensation and Peak Inductor Current

Slope compensation provides stability in constant

frequency architectures by preventing sub- harmonic

oscillations at duty cycles greater than 50%. It is

a ccomplished internally by adding a compensating ra mp

to the inductor current signal. Normally , the peak inductor

current is reduced when slope compensation is added.

For the IC, however , separated inductor current signal is

used to monitor over current condition, so the maximum

output current stays relatively consta nt regardless of the

duty cycle.

Hiccup Mode Under Voltage Protection

A Hiccup Mode U nder V oltage Protection (UVP) function

is provided for the IC. When the FB voltage drops below

half of the feedback reference voltage, VFB, the UVP

function is triggered to auto soft-start the power stage

until this event is cleared. The Hiccup Mode UVP reduces

the input current in short circuit conditions, but will not be

triggered during soft-start process.

Under Voltage Lockout Threshold

The RT8070 includes an input under voltage lockout

protection (UVLO) function. If the input voltage exceeds

the UVLO rising threshold voltage, the converter will reset

and prepare the PWM for operation. However , if the input

voltage falls below the UVLO falling threshold voltage during

normal operation, the device will stop switching. The UVLO

rising and falling threshold voltage has a hysteresis to

prevent noise caused reset.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

0.0

0.4

0.8

1.2

1.6

2.0

2.4

0 300 600 900 1200 1500 1800 2100

RRT (k )

Switchi ng Frequency (M H z) 1

RT8070

10 DS8070-06 July 2012www.richtek.com

Figure 3. Derating Curve of Maximum Power Dissipation

Layout Considerations

Follow the PCB layout guidelines for optimal performance

of the IC.

`Connect the terminal of the input capacitor(s), CIN, as

close to the VIN pin as possible. This ca pacitor provides

the AC current into the internal power MOSFETs.

`LX node experiences high frequency voltage swings so

should be kept within a small area.

`Keep all sensitive small signal nodes away from the LX

node to prevent stray ca pa citive noise pick up.

`Connect the FB pin directly to the feedback resistors.

The resistive voltage divider must be connected between

VOUT and GND.

Figure 4. PCB Layout Guide

COMP

VIN

PGOOD

GND

Place the compensation

components as close to

the IC as possible

VOUT

GND

VIN

CIN COUT

VOUT

RCOMP

CCOMP

LX should be connected

to inductor by wide and

short trace, and keep

sensitive components

away from this trace

Place the feedback

resistors as close to

the IC as possible

Place the input and output capacitors

as close to the IC as possible

GND

ROSC

GND

CSS

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX) − TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the ambient temperature, and θJA is the junction to a mbient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

a mbient thermal resistance, θJA, is layout dependent. For

SOP-8 (Exposed Pad) pa ckages, the thermal resistance,

θJA, is 75°C/W on a standard JEDEC 51-7 four-layer

thermal test board. For WDFN-8L 3x3 packages, the

thermal resistance, θJA, is 70°C/W on a sta ndard JEDEC

51-7 four-layer thermal test board. The maximum power

dissipation at TA = 25°C can be calculated by the following

formulas :

PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for

SOP-8 (Exposed Pad) pa ckage

PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for

W DF N-8L 3x3 package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance, θJA. The derating curves in Figure 3 allow the

designer to see the ef fe ct of rising ambient temperature

on the maximum power dissipation.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

0 25 50 75 100 125

Ambient Tem pera ture (°C)

Maximum P ow er Dissipation (W ) 1

Four Layer PCB

WDFN-8L 3x3

SOP-8 (Exposed Pad)

Place the compensation

components as close to

the IC as possible

VOUT

GND

VIN

CIN COUT

VOUT

RCOMP

CCOMP

LX should be connected

to inductor by wide and

short trace, and keep

sensitive components

away from this trace

Place the feedback

resistors as close to

the IC as possible

Place the input and output capacitors

as close to the IC as possible

GND

ROSC

GND

CSS

COMP

VIN

PGOOD

EN 7

GND

(a) For SOP-8 (Exposed Pad) pa ckage

(b) For WDF N-8L 3x3 package

RT8070

DS8070-06 July 2012 www.richtek.com

Outline Dimension

EXPOSED THERMAL PAD

(Bottom of Package)

8-Lead SOP (Exposed Pad) Plastic Package

Dim e nsions In Mill imeters Dim e n sions I n Inch e s

Symbol Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 4.000 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.510 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.170 0.254 0.007 0.010

I 0.000 0.152 0.000 0.006

J 5.791 6.200 0.228 0.244

M 0.406 1.270 0.016 0.050

X 2.000 2.300 0.079 0.091

Op ti o n 1 Y 2.000 2.300 0.079 0.091

X 2.100 2.500 0.083 0.098

Op ti o n 2 Y 3.000 3.500 0.118 0.138

RT8070

12 DS8070-06 July 2012www.richtek.com

Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

Dimensions In Millimeters Dimensions In Inches

Symbol Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.200 0.300 0.008 0.012

D 2.950 3.050 0.116 0.120

D2 2.100 2.350 0.083 0.093

E 2.950 3.050 0.116 0.120

E2 1.350 1.600 0.053 0.063

e 0.650 0.026

L 0.425 0.525

0.017 0.021

W-Type 8L DFN 3x3 Package

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

DETAIL A

Pin #1 ID a nd T ie Bar M ark Options

SEE DETAIL A