83905AKLF - IDT, Integrated Device Technology Inc

General Description

The 83905 is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer.

The low impedance LVCMOS/LVTTL outputs are designed to

drive 50 series or parallel terminated transmission lines. The

effective fanout can be increased from 6 to 12 by utilizing the

ability of the outputs to drive two series terminated lines.

The 83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed

3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply

mode. Guaranteed output and part-to-part skew characteristics

along with the 1.8V output capabilities makes the 83905 ideal fo r

high performance, single ended application s that also require a

limited output voltage.

Pin Assignments

Features

•Six LVCMOS / LVTTL outputs

•Outputs able to drive 12 series terminated lines

•Crystal Oscillator Interface

•Crystal input frequency range: 10MHz to 40MHz

•Output skew: 80ps (maximum)

•RMS phase jitter @ 25MHz, (100Hz – 1MHz): 0.26ps (typical),

VDD = VDDO = 2.5V

Offset Noise Power

100Hz.................-129.7 dBc/Hz

1kHz...................-144.4 dBc/Hz

10kHz.................-147.3 dBc/Hz

100kHz...............-157.3 dBc/Hz

•5V tolerant enable inputs

•Synchronous output enables

•Operating power supply modes:

Full 3.3V, 2.5V, 1.8V

Mixed 3.3V core/2.5V output operating supply

Mixed 3.3V core/1.8V output operating supply

Mixed 2.5V core/1.8V output operating supply

•0°C to 70°C ambient operating temperature

•Lead-free (RoHS 6) packaging

Block Diagram

6 7 8 9 10

20 18 17 16

GND

VDDO

GND

CLK0

CLK1

BCLK

VDDO

GND

VDD

CLK2

GND

CLK3

ENABLE1

ENABLE2

XTAL_IN

XTAL_OU

XTAL_IN

ENABLE

BCLK5

VDDO

BCLK4

GND

BCLK3

BCLK2

GND

BCLK1

VDDO

BCLK0

GND

ENABLE2

TAL_OUT

83905

16-Lead SOIC, 150 Mil

3.9mm x 9.9mm x 1.38mm

package body

M Package

Top View

16-Lead TSSOP

4.4mm x 5. 0mm x 0.925mm

package body

G Package

Top View

83905

20-Lead VFQFN

4mm x 4mm x 0.925mm

package body

K Package

Top View

SYNCHRONIZE

BCLK

XTAL_IN

TAL_OUT

ENABLE 1

ENABLE 2

83905

Datasheet

Low Skew, 1:6 Crystal-to-LVCMOS/

LVTTL Fanout Buffer

83905 Datashee t

Pin Descriptions and Characteristics

Table 1. Pin Descriptions

Table 2. Pin Characteristics

Function Table

Table 3. Clock Enable Function Table

Figure 1. Enable Timing Diagram

Name Type Description

XTAL_OUT Output Crystal oscillator interface. XTAL_OUT is the output.

XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input.

ENABLE1, ENABLE2 Input Clock enable. LVCMOS/LVTTL interface levels. See Table 3.

BCLK0, BCLK1, BCL K2,

BCLK3, BCLK4, BCLK5 Output Clock outputs. LVCMOS/LVTTL interface levels.

GND Power Power supply ground.

VDD Power Pow er su pp l y pi n.

VDDO Power Output supply pin.

nc Unused No connect.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4 pF

CPD

Power Dissipation

Capacitance

(per output)

VDDO = 3.465V 19 pF

VDDO = 2.625V 18 pF

VDDO = 2.0V 16 pF

ROUT Output Impedance

VDDO = 3.3V ± 5% 7 

VDDO = 2.5V ± 5% 7 

VDDO = 1.8V ± 0.2V 10 

Control Inputs Outputs

ENABLE 1 ENABLE2 BCLK[0:4] BCLK5

0 0 LOW LOW

0 1 LOW Toggling

1 0 Toggling LOW

1 1 Toggling Toggling

BCLK5

BCLK[0:4]

ENABLE2

ENABLE1

83905 Datashee t

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only. Fun c tional operation of product at these conditions or any conditions beyond those listed in the DC

Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C

Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C

Table 4C. Power Supply DC Characteristics, VDD = VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C

Item Rating

Supply Voltage, VDD 4.6V

Inputs, VI-0.5V to VDD + 0.5V

Outputs, VO-0.5V to VDDO+ 0.5V

Package Thermal Impedan ce, JA

16-Lead SOIC package

16-Lead TSSOP package

20-Lead VFQFN package

78.8C/W (0 mps)

100.3C/W (0 mps)

57.5C/W (0 mps)

Storage Temperature, TSTG -65C to 150C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 3.135 3.3 3.465 V

VDDO Output Supply Voltage 3.135 3.3 3.465 V

IDD Power Supply Current ENABLE [1:2] = 00 10 mA

IDDO Output Supply Current ENABLE [1:2] = 00 5 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 2.375 2.5 2.625 V

VDDO Output Supply Voltage 2.375 2.5 2.625 V

IDD Power Supply Current ENABLE [1:2] = 00 8 mA

IDDO Output Supply Current ENABLE [1:2] = 00 4 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 1.6 1.8 2.0 V

VDDO Output Supply Voltage 1.6 1.8 2.0 V

IDD Power Supply Current ENABLE [1:2] = 00 5 mA

IDDO Output Supply Current ENABLE [1:2] = 00 3 mA

83905 Datashee t

Table 4D. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C

Table 4E. Power Supply DC Characteristics, 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C

Table 4F. Power Supply DC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 3.135 3.3 3.465 V

VDDO Output Supply Voltage 2.375 2.5 2.625 V

IDD Power Supply Current ENABLE [1:2] = 00 10 mA

IDDO Output Supply Current ENABLE [1:2] = 00 4 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 3.135 3.3 3.465 V

VDDO Output Supply Voltage 1.6 1.8 2.0 V

IDD Power Supply Current ENABLE [1:2] = 00 10 mA

IDDO Output Supply Current ENABLE [1:2] = 00 3 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Power Supply Voltage 2.375 2.5 2.625 V

VDDO Output Supply Voltage 1.6 1.8 2.0 V

IDD Power Supply Current ENABLE [1:2] = 00 8 mA

IDDO Output Supply Current ENABLE [1:2] = 00 3 mA

83905 Datashee t

Table 4G. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C

NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.

Table 5. Crystal Characteristics

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input

High Voltage ENABLE1,

ENABLE2

VDD = 3.3V ± 5% 2 VDD + 0.3 V

VDD = 2.5V ± 5% 1.7 VDD + 0.3 V

VDD = 1.8V ± 0.2V 0.65 * VDD VDD + 0.3 V

VIL Input

Low Voltage ENABLE1,

ENABLE2

VDD = 3.3V ± 5% -0.3 0.8 V

VDD = 2.5V ± 5% -0.3 0.7 V

VDD = 1.8V ± 0.2V -0.3 0.35 * VDD V

VOH Output High Voltage

VDDO = 3.3V ± 5%; NOTE 1 2.6 V

VDDO = 2.5V ± 5%; IOH = -1mA 2.0 V

VDDO = 2.5V ± 5%; NOTE 1 1.8 V

VDDO = 1.8V ± 0.2V; NOTE 1 VDDO - 0.3 V

VOL Output Low Voltage; NOTE 1

VDDO = 3.3V ± 5%; NOTE 1 0.5 V

VDDO = 2.5V ± 5%; IOL = 1mA 0.4 V

VDDO = 2.5V ± 5%; NOTE 1 0.45 V

VDDO = 1.8V ± 0.2V; NOTE 1 0.35 V

Parameter Test Conditions Minimum Typical Maximum Units

Mode of Oscillation Fundamental

Frequency 10 40 MHz

Equivalent Series Resistance (ESR) 50 

Shunt Capacitance 7pF

Drive Level 1mW

83905 Datashee t

AC Electrical Characteristics

Table 6A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed ov er the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

All parameters measured at ƒ  fMAX using a crystal input unless noted otherwise.

Terminated at 50 to VDDO/2.

NOTE 1: XTAL_IN can be overdriven by a single-ende d LVCMOS signal. Please refer to Application Information section.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equa l load conditions. Measured at VDDO/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: See phase noise plot.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

Table 6B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed ov er the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

All parameters measured at ƒ  fMAX using a crystal input unless noted otherwise.

Terminated at 50 to VDDO/2.

NOTE 1: XTAL_IN can be overdriven by a single-ende d LVCMOS signal. Please refer to Application Information section.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equa l load conditions. Measured at VDDO/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: See phase noise plot.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency Using External Crystal 10 40 MHz

Using External Clock

Source NOTE 1 DC 100 MHz

tsk(o) Output Skew; NOTE 2, 3 80 ps

tjit(Ø) RMS Phase Jitter (Random); NOTE 4 25MHz, Integration Range:

100Hz – 1MHz 0.13 ps

tR / tFOutput Rise/Fall Time 20% to 80% 200 800 ps

odc Output Duty Cycle 48 52 %

tEN Output Enable

Time; NOTE 5 ENABLE1 4 cycles

ENABLE2 4 cycles

tDIS Output Disable

Time; NOTE 5 ENABLE1 4 cycles

ENABLE2 4 cycles

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency Using External Crystal 10 40 MHz

Using External Clock

Source NOTE 1 DC 100 MHz

tsk(o) Output Skew; NOTE 2, 3 80 ps

tjit RMS Phase Jitter (Random); NOTE 4 25MHz, Integration Range:

100Hz – 1MHz 0.26 ps

tR / tFOutput Rise/Fall Time 20% to 80% 200 800 ps

odc Output Duty Cycle 47 53 %

tEN Output Enable

Time; NOTE 5 ENABLE1 4 cycles

ENABLE2 4 cycles

tDIS Output Disable

Time; NOTE 5 ENABLE1 4 cycles

ENABLE2 4 cycles

83905 Datashee t

Table 6C. AC Characteristics, VDD = VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed ov er the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

All parameters measured at ƒ  fMAX using a crystal input unless noted otherwise.

Terminated at 50 to VDDO/2.

NOTE 1: XTAL_IN can be overdriven by a single-ende d LVCMOS signal. Please refer to Application Information section.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equa l load conditions. Measured at VDDO/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: These parameters are guaranteed by characterization. Not tested in production.

Table 6D. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed ov er the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

All parameters measured at ƒ  fMAX using a crystal input unless noted otherwise.

Terminated at 50 to VDDO/2.

NOTE 1: XTAL_IN can be overdriven by a single-ende d LVCMOS signal. Please refer to Application Information section.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equa l load conditions. Measured at VDDO/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: These parameters are guaranteed by characterization. Not tested in production.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency Using External Crystal 10 40 MHz

Using External Clock

Source NOTE 1 DC 100 MHz

tsk(o) Output Skew; NOTE 2, 3 80 ps

tjit(Ø) RMS Phase Jitter (Random) 25MHz, Integration Range:

100Hz – 1MHz 0.27 ps

tR / tFOutput Rise/Fall Time 20% to 80% 200 900 ps

odc Output Duty Cycle 47 53 %

tEN Output Enable

Time; NOTE 4 ENABLE1 4 cycles

ENABLE2 4 cycles

tDIS Output Disable

Time; NOTE 4 ENABLE1 4 cycles

ENABLE2 4 cycles

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency Using External Crystal 10 40 MHz

Using External Clock

Source NOTE 1 DC 100 MHz

tsk(o) Output Skew; NOTE 2, 3 80 ps

tjit RMS Phase Jitter (Random) 25MHz, Integration Range:

100Hz – 1MHz 0.14 ps

tR / tFOutput Rise/Fall Time 20% to 80% 200 800 ps

odc Output Duty Cycle 48 52 %

tEN Output Enable

Time; NOTE 4 ENABLE1 4 cycles

ENABLE2 4 cycles

tDIS Output Disable

Time; NOTE 4 ENABLE1 4 cycles

ENABLE2 4 cycles

83905 Datashee t

Table 6E. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed ov er the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

All parameters measured at ƒ  fMAX using a crystal input unless noted otherwise.

Terminated at 50 to VDDO/2.

NOTE 1: XTAL_IN can be overdriven by a single-ende d LVCMOS signal. Please refer to Application Information section.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equa l load conditions. Measured at VDDO/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: These parameters are guaranteed by characterization. Not tested in production.

Table 6F. AC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed ov er the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

All parameters measured at ƒ  fMAX using a crystal input unless noted otherwise.

Terminated at 50 to VDDO/2.

NOTE 1: XTAL_IN can be overdriven by a single-ende d LVCMOS signal. Please refer to Application Information section.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equa l load conditions. Measured at VDDO/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: These parameters are guaranteed by characterization. Not tested in production.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency Using External Crystal 10 40 MHz

Using External Clock

Source NOTE 1 DC 100 MHz

tsk(o) Output Skew; NOTE 2, 3 80 ps

tjit RMS Phase Jitter (Random) 25MHz, Integration Range:

100Hz – 1MHz 0.18 ps

tR / tFOutput Rise/Fall Time 20% to 80% 200 900 ps

odc Output Duty Cycle 48 52 %

tEN Output Enable

Time; NOTE 4 ENABLE1 4 cycles

ENABLE2 4 cycles

tDIS Output Disable

Time; NOTE 4 ENABLE1 4 cycles

ENABLE2 4 cycles

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency Usin g External Crystal 10 40 MHz

Using External Clock

Source NOTE 1 DC 100 MHz

tsk(o) Output Skew; NOTE 2, 3 80 ps

tjit RMS Phase Jitter (Random) 25MHz, Integration Rang e:

100Hz – 1MHz 0.19 ps

tR / tFOutput Rise/Fall Time 20% to 80% 200 900 ps

odc Outpu t D ut y Cycl e 4 7 53 %

tEN Output Enable

Time; NOTE 4 ENABLE1 4 cycles

ENABLE2 4 cycles

tDIS Output Disable

Time; NOTE 4 ENABLE1 4 cycles

ENABLE2 4 cycles

83905 Datashee t

Typical Phase Noise at 25MHz (2.5V Core/2.5V Output)

Raw Phase Noise Data

25MHz

RMS Phase Jitter (Random)

100Hz to 1MHz = 0.26ps (typical)

Noise Power(dBc/Hz)

Offset Frequency (Hz)

83905 Datashee t

Parameter Measurement Information

3.3V Core/3.3V LVCMOS Output Load AC Test Circuit

1.8V Core/1.8V LVCMOS Output Load AC Test Circuit

3.3V Core/1.8V LVCMOS Output Load AC Test Circuit

2.5V Core/2.5V LVCMOS Output Load AC Test Circuit

3.3V Core/2.5V LVCMOS Output Load AC Test Circuit

2.5V Core/1.8V LVCMOS Output Load AC Test Circuit

SCOPE

GND

VDD,

-1.65V±5%

1.65V±5%

VDDO

SCOPE

GND

DD,

-0.9V±0.1V

0.9V±0.1V

VDDO

SCOPE

GND

VDD

-0.9V±0.1V

2.4V±0.9V

VDDO

0.9V±0.1V

SCOPE

GND

DD,

-1.25±5%

1.25V±5%

VDDO

SCOPE

GND

VDD

-1.25±5%

2.05V±5%

VDDO

1.25V±5%

SCOPE

GND

VDD

-0.9V±0.1V

1.6V±0.025%

VDDO

0.9V±0.1V

83905 Datashee t

Parameter Measurement Information, continued

Output Skew

Output Rise/Fall Time

Output Duty Cycle/Pulse Width/Period

tsk(b)

VDDO

20%

80% 80%

20%

tRtF

BCLK[0:5]

83905 Datashee t

Application Information

Crystal Input Interface

Figure 2 shows an example of 83905 crystal in terface with a

parallel resonant crystal. The frequency accuracy can be fine

tuned by adjusting the C1 and C2 values. For a parallel crystal with

loading capacitance CL = 18pF, to start with, we suggest C1 =

15pF and C2 = 15pF. These values may be slightly fine tuned

further to optimize the frequency accuracy for different board

layouts. Slightly increasing the C1 and C2 values will slightly

reduce the frequency. Slightly decreas ing the C1 and C2 values

will slightly increase the frequency. For the oscillator circuit below,

R1 can be used, but is not required. For new designs, it is

recommended that R1 not be used.

Figure 2. Crystal Input Int erface

LVCMOS to XTAL Interface

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A gene ral interface diagram is

shown in Figure 3. The XTAL_OUT pin can be left floating. The

input edge rate can be as slow as 10ns. For LVCMOS inputs, it is

recommended that the amplitude be reduced from full swing to half

swing in order to prevent signal interference with the power rail and

to reduce noise. This configuration requires that the output

impedance of the driver (Ro) plus the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination

at the crystal input will attenuate the signal in half. This can be

done in one of two ways. First, R1 and R2 in parallel should equal

the transmission line impedance. For most 50 app lications, R1

and R2 can be 100. This can also be accomplished by removing

R1 and making R2 50. By overdriving th e cr ystal oscillator, the

device will be functional, but note, the device performance is

guaranteed by using a quartz crystal.

Figure 3. General Diagram f or LVCMOS Driver to XTAL Input Interface

XTAL_IN

XTAL_OUT

15p

18pF Parallel Crystal

R1 (optional)

XTAL_IN

XTAL_OUT

Ro Rs

Zo = Ro + Rs

50Ω0.1µf

83905 Datashee t

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package

and the electrical performance, a land pattern must be

incorporated on the Printed Circuit Board (PCB) within the footprint

of the package corresponding to the exposed metal pad or

exposed heat slug on the package, as sh own in Figure 4. The

solderable area on the PCB, as defined by the solder mask, should

be at least the same size/shape as the exposed pad/slug area on

the package to maximize the thermal/electrical performance.

Sufficient clearance should be designed on the PCB between the

outer edges of the land pattern and the inner edges of pad pattern

for the leads to avoid any shorts.

While the land pattern on the PC B provides a means of heat

transfer and electrical grounding from the package to the board

through a solder joint, thermal vias are necessary to effectively

conduct from the surface of the PCB to the ground plane(s). The

land pattern must be connected to ground through these vias. The

vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are

application speci fic and dependent upon the packag e power

dissipation as well as electrical conductivity requirements. Thus,

thermal and electrical analysis and/or testing are recommended to

determine the minimum number needed. Maximum thermal and

electrical performance is achieved when an array of vias is

incorporated in the land pattern. It is recommended to use as many

vias connected to ground as possible. It is also recommended that

the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz

copper via barrel plating. This is desirable to avoid any solder

wicking inside th e via during the soldering process which may

result in voids in solder between the exposed pad/slug and the

thermal land. Precautions should be taken to eliminate any solder

voids between the exposed heat slug and the land pattern. Note:

These recom mendations are to be used as a gu i d el i ne only. For

further information, please refer to the Application Note on the

Surface Mount Assembly of Amkor’s Thermally/Electrically

Enhance Leadframe Base Package, Amkor Technology.

Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k resistor can be used .

Outputs:

LVCMOS Outputs

All unused L VCMOS output can be left floating. There should be no

trace attached.

SOLDERSOLDER PINPIN EXPOSED HEAT SLUG

PIN PAD PIN PADGROUND PLANE LAND PATTERN

(GROUND PAD)

THERMAL VIA

83905 Datashee t

Layout Guideline

Figure 5 shows an example of 83905 application schematic. The

schematic example focuses on functional connections and is not

configuration specific. In this example, the device is operated at

VDD = 3.3V and VDDO = 1.8V. The crystal inputs are loaded with an

18pf load resonant quartz crystal. The tuning capacitors (C1, C2)

are fairly accurate, but minor adjustments might be required. Refer

to the pin description and functional tables in the datasheet to

ensure the logic control inputs are properly set. For the LVCMOS

output drivers, two termination examples are shown in the

schematic. For additional termination examples are shown in the

LVCMOS Termination Application Note.

As with any high speed analog circuitry , the power supply pins are

vulnerable to random noise. To achieve optimum jitter

performance, power supply isolation is required. The 83905

provides separate VDD and VDDO power supplies to isolate any

high switching noise from coupling into the internal oscillator. In

order to achieve the best possible filtering, it is highly

recommended that the 0.1uF capacitors on the device side of the

ferrite beads be placed on the device side of the PCB as close to

the power pins as possible. This is represented by the placement

of these capacitors in the schematic. If space is limited, the ferrite

beads, 10uF and 0.1uF capacitor connected to the board supplies

can be placed on the opposite side of the PCB. If space permits,

place all filter components on the device side of the board.

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices .

The filter performance is desig ned for a wide range of noise

frequencies. This low-pass filter starts to attenuate noise at

approximately 0kHz. If a specific frequency noise component is

known, such as switching power supplies frequencies, it is

recommended that component values be adjusted and if required,

additional filtering be added. Additionally, good general design

practices for power plane voltage stability suggests adding bu lk

capacitance in the local area of all devi ces.

Figure 5. Schematic of Recommended Layout

83905 Datashee t

Power Considerations

This section provides information on power dissipation and jun c tion temperature for the 83905.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 83905 is the sum of the core power plus the analog power plus the power dissipated due to the load.

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core) MAX = VDD_MAX * (IDD + IDDO) = 3.465V *(10mA + 5mA) = 51.9mW

• Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2

Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 7)] = 30.4mA

• Power Dissipation on the ROUT per LVCMOS output

Power (ROUT) = ROUT * (IOUT)2 = 7 * (30.4mA)2 = 6.5mW per output

•Total Power Dissipation on the ROUT

Total Power (ROUT) = 6.5mW * 6 = 39mW

Dynamic Pow er Dissipatio n at 25 MH z

Power (25MHz) = CPD * Frequency * (VDD)2 = 19pF * 25MHz * (3.465V)2 = 5.70mW per output

Total Power (25MHz) = 5.70mW * 6 = 34.2mW

Total Power Dissipation

•Total Power

= Power (core)MAX + Total Power (ROUT) + Total Power (25MHz)

= 51.98mW + 39mW + 34.2mW

= 125.1mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.

The maximum recommended junction temperature is 125°C.

The equation for Tj is as follows: Tj = JA * Pd_total + TA

Tj = Junction Temperature

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow

and a multi-layer board, the appropriate va lue is 100.3°C/W per Table 7 belo w.

Therefore, Tj for an ambient te mperature of 70°C with all outputs switching is:

70°C + 0.125W *100.3°C/W = 82.5°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the

type of board (multi-layer).

Table 7. Thermal Resistance JA for 16-Lead TSSOP, Forced Convection

JA by Velocity

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 100.3°C/W 96.0°C/W 93.9°C/W

83905 Datashee t

Reliability Information

Table 8A. JA vs. Air Flow Table for a 16-Lead TSSOP

Table 8B. JA vs. Air Flow Table for a 16-Lead SOIC

Table 8C. JA vs. Air Flow Table for a 20-Lead VFQFN

Transistor Count

The transistor count for 83905: 339

JA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 100.3°C/W 96.0°C/W 93.9°C/W

JA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 78.8°C/W 71.1°C/W 66.2°C/W

JA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 57.5°C/W 50.3°C/W 45.1°C/W

83905 Datashee t

Package Outline and Package Dimensions

Package Outline - G Suffix for 16-Lead TSSOP

Table 9A. Package Dimensions for 16-Lead TSSOP

Reference Document: JEDEC Publication 95, MO-153

Package Outline - M Suffix for 16-Lead SOIC

Table 9B. Package Dimensions for 16-Lead SOIC

Reference Document: JEDEC Publication 95, MS-012

All Dimensions in Millimeters

Symbol Minimum Maximum

N16

A1.20

A1 0.05 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D4.90 5.10

E6.40 Basic

E1 4.30 4.50

e0.65 Basic

L0.45 0.75

0° 8°

aaa 0.10

All Dimensions in Millimeters

Symbol Minimum Maximum

N16

A1.35 1.75

A1 0.10 0.25

B0.33 0.51

C0.19 0.25

D9.80 10.00

E3.80 4.00

e1.27 Basic

H5.80 6.20

h0.25 0.50

L0.40 1.27

0° 8°

150 il (N B d ) SOIC

83905 Datashee t

Package Outline and Package Dimensions

Package Outline - K Suffix for 20-Lead VFQFN

Table 10. Package Dimensions

Reference Document: JEDEC Publication 95, MO-220

NOTE:

The drawing and dime nsion data originate from IDT package

outline drawing PSC-4170, rev03.

1. Dimensions and tolerances conform to ASME Y14.5M-1994

2. All dimensions are in millimeters. All angles are in degrees.

3. N is the total number of terminals.

4. All specifications comply with JEDEC MO-220.

All Dimensions in Millimeters

Symbol Minimum Nominal Maximum

N20

A0.80 1.00

A1 00.05

A3 0.2 Ref.

b0.20 0.25 0.30

ND & NE5

D & E 4.00 Basic

D2 & E2 1.95 2.25

e0.50 Basic

L0.45 0.55 0.65

83905 Datashee t

Ordering Information

Table 11. Ordering Information

Part/Order Number Marking Package Shipping Packaging Temperature

83905AMLF 83905AML “Lead-Free” 16-Lead SOIC Tube 0C to 70C

83905AMLFT 83905AML “Lead-Free” 16-Lead SOIC Tape & Reel 0C to 70C

83905AGLF 83905AGL “Lead-Free” 16-Lead TSSOP Tube 0C to 70C

83905AGLFT 83905AGL “Lead-Free” 16-Lead TSSOP Tape & Reel 0C to 70C

83905AKLF 3905AL “Lead-Free” 20-Lead VFQFN Tray 0C to 70C

83905AKLFT 3905AL “Le ad-Free” 20-Lead VFQFN Tape & Reel 0C to 70C

83905 Datashee t

Revision History Sheet

Rev Table Page Description of Change Date

A 2 Added Enable Timing Diagram. 3/28/05

BT6A - T6F 1

5 - 7

Features Section - added RMS Phase Jitter bullet.

AC Characteristics Tables - added RMS Phase Jitter specs.

Added Phase Noise Plot. 4/8/05

B T9 14 Ordering Information Table - added TSSOP, non -LF part number. 4/25/05

B11

12 Added Crystal Input Interface in Application Section.

Added Schematic layout. 5/16/05

Absolute Maximum Ratings - corrected 20-Lead VFQFN package Thermal

Impedance.

Added Recommendations for Unused Input and Output Pins.

Corrected Theta JA Air Flow Table for 20-Lead VFQFN.

10/2/06

BT9

Added LVCMOS to XTAL Interface section.

Added Thermal Release Path section.

AC Characteristics Table - added lead-free marking for 20-Lead VFQFN package. 7/9/07

BT7B - T7C

Absolute Maximum Ratings - updated TSSOP and VFQFN Thermal Impedance.

Updated Thermal Release Path section.

Updated TSSOP and VFQFN Th ermal Impedance.

Added note to VFQFN Package Outline.

1/24/08

B15 Added Power Considerations section.

Converted datasheet format. 7/20/09

B T10 19 Removed leaded order-able parts from Ordering Information table 11/14/12

T6D

T9A

T11

1, 15

Deleted HiPerClockS references.

Features, last bullet: updated packaging note.

Mixed AC Characteristics Table - corrected typo, switched Output Rise/Fall Time

spec with Output Duty Cycle spec.

Replaced schematic.

16-Lead TSSOP Package Table - corrected dimensi on A1 Minimum = 0.05.

Updated VFQFN package outline page.

Ordering Information table - deleted Lead-free note, and quantit y from Tape and

Reel.

4/18/13

C 1 Pin Assignment: Corrected 20-Lead illustration cut-off text 2/27/14

T6A - T6F

T10

6 - 8

Pin Assignment, 20-Lead VFQFN: removed the Epad dimensio ns.

Changed NOTE 1to XTAL_IN can be overdriven by a single-ended LVCMOS signal.

Please refer to Application Information section.

Deleted 3.3V Phase Noise Plot

Deleted RMS Phase Jitter graph.

Modified dimensions to reflect tightened tolerance s .

Updated contact information.

8/6/14

D2 Figure 1 corrected.

Updated datasheet header/footer.

Deleted “ICS” prefix from part number throughout the datasheet 9/27/16

83905 Datashee t

DISCLAIMER Integrated Device Technology, Inc. (IDT ) res erves the right to modify the products and/or specifications desc rib ed here i n at any time, without notice, at IDT's sole discretion. Performance spec-

ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information

contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied

warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of

IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-

sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are tr ademarks or registered trademarks of IDT and its subsidiaries in the United States and other coun tries. Other trade marks used herein are the pr operty

Tech Support

www.IDT.com/go/support

Sales

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA