LTM9011-14/ LTM9010-14/LTM9009-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Octal ADCs FEATURES n n n n n n n n n n n n DESCRIPTION 8-Channel Simultaneous Sampling ADC 73.1dB SNR 88dB SFDR Low Power: 140mW/113mW/94mW per Channel Single 1.8V Supply Serial LVDS Outputs: 1 or 2 Bits per Channel Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full Power Bandwidth S/H Shutdown and Nap Modes Serial SPI Port for Configuration Internal Bypass Capacitance, No External Components 140-Pin (11.25mm x 9mm) BGA Package The LTM(R)9011-14/LTM9010-14/LTM9009-14 are 8-channel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. AC performance includes 73.1dB SNR and 88dB spurious free dynamic range (SFDR). Low power consumption per channel reduces heat in high channel count applications. Integrated bypass capacitance and flow-through pinout reduces overall board space requirements. DC specs include 1LSB INL (typ), 0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). APPLICATIONS n n n n n n Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multichannel Data Acquisition Nondestructive Testing The ENC+ and ENC- inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION 1.8V VDD OUT1A 0 OUT1B -10 14-BIT ADC CORE OUT2A S/H ENCODE INPUT *** DATA SERIALIZER -30 OUT2B *** S/H SERIALIZED LVDS OUTPUTS OUT8A 14-BIT ADC CORE OUT8B DATA CLOCK OUT PLL FRAME GND GND AMPLITUDE (dBFS) CHANNEL 8 ANALOG INPUT 14-BIT ADC CORE -20 *** CHANNEL 2 ANALOG INPUT S/H *** CHANNEL 1 ANALOG INPUT LTM9011-14, 125Msps, 2-Tone FFT, fIN = 70MHz and 75MHz 1.8V OVDD -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 FREQUENCY (MHz) 50 60 9009101114 TA01b 9009101114 TA01 Rev D Document Feedback For more information www.analog.com 1 LTM9011-14/ LTM9010-14/LTM9009-14 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) Supply Voltages VDD, OVDD................................................ -0.3V to 2V Analog Input Voltage (AIN+, AIN -, PAR/SER, SENSE) (Note 3) .......... -0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC-, CS, SDI, SCK) (Note 4) .................................... -0.3V to 3.9V SDO (Note 4)............................................. -0.3V to 3.9V Digital Output Voltage ................ -0.3V to (OVDD + 0.3V) Operating Temperature Range LTM9011C, LTM9010C, LTM9009C ......... 0C to 70C LTM9011I, LTM9010I, LTM9009I .........-40C to 85C Storage Temperature Range .................. -55C to 125C TOP VIEW A B C D E F G H J K L M N P 1 2 3 4 5 6 7 8 9 10 BGA PACKAGE 140-LEAD (11.25mm x 9.00mm x 2.72mm) TJMAX = 150C, JA = 30C/W, JC = 25C/W, JB = 15C/W, JCbottom = 12C/W ORDER INFORMATION http://www.linear.com/product/LTM9011-14#orderinfo LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION LTM9011CY-14#PBF LTM9011CY-14#PBF LTM9011Y14 140-Lead (11.25mm x 9mm x 2.72mm) BGA 0C to 70C TEMPERATURE RANGE LTM9011IY-14#PBF LTM9011IY-14#PBF LTM9011Y14 140-Lead (11.25mm x 9mm x 2.72mm) BGA -40C to 85C LTM9010CY-14#PBF LTM9010CY-14#PBF LTM9010Y14 140-Lead (11.25mm x 9mm x 2.72mm) BGA 0C to 70C LTM9010IY-14#PBF LTM9010IY-14#PBF LTM9010Y14 140-Lead (11.25mm x 9mm x 2.72mm) BGA -40C to 85C LTM9009CY-14#PBF LTM9009CY-14#PBF LTM9009Y14 140-Lead (11.25mm x 9mm x 2.72mm) BGA 0C to 70C LTM9009IY-14#PBF LTM9009IY-14#PBF LTM9009Y14 140-Lead (11.25mm x 9mm x 2.72mm) BGA -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev D 2 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) LTM9011-14 PARAMETER CONDITIONS Resolution (No Missing Codes) MIN l LTM9010-14 TYP MAX MIN 14 LTM9009-14 TYP MAX MIN 14 TYP MAX UNITS 14 Bits Integral Linearity Error Differential Analog Input (Note 6) l -4.1 1.2 4.1 -3.25 1 3.25 -2.75 1 2.75 LSB Differential Linearity Error Differential Analog Input l -0.9 0.3 0.9 -0.8 0.3 0.8 -0.8 0.3 0.8 LSB Offset Error (Note 7) l -12 3 12 -12 3 12 -12 3 12 mV Gain Error Internal Reference External Reference -2.6 -1.3 -1.3 -2.6 -1.3 -1.3 -2.6 -1.3 -1.3 0 %FS %FS l Offset Drift 0 0 20 20 20 V/C Full-Scale Drift Internal Reference External Reference 35 25 35 25 35 25 ppm/C ppm/C Gain Matching External Reference 0.2 0.2 0.2 %FS 3 3 3 mV External Reference 1.2 1.2 1.2 LSBRMS Offset Matching Transition Noise ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(CM) Analog Input Range (AIN+ - AIN-) Analog Input Common Mode (AIN+ + AIN-)/2 VSENSE External Voltage Reference Applied to SENSE External Reference Mode IINCM Analog Input Common Mode Current Per Pin, 125Msps Per Pin, 105Msps Per Pin, 80Msps IIN1 Analog Input Leakage Current 0 < AIN+, AIN- < VDD, No Encode l -1 1 A IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l -3 3 A IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l -6 6 A tAP Sample-and-Hold Acquisition Delay Time 0 tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 CMRR Analog Input Common Mode Rejection Ratio BW-3B Full-Power Bandwidth VIN 1.7V < VDD < 1.9V l Differential Analog Input (Note 8) l VCM - 100mV 1 to 2 VCM VCM + 100mV VP-P V l 0.625 1.250 1.300 V 155 130 100 Figure 6 Test Circuit A A A ns psRMS 80 dB 800 MHz Rev D For more information www.analog.com 3 LTM9011-14/ LTM9010-14/LTM9009-14 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 5) LTM9011-14 SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input 70MHz Input 140MHz Input SFDR S/(N+D) MAX LTM9010-14 MAX LTM9009-14 MIN TYP MIN TYP MIN TYP l 70.8 73.1 73 72.6 70.6 73 72.9 72.6 69.7 73 72.9 72.5 MAX UNITS dBFS dBFS dBFS Spurious Free Dynamic Range 5MHz Input 2nd or 3rd Harmonic 70MHz Input 140MHz Input l 69 88 85 82 71 88 85 82 74 88 85 82 dBFS dBFS dBFS Spurious Free Dynamic Range 5MHz Input 4th Harmonic or Higher 70MHz Input 140MHz Input l 81 90 90 90 81 90 90 90 82 90 90 90 dBFS dBFS dBFS l 68.4 73 72.6 72 69.7 73 72.6 72 69.6 72.9 72.6 72 dBFS dBFS dBFS Signal-to-Noise Plus Distortion Ratio 5MHz Input 70MHz Input 140MHz Input Crosstalk, Near Channel 10MHz Input (Note 12) -90 -90 -90 dBc Crosstalk, Far Channel 10MHz Input (Note 12) -105 -105 -105 dBc INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 5) PARAMETER CONDITIONS VCM Output Voltage IOUT = 0 MIN TYP MAX 0.5 * VDD - 25mV 0.5 * VDD 0.5 * VDD + 25mV VCM Output Temperature Drift 25 VCM Output Resistance -600A < IOUT < 1mA VREF Output Voltage IOUT = 0 VREF Output Temperature Drift 1.250 25 VREF Output Resistance -400A < IOUT < 1mA VREF Line Regulation 1.7V < VDD < 1.9V 7 0.6 V ppm/C 4 1.225 UNITS 1.275 V ppm/C mV/V Rev D 4 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC- ) Differential Encode Mode (ENC- Not Tied to GND) VID Differential Input Voltage (Note 8) l 0.2 VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 l 0.2 VIN Input Voltage Range ENC+, ENC- to GND RIN Input Resistance (See Figure 10) CIN Input Capacitance V 1.2 1.6 V V 3.6 V 10 k 3.5 pF Single-Ended Encode Mode (ENC- Tied to GND) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level Input Voltage VDD = 1.8V l VIN Input Voltage Range ENC+ to GND l RIN Input Resistance (See Figure 11) CIN Input Capacitance 1.2 V 0.6 0 3.6 V V 30 k 3.5 pF DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level Input Voltage VDD = 1.8V l IIN Input Current VIN = 0V to 3.6V l CIN Input Capacitance 1.3 V -10 0.6 V 10 A 3 pF 200 SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used) ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V IOH Logic High Output Leakage Current SDO = 0V to 3.6V COUT Output Capacitance l -10 10 3 A pF DIGITAL DATA OUTPUTS VOD Differential Output Voltage 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode l l 247 125 350 175 454 250 VOS Common Mode Output Voltage 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode l l 1.125 1.125 1.250 1.250 1.375 1.375 RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 mV mV V V Rev D For more information www.analog.com 5 LTM9011-14/ LTM9010-14/LTM9009-14 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9) LTM9011-14 SYMBOL PARAMETER LTM9009-14 MIN TYP MAX MIN TYP MAX MIN TYP (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V Analog Supply Current Sine Wave Input l 582 632 476 508 395 450 mA IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 54 98 62 108 52 96 62 106 50 94 58 104 mA mA PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 1145 1224 1249 1332 950 1030 1026 1105 801 880 914 997 mW mW PSLEEP Sleep Mode Power 2 2 2 mW PNAP Nap Mode Power 170 170 170 mW PDIFFCLK Power Decrease With Single-Ended Encode Mode Enabled (No Decrease for Sleep Mode) 40 40 40 mW VDD Analog Supply Voltage OVDD IVDD CONDITIONS LTM9010-14 MAX UNITS 1.9 V TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) LTM9011-14 SYMBOL PARAMETER CONDITIONS MIN fS Sampling Frequency (Notes 10,11) l 5 tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l tAP Sample-and-Hold Acquisition Delay Time SYMBOL PARAMETER LTM9010-14 TYP MAX MIN 125 5 3.8 2 4 4 100 100 3.8 2 4 4 100 100 LTM9009-14 TYP MAX 105 5 4.52 2 4.76 4.76 100 100 4.52 2 4.76 4.76 100 100 0 MIN TYP MAX 80 MHz 5.93 2 6.25 6.25 100 100 ns ns 5.93 2 6.25 6.25 100 100 ns ns 0 CONDITIONS MIN 0 TYP UNITS ns MAX UNITS Digital Data Outputs (RTERM = 100 Differential, CL = 2pF to GND on Each Output) 1/(8 * fS) 1/(7 * fS) 1/(6 * fS) 1/(16 * fS) 1/(14 * fS) 1/(12 * fS) tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 2-Lanes, 14-Bit Serialization 2-Lanes, 12-Bit Serialization 1-Lane, 16-Bit Serialization 1-Lane, 14-Bit Serialization 1-Lane, 12-Bit Serialization tFRAME FR to DCO Delay (Note 8) l tDATA DATA to DCO Delay (Note 8) l tPD Propagation Delay (Note 8) l tR Output Rise Time tF s s s s s s 0.35 * tSER 0.5 * tSER 0.65 * tSER s 0.35 * tSER 0.5 * tSER 0.65 * tSER s 0.7n + 2 * tSER 1.1n + 2 * tSER 1.5n + 2 * tSER s Data, DCO, FR, 20% to 80% 0.17 ns Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns Pipeline Latency 60 psP-P 6 Cycles Rev D 6 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SPI Port Timing (Note 8) tSCK SCK Period tS Write Mode Read Back Mode, CSDO = 20pF, RPULLUP = 2k l l 40 250 ns ns CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Read Back Mode, CSDO = 20pF, RPULLUP = 2k Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTM9011), 105MHz (LTM9010), or 80MHz (LTM9009), 2-lane output mode, differential ENC+/ ENC- = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. l 125 ns Note 7: Offset error is the offset voltage measured from -0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2's complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTM9011), 105MHz (LTM9010), or 80MHz (LTM9009), 2-lane output mode, differential ENC+/ENC- = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. The supply current and power dissipation specifications are totals for the entire device, not per channel. Note 10: Recommended operating conditions. Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps so tSER must be greater than or equal to 1ns. Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.7 to Ch.8. Far-channel crosstalk refers to Ch.1 to Ch.7, Ch.1 to Ch.8, Ch.2 to Ch.7, and Ch.2 to Ch.8. Rev D For more information www.analog.com 7 LTM9011-14/ LTM9010-14/LTM9009-14 TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization* tAP ANALOG INPUT N+1 N tENCH ENC- tENCL ENC+ tSER DCO- DCO+ tFRAME FR- FR+ tDATA tSER tPD OUT#A- OUT#A+ OUT#B- OUT#B+ tSER D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 9009101114 TD01 *SEE THE DIGITAL OUTPUTS SECTION 2-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+2 N tENCH ENC- N+1 tENCL ENC+ tSER DCO- DCO+ tFRAME FR- FR+ OUT#A- OUT#A+ OUT#B- OUT#B+ tDATA tSER tPD tSER D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 9009101114 TD02 NOTE THAT IN THIS MODE FR+/FR- HAS TWO TIMES THE PERIOD OF ENC+/ENC- Rev D 8 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 TIMING DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N N+1 tENCH ENC- tENCL ENC+ tSER DCO- DCO+ FR+ tFRAME tDATA tPD tSER FR- OUT#A- OUT#A+ OUT#B- OUT#B+ tSER D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 9009101114 TD03 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC- tENCL ENC+ tSER DCO- DCO+ tFRAME FR- FR+ OUT#A- OUT#A+ tDATA tSER tPD D1 D0 SAMPLE N-6 0 tSER 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 SAMPLE N-5 D1 D0 0 0 D13 D12 D11 D10 SAMPLE N-4 9009101114 TD04 OUT#B+, OUT#B- ARE DISABLED Rev D For more information www.analog.com 9 LTM9011-14/ LTM9010-14/LTM9009-14 TIMING DIAGRAMS 1-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC- tENCL ENC+ tSER DCO- DCO+ tFRAME FR- FR+ OUT#A- OUT#A+ tDATA tSER tPD D3 D2 D1 tSER D0 D13 D12 D11 D10 D9 SAMPLE N-6 D8 D7 D6 D5 D4 D3 D2 SAMPLE N-5 D1 D0 D13 D12 D11 D10 SAMPLE N-4 9009101114 TD06 OUT#B+, OUT#B- ARE DISABLED 1-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N+1 N tENCH ENC- tENCL ENC+ tSER DCO- DCO+ tFRAME FR- FR+ OUT#A- OUT#A+ tDATA tSER tPD D5 D4 SAMPLE N-6 D3 tSER D2 D13 D12 D11 D10 D9 D8 D7 D6 D5 SAMPLE N-5 D4 D3 D2 D13 D12 D11 SAMPLE N-4 9009101114 TD07 OUT#B+, OUT#B- ARE DISABLED Rev D 10 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 TIMING DIAGRAMS SPI Port Timing (Readback Mode) tDS tS tDH tSCK tH CS SCK tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 HIGH IMPEDANCE XX D6 XX D5 XX D4 XX D3 XX D2 XX XX D1 D0 SPI Port Timing (Write Mode) CS SCK SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 9009101114 TD08 HIGH IMPEDANCE Rev D For more information www.analog.com 11 LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9011-14: Integral Nonlinearity (INL) LTM9011-14: Differential Nonlinearity (DNL) 2.0 1.0 0 1.5 0.8 -10 0 -0.5 -1.0 0 -0.2 -0.4 0 4096 8192 12288 OUTPUT CODE -1.0 16384 0 4096 9009101114 G01 LTM9011-14: 8k Point FFT, fIN = 30MHz, -1dBFS, 125Msps 0 -40 -50 -60 -70 -80 -90 -100 -0.8 8192 12288 OUTPUT CODE 16384 -110 -120 LTM9011-14: 8k Point FFT, fIN = 70MHz, -1dBFS, 125Msps 0 -10 -20 -20 -20 -30 -30 -30 -50 -60 -70 -80 AMPLITUDE (dBFS) -10 -40 -40 -50 -60 -70 -80 -110 -120 60 0 10 20 30 40 FREQUENCY (MHz) 50 60 LTM9011-14: 8k Point FFT, fIN = 140MHz, -1dBFS, 125Msps -80 -110 -120 9009101114 G04 0 10 9009101114 G05 LTM9011-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, -7dBFS per Tone, 125Msps 60 9009101114 G03 -70 -110 -120 50 50 -60 -90 -100 20 30 40 FREQUENCY (MHz) 20 30 40 FREQUENCY (MHz) -40 -90 -100 10 10 -50 -90 -100 0 0 9009101114 G02 -10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0.2 -0.6 -1.5 0 -30 0.4 AMPLITUDE (dBFS) DNL ERROR (LSB) INL ERROR (LSB) 0.5 -2.0 -20 0.6 1.0 LTM9011-14: 8k Point FFT, fIN = 5MHz, -1dBFS, 125Msps 20 30 40 FREQUENCY (MHz) 50 60 9009101114 G06 LTM9011-14: Shorted Input Histogram 0 6000 -10 -20 5000 -40 4000 -50 COUNT AMPLITUDE (dBFS) -30 -60 -70 3000 -80 2000 -90 -100 1000 -110 -120 0 10 20 30 40 FREQUENCY (MHz) 50 60 0 8178 9009101114 G07 8180 8182 8184 OUTPUT CODE 8186 9009101114 G08 Rev D 12 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9011-14: SNR vs Input Frequency, -1dBFS, 2V Range, 125Msps LTM9011-14: SFDR vs Input Frequency, -1dBFS, 2V Range, 125Msps 95 74 110 90 90 SFDR (dBFS) 71 70 69 SFDR (dBc AND dBFS) 72 85 80 75 68 67 80 70 dBc 60 50 40 30 20 70 10 100 150 200 250 300 INPUT FREQUENCY (MHz) 65 350 0 100 150 200 250 300 INPUT FREQUENCY (MHz) 50 80 0 9009101114 G11 LTM9011-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, -1dBFS LTM9011-14: SNR vs Input Level, fIN = 70MHz, 2V Range, 125Msps 580 dBFS 70 560 60 540 dBc IVDD (mA) 50 40 30 520 500 480 20 460 10 440 0 -60 -50 -40 -30 -20 INPUT LEVEL (dBFS) -10 420 0 0 25 9009101114 G12 50 75 100 SAMPLE RATE (Msps) 125 9009101114 G13 IOVDD vs Sample Rate, 5MHz Sine Wave Input, -1dBFS 74 100 2-LANE, 3.5mA LTM9011-14: SNR vs SENSE, fIN = 5MHz, -1dBFS 73 80 72 1-LANE, 3.5mA 60 2-LANE, 1.75mA 40 71 70 69 68 1-LANE, 1.75mA 20 0 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 350 9009101114 G10 9009101114 G09 SNR (dBFS) 50 SNR (dBc AND dBFS) 0 IOVDD (mA) SNR (dBFS) dBFS 100 73 66 LTM9011-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps 67 0 25 50 75 100 SAMPLE RATE (Msps) 125 66 0.6 9009101114 G14 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 9009101114 G15 Rev D For more information www.analog.com 13 LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9010-14: Integral Nonlinearity (INL) LTM9010-14: Differential Nonlinearity (DNL) 2.0 1.0 0 1.5 0.8 -10 0 -0.5 -1.0 0 -0.2 -0.4 0 4096 8192 12288 OUTPUT CODE -1.0 16384 -40 -50 -60 -70 -80 -90 -100 -0.8 0 4096 9009101114 G16 8192 12288 OUTPUT CODE 16384 -110 -120 0 -10 -20 -20 -20 -30 -30 -30 -60 -70 -80 AMPLITUDE (dBFS) 0 -10 -50 -40 -50 -60 -70 -80 -70 -80 -110 -120 -110 -120 -110 -120 50 0 10 9009101114 G19 20 30 40 FREQUENCY (MHz) LTM9010-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, -7dBFS per Tone, 105Msps 9009101114 G18 -60 -90 -100 20 30 40 FREQUENCY (MHz) 50 -40 -90 -100 10 20 30 40 FREQUENCY (MHz) -50 -90 -100 0 10 LTM9010-14: 8k Point FFT, fIN = 140MHz, -1dBFS, 105Msps -10 -40 0 9009101114 G17 LTM9010-14: 8k Point FFT, fIN = 70MHz, -1dBFS, 105Msps LTM9010-14: 8k Point FFT, fIN = 30MHz, -1dBFS, 105Msps AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0.2 -0.6 -1.5 0 -30 0.4 AMPLITUDE (dBFS) DNL ERROR (LSB) INL ERROR (LSB) 0.5 -2.0 -20 0.6 1.0 LTM9010-14: 8k Point FFT, fIN = 5MHz, -1dBFS, 105Msps 50 0 10 9009101114 G20 20 30 40 FREQUENCY (MHz) 50 9009101114 G21 LTM9010-14: Shorted Input Histogram 0 6000 -10 -20 5000 -40 4000 -50 COUNT AMPLITUDE (dBFS) -30 -60 -70 3000 -80 2000 -90 -100 1000 -110 -120 0 10 20 30 40 FREQUENCY (MHz) 50 0 8195 9009101114 G22 8197 8199 8201 OUTPUT CODE 8203 9009101114 G23 Rev D 14 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9010-14: SNR vs Input Frequency, -1dBFS, 2V Range, 105Msps LTM9010-14: SFDR vs Input Frequency, -1dBFS, 2V Range, 105Msps 74 95 110 90 90 SFDR (dBFS) 71 70 69 SFDR (dBc AND dBFS) 72 85 80 75 68 67 80 70 dBc 60 50 40 30 20 70 10 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 65 0 50 9009101114 G24 100 150 200 250 300 INPUT FREQUENCY (MHz) LTM9010-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, -1dBFS 0 -80 -70 -60 -50 -40 -30 -20 -10 0 INPUT LEVEL (dBFS) 9009101114 G26 LTM9010-14: SNR vs SENSE, fIN = 5MHz, -1dBFS 460 74 440 73 72 420 400 380 360 71 70 69 68 340 320 350 9009101114 G25 SNR (dBFS) 0 IVDD (mA) SNR (dBFS) dBFS 100 73 66 LTM9010-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 105Msps 67 0 25 50 75 SAMPLE RATE (Msps) 100 66 0.6 0.7 9009101114 G27 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 9009101114 G28 Rev D For more information www.analog.com 15 LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9009-14: Integral Nonlinearity (INL) LTM9009-14: Differential Nonlinearity (DNL) 2.0 1.0 0 1.5 0.8 -10 0 -0.5 -1.0 0.2 0 -0.2 -0.4 -0.8 0 4096 8192 12288 OUTPUT CODE -1.0 16384 0 4096 9009101114 G29 LTM9009-14: 8k Point FFT, fIN = 30MHz, -1dBFS, 80Msps -40 -50 -60 -70 -80 -90 -100 -0.6 -1.5 8192 12288 OUTPUT CODE 16384 -110 -120 0 0 -10 -10 -20 -20 -20 -30 -30 -30 -60 -70 -80 AMPLITUDE (dBFS) 0 -50 -40 -50 -60 -70 -80 -60 -70 -80 -90 -100 -110 -120 -110 -120 -110 -120 20 30 FREQUENCY (MHz) 40 0 10 9009101114 G32 20 30 FREQUENCY (MHz) 40 0 0 10 9009101114 G33 LTM9009-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, -7dBFS per Tone, 80Msps 40 9009101114 G31 -40 -90 -100 10 20 30 FREQUENCY (MHz) -50 -90 -100 0 10 LTM9009-14: 8k Point FFT, fIN = 140MHz, -1dBFS, 80Msps -10 -40 0 9009101114 G30 LTM9009-14: 8k Point FFT, fIN = 70MHz, -1dBFS, 80Msps AMPLITUDE (dBFS) AMPLITUDE (dBFS) -30 0.4 AMPLITUDE (dBFS) DNL ERROR (LSB) INL ERROR (LSB) 0.5 -2.0 -20 0.6 1.0 LTM9009-14: 8k Point FFT, fIN = 5MHz, -1dBFS, 80Msps 20 30 FREQUENCY (MHz) 40 9009101114 G34 LTM9009-14: Shorted Input Histogram 6000 -10 -20 5000 -40 4000 -50 COUNT AMPLITUDE (dBFS) -30 -60 3000 -70 -80 2000 -90 -100 1000 -110 -120 0 10 20 30 FREQUENCY (MHz) 40 0 8184 9009101114 G35 8186 8188 8190 OUTPUT CODE 8192 9009101114 G36 Rev D 16 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL PERFORMANCE CHARACTERISTICS LTM9009-14: SNR vs Input Frequency, -1dBFS, 2V Range, 80Msps LTM9009-14: SFDR vs Input Frequency, -1dBFS, 2V Range, 80Msps 74 LTM9009-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 80Msps 95 73 110 100 90 70 69 SFDR (dBc AND dBFS) SFDR (dBFS) SNR (dBFS) 71 85 80 75 68 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) dBc 60 50 40 30 0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 350 9009101114 G38 LTM9009-14: IVDD vs Sample Rate, 5MHz Sine Wave Input, -1dBFS 380 74 LTM9009-14: SNR vs SENSE, fIN = 5MHz, -1dBFS DCO Cycle-Cycle Jitter vs Serial Data Rate 350 PEAK-TO-PEAK JITTER (ps) 300 SNR (dBFS) 72 340 320 71 70 69 68 300 20 40 60 SAMPLE RATE (Msps) 80 9009101114 G40 66 250 200 150 100 50 67 0 0 9009101114 G39 73 360 IVDD (mA) 70 10 65 9009101114 G37 280 80 20 70 67 dBFS 90 72 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 9009101114 G41 0 0 200 400 600 800 SERIAL DATA RATE (Mbps) 1000 9009101114 G42 Rev D For more information www.analog.com 17 LTM9011-14/ LTM9010-14/LTM9009-14 PIN FUNCTIONS AIN1+ (B2): Channel 1 Positive Differential Analog Input. AIN8+ (N1): Channel 8 Positive Differential Analog Input. AIN1- (B1): Channel 1 Negative Differential Analog Input. AIN8- (N2): Channel 8 Negative Differential Analog Input VCM14 (B3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 1 and 4. VCM is internally bypassed to ground with a 0.1F ceramic capacitor. No external capacitance is required. VDD (D3, D4, E3, E4, K3, K4, L3, L4): 1.8V Analog Power Supply. VDD is internally bypassed to ground with 0.1F ceramic capacitors. AIN2+ (C2): Channel 2 Positive Differential Analog Input. AIN2- (C1): Channel 2 Negative Differential Analog Input. AIN3+ (E2): Channel 3 Positive Differential Analog Input. AIN3- (E1): Channel 3 Negative Differential Analog Input. VCM23 (F3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 2 and 3. VCM is internally bypassed to ground with a 0.1F ceramic capacitor. No external capacitance is required. AIN4+ (G2): Channel 4 Positive Differential Analog Input. AIN4- (G1): Channel 4 Negative Differential Analog Input. AIN5+ (H1): Channel 5 Positive Differential Analog Input. AIN5- (H2): Channel 5 Negative Differential Analog Input. VCM67 (J3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 6 and 7. VCM is internally bypassed to ground with a 0.1F ceramic capacitor. No external capacitance is required. AIN6+ (K1): Channel 6 Positive Differential Analog Input. AIN6- (K2): Channel 6 Negative Differential Analog Input. AIN7+ (M1): Channel 7 Positive Differential Analog Input. AIN7- (M2): Channel 7 Negative Differential Analog Input. VCM58 (N3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channels 5 and 8. VCM is internally bypassed to ground with a 0.1F ceramic capacitor. No external capacitance is required. ENC+ (P5): Encode Input. Conversion starts on the rising edge. ENC- (P6): Encode Complement Input. Conversion starts on the falling edge. CSA (L5): In serial programming mode, (PAR/SER = 0V), CSA is the serial interface chip select input for registers controlling channels 1, 4, 5 and 8. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. CSB (M5): In serial programming mode, (PAR/SER = 0V), CSB is the serial interface chip select input for registers controlling channels 2, 3, 6 and 7. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In parallel programming mode (PAR/SER = VDD), CS selects 2-lane or 1-lane output mode. CS can be driven with 1.8V to 3.3V logic. SCK (L6): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In parallel programming mode (PAR/SER = VDD), SCK selects 3.5mA or 1.75mA LVDS output currents. SCK can be driven with 1.8V to 3.3V logic. SDI (M6): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In parallel programming mode (PAR/SER = VDD), SDI can be used to power down the part. SDI can be driven with 1.8V to 3.3V logic. GND (See Pin Configuration Table): ADC Power Ground. Use multiple vias close to pins. Rev D 18 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 PIN FUNCTIONS OVDD (G9, G10): Output Driver Supply. OVDD is internally bypassed to ground with a 0.1F ceramic capacitor. SDOA (E6): In serial programming mode, (PAR/SER = 0V), SDOA is the optional serial interface data output for registers controlling channels 1, 4, 5 and 8. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain N-channel MOSFET output that requires an external 2k pull-up resistor from 1.8V to 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In parallel programming mode (PAR/SER = VDD), SDOA is an input that enables internal 100 termination resistors on the digital outputs of channels 1, 4, 5 and 8. When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. SDOB (D6): Serial Data Output Pin for Channels 2, 3, 6 and 7. See description for SDOA. PAR/SER (A7): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CSA, CSB, SCK, SDI, SDOA and SDOB become a serial interface that control the A/D operating modes. Connect to VDD to enable parallel programming mode where CSA, CSB, SCK, SDI, SDOA and SDOB become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/ SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. VREF (B6): Reference Voltage Output. VREF is internally bypassed to ground with a 1F ceramic capacitor, nominally 1.25V. SENSE (C5): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a 1V input range. Connecting SENSE to ground selects the internal reference and a 0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of 0.8 * VSENSE. SENSE is internally bypassed to ground with a 0.1F ceramic capacitor. LVDS Outputs All pins in this section are differential LVDS outputs. The output current level is programmable. There is an optional internal 100 termination resistor between the pins of each LVDS output pair. OUT1A-/OUT1A+, OUT1B-/OUT1B+ (E7/E8, C8/D8): Serial Data Outputs for Channel 1. In 1-lane output mode only OUT1A-/OUT1A+ are used. OUT2A-/OUT2A+, OUT2B-/OUT2B+ (B8/A8, D7/C7): Serial Data Outputs for Channel 2. In 1-lane output mode only OUT2A-/OUT2A+ are used. OUT3A-/OUT3A+, OUT3B-/OUT3B+ (D10/D9, E10/E9): Serial Data Outputs for Channel 3. In 1-lane output mode only OUT3A-/OUT3A+ are used. OUT4A-/OUT4A+, OUT4B-/OUT4B+ (C9/C10, F7/F8): Serial Data Outputs for Channel 4. In 1-lane output mode only OUT4A-/OUT4A+ are used. OUT5A-/OUT5A+, OUT5B-/OUT5B+ (J8/J7, K8/K7): Serial Data Outputs for Channel 5. In 1-lane output mode only OUT5A-/OUT5A+ are used. OUT6A-/OUT6A+, OUT6B-/OUT6B+ (K9/K10, L9/L10): Serial Data Outputs for Channel 6. In 1-lane output mode only OUT6A-/OUT6A+ are used. OUT7A-/OUT7A+, OUT7B-/OUT7B+ (M7/L7, P8/N8): Serial Data Outputs for Channel 7. In 1-lane output mode only OUT7A-/OUT7A+ are used. OUT8A-/OUT8A+, OUT8B-/OUT8B+ (L8/M8, M10/M9): Serial Data Outputs for Channel 8. In 1-lane output mode only OUT8A-/OUT8A+ are used. FRA-/FRA+ (H7/H8): Frame Start Outputs for Channels 1, 4, 5 and 8. FRB-/FRB+ (J9/J10): Frame Start Outputs for Channels 2, 3, 6 and 7. DCOA-/DCOA+ (G8/G7): Data Clock Outputs for Channels 1, 4, 5 and 8. DCOB-/DCOB+ (F10, F9): Data Clock Outputs for Channels 2, 3, 6 and 7. Rev D For more information www.analog.com 19 LTM9011-14/ LTM9010-14/LTM9009-14 PIN CONFIGURATION TABLE 1 2 3 4 5 6 7 8 9 10 A GND GND GND GND GND GND PAR/SER OUT2A+ GND GND B AIN1- AIN1+ VCM14 GND GND VREF GND OUT2A- GND GND C AIN2 - + AIN2 GND GND SENSE GND OUT2B+ OUT1B- OUT4A- OUT4A+ D GND GND VDD VDD GND SDOB OUT2B- OUT1B+ OUT3A+ OUT3A- E AIN3- AIN3+ VDD VDD GND SDOA OUT1A- OUT1A+ OUT3B+ OUT3B- F GND GND VCM23 GND GND GND OUT4B- OUT4B+ DCOB+ DCOB- G AIN4- AIN4+ GND GND GND GND DCOA+ DCOA- OVDD OVDD H + - GND FRA- FRA+ GND GND OUT5A- FRB- FRB+ AIN5 AIN5 GND GND GND J GND GND VCM67 GND GND GND OUT5A+ K AIN6+ AIN6- VDD VDD GND GND OUT5B+ OUT5B- OUT6A- OUT6A+ L GND GND VDD VDD CSA SCK OUT7A+ OUT8A- OUT6B- OUT6B+ M AIN7+ AIN7- GND GND CSB SDI OUT7A- OUT8A+ OUT8B+ OUT8B- N + - GND OUT7B+ GND GND GND OUT7B- GND GND AIN8 P GND AIN8 GND VCM58 GND GND GND GND GND ENC+ ENC- Top View of BGA Package (Looking Through Component). Rev D 20 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 FUNCTIONAL BLOCK DIAGRAM VDD = 1.8V OVDD = 1.8V CH 1 ANALOG INPUT S/H 14-BIT ADC CORE OUT1A+ OUT1A- OUT1B+ OUT1B- CH 2 ANALOG INPUT S/H 14-BIT ADC CORE OUT2A+ OUT2A- OUT2B+ OUT2B- CH 3 ANALOG INPUT S/H 14-BIT ADC CORE OUT3A+ OUT3A- OUT3B+ OUT3B- CH 4 ANALOG INPUT S/H 14-BIT ADC CORE OUT4A+ OUT4A- OUT4B+ OUT4B- DATA SERIALIZER CH 5 ANALOG INPUT S/H 14-BIT ADC CORE OUT5A+ OUT5A- OUT5B+ OUT5B- CH 6 ANALOG INPUT S/H 14-BIT ADC CORE OUT6A+ OUT6A- OUT6B+ OUT6B- CH 7 ANALOG INPUT S/H 14-BIT ADC CORE OUT7A+ OUT7A- OUT7B+ OUT7B- CH 8 ANALOG INPUT S/H 14-BIT ADC CORE OUT8A+ OUT8A- OUT8B+ OUT8B- ENC+ DCOA DCOB FRA FRB PLL ENC- 1.25V REFERENCE VREF REFH RANGE SELECT REFL REF BUFFER SDOA SDOB SDI SCK CSA CSB PAR/SER MODE CONTROL REGISTERS VDD/2 DIFF REF AMP GND 9009101114 F01 SENSE VCM14 Figure 1. Figure 1. Functional Block Diagram For more information www.analog.com VCM58 VCM23 VCM67 Rev D 21 LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION CONVERTER OPERATION INPUT DRIVE CIRCUITS The LTM9011-14/LTM9010-14/LTM9009-14 are low power, 8-channel, 14-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). Many additional features can be chosen by programming the mode control registers through a serial SPI port. Input Filtering ANALOG INPUT The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the appropriate VCM output pins, which are nominally VDD/2. For the 2V input range, the inputs should swing from VCM - 0.5V to VCM + 0.5V. There should be 180 phase difference between the inputs. The eight channels are simultaneously sampled by a shared encode circuit (Figure 2). If possible, there should be an RC low pass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application's input frequency. Transformer Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion. 50 0.1F 0.1F ANALOG INPUT T1 1:1 25 25 AIN+ VDD RON 25 10 AIN- CSAMPLE 3.5pF RON 25 10 VDD CSAMPLE 3.5pF LTM9011-14 0.1F 25 T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE CPARASITIC 1.8pF VDD AIN+ 12pF 25 LTM9011-14 VCM AIN- 9009101114 F03 Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz CPARASITIC 1.8pF 1.2V 10k ENC+ ENC- 10k 1.2V 9009101114 F02 Figure 2. Equivalent Input Circuit. Only One of the Eight Analog Channels Is Shown Rev D 22 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC-coupled to the A/D so the amplifier's output common mode voltage can be optimally set to minimize distortion. See back page for a DC-coupled example. 50 At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 4 to 6) should convert the signal to differential before driving the A/D. 50 VCM VCM 0.1F 0.1F ANALOG INPUT 0.1F 0.1F AIN+ T2 T1 25 LTM9011-14 0.1F ANALOG INPUT AIN+ T2 T1 25 LTM9011-14 0.1F 4.7pF 0.1F 25 1.8pF 0.1F - AIN 25 AIN- 9009101114 F04 T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1LB RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE T1: MA/COM MABA-007159-000000 T2: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 4. Recommended Front End Circuit for Input Frequencies from 70MHz to 170MHz 50 9009101114 F05 Figure 5. Recommended Front End Circuit for Input Frequencies from 170MHz to 300MHz VCM VCM HIGH SPEED DIFFERENTIAL 0.1F AMPLIFIER 0.1F 0.1F 2.7nH ANALOG INPUT 25 + AIN LTM9011-14 0.1F T1 0.1F 25 2.7nH AIN- ANALOG INPUT + + - - 200 200 25 0.1F AIN+ LTM9011-14 12pF 0.1F 25 AIN- 9009101114 F07 9009101114 F06 T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 6. Recommended Front End Circuit for Input Frequencies Above 300MHz Figure 7. Front End Circuit Using a High Speed Differential Amplifier Rev D For more information www.analog.com 23 LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Reference The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 * VSENSE. The reference is shared by all eight ADC channels, so it is not possible to independently adjust the input range of individual channels. The LTM9011-14/LTM9010-14/LTM9009-14 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). VREF 1.25V LTM9011-14 The VREF , SENSE, REFH and REFL pins are internally bypassed, as shown in Figure 8. 5 1.25V BANDGAP REFERENCE 1F 0.625V TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; RANGE = 1.6 * VSENSE FOR 0.65V < VSENSE < 1.300V RANGE DETECT AND CONTROL SENSE 0.1F INTERNAL ADC BUFFER HIGH REFERENCE 0.1F 2.2F REFH 0.1F 0.1F 0.8x DIFF AMP REFL INTERNAL ADC LOW REFERENCE 9009101114 F08 Figure 8. Reference Circuit 1.25V EXTERNAL REFERENCE LTM9011-14 SENSE 1F 9009101114 F09 Figure 9. Using an External 1.25V Reference Rev D 24 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals--do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11). The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13). LTM9011-14 The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC- should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC- is connected to ground and ENC+ is driven with a square wave VDD DIFFERENTIAL COMPARATOR VDD 15k ENC+ LTM9011-14 1.8V TO 3.3V ENC- 0V 30k ENC+ ENC- 30k 9009101114 F11 9009101114 F10 Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode 0.1F ENC+ T1 0.1F Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode LTM9011-14 0.1F 50 100 PECL OR LVDS CLOCK 50 0.1F CMOS LOGIC BUFFER ENC- 9009101114 F12 ENC+ LTM9011-14 0.1F ENC- 9009101114 F13 T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 12. Sinusoidal Encode Drive Figure 13. PECL or LVDS Encode Drive Rev D For more information www.analog.com 25 LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. serialization (see the Timing Diagrams section for details). Note that with 12-bit serialization the two LSBs are not available--this mode is included for compatibility with 12-bit versions of these parts. Clock PLL and Duty Cycle Stabilizer The output data should be latched on the rising and falling edges of the data clock out (DCO). A data frame output (FR) can be used to determine when the data from a new conversion result begins. In the 2-lane, 14-bit serialization mode, the frequency of the FR output is halved. The encode clock is multiplied by an internal phase-locked loop (PLL) to generate the serial digital output data. If the encode signal changes frequency or is turned off, the PLL requires 25s to lock onto the input clock. A clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. In the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. In the parallel programming mode the duty cycle stabilizer is always enabled. DIGITAL OUTPUTS The digital outputs of the LTM9011-14/LTM9010-14/ LTM9009-14 are serialized LVDS signals. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). The data can be serialized with 16, 14, or 12-bit The maximum serial data rate for the data outputs is 1Gbps, so the maximum sample rate of the ADC will depend on the serialization mode as well as the speed grade of the ADC (see Table 1). The minimum sample rate for all serialization modes is 5Msps. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100 differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD which is independent from the A/D core power. Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTM9011-14. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTM9010-14) or 80MHz (LTM9009-14). SERIALIZATION MODE MAXIMUM SAMPLING FREQUENCY, fS (MHz) DCO FREQUENCY FR FREQUENCY SERIAL DATA RATE 2-Lane 16-Bit Serialization 125 4 * fS fS 8 * fS 2-Lane 14-Bit Serialization 125 3.5 * fS 0.5 * fS 7 * fS 2-Lane 12-Bit Serialization 125 3 * fS fS 6 * fS 1-Lane 16-Bit Serialization 62.5 8 * fS fS 16 * fS 1-Lane 14-Bit Serialization 71.4 7 * fS fS 14 * fS 1-Lane 12-Bit Serialization 83.3 6 * fS fS 12 * fS Rev D 26 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Programmable LVDS Output Current Table 2. Output Codes vs Input Voltage The default output driver current is 3.5mA. This current can be adjusted by control register A2 in the serial programming mode. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the parallel programming mode, the SCK pin can select either 3.5mA or 1.75mA. Optional LVDS Driver Internal Termination In most cases, using just an external 100 termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100 termination resistor can be enabled by serially programming mode control register A2. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. In the parallel programming mode the SDO pin enables internal termination. Internal termination should only be used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes. DATA FORMAT Table 2 shows the relationship between the analog input voltage and the digital data output bits. By default the output data format is offset binary. The 2's complement format can be selected by serially programming mode control register A1. AIN+ - AIN- (2V RANGE) D13-D0 (OFFSET BINARY) D13-D0 (2's COMPLEMENT) >1.000000V 11 1111 1111 1111 01 1111 1111 1111 +0.999878V 11 1111 1111 1111 01 1111 1111 1111 +0.999756V 11 1111 1111 1110 01 1111 1111 1110 +0.000122V 10 0000 0000 0001 00 0000 0000 0001 +0.000000V 10 0000 0000 0000 00 0000 0000 0000 -0.000122V 01 1111 1111 1111 11 1111 1111 1111 -0.000244V 01 1111 1111 1110 11 1111 1111 1110 -0.999878V 00 0000 0000 0001 10 0000 0000 0001 -1.000000V 00 0000 0000 0000 10 0000 0000 0000 <-1.000000V 00 0000 0000 0000 10 0000 0000 0000 Digital Output Randomizer Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. The digital output is randomized by applying an exclusiveOR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied --an exclusive-OR operation is applied between the LSB and all other bits. The FR and DCO outputs are not affected. The output randomizer is enabled by serially programming mode control register A1. Rev D For more information www.analog.com 27 LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Digital Output Test Pattern DEVICE PROGRAMMING MODES To allow in-circuit testing of the digital interface to the A/D, there is a test mode that forces the A/D data outputs (D13-D0) of all channels to known values. The digital output test patterns are enabled by serially programming mode control registers A3 and A4. When enabled, the test patterns override all other formatting modes: 2's complement and randomizer. The operating modes of the LTM9011-14/LTM9010-14/ LTM9009-14 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Output Disable The digital outputs may be disabled by serially programming mode control register A2. The current drive for all digital outputs including DCO and FR are disabled to save power or enable in-circuit testing. When disabled the common mode of each output pair becomes high impedance, but the differential impedance may remain low. Sleep and Nap Modes The A/D may be placed in sleep or nap modes to conserve power. In sleep mode the entire device is powered down, resulting in 2mW power consumption. Sleep mode is enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode). The time required to recover from sleep mode is about 2ms. In nap mode any combination of A/D channels can be powered down while the internal reference circuits and the PLL stay active, allowing faster wakeup than from sleep mode. Recovering from nap mode requires at least 100 clock cycles. If the application demands very accurate DC settling then an additional 50s should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the A/D leaves nap mode. Nap mode is enabled by mode control register A1 in the serial programming mode. Parallel Programming Mode To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK, SDI and SDO pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V CMOS logic. When used as an input, SDO should be driven through a 1k series resistor. Table 3 shows the modes set by CS, SCK, SDI and SDO. Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD) Pin DESCRIPTION CS 2-Lane / 1-Lane Selection Bit 0 = 2-Lane, 16-Bit Serialization Output Mode 1 = 1-Lane, 14-Bit Serialization Output Mode SCK LVDS Current Selection Bit 0 = 3.5mA LVDS Current Mode 1 = 1.75mA LVDS Current Mode SDI Power Down Control Bit 0 = Normal Operation 1 = Sleep Mode SDO Internal Termination Selection Bit 0 = Internal Termination Disabled 1 = Internal Termination Enabled Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising Rev D 28 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. bits (A6:A0) will be read back on the SDO pin (see the Timing Diagrams section). During a read back command the register is not updated and data on SDI is ignored. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). The SDO pin is an open-drain output that pulls to ground with a 200 impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 4 shows a map of the mode control registers. If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address Table 4. Serial Programming Mode Register Map (PAR/SER = GND) REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 D6 D5 D4 D3 D2 D1 D0 RESET X X X X X X X Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. RESET Bit 7 Software Reset Bit 0 = Not Used 1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. After the Reset SPI Write Command Is Complete, Bit D7 Is Automatically Set Back to Zero. The Reset Register Is Write Only. Bits 6-0 Unused, Don't Care Bits. REGISTER A1 (CSA): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSA = GND) D7 D6 D5 D4 D3 D2 D1 D0 DCSOFF RAND TWOSCOMP SLEEP NAP_8 NAP_5 NAP_4 NAP_1 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended. Bit 6 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 5 TWOSCOMP Two's Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two's Complement Data Format Bits 4-0 SLEEP: NAP_X Sleep/Nap Mode Control Bits 00000 = Normal Operation 0XXX1 = Channel 1 in Nap Mode 0XX1X = Channel 4 in Nap Mode 0X1XX = Channel 5 in Nap Mode 01XXX = Channel 8 in Nap Mode 1XXXX = Sleep Mode. Channels 1, 4, 5 and 8 Are Disabled Note: Any Combination of Channels Can Be Placed in Nap Mode. Rev D For more information www.analog.com 29 LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION REGISTER A1 (CSB): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSB = GND) D7 D6 D5 D4 D3 D2 D1 D0 DCSOFF RAND TWOSCOMP SLEEP NAP_7 NAP_6 NAP_3 NAP_2 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer On 1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended. Bit 6 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 5 TWOSCOMP Two's Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two's Complement Data Format Bits 4-0 SLEEP: NAP_4:NAP_1 Sleep/Nap Mode Control Bits 00000 = Normal Operation 0XXX1 = Channel 2 in Nap Mode 0XX1X = Channel 3 in Nap Mode 0X1XX = Channel 6 in Nap Mode 01XXX = Channel 7 in Nap Mode 1XXXX = Sleep Mode. Channels 2, 3, 6 and 7 Are Disabled Note: Any Combination of Channels Can Be Placed in Nap Mode. REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 D6 D5 D4 D3 D2 D1 D0 ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE2 OUTMODE1 OUTMODE0 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bits 7-5 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current Bit 4 TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current Is 2x the Current Set by ILVDS2:ILVDS0. Internal Termination Should Only Be Used with 1.75mA, 2.1mA or 2.5mA LVDS Output Current Modes. Bit 3 OUTOFF Output Disable Bit 0 = Digital Outputs Are Enabled. 1 = Digital Outputs Are Disabled. Bits 2-0 OUTMODE2:OUTMODE0 Digital Output Mode Control Bits 000 = 2-Lanes, 16-Bit Serialization 001 = 2-Lanes, 14-Bit Serialization 010 = 2-Lanes, 12-Bit Serialization 011 = Not Used 100 = Not Used 101 = 1-Lane, 14-Bit Serialization 110 = 1-Lane, 12-Bit Serialization 111 = 1-Lane, 16-Bit Serialization Rev D 30 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h) D7 D6 D5 D4 D3 D2 D1 D0 OUTTEST X TP13 TP12 TP11 TP10 TP9 TP8 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7 OUTTEST Digital Output Test Pattern Control Bit 0 = Digital Output Test Pattern Off 1 = Digital Output Test Pattern On Bit 6 Unused, Don't Care Bit. Bit 5-0 TP13:TP8 Test Pattern Data Bits (MSB) TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8. REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h) D7 D6 D5 D4 D3 D2 D1 D0 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7. Bit 7-0 TP7:TP0 Test Pattern Data Bits (LSB) TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB). Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset SPI write command is complete, bit D7 is automatically set back to zero. GROUNDING AND BYPASSING The LTM9011-14/LTM9010-14/LTM9009-14 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. Bypass capacitors are integrated inside the package; additional capacitance is optional. The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. The pin assignments of the LTM9011-14/LTM9010-14/ LTM9009-14 allow a flow-through layout that makes it possible to use multiple parts in a small area when a large number of ADC channels are required. The LTM9011 module has similar layout rules to other BGA packages. The layout can be implemented with 6mil blind vias and 5mil traces. The pinout has been designed to minimize the space required to route the analog and digital traces. The analog and digital traces can essentially be routed within the width of the package. This allows multiple packages to be located close together for high channel count applications. Trace lengths for the analog inputs and digital outputs should be matched as well as possible. Rev D For more information www.analog.com 31 LTM9011-14/ LTM9010-14/LTM9009-14 APPLICATIONS INFORMATION Table 5 lists the trace lengths for the analog inputs and digital outputs inside the package from the die pad to the package pad. These should be added to the PCB trace lengths for best matching. The material used for the substrate is BT (bismaleimidetriazine), supplied by Mitsubishi Gas and Chemical. In the DC to 125MHz range, the speed for the analog input signals is 198ps/in or 7.795ps/mm. The speed for the digital outputs is 188.5ps/in or 7.417ps/mm. HEAT TRANSFER Most of the heat generated by the LTM9011-14/LTM9010-14/ LTM9009-14 is transferred from the die through the bottom of the package onto the printed circuit board. The ground pins should be connected to the internal ground planes by multiple vias. Table 5. Internal Trace Lengths PIN NAME LENGTH (mm) PIN NAME LENGTH (mm) PIN NAME LENGTH (mm) PIN NAME LENGTH (mm) E7 OUT1A- 1.775 K8 OUT5B- 0.379 E1 AIN3- 2.491 F10 DCOB- 1.811 E8 OUT1A+ 1.947 K7 OUT5B+ 0.528 E2 AIN3+ 2.505 F9 DCOB+ 1.812 C8 OUT1B- K9 OUT6A- G1 - H7 FRA- 1.117 D8 OUT1B+ 1.850 K10 OUT6A+ 1.865 1.038 B8 OUT2A- 3.233 L9 OUT6B- 2.268 1.644 A8 OUT2A+ 3.246 L10 OUT6B+ D7 OUT2B- 0.179 M7 OUT7A- C7 OUT2B+ 1.127 L7 OUT7A+ D10 OUT3A- 2.126 P8 OUT7B- D9 OUT3A+ 2.177 N8 OUT7B+ E10 OUT3B- L8 OUT8A- E9 OUT3B+ 1.812 M8 OUT8A+ 1.847 C9 OUT4A- 3.199 M10 OUT8B- 4.021 C10 OUT4A+ 3.196 M9 OUT8B+ F7 OUT4B- 0.706 B1 AIN1- F8 OUT4B+ B2 + J8 OUT5A- 0.392 J7 OUT5A+ 0.436 1.847 1.811 0.639 AIN1 1.866 AIN4 3.376 G2 AIN4 + 3.372 H8 FRA+ H2 AIN5- 3.301 J9 FRB- 2.267 H1 AIN5 + 3.346 J10 FRB+ 1.643 1.089 K2 AIN6- 2.506 A7 PAR/SER 3.838 0.179 K1 AIN6+ 2.533 L6 SCK 0.240 3.281 M2 AIN7 - 3.198 E6 SDOA 0.453 3.149 M1 AIN7+ 3.214 D6 SDOB 0.274 N2 - 4.726 M6 SDI 1.069 N1 AIN8 + 4.691 B3 VCM14 3.914 P6 ENC- 4.106 F3 VCM23 0.123 4.016 P5 ENC+ 4.106 J3 VCM67 0.079 4.689 L5 CSA 0.919 N3 VCM58 3.915 4.709 M5 CSB 1.162 1.157 1.088 1.862 AIN8 C1 AIN2 - 4.724 G8 DCOA- C2 AIN2+ 4.769 G7 DCOA+ Rev D 32 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL APPLICATIONS Silkscreen Top Top Side Rev D For more information www.analog.com 33 LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL APPLICATIONS Inner Layer 2 Inner Layer 3 Rev D 34 For more information www.analog.com LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL APPLICATIONS Inner Layer 4 Inner Layer 5 Rev D For more information www.analog.com 35 LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL APPLICATIONS Bottom Side Silkscreen Bottom Rev D 36 For more information www.analog.com CLK+ CLK+ R27 (OPT) +1.8V GND E4 E3 C3 0.01F R15 (OPT) C10 4.7F 6.3V 0603 R16 (OPT) C12 1F 0603 C19 (OPT) R37 100 R14 (OPT) R25 (OPT) R18 (OPT) 4 1 2 3 9 AIN1+ B2 AIN1- B1 VCM14 B3 AIN2+ C2 AIN2- C1 AIN3+ E2 AIN3- E1 VCM23 F3 AIN4+ G2 AIN4- G1 AIN5+ H2 AIN5- H1 VCM67 J3 AIN6+ K1 AIN6- K2 AIN7+ M1 AIN7- M2 AIN8+ N1 AIN8- N2 VCM58 N3 C56 0.1F R29 180k 1% C11 1F 0603 + ENC+ P5 ENC- P6 +1.8V D3 C5 D4 E3 4.7pF E4 K3 K4 L3 L4 +1.8VO G9 G10 R20 R24 100 C7 (OPT) 4.7pF C2 (OPT) (SAME FOR OTHER CHANNELS) R38 0 0603 LT3080EDD OUT OUT OUT 5 OUT VCTRL 6 NC SET 7 IN 8 IN R17 5.1 R21 49.9 1% R22 49.9 1% R23 5.1 L1 (OPT) C23 (OPT) C18 (OPT) C15 (OPT) R32 0 0603 VCM14 AIN2+ AIN2- AIN3+ AIN3- VCM23 AIN4+ AIN4- AIN5+ AIN5- VCM67 AIN6+ AIN6- AIN7+ AIN7- AIN8+ AIN8- VCM58 ENC+ ENC- +1.8V +1.8V +1.8V +1.8V +1.8V +1.8V +1.8V +1.8V +1.8VO +1.8VO AIN1+ AIN1- SENSE PAR/SER PAR/SER +1.8V C1 2.2F, 0603 EXT REF E1 R10 1k VREF M6 LTM9011-14 SCI SCK R7 1k +1.8V ILVDS 1 1.7mA 2 3 3.5mA MOSI JP5 JP2 CSA CSB SDOB SCK CSA CSB SDOA SDOB R13 31.6k 1% R11 10k R8 1k JP6 C13 100F 10V R28 3k FB2 BLM31PG330SN1L FB1 BLM31PG330SN1L +1.8V +1.8VO C14 0.1F R3 1k E8 E7 D8 C8 A8 B8 C7 D7 D9 D10 E9 E10 C10 C9 F8 F7 J7 J8 K7 K8 K10 K9 L10 L9 M8 L8 M9 M10 H8 H7 J10 J9 G7 G8 F9 F10 DIS TERM EN OUT1A+ OUT1A- OUT1B+ OUT1B- OUT2A+ OUT2A- OUT2B+ OUT2B- OUT3A+ OUT3A- OUT3B+ OUT3B- OUT4A+ OUT4A- OUT4B+ OUT4B- OUT5A+ OUT5A- OUT5B+ OUT5B- OUT6A+ OUT6A- OUT6B+ OUT6B- OUT7A+ OUT7A- OUT7B+ OUT7B- FRA+ FRA- FRB+ FRB- DCOA+ DCOA- DCOB+ DCOB- 1 2 3 R5 31.6k 1% R4 10k 3.3 AUX +1.8V 3.3 AUX +1.8V R1 LANE 1k 1 1 LANE 2 3 2 LANE JP3 SDOA JP3 DIS TERM EN 9009101114 TA02 OUT1A+ OUT1A- OUT1B+ OUT1B- OUT2A+ OUT2A- OUT2B+ OUT2B- OUT3A+ OUT3A- OUT3B+ OUT3B- OUT4A+ OUT4A- OUT4B+ OUT4B- OUT5A+ OUT5A- OUT5B+ OUT5B- OUT6A+ OUT6A- OUT6B+ OUT6B- OUT7A+ OUT7A- OUT7B+ OUT7B- FRA+ FRA- FRB+ FRB- DCOA+ DCOA- DCOB+ DCOB- 1 2 3 TYPICAL APPLICATION V+ 3V TO 6V J1 J2 R26 (OPT) R48 100 C17 R37 (OPT) 0 0805 R36 0 0603 C4 T1 R19 0.01F MABA100 007159-000000 5 1 2 C6 C9 0.01F C8 4 3 0.01F (OPT) 0.01F VCM14 IN- IN+ R31 0 0805 R6 1k R9 100 2 LANE L5 A1 A2 A3 A4 A5 A6 B4 B5 B7 C3 C4 C6 D1 D2 D5 E5 F1 F2 F4 F5 F6 G3 G4 G5 G6 H3 H4 H5 H6 J1 J2 J4 J5 J6 K5 K6 L1 L2 M3 M4 N4 N5 N6 N7 P1 P2 P3 P4 P7 R30 0 0603 PAR/SER 1 PAR 2 3 SER JP4 A7 +1.8V A9 A10 B9 B10 H9 H10 N9 N10 P9 P10 For more information www.analog.com GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND C5 1 LANE L6 +1.8V B6 R2 1k M5 +1.8V E6 LANE D6 LTM9011-14 Schematic LTM9011-14/ LTM9010-14/LTM9009-14 Rev D 37 2.000 2.000 SUGGESTED PCB LAYOUT TOP VIEW 1.200 aaa Z 0.4 O 140x 0.000 PACKAGE TOP VIEW 0.400 4 0.400 PIN "A1" CORNER 2.800 E 1.200 X D For more information www.analog.com 5.200 4.400 3.600 2.800 2.000 1.200 0.400 0.400 1.200 2.000 2.800 3.600 4.400 5.200 Y 0.000 aaa Z SYMBOL A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee b1 DETAIL A NOM 2.72 0.40 2.32 0.50 0.40 11.25 9.0 0.80 10.40 7.2 0.32 2.00 MAX 2.87 0.45 2.42 0.55 0.43 DIMENSIONS BALL DIMENSION PAD DIMENSION BALL HT NOTES DETAIL B PACKAGE SIDE VIEW Z SUBSTRATE THK 0.37 MOLD CAP HT 2.05 0.15 0.10 0.12 0.15 0.08 TOTAL NUMBER OF BALLS: 140 0.27 1.95 MIN 2.57 0.35 2.22 0.45 0.37 H1 SUBSTRATE ddd M Z X Y eee M Z DETAIL B H2 MOLD CAP ccc Z A1 A2 A (Reference LTC DWG # 05-08-1849 Rev C) Ob (140 PLACES) // bbb Z 38 Z BGA Package 140-Lead (11.25mm x 9.00mm x 2.72mm) e 10 9 7 6 5 4 3 PACKAGE BOTTOM VIEW 8 b G 2 1 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE BALL DESIGNATION PER JESD MS-028 AND JEP95 P N M L K J H G F E D C B A TRAY PIN 1 BEVEL COMPONENT PIN "A1" 7 ! PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX Module PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG Module PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY 7 DETAIL A PIN 1 SEE NOTES BGA 140 1116 REV C 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu OR Sn Pb EUTECTIC 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 3 SEE NOTES F b e LTM9011-14/ LTM9010-14/LTM9009-14 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM9011-14#packaging for the most recent package drawings. Rev D 3.600 2.800 3.600 LTM9011-14/ LTM9010-14/LTM9009-14 REVISION HISTORY REV DATE DESCRIPTION A 9/11 Updated Functional Block Diagram. 21 B 3/15 Removed mention of OGND. 26 C 2/17 Fixed VCM channel pairs: VCM12 changed to VCM14, VCM34 changed to VCM23, VCM56 changed to VCM67, VCM78 changed to VCM58. 18, 20, 21, 32, 37, 40 Corrected pin names for ENC and OUTXX. 20, 32, 37, 40 D 4/18 Corrected J3/N3 pin names. PAGE NUMBER 20 Rev D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. moreby information www.analog.com 39 LTM9011-14/ LTM9010-14/LTM9009-14 TYPICAL APPLICATION Single-Ended to Differential Conversion Using LTC6409 and 50MHz Lowpass Filter (Only One Channel Shown). Filter for Use at 92.16Msps 0.8pF 1.8V 1.8V 0.1F 150 49.9 IN- 68pF 150pF LTC6409 - SHDN 75 33pF 68pF OUT+ VOCM 474 180nH 37.4 150pF 180nH + B2 AIN1 OUT1A+ E8 - B1 AIN1 OUT1A- E7 75 B3 C2 0.8pF 66.9 100pF C1 F2 GND VREF 180nH VDD OUT - SENSE + 180nH 37.4 V+ IN+ B6 *** 0.1F C5 F1 50 F3 G2 *** G1 N1 N2 DCO+ G7 VCM14 AIN2+ LTM9010-14 AIN2- DCO- G8 FR+ H8 FR- H7 AIN3+ AIN3- VCM23 AIN4+ AIN4- AIN8+ AIN8- ENC- 66.9 474 ENC+ 150 OVDD 3.3V P5 P6 9009101114 TA03 RELATED PARTS PART NUMBER ADCs LTC2170-14/LTC2171-14/ LTC2172-14 LTC2170-12/LTC2171-12/ LTC2172-12 LTC2173-12/LTC2174-12/ LTC2175-12 LTC2173-14/LTC2174-14/ LTC2175-14 Amplifiers/Filters LTC6412 LTC6420-20 LTC6421-20 LTC6605-7/LTC6605-10/ LTC6605-14 Signal Chain Receivers LTM9002 DESCRIPTION COMMENTS 14-Bit, 25Msps/40Msps/65Msps 1.8V Quad ADCs, Ultralow Power 12-Bit, 25Msps/40Msps/65Msps 1.8V Quad ADCs, Ultralow Power 12-Bit, 80Msps/105Msps/125Msps 1.8V Quad ADCs, Ultralow Power 14-Bit, 80Msps/105Msps/125Msps 1.8V Quad ADCs, Ultralow Power 178mW/234mW/360mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm x 8mm QFN-52 178mW/234mW/360mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm x 8mm QFN-52 412mW/481mW/567mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm x 8mm QFN-52 412mW/481mW/567mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 7mm x 8mm QFN-52 800MHz, 31dB Range, Analog-Controlled Variable Gain Amplifier 1.8GHz Dual Low Noise, Low Distortion Differential ADC Drivers for 300MHz IF 1.3GHz Dual Low Noise, Low Distortion Differential ADC Drivers Dual Matched 7MHz/10MHz/14MHz Filters with ADC Drivers Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, 4mm x 4mm QFN-24 Fixed Gain 10V/V, 1nV/Hz Total Input Noise, 80mA Supply Current per Amplifier, 3mm x 4mm QFN-20 Fixed Gain 10V/V, 1nV/Hz Total Input Noise, 40mA Supply Current per Amplifier, 3mm x 4mm QFN-20 Dual Matched 2nd Order Lowpass Filters with Differential Drivers, Pin-Programmable Gain, 6mm x 3mm DFN-22 14-Bit Dual Channel IF/Baseband Receiver Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers Subsystem Rev D 40 D16880-0-5/18(D) For more information www.analog.com www.analog.com ANALOG DEVICES, INC. 2011-2018