High Frequency Divider/PLL Synthesizer
ADF4007
Rev. 0
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Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
7.5 GHz bandwidth
Maximum PFD frequency of 120 MHz
Divide ratios of 8, 16, 32, or 64
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows
extended tuning voltage in 3 V systems
RSET contol of charge pump current
Hardware power-down mode
APPLICATIONS
Satellite communications
Broadband wireless access
CATV
Instrumentation
Wireless LANs
GENERAL DESCRIPTION
The ADF4007 is a high frequency divider/PLL synthesizer that
can be used in a variety of communications applications. It can
operate to 7.5 GHz on the RF side and to 120 MHz at the PFD.
It consists of a low noise digital PFD (phase frequency
detector), a precision charge pump, and a divider/prescaler. The
divider/ prescaler value can be set by two external control pins
to one of four values (8, 16, 32, or 64). The reference divider is
permanently set to 2, allowing an external REFIN frequency of
up to 240 MHz.
A complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and a VCO
(voltage controlled oscillator). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
FUNCTIONAL BLOCK DIAGRAM
REF
IN
RF
IN
A
RF
IN
B
V
DD
N2 N1 GND
R COUNTER
÷2
MUX MUXOUT
CPGND R
SET
V
P
CP
PHASE
FREQUENCY
DETECTOR
REFERENCE
CHARGE
PUMP
ADF4007
N COUNTER
÷8, ÷16,
÷32, ÷64
M2 M1
04537-0-001
Figure 1.
ADF4007
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Reference Input Section............................................................... 9
RF Input Stage............................................................................... 9
Prescaler P ..................................................................................... 9
R Counter .......................................................................................9
Phase Frequency Detector (PFD) and Charge Pump...............9
MUXOUT ................................................................................... 10
Applications..................................................................................... 11
Fixed High Frequency Local Oscillator................................... 11
Using the ADF4007 as a Divider .............................................. 12
PCB Design Guidelines for Chip Scale Package......................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
Revision 0: Initial Version
ADF4007
Rev. 0 | Page 3 of 16
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω,
TA = TMAX to TMIN, unless otherwise noted.
Table 1.
Parameter B Version1Unit Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RFIN) 1.0/7.0 GHz min/max RF input level: +5 dBm to −10 dBm
RF Input Frequency 0.5/7.5 GHz min/max RF input level: +5 dBm to −5 dBm
For lower frequencies, ensure that slew rate (SR) > 560 V/µs
REFIN CHARACTERISTICS
REFIN Input Sensitivity 0.8/VDD V p-p min/max Biased at AVDD/22
REFIN Input Frequency 20/240 MHz min/max For f < 20 MHz, use square wave (slew rate > 50 V/µs)
REFIN Input Capacitance 10 pF max
REFIN Input Current ±100 µA max
PHASE DETECTOR
Phase Detector Frequency3120 MHz max
MUXOUT
MUXOUT Frequency3 200 MHz max CL = 15 pF
CHARGE PUMP
ICP Sink/Source 5.0 mA typ With RSET = 5.1 kΩ
Absolute Accuracy 2.5 % typ With RSET = 5.1 kΩ
RSET Range 3.0/11 kΩ typ
ICP Three-State Leakage 10 nA max TA = 85°C
Sink and Source Current Matching 2 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. VCP 1.5 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. Temperature 2 % typ VCP = VP/2
LOGIC INPUTS
VIH, Input High Voltage 1.4 V min
VIL, Input Low Voltage 0.6 V max
IINH, IINL, Input Current ±1 µA max TA = 25°C
CIN, Input Capacitance 10 pF max
LOGIC OUTPUTS
VOH, Output High Voltage VDD − 0.4 V min IOH = 100 µA
VOL, Output Low Voltage 0.4 V max IOL = 500 µA
POWER SUPPLIES
AVDD 2.7/3.3 V min/max
DVDD AVDD
VPAVDD/5.5 V min/max AVDD ≤ VP ≤ 5.5 V
IDD4 (AIDD DD
+ DI ) 17 mA max 15 mA typ
IP2.0 mA max TA = 25°C
NOISE CHARACTERISTICS
Normalized Phase Noise Floor5−219 dBc/Hz typ
1 Operating temperature range (B version) is −40°C to +85°C.
2 AC coupling ensures AVDD/2 bias. See for typical circuit. Figure 13
3 Guaranteed by design. Characterized to ensure compliance.
4 TA = 25°C; AVDD = DVDD = 3 V; N = 64; RFIN = 7.5 GHz.
5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logFPFD. PNSYNTH = PNTOT − 10logFPFD − 20logN. The in-band phase noise (PNTOT) is measured using the HP8562E Spectrum Analyzer from Agilent.
ADF4007
Rev. 0 | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
AVDD to GND1−0.3 V to +3.6 V
AVDD to DVDD −0.3 V to +0.3 V
VP to GND −0.3 V to +5.8 V
VP to AVDD −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
CSP θJA Thermal Impedance 122°C/W
Lead Temperature, Soldering
Vapor Phase (60 s) 215°C
Infrared (15 s) 220°C
Transistor Count
CMOS 6425
Bipolar 303
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
1 GND = AGND = DGND = 0 V.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADF4007
Rev. 0 | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15 MUXOUT
14 M1
13 M2
12 N1
CPGND 1
AGND 2
AGND 3
20 CP
11 N2
AV
DD
6
AV
DD
7
REF
IN
8
DGND 9
DGND 10
RF
IN
B4
RF
IN
A5
19 R
SET
18 V
P
17 DV
DD
16 DV
DD
PIN1
INDICATOR
TOPVIEW
ADF4007
04537-0-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Function
1 CPGND Charge Pump Ground. The ground return path of the charge pump.
2, 3 AGND Analog Ground. The ground return path of the prescaler.
4 RFINB Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
5 RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
6, 7 AVDD Analog Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8 REF
IN
Reference Input. A CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resistance of 100 kΩ.
This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9, 10 DGND Digital Ground.
11, 12 N2, N1 These two bits set the N value. See Table 4.
13, 14 M2, M1 These two bits set the status of MUXOUT and PFD polarity. See Table 5.
15 MUXOUT This multiplexer output allows either the N divider output or the R divider output to be accessed externally.
16, 17 DVDD Digital Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
18 VPCharge Pump Power Supply. This pin should be greater than or equal to VDD. In systems where VDD is 3 V, it can be
set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
19 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAXCP
R
I5.25
=
Therefore, if RSET = 5.1 kΩ, then ICP = 5 mA.
20 CP Charge Pump Output. When enabled, this pin provides ±I
CP
to the external loop filter, which in turn drives the
external VCO.
ADF4007
Rev. 0 | Page 6 of 16
Table 4. N Truth Table
N2 N1 N Value
0 0 8
0 1 16
1 0 32
1 1 64
Table 5. M Truth Table
M2 M1 Operation
0 0 CP: Active
MUXOUT: VDD
PFD polarity: +ve
0 1 CP: Three-state
MUXOUT: R divider output
PFD polarity: +ve
1 0 CP: Active
MUXOUT: N divider output
PFD polarity: +ve
1 1 CP: Active
MUXOUT: GND
PFD polarity: −ve
ADF4007
Rev. 0 | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
Table 6. S-Parameter Data for the RF Input
Frequency1MagS11 AngS11
0.60000 0.87693 −19.9279
0.70000 0.85834 −23.5610
0.80000 0.85044 −26.9578
0.90000 0.83494 −30.8201
1.00000 0.81718 −34.9499
1.10000 0.80229 −39.0436
1.20000 0.78917 −42.3623
1.30000 0.77598 −46.3220
1.40000 0.75578 −50.3484
1.50000 0.74437 −54.3545
1.60000 0.73821 −57.3785
1.70000 0.72530 −60.6950
1.80000 0.71365 −63.9152
1.90000 0.70699 −66.4365
2.00000 0.70380 −68.4453
2.10000 0.69284 −70.7986
2.20000 0.67717 −73.7038
2.30000 0.67107 −75.8206
2.40000 0.66556 −77.6851
2.50000 0.65640 −80.3101
2.60000 0.63330 −82.5082
2.70000 0.61406 −85.5623
2.80000 0.59770 −87.3513
2.90000 0.56550 −89.7605
3.00000 0.54280 −93.0239
3.10000 0.51733 −95.9754
3.20000 0.49909 −99.1291
3.30000 0.47309 −102.208
3.40000 0.45694 −106.794
3.50000 0.44698 −111.659
3.60000 0.43589 −117.986
3.70000 0.42472 −125.620
3.80000 0.41175 −133.291
3.90000 0.41055 −140.585
4.00000 0.40983 −147.970
4.10000 0.40182 −155.978
Frequency1MagS11 AngS11
4.20000 0.41036 −162.939
4.30000 0.41731 −168.232
4.40000 0.43126 −174.663
4.50000 0.42959 −179.797
4.60000 0.42687 174.379
4.70000 0.43450 171.537
4.80000 0.42275 167.201
4.90000 0.40662 163.534
5.00000 0.39103 159.829
5.10000 0.37761 157.633
5.20000 0.34263 152.815
5.30000 0.30124 147.632
5.40000 0.27073 144.304
5.50000 0.23590 138.324
5.60000 0.17550 131.087
5.70000 0.12739 124.568
5.80000 0.09058 119.823
5.90000 0.06824 114.960
6.00000 0.04465 84.4391
6.10000 0.04376 34.2210
6.20000 0.06621 4.70571
6.30000 0.08498 −12.6228
6.40000 0.10862 −26.6069
6.50000 0.12161 −38.5860
6.60000 0.12917 −47.1990
6.70000 0.12716 −55.8515
6.80000 0.11678 −63.0234
6.90000 0.10533 −66.9967
7.00000 0.09643 −75.4961
7.10000 0.08919 −89.2055
7.20000 0.08774 −103.786
7.30000 0.09289 −127.153
7.40000 0.10803 −150.582
7.50000 0.13956 −170.971
1Frequency unit: GHz; parameter type: s; data format: MA; keyword: R;
impedance: 50.
ADF4007
Rev. 0 | Page 8 of 16
–40
–35
–30
–25
–20
–15
–10
–5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
V
DD
= 3V
V
P
= 3V
RF INPUT FREQUENCY (GHz)
RF INPUT POWER (dBm)
0
T
A
= +85°C
T
A
= +25°CT
A
= –40°C
04537-0-003
Figure 3. Input Sensitivity
0
–60
–2k
–10
–50
–70
–90
–30
–40
–80
–20
2k6780M–1k 1k
–100
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 106kHz
LOOP BANDWIDTH = 1MHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9s
AVERAGES = 10
–99dBc/Hz
FREQUENCY (Hz)
OUTPUT POWER (dB)
REF LEVEL = –14.3dBm
04537-0-005
Figure 4. Phase Noise (6.78 GHz RFOUT, 106 MHz PFD,
and 1 MHz Loop Bandwidth)
10k 100M
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
FREQUENCY OFFSET FROM CARRIER (Hz)
PHASE NOISE (dBc/Hz)
10dB/DIV
RL = –40dBc/Hz
RMS NOISE = 4.2°
04537-0-006
100k 1M 10M
Figure 5. Integrated Phase Noise (6.78 GHz RFOUT, 106 MHz PFD,
and 1 MHz Loop Bandwidth)
0
–60
–10
–50
–70
–90
–30
–40
–80
–20
–100
OUTPUT POWER (dB)
REF LEVEL = –14.0dBm
–212 2126780–106 106
FREQUENCY (MHz)
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 106MHz
LOOP BANDWIDTH = 1MHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5s
AVERAGES = 30
–91.0dBc/Hz
04537-0-007
Figure 6. Reference Spurs (6.78 GHz RFOUT, 106 MHz PFD,
and 1 MHz Loop Bandwidth)
–120
–130
–18010k 120M
100k 1M 10M
–140
–150
–160
–170
PHASE DETECTOR FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
V
DD
= 3V
V
P
= 5V
04537-0-013
Figure 7. Phase Noise (Referred to CP Output) vs. PFD Frequency
–6
–5
60 2.00.5 1.0 1.5
–4
–3
–2
–1
VCP (V)
ICP (mA)
0
1
2
3
4
5
4.02.5 3.0 3.5 5.04.5
VP = 5V
ICP = 5mA
04537-0-014
Figure 8. Charge Pump Output Characteristics
ADF4007
Rev. 0 | Page 9 of 16
THEORY OF OPERATION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 9. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
100kΩ
NC
REF
IN
NC
NO
SW1
SW2
BUFFER
SW3
TO R COUNTER
POWER-DOWN
CONTROL
04537-0-015
Figure 9. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 10 . It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
500Ω
1.6V
500Ω
AGND
BIAS
GENERATOR
RF
IN
A
RF
IN
B
AV
DD
04537-0-016
Figure 10. RF Input Stage
PRESCALER P
The prescaler, operating at CML levels, takes the clock from the
RF input stage and divides it down to a manageable frequency
for the PFD. The prescaler can be selected to be either 8, 16, 32,
or 64, and is effectively the N value in the PLL synthesizer. The
terms N and P are used interchangeably in this data sheet. N1
and N2 set the prescaler values. The prescaler value should be
chosen so that the prescaler output frequency is always less than
or equal to 120 MHz, the maximum specified PFD frequency.
Thus, with an RF frequency of 4 GHz, a prescaler value of 64 is
valid, but a value of 32 or less is not valid.
2
][ REFIN
VCO
f
Nf ×=
R COUNTER
The R counter is permanently set to 2. It allows the input
reference frequency to be divided down by 2 to produce the
reference clock to the phase frequency detector (PFD).
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and the N counter
(prescaler, P) and produces an output proportional to the phase
and frequency difference between them. Figure 11 is a
simplified schematic. The PFD includes a fixed, 3 ns delay
element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs.
LOGIC HI D1
D2
Q1
Q2
CLR1
CLR2
CP
U1
U2
UP
DOWN
CPGND
U3
R DIVIDER
3ns
DELAY
N DIVIDER
VPCHARGE
PUMP
04537-0-017
LOGIC HI
Figure 11. PFD Simplified Schematic and Timing (In Lock)
ADF4007
Rev. 0 | Page 10 of 16
MUXOUT
The output multiplexer on the ADF4007 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by the M2 and M1 pins. Figure 12
shows the MUXOUT section in block diagram form.
DGND
DVDD
CONTROL
MUX
DVDD
R COUNTER OUTPUT
N COUNTER OUTPUT
DGND
MUXOUT
04537-0-018
Figure 12. MUXOUT Circuit
PFD Polarity
The PFD polarity is set by the state of M2 and M1 pins as given
in the Table 5. The ability to set the polarity allows the use of
VCOs with either positive or negative tuning characteristics. For
standard VCOs with positive characteristics (output frequency
increases with increasing tuning voltage), the polarity should be
set to positive. This is accomplished by tying M2 and M1 to a
logic low state.
CP Output
The CP output state is also controlled by the state of M2 and
M1. It can be set either to active (so that the loop can be locked)
or to three-state (open the loop). The normal state is CP output
active.
ADF4007
Rev. 0 | Page 11 of 16
APPLICATIONS
FIXED HIGH FREQUENCY LOCAL OSCILLATOR
Figure 13 shows the ADF4007 being used with the
HMC358MS8G VCO from Hittite Microwave Corporation to
produce a fixed-frequency LO (local oscillator), which could be
used in satellite or CATV applications. In this case, the desired
LO is 6.7 GHz.
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 Ω. Many systems would
have either a TCXO or an OCXO driving the reference input
without any 50 Ω termination. To bias the REFIN pin at AVDD/2,
ac coupling is used. The value of the coupling capacitor used
depends on the input frequency. The equivalent impedance at
the input frequency should be less than 10 Ω. Given that the dc
input impedance at the REFIN pin is 100 kΩ, less than 0.1% of
the signal is lost.
The charge pump output of the ADF4007 drives the loop filter.
In calculating the loop filter component values, a number of
items need to be considered. In this example, the loop filter was
designed so that the overall phase margin for the system is 45°.
Other PLL system specifications are as follows:
KD = 5 mA
KV = 100 MHz/V
Loop Bandwidth = 300 kHz
FPFD = 106 MHz
N = 64
All these specifications are needed and used with the
ADIsimPLL to derive the loop filter component values shown in
Figure 13.
The circuit in Figure 13 gives a typical phase noise performance
of −100 dBc/Hz at 10 kHz offset from the carrier. Spurs are
heavily attenuated by the loop filter and are below −90 dBc.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output, and the RFIN
terminal of the synthesizer.
ADF4007
N2
N1
M2
M1
100pF 100pF
100pF
CP
MUXOUT
GND
GND
GND
5.6nF
51Ω
18Ω
22Ω
NOTE
DECOUPLING CAPACITORS (0.1mF/10pF) ON AV
DD
, DV
DD
, AND V
P
OF THE ADF4007 AND ON
V
CC
OF THE AD820 AND THE HMC358MS8G HAVE BEEN OMITTED FROM THE DIAGRAM
TO AID CLARITY.
R
SET
AV
DD
DV
DD
V
P
FREF
IN
VCO
100MHz/V
HMC358MS8G
R
SET
5.1kΩ
617 18
8
20
15
19
9
32
10
04537-0-019
RF
IN
A
RF
IN
B
5
4
11
12
13
14
GND
47nF
AV
DD
7
DV
DD
16
REF
IN
AV
DD
= 3.3V
1kΩ
18kΩ
V
CC
= 12V
V
CC
= 3.3V
1kΩ
AD820
10pF
18Ω
100pF 18Ω100pF RF
OUT
LOGIC HI
LOGIC HI
LOGIC LO
LOGIC LO
Figure 13. 6.78 GHz Local Oscillator Using the ADF4007
ADF4007
Rev. 0 | Page 12 of 16
USING THE ADF4007 AS A DIVIDER
In addition to its use as a standard PLL synthesizer, the
ADF4007 can also be used as a high frequency counter/divider
with a value of 8, 16, 32, or 64.This can prove useful in a wide
variety of applications where a higher frequency signal is readily
available. Figure 14 shows the ADF4007 used in this manner
with the ADF4360-7.
This part is an integrated synthesizer and VCO, in this case
operating over a range of 1200 MHz to 1500 MHz. With divide-
by-8 chosen in the ADF4007 (N2 = 0, N1 = 0), the output range
is 150 MHz to 187.50 MHz.
ADF4360-7
ADF4007
470pF 6.8nF
6.2kΩ
13kΩ
220pF
CLK
DATA
LE
4.7kΩ
R
SET
CP
V
TUNE
17
18
RF
OUT
A
1nF
C
C
CPGND AGND DGND
AV
DD
DV
DD
V
VCO
C
N
10µF
V
VCO
CE
REF
IN
FREF
IN
1nF
MUXOUT
LOCK
DETECT
RF
IN
B
V
P
AV
DD
100pF
100pF
V
VCO
CMOS OUTPUT
51Ω
19
12
13
1310
811 22 15 5
4
7
24
20
23
2
21
6
14
16
9
L2
51Ω
2.2nH
MUXOUT
REF
IN
PHASE
FREQUENCY
DETECTOR MUX
CHARGE
PUMP
CP
R COUNTER
÷2
R
SET
NCOUNTER
÷8, ÷16
÷32, ÷64
N1 N2
CPGND GND
M2 M1
4.7kΩ
V
DD
SPI COMPATIBLE SERIAL BUS
RF
OUT
B
2.2nH
L1
1nF
V
DD
RF
IN
A
51Ω
04537-0-020
DV
DD
Figure 14. Using the ADF4007 to Divide-Down the Output of the ADF4360-7
ADF4007
Rev. 0 | Page 13 of 16
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the pad
to ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. The printed circuit board should
have a clearance of at least 0.25 mm between the thermal pad
and the inner edges of the pad pattern to ensure that shorting is
avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.30 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper
to plug the via.
The user should connect the printed circuit board thermal pad
to AGND.
ADF4007
Rev. 0 | Page 14 of 16
OUTLINE DIMENSIONS
1
20
5
6
11
16
15
BOTTOM
VIEW
10
2.25
2.10 SQ
1.95
0.75
0.55
0.35 0.30
0.23
0.18
0.50
BSC
12° MAX
0.20
REF
0.80 MAX
0.65 TYP 0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
PIN 1
INDICATOR TOP
VIEW 3.75
BSC SQ
4.0
BSC SQ
COPLANARITY
0.08
0.60
MAX
0.60
MAX
0.25MIN
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 15. 20-Lead Frame Chip Scale Package [LFCSP]
(CP-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADF4007BCP −40°C to + 85°C 20-lead frame chip scale package (LFCSP) CP-20
ADF4007BCP–REEL −40°C to + 85°C 20-lead frame chip scale package (LFCSP) CP-20
ADF4007BCP–REEL7 −40°C to + 85°C 20-lead frame chip scale package (LFCSP) CP-20
CP = chip scale package.
ADF4007
NOTES
Rev. 0 | Page 15 of 16
ADF4007
Rev. 0 | Page 16 of 16
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04537–0–2/04(0)
