PRELIMINARY
3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO
CY7C43646AV
CY7C43666AV
CY7C43686AV
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06026 Rev. ** Revised March 19, 2001
3686AV
Features
• 3.3V high-speed, low-power, First-In First-Out (FIFO)
memories w/ three independent ports (one bidirectional
x36, and two unidirec tiona l x18)
• 1K x36/x18x2 (CY7C43646AV)
• 4K x36/x18x2 (CY7C43666AV)
• 16K x36/x18x2 (CY7C43686AV)
• 0.25-micron CMOS for optimum speed/power
• High-speed 133-MHz operation (7.5-ns read/write cycle
times)
• Low power
—ICC= 60 mA
—ISB= 10 mA
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and Serial Prog ramm able Almo st Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT user selectable mode
• Partial and Master reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
Logic Block D iagram
Port A
Control
Logic
Port B
Control
Logic
Mail1
Register
Input
Register
Write
Pointer Read
Pointer
Status
Flag Logic
Programmable Timing
Mode
Status
Flag Logic
Read
Pointer Write
Pointer
1K/4K/16K
x36
Dual Por ted
Memory
1K/4K/16K
x36
Dual Ported
Memory
Mail2
Register
Output
Register
Input
Register
FIFO1,
Mail1
Reset
Logic
FIFO2,
Mail2
Reset
Logic
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A0–35
EFA/ORA
AEA
MBF2
MRS2
PRS2
FFC/IRC
AFC
BE/FWFT
B0–17
CLKB
CSB
RENB
MBB
SIZEB
RTI
EFB/ORB
AEB
MBF1
Output
Register
Bus Matching
Common
Port Logic
(B and C)
BE
Output
C0–17
Port C
Control
Logic
CLKC
WENC
MBC
SIZEC
Bus Matching
Input
Flag Offset
Registers
(FIFO1)
(FIFO2)
CY7C43646AV
CY7C43666AV
CY7C43686AV
PRELIMINARY
Document #: 38-06026 Rev. ** Page 2 of 40
Pin Configurati o n
CY7C43646AV
CY7C43666AV
CY7C43686AV
TQFP
Top View
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
FS0/SD
MRS2
FS1/SEN
GND
CLKC
MRS1
MBA
MBF2
AEA
AFA
V
CC
PRS1
EFA/ORA
FFA/IRA
CSA
RENB
WENC
CSB
GND
FFC/IRC
EFB/ORB
AFC
AEB
V
CC
MBF1
MBB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
C12
C8
C9
C10
C11
C13
MBC
GND
C14
C15
C16
C17
VCC
PRS2
CLKB
GND
SIZEC
B16
B17
C0
C1
C2
C3
C4
C5
GND
SIZEB
C6
C7
RT1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A
2
B
0
GND
A
0
A
1
V
CC
SPM
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
B
9
B
8
B
7
V
CC
B
6
GND
B
5
B
4
B
3
B
2
B
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VCC
A29
GND
A30
A31
A32
A34
A35
GND
CLKA
ENA
W/RA
A12
A20
GND
A18
A19
A21
VCC
A22
GND
BE/FWFT
A23
A24
A25
A26
A27
A28
A33
72
71
70
69
68
67
66
65
B12
B10
B11
GND
B13
B14
B15
VCC
30
31
32
33
34
35
36
37
38
RT2
A10
A11
GND
A13
A14
A15
A16
A17
CY7C43646AV
CY7C43666AV
CY7C43686AV
PRELIMINARY
Document #: 38-06026 Rev. ** Page 3 of 40
Functional Description
The CY7C436X6AV is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous FIFO memory which sup-
ports clock frequencies up to 133 MHz and has read access
times as fast as 6 ns. Two independent 1K/4K/16K x 36 dual-
port SRAM FIFOs on board each chip buffer data in opposite
directions.
The CY7C436X6AV is a synchronous (clocked) FIFO, mean-
ing eac h port emp loys a sy nchronous interface . All data trans-
fers thro ugh a port a re gated to the LOW -to-HIGH tr ansition of
a port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or co-
incident. The enables for each port are arranged to provide a
simple bidirectional interface bet ween microprocessors and/or
buses w ith sy nc hron ous cont rol.
Comm unicatio n betwee n each port may bypa ss the FIF Os via
two mailbox registers. The mailbox registers’ width matches
the se lected P ort B o r Port C bus wi dth. Ea ch m ailbox regis ter
has a flag (MBF1 and MBF2) to signal when new mail has
been stored. Two kinds of reset are available on the
CY7C 436X6AV: Maste r Reset and Pa rtial Reset. Mast er Re-
set initi aliz es the re ad and writ e po inters t o the firs t locat ion of
the mem ory array, config ures the FIFO for Big o r Little En dian
byte arrangement and selects serial flag programming, parallel
flag pro gramm ing, o r one o f the three p ossib le de fault f lag of f-
set setti ngs , 8, 1 6, or 64 . Eac h FIF O ha s it s ow n inde pe nde nt
Master R eset pin, MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first
locatio n o f th e m em ory. Unli ke Ma ste r Res et, any s etti ngs e x-
isting prior to Partial Reset (i.e., programming method and par-
tial flag default offsets) are retained. Partial Reset is useful
since it permits fl ushing of the FIFO mem ory withou t changin g
any configuration settings. Each FIFO has its own indepen-
dent Partial Rese t pin, PRS1 and PRS2.
The CY7C436X6A V have two modes of operation CY standard
mode and FWFT mode: In the CY Standard Mode, the first
word written to an empty FIFO is deposited into the memory
array. A read operation is required to access that word (along
with all other words residing in memory). In the First-Word Fall-
Through Mode (FWFT), the first long-word (36-bit wide) writ-
ten to an empty FIF O appears automatically on the o utputs, no
read operati on requir ed (nev erthel ess, acce ssing subseq uent
words does necessitate a formal read request). The state of
the FWFT/STAN pin during FIFO operation determines the
mode in use.
Each FIFO has a combined Empty/Output Ready Flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
Flag (FFA/IRA and FFC/IRC). The EF and FF functions are
selected in the CY Standard Mode. EF indicates whether the
memory is empty or not. FF indicates whether the memory is
full or not. The IR and OR functions are selected in the First
Word Fall Through Mo de. IR indicates whether or not the FIFO
has avai lable me mory lo cat ions. OR shows wh ether the FIFO
has data av ailabl e for readin g or not. It mark s the presenc e of
valid data on the outputs.
Each FIFO has a programmabl e Almost Emp ty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFC).
AEA and AEB indica te when a selec ted numb er of wo rds read
from the FIFO memory achieve a predetermine d “almost emp-
ty state.” AFA and AFC indicate when a selected number of
words writt en to the memory ach ieve a predetermine d “almost
full stat e.” (See Note 50)
IRA, IRC, AFA, and AFC are synchronized to the port clock
that writes data into its array. ORA, ORB, AEA, and AEB are
synchronized to the port clock that reads data from its array.
Programmabl e offset fo r AEA, AEB, AF A, and AFC a re loaded
in parallel using Port A or in serial via the SD input. Three
default offset settings are also provided. The AEA and AEB
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AFA and AFC threshold can be set at 8, 16, or
64 locations from the full boundary . All these choices are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data pat hs. Such a width expan sion require s no a dditio nal ex -
ternal logic.
The CY7C436X6AV FIFOs are characterized for operation
from 0°C to 70°C commercial, and from –40°C to 8 5°C in dus -
trial. In put ESD protec tion i s greater than 20 01V, and l atch-up
is prevented by the use of guard rings.
Selection Guide
7C43646/66/86AV-7 7C43646/66/86AV-10 7C43646/66/86AV-15
Maximu m Frequency (MHz) 133 100 66.7
Maximum Access Time (ns) 6 8 10
Minimum Cycle Time (ns) 7.5 10 15
Minimum Data or Enable Set-Up (ns) 3 4 5
Minimum Data or Enable Hold (ns) 0 0 0
Maximum Flag Delay (ns) 6 8 10
Active Power Supply
Current (ICC1) (mA) Commercial 60 60 60
Industrial 60
7C43646AV 7C43666AV 7C43686AV
Density 1K x 36/x18x2 4K x 36/18x2 16K x 36/x18x2
Package 128 TQFP 128 TQFP 128 TQFP
CY7C43646AV
CY7C43666AV
CY7C43686AV
PRELIMINARY
Document #: 38-06026 Rev. ** Page 4 of 40
Pin Definitions
Signal Name Description I/O Function
A0–35 Port A Data I/O 36-bit bidirectional da ta port for side A.
AEA Port A Almost
Empty Flag O Program mable Almost Empty flag sy nchroniz ed to CLKA. It is LO W when the num ber
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2. (See Note 50)
AEB Port B Almost
Empty Flag O Program mable Almost Empty flag sy nchroniz ed to CLKB. It is LO W when the num ber
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1. (See Note 50)
AFA Port A Almost
Full Flag O Program mable Almost Ful l flag s ynch ronize d to CLKA. It is LO W when the numbe r of
empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1. (See Note 50)
AFC Port C Almost
Full Flag O Program mable Almost F ull flag synchron ized to CL KC. It is LOW when th e num ber of
empty loc ati ons in FIF O2 is less than or eq ual to the v alu e in th e A lm ost Full C offset
register, Y2. (See Note 50)
B0–17 Port B Data O 18-bit output data port for port B.
BE/FWFT BigEndian/
First-Word Fall-
Through Select
I This is a dua l-purpose pin . During Mast er Re set, a HIGH on BE wi ll sel ect Bi g Endia n
operation. In this case, depending on the bus siz e, the most significant byte or word on
Port A is tra nsferred to Port B first for A-to -B data f low. For data fl owing fro m port C to
Port A, the first word/byte written to Port C will come out as the most significant
word/byte on Port A. A LOW on BE wi ll select Little Endia n operation . In this ca se, the
least s ignificant byte o r word on Port A is transferred to Port B first fo r A-to-B data flow.
For data flowing from port C to Port A, the first word/byte written to Port C will come
out as the least signi ficant word/byte o n port A. After Master Reset, this pin selec ts the
timing mode . A HIGH on FWFT selects CY Standard Mode, a LOW se lects First-W ord
Fall-Through Mode. Once the timing mode has been selected, the level on FWF T must
be static throughout device operation.
C0–17 Port CData I 18-bit input data port for port C.
CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through Port A and can
be asyn chronous or coin cident to CLKB or C LKC. FF A /IRA, EFA/ORA, AFA, and AEA
are all sy nchronized to the LOW-to-HIGH transition of CLKA.
CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through Port B and can
be asyn chron ous o r coin ciden t to C LKA o r CLKC. EFB/OR B and AEB are all synchro-
nized to the LOW-to-HIGH transition of CLKB.
CLKC Port C Clock I CLKC is a continuous clock that synchronizes all data transfers through Port C and can
be asynchronous or coincident to CLKA or CLKB. FFC/IRC and AFC are all synchro-
nized to the LOW-to-HIGH transition of CLKC.
CSA Port A Chip
Select ICSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip
Select ICSB must be LO W to ena bl e a L O W -to H IG H tran si tio n of C LKB to rea d fro m Port B.
The B0–17 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA Port A Empty/
Output Ready
Flag
O This is a dual-function pin. In the CY Standard Mode, the EF A function is selected. EF A
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selec ted. ORA ind icates t he presence of valid da ta on A0–35 outputs, avail-
able for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.
EFB/ORB Port B Empty/
Output Ready
Flag
O This is a dual-function pin. In the CY Standard Mode, the EFB function is selected. EFB
indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selec ted. ORB ind icates t he presence of valid da ta on B0–17 outputs, avail-
able for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.
ENA Port A Enable I ENA must be HIGH to ena ble a LOW -to-HIGH transition of CLKA to read or write data
on Port A.
RENB Port B Read En-
able I RENB must be HIGH to en abl e a LO W -t o-H IGH trans it ion of CLKB to rea d data from
Port B.
CY7C43646AV
CY7C43666AV
CY7C43686AV
PRELIMINARY
Document #: 38-06026 Rev. ** Page 5 of 40
FFA/IRA Port A Full/Input
Ready Flag O This is a dual-function pin. In the CY Standard Mode, the FFA function is selected. FF A
indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function
is selected. IRA indicates whether or not there is space available for writing to the FIFO1
memory. FFA/IRA is synchronized to the LO W-to-HIGH transition of CLKA.
FFC/IRC Port C Full/Input
Ready Flag O This is a dual-function pin. In the CY Standard Mode, the FFC function is selected. FFC
indicates whether or not the FIFO2 memory is full. In the FWF T mode, the IRC function
is selected. IRC indicates whether or not there is space available for writing to the FIFO2
memory. FFC/IRC is synchronized to the LOW-to-HIGH transition of CLKC.
FS1/SEN Flag Offset
Select 1/Serial
Enable
I FS1/SEN and FS0/SD are dual-purpose inputs us ed for flag offset register program-
ming. D uring Master Reset, FS1/SEN and FS0/SD, t ogether w ith SPM, selec t the flag
offset programming method. Three offset register programming methods are available:
automati ca lly loa d one of thre e pre se t val ues (8, 16 , or 64 ), para lle l lo ad fro m Por t A,
and serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an en abl e s ynchronous to th e L O W -to -H IGH tra nsi tio n of C L KA.
When FS1/SEN is LOW, a rising edge on C L KA loa ds the b it p res ent on F S 0/SD i nto
the X and Y registers. T he number of bit writes required to pr ogram the of fset register s
is 40 fo r the C Y7C436 46AV, 48 for t he C Y7C43666 AV, and 56 fo r the CY 7C436 86AV.
The first bit wri te s tore s th e Y-register MSB and th e la st b it write stores the X-registe r
LSB.
FS0/ SD Flag Offset
Select 0/Serial
Data
I
MBA Port A Mailbox
Select I A HIGH level on MBA chooses a mailbox re gister for rea d or write operation on Port A.
When a read operation is performed on Port A, a HIGH level on MBA selects data from
the Mail2 register for output and a LOW level selects FIFO2 output register data for
output. When writing data into Port A, a HIGH level on MBA will write the data into Mail1
register and a LOW will write into FIFO1.
MBB Port B Mailbox
Select I When a read operation is performed on Port B, a HIGH level on MBB selects data from
the Mail1 register for output and a LOW level selects FIFO1 output register data for
output.
MBC Port C Mailbox
Select I When writing data into Port C, a HIGH level on MBC will write the data into Mail2 register
and a LOW will write into FIFO2.
MBF1 Mail1 Register
Flag OMBF1 is set LOW by a LOW -to-HIGH transiti on of CL KA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW -to -HIGH transi tion o f CL KB when a Port B read is s elect ed and MBB
is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2 Mail2 Register
Flag OMBF2 is set LOW by a LO W-to-HIGH trans iti on o f CLKC tha t write s da ta to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW -to -HIGH transi tion o f CL KA when a Port A read is s elect ed and MBA
is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1 FIFO1 Master
Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag default
of fsets for FIF O1. It also co nfigures Port B for bus size an d endian arra ngement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
MRS2 FIFO2 Master
Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2 selects
one of three programmabl e flag default offsets for FIFO2. Four LOW-to-HIGH transi-
tions of C LKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is
LOW.
PRS1 FIFO1 Pa rtia l
Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or par-
allel), and programmable flag settings are all retained.
PRS2 FIFO2 Pa rtia l
Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port A output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or par-
allel), and programmable flag settings are all retained.
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43646AV
CY7C43666AV
CY7C43686AV
PRELIMINARY
Document #: 38-06026 Rev. ** Page 6 of 40
Maximum Ratings[1]
(Above w hi ch the useful life m ay be im pai red. For user guid e-
lines, not tes ted .)
Storage Temperature .......................................−65°C to +150°C
Ambient Temperature with
Power Applied....................................................−55°C to +125°C
Supply Voltage to Ground Potential.................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State [2] ..........................................−0.5V to VCC+0.5V
DC Input Voltage[2] .......................................−0.5V to VCC+0.5V
Output Current into Outputs (LOW).............................20 mA
Static Disc harge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Notes:
1. Stresses beyond tho se listed under “Absolute Maximum Rating s” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
3. Oper ating VCC Rang e for –7 speed is 3.3V ± 5%.
RENB Port B Read
Enable I RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on
Port B.
RT1 FIFO1
Retransmit I A LOW strobe on this pin will retransmit data on FIFO1. This is achieved by bringing
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
RT2 FIFO2
Retransmit I A LOW strobe on this pin will retransmit data on FIFO2. This is achieved by bringing
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
SIZEB Bus Size Select I A HIGH on this pin selects byte bus (9-bit) size on Port B. A LOW on this pin selects
word (18-bit) bus size. SIZEB works with BE to select the bus size and end ian arrange-
ment for Port B. The level of SIZEB must be static throughout device operation.
SIZEC Bus Size Select I A HIGH on this pin selects byte bus (9-bit) size on Port C. A LOW on this pin selects
word (18-bit) bus size. SIZEC works with BE to select the bus size and e ndian arrange-
ment for Port C. The level of SIZEC must be static throughout device operation.
SPM Serial
Programming I A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin
selects parallel programming or default offsets (8, 16, or 64).
W/RA Port A
Write/Read
Select
I A HIGH sele cts a w ri te operation and a LO W se lec ts a re ad o pe r atio n o n Po rt A fo r a
LOW -to-HIGH transiti on of CLKA. The A0–35 out puts are i n the HIGH impedance s tate
when W/RA is HIGH.
WENC Port C Write
Enable I WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on
Port C.
Pin Definitions (continued)
Signal Name Description I/O Function
Operating Range
Range Ambient
Temperature VCC[3]
Commercial 0°C to +7 0°C 3.3V ± 10%
Industrial −40°C to +85°C 3.3V ± 10%
CY7C43646AV
CY7C43666AV
CY7C43686AV
PRELIMINARY
Document #: 38-06026 Rev. ** Page 7 of 40
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
7C43646/66/86AV
UnitMin. Max.
VOH Output HIGH Vo ltage VCC = 3.0V,
IOH = −2.0 mA 2.4 V
VOL Output LOW Voltage VCC = 3.0V,
IOL = 8.0 mA 0.5 V
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LOW Voltage −0.5 0.8 V
IIX Input Leakage Current VCC = Max. −10 +10 µA
IOZL
IOZH Output OFF, High Z
Current VSS < VO< VCC −10 +10 µA
ICC1[4] Active Power Supply
Current Com’l60 mA
Ind 60 mA
ISB[5] Average Standby
Current Com’l10 mA
Ind 10 mA
Capacitance[6]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.3V 4pF
COUT Output Capacitance 8pF
AC Test Loads and Waveforms (-10 & -15)
AC Test Loads and Waveforms (-7)
Notes:
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
5. All inputs = VCC – 0.2V, except CLKA, CLKB and CLKC (which are at frequency = 0 MHz). All outputs are unloaded.
6. Tested initially and after any design or process changes that may affect these parameters.
7. CL = 5 pF for tDIS.
3.0V
3.3V
OUTPUT
R2=680ΩCL=30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
R1=330Ω
[7]
3.0V
GND
90%
10%
90%
10%
≤3ns ≤3ns
ALL INPUT PULSES
I/O
50Ω
V
CC
/2
Z0=50Ω
CY7C43646AV
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 8 of 40
Switching Characteristics Over the Operating Range
Parameter Description
7C43646/
66/86AV
–7
7C43646/
66/86AV
–10
7C43646/
66/86AV
–15
UnitMin. Max. Min. Max. Min. Max.
fSClock Frequency, CLKA, CLKB, or CLKC 133 100 67 MHz
tCLK Clock Cycle Time, CLKA, CLKB, or CLKC 7.5 10 15 ns
tCLKH Pulse Duration, CLKA, CLKB, or CLKC HIGH 3.5 4 6 ns
tCLKL Pulse Duration, CLKA, CLKB, or CLKC LOW 3.5 4 6 ns
tDS Set-Up Time, A0–35 before CLKA↑, a nd C0–17 befo re CLKC↑3 4 5 ns
tENS Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA↑;
RENB and MBB before CLKB↑, and WENC and MBC before
CLKC↑
3 4 5 ns
tRSTS Set-Up Time, M RS1, MRS2, PRS1, PRS2, RT1 or RT2 LOW
before CLKA↑ or CLKB↑[8] 2.5 4 5 ns
tFSS Set-Up Time, FS0 and FS1 before MRS1 and MRS2 HIGH 5 7 7.5 ns
tBES Set-Up Time, BE/FWFT before MRS1 and MRS2 HIGH 5 7 7.5 ns
tSPMS Set-Up Time, SPM before MRS1 and MRS2 HIGH 5 7 7.5 ns
tSDS Set-Up Time, FS0/SD before CLKA↑3 4 5 ns
tSENS Set-Up Time, FS1/SEN before CLKA↑3 4 5 ns
tFWS Set-Up Time, FWFT be fore CLKA↑0 0 0 ns
tDH Hold Time, A0–35 after CLKA↑, and C0–17 after CLKC↑0 0 0 ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; RENB
and MBB after CLKB↑, and WENC and MBC after CLKC↑0 0 0 ns
tRSTH Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 LOW after
CLKA↑ or CLKB↑[8] 1 2 2 ns
tFSH Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH 1 1 2 ns
tBEH Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 1 1 2 ns
tSPMH Hold Time, SPM after MRS1 and MRS2 HIGH 1 1 2 ns
tSDH Hold Time, FS0/SD after CLKA↑0 0 0 ns
tSENH Hold Time, FS1/SEN after CLKA↑0 0 0 ns
tSPH Hold Time, FS1/SEN HIGH af ter MRS1 and MRS2 HIGH 1 1 2 ns
tSKEW1[9] Skew Time betw een CLKA↑ and CLKB↑ and CLKA↑ and
CLKC↑ for EFA/ORA, EFB/ORB, FFA/IRA, and FFC/IRC 5 5 7.5 ns
tSKEW2[9] Skew Time betw een CLKA↑ and CLKB↑ and CLKA↑ and
CLKC↑ for AEA, AEB, AFA, AFC 7 8 12 ns
tAAccess Time, CLKA↑ to A0–35 and CLKB↑ to B0–17 1618310 ns
tWFF Propagation Delay Time, CLKA↑ to FFA/IRA and CLKC↑ to
FFC/IRC 1618210 ns
tREF Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to
EFB/ORB 1618210 ns
tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 1618110 ns
tPAF Propagation Delay Time, CLKA↑ to AFA and CLKC↑ to AFC 1618110 ns
Notes:
8. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
9. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
CY7C43646AV
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 9 of 40
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH
and CLKB↑ to MBF2 LOW or MBF1 HIGH 0608012 ns
tPMR Propagation Delay Time, CLKA↑ to B0–17[10] and CLKC ↑ to
A0–35[11] 1 7 2 11 312 ns
tMDV Propagation Delay Time, MBA to A0–35 valid and MBB to B0–17
Valid 1629311 ns
tRSF Propagation Delay Time, MRS1 or PRS1 LOW to AEB LO W,
AFA HIGH, FF A / IRA LOW , EFB /ORB LOW an d MBF1 HIGH
and MRS2 or PRS2 LOW to AEA LOW , AFC HIGH, FFC / IRC
LOW, EFA /ORA LOW and MBF2 HIGH
1 6 1 10 115 ns
tEN Enable Time, CSA or W/RA LOW to A0–35 Active and CSB
LOW and RENB HIGH to B0–17 Active 1628210 ns
tDIS Disable Time, CSA or W/RA HIGH to A0–35 at High Impedance
and CSB HIGH or RENB LOW to B0–17 at High Impedance 1 5 1 6 1 8 ns
tRTR Re transmit Recovery Time 90 90 90 ns
Notes:
10. Writing data to the Mail1 register when the B0–17 outputs are active and MBB is HIGH.
11. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
Switching Characteristics Over the Operating Range (continued)
Parameter Description
7C43646/
66/86AV
–7
7C43646/
66/86AV
–10
7C43646/
66/86AV
–15
UnitMin. Max. Min. Max. Min. Max.
CY7C43646AV
CY7C43666AV
CY7C43686AV
PRELIMINARY
Document #: 38-06026 Rev. ** Page 10 of 40
Switching Waveforms
Notes:
12. PRS1 and MBC must be HIGH during Master Reset until the rising edge of FFA/I RA goes HIGH.
13. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.
FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight
CLKA
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tSPMS tSPMH
tBES tBEH
tRSTH
tRSTS
tFWS
CLKB
MRS1
BE/FWFT
SPM
FS1/SEN,
FS0/SD
FFA/IRA
EFB/ORB
AEB
AFA
MBF1
[12, 13]
tRSF
tRSF
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 1 1 of 40
Notes:
14. PRS2 and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.
15. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than the case where BE/FWFT is LOW.
Switching Waveforms (continued)
FIFO2 Master Reset Loading X1 and Y1 with a Preset Value of Eight
CLKC
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tSPMS tSPMH
tBES tBEH
tRSTH
tRSTS
tFWS
CLKA
MRS2
BE/FWFT
SPM
FS1/SEN,
FS0/SD
FFC/IRC
EFA/ORA
AEA
AFC
MBF2
[14, 15]
tRSF
tRSF
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 12 of 40
Notes:
16. MRS1 must be HIGH during Partial Reset.
17. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.
18. MRS2 must be HIGH during Partial Reset.
19. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than the case where BE/FWFT is LOW.
Switching Waveforms (continued)
FIFO1 Partial Reset (CY Standard and FWFT Modes)
tRSF
tRSF
tRSF
tRSTS tRSTH
CLKA
CLKB
PRS1
FFA/IRA
EFB/ORB
AEB
AFA
MBF1
[16, 17]
tWFF
tRSF
tRSF
FIFO2 Partial Reset (CY Standard and FWFT Modes)
tRSF
tRSF
tRSF
tRSTS tRSTH
CLKC
CLKA
PRS2
FFC/IRC
EFA/ORA
AEA
AFC
MBF2
[18, 19]
tWFF
tRSF
tRSF
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Document #: 38-06026 Rev. ** Page 13 of 40
Notes:
20. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles. FIFO can only be programmed in parallel
when FF A/IRA is HIGH.
21. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC for FFC/IRC to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one cycle later than shown.
22. It is not necessary to program offset register bits on consecutive clock cycles. Attempts to write into FIFO memory are ignored until FF A/IRA is set HIGH.
23. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC for FFC/IRC to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one cycle later than shown.
24. Pr ogr am ma ble offsets are w ritte n serial ly to the SD i npu t in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
Switching Waveforms (continued)
Paral lel Programming of the Almost-Full Flag and Almost-Empty Flag Offs et Values after Reset
(CY Standard and FWFT Modes)
tWFF
tFSS
tDS
tFSS tFSH
tFSH
tENS tENH
tDH
tSKEW1[21]
AFA Offset (Y1) AFC Offset (Y2) First Word to FIFO1
CLKA
MRS1, MRS2
SPM
FS1/SEN,
FS0/SD
FFA/IRA
ENA
A0 − 35
CLKC
FFC/IRC
[20]
AEB Offset (X1) AEA Offset (X2)
tWFF
Serial Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes)
tFSS tSPH tSENS tSENH tSENH
tSENS
tSDH
tSDS tSDH
tSDS
tSKEW1[23]
tWFF
AFA Offset (Y1) MSB
tFSS tFSH
tWFF
CLKA
MRS1, MRS2
SPM
FFA/IRA
FS1/SEN
CLKC
FFC/IRC
[22, 24]
FS0/SD [24]
AEA Offset (X2) LSB
tFSS tFSH
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 14 of 40
Note:
25. Written to FIFO1.
26. If W/RA switches from read to write before the assertion of CSA, tENS=tDIS+tENS.
Switching Waveforms (continued)
tCLKH tCLKL
tENS tENH
tENS tENH
tENS tENH
tENS tENH
tDS tDH
tENS tENH tENS tENH
HIGH
W1[25] W2[25]
tCLK
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A0–35
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
[26]
tENS
tENS tENH
tENS tENH
tDS tDH
tENS
HIGH tENH
tENH
CLKC
FFC/IRC
MBC
WENC
C0–17
Port C Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CY7C43646AV
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 15 of 40
Note:
27. Unused bytes B9–17 contain all zeroes for byte-size reads.
Switching Waveforms (continued)
Port C Byte Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
tENS tENH
tENS tENH
tDS tDH
tENS
HIGH tENH
tENH
CLKC
FFC/IRC
MBC
WENC
C0–8
OR
tDIS
tENStENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
tA
tA
tA
tA
Previous Data
Read 1
Read 1
Read 2
Read 2
Read 3
Read 3
Read 4
Read 4
Read 5
No Operation
HIGH
CLKB
EFB/ORB
CSB
MBB
RENB
B0–8
(Standard Mode)
B0–8
(FWFT Mode)
Port B Byte Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)[27]
CY7C43646AV
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Document #: 38-06026 Rev. ** Page 16 of 40
Note:
28. Read f rom FIFO2.
Switching Waveforms (continued)
OR
tDIS
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
Previous Data
Read 1
Read 1
Read 2
Read 2
Read 3
No Operation
CLKB
EFB/ORB
CSB
MBB
ENB
B0–17
(Standard Mode)
B0–17
(FWFT Mode)
Port B Word Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
OR
tCLKH tCLKL
tENS
tDIS
tENS tENH
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[28] W2[28]
W1[28] W2[28]
W3[28]
Previous Data
No Operation
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A0−35
(Standard Mode)
A0−35
(FWFT Mode)
Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
[26]
CY7C43646AV
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 17 of 40
Notes:
29. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO2, respectively.
30. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO 1 ou tpu t
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and
load of the first word to the output register may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tCLK
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO1 Empty
LOW
LOW
Old Data in FIFO1 Output Register W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[30]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A0–35
CLKB
EFB/ORB
CSB
MBB
RENB
B0–17
ORB Flag Timing and First Data Word Fall Through w hen FIFO1 is Empty (FWFT Mode)[29]
CY7C43646AV
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 18 of 40
Notes:
31. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.
32. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO1 Empty
LOW
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[32]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A0–35
CLKB
EFB/ORB
CSB
MBB
RENB
B0–17
EFB Flag Timing and First Data Read Fall Through when FIFO1 is
Empty (CY Standard Mode)[31]
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 19 of 40
Notes:
33. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
34. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output
register in three CLKA cycles. If the time between the rising CLKC edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and
load of the first word to the output register may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tA
W1
tDH
HIGH
FIFO2 Empty
LOW
LOW
LOW
Old Data in FIFO2 Output Register W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW1[34]
tCLK
tDS
CLKC
WENC
FFC/IRC
C0–17
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A0–35
ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
[33]
(FWFT Mode)
tENH
tENS
MBC
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 20 of 40
Notes:
35. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
36. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKC edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
tDH
HIGH
FIFO2 Empty
LOW
LOW
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[36]
CLKC
MBC
WENC
FFC/IRC
C0–17
CLKA
EFA/ORA
CSA
W/RA
MBA
ENA
A0–35
[35]
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 21 of 40
Notes:
37. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
38. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time bet wee n the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
FIFO1 Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[38]
tDH
tDS
tENH
tENS
Previous Word in FIFO1 Output Register Next Word From FI FO1
To FIFO1
CLKB
CSB
MBB
RENB
EFB/ORB
B0–17
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A0–35
IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)[37]
LOW
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 22 of 40
Note:
39. tSKEW1 i s the minimum time between a rising CLKB edge and a rising CLKA edge for FF A to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
FIFO1 Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[39]
tDH
tDS
tENH
tENS
Previous Word in FIFO1 Output Register Next Word From FIFO1
CLKB
CSB
MBB
RENB
EFB/ORB
B0–17
CLKA
FFA/IRA
CSA
W/RA
MBA
ENA
A0−35
FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode)[37]
Read Disabled
LOW
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Document #: 38-06026 Rev. ** Page 23 of 40
Notes:
40. If Port C size is word or byte, IRC is set LOW by the last word or byte write of the long word, respectively.
41. tSKEW1 i s the minimum time between a rising CLKA edge and a rising CLKC edge for IRC to transition HIGH in the next CLKC cycle. If the time between the
rising CLKA edge and rising CLKC edge is less than tSKEW1, then the transition of IRC HIGH may occur one CLKC cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
LOW
HIGH
FIFO2 Full
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[41]
tDH
tDS
tENH
tENS
Previous Word in FIFO2 Output Register Next Word From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A0–35
CLKC
FFC/IRC
MBC
WENC
C0–17
IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)[40]
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PRELIMINARY
Document #: 38-06026 Rev. ** Page 24 of 40
Notes:
42. If Port C size is word or byte, FFC is set LOW by the last word or byte write of the long word, respectively.
43. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKC edge for FFC to transition HIGH in the next CLKC cycle. If the time between
the rising CLKA edge and rising CLKC edge is less than tSKEW1, then the transition of FFC HIGH may occur one CLKC cycle later than shown.
Switching Waveforms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
LOW
HIGH
FIFO2 Full
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[43]
tDH
tDS
tENH
tENS
Previous Word in FIFO2 Output Register Next Word From FIFO2
To FI FO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/IRA
A0–35
CLKC
FFC/IRC
MBC
WENC
C0–17
FFC Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode)[42]
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Document #: 38-06026 Rev. ** Page 25 of 40
Notes:
44. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW , RENB = HIGH, MBB = LOW). Data in the FIFO1 output register has
been read from the FIFO.
45. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
46. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between
the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
47. FIFO2 Write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
48. If Port C size is word or byte, tSKEW2 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
49. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between
the rising CLKC edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
50. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to 2 clock cycles for flag deassertion, but the flag will always
be asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to “Designing
with CY7C436xx Synchronous FIFOs” application note for more details on flag uncertainties.
Switching Waveforms (continued)
CLKA
ENA
CLKB
AEB
RENB
Tim ing f or AEB when FIFO1 is Almost Empty (CY Standard and FWFT Modes)[44, 45, 50]
X1 Word in FIFO1
tENH
tENS
tSKEW2[46]
tPAE
tPAE
tENS tENH
(X1+2)Words in FIFO1
tENS tENH
tENH
tENS X1 Words in FIFO
(X1+1) Words in FIFO1 (X1+2) Words in FIFO1
CLKC
WENC
CLKA
AEA
ENA
Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes)[47, 48, 50]
X2 Word in FIFO2
tENH
tENS
tSKEW2[49]
(X2+2)W o rds i n FIF O2
tPAE
tPAE
tENS tENH
tENS tENH
tENH
tENS X2 Word s in FIFO
(X2+1) Words in FIFO2 (X2+2) Words in FIFO2
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Notes:
51. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW , MBB = LOW). Data in the FIFO1 output register has been read from the
FIFO.
52. D = Maximum FIFO Depth =1K for the CY7C43646AV, 4K for the CY7C43666AV, and 16K for the CY7C43686AV.
53. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.
54. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
55. If Port C size is word or byte, AFC is set LOW by the last word or byte write, respectively.
56. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between
the rising CLKC edge and rising CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKA cycle later than shown.
Switching Waveforms (continued)
Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)
tENH
tENS
tPAF
[D–(Y1+1)] Words in FIFO1 (D–Y1)Words in FIFO1
CLKA
ENA
AFA
CLKB
RENB
[50, 51, 52, 53]
tPAF
tENS tENH
tSKEW2[54]
[D–(Y1+2)]Words in FIFO1
tENS tENH
tENH
tENS
tPAF
[D–(Y2+1 )] Word s in FIFO2 (D–Y2)Wor ds in FIFO 2
CLKC
WENC
AFC
CLKA
ENA
Timing for AFC when FIFO2 is Almost Full (CY Standard and FWFT Modes)[47 , 50 , 52 , 55 ]
tENS tENH
tPAF [D-(Y2+2)] words in FIF O
tSKEW2[56]
tENS tENH
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Note:
57. If Port B is configured for word size, data can be written to the Mail1 register using A0–17 (A18–35 are “Don’t Care” inputs). In this first case B0–17 will have
valid data). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are “Don’t Care” inputs). In this second case,
B0–8 will have valid data (B9–17 will be indeterminate).
Switching Waveforms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO1 Output Register W1 (Remains valid in Mail1 Register after read)
CLKA
CSA
W/RA
MBA
ENA
A0–35
CLKB
MBF1
CSB
MBB
RENB
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)[57]
B0–17
[26]
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Document #: 38-06026 Rev. ** Page 28 of 40
Notes:
58. If Port C is configured for word size, data can be written to the Mail2 register using C0–17. In this first case A0–17 will have valid data (A18–35 will be
indeterminate). If Port C is configured for byte size, data can be written to the Mail2 Register using C0–8 (C9–17 are “Don’t Car e” inputs). In this second case,
A0–8 will have valid data (A9–35 will be indeterminate).
59. Retransmit is performed in the same manner for FIFO2.
60. Clocks are free running in this case. CY standard mode only. Write operation should be prohibited one write clock cycle before the falling edge of RT1, and
during the retransmit operation, i.e, when RT1 is LOW and tRTR after the RT1 rising edge.
61. The Empty and Full flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
62. For the AEA, AEB, AFA, and AFC flags, two clock cycle are necessary after tRTR to up date t hese f lags.
Switching Waveforms (continued)
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO2 Output Register W1 (Remains valid in Mail2 Register after read)
CLKC
MBC
WENC
C0–17
CLKA
MBF2
CSA
W/RA
MBA
ENA
A0−35
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes ) [58]
[26]
FIFO1 Retransmit Timing
RENB
RT1
tRTR
EFB/FFA
[59, 60, 61, 62]
tRSTS tRSTH
CLKA
CLKB
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Signal Descript ion
Master Reset (MRS1, MRS2)
Each of the two FIFO me mories of the CY 7C4 36X6 AV under-
goes a complete reset by taking its associated Master Reset
(MRS1, MRS2) input LOW for at least four Port A clock (CLKA)
and four Port B clock (CLKB) LOW-to-HIGH transitions. The
Master Reset inputs can switch asynchronously to the clocks.
A Master Reset initializes the internal read and write pointers
and forces the Full/Input Ready flag (FF A/IRA, FFC/IRC) LOW ,
the Empty/Output Ready flag (EF A/ORA, EFB/ORB) L OW , the
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFC) HIGH. A Master Res et also forces the Mailbox flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Master Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycle s to begin normal operation. A Master R e-
set must be performed on the FIFO after power up, before data
is written to its memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latche s the val ue of the Bi g End ian (BE ) inpu t or
determ ining the order by which bytes are transferred through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input lat ches t he valu es of th e Flag s elect (F S0, FS1) and Se-
rial Program ming Mode (SPM) inpu ts for choosi ng the Almost
Full and Almost Empty offset programming method (see Al-
most Empty and Almost Full flag offset programming below).
Partial Reset (PRS1, PRS2)
Each of the two FIFO me mories of the CY 7C4 36X6 AV under-
goes a limited reset by taking its associated Partial Reset
(PRS1, PRS2) in put LOW for at least four Port A clock (CLKA)
and four Port B clock (CLKB) LOW-to-HIGH transitions. The
Partial Reset inputs can switch asynchronously to the clocks.
A Partial Rest initializes the internal read and write pointers
and forces the Full/Input Ready flag (FF A/IRA, FFC/IRC) LOW ,
the Empty/Output Ready flag (EF A/ORA, EFB/ORB) LOW , the
Almost Empty flag (AEA, AEB) LOW, and the Almost Full flag
(AFA, AFC) H IGH. A Partial Rese t also forc es the Mailbox fla g
(MBF1, MBF2) of the parallel mailbox register HIGH. After a
Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH
after two clock cycles to begin normal operation.
What ever fl ag offsets, program ming met hod (pa rallel or seri-
al), and timing mode (FWFT or CY Standard mode) are cur-
rently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be in-
convenient.
Big Endian/Fir st-Word Fall-Through (BE/FWFT)
This is a dual-purpo se pin. At the time of Mast er Reset, the BE
select function is active, permitting a choice of big or little en-
dian byte arrangement for data written to or read from Port B.
This sel ectio n determ ines th e order by which by tes (or word s)
of data are trans ferred throug h this port. For the fol lowing illu s-
trations, assume that a byte (or word) bus size has been se-
lected for Port B.
A HIGH on t he BE/FWFT input when th e Master Reset (MRS1
and MRS2) inputs go from LOW to HIG H will sele ct a Big En-
dian arrangement. When data is moving in the direction from
Port A to Port B, the most significant byte (word) of the long-
word written to Port A will be transferred to Port B first; the least
signifi cant byte (word) of the long-word writt en to Port A will b e
transferre d to Port B last. Wh en data is moving in the direc tion
from Port C to Port A, the byte (wo rd) written to Port C first will
be transferred to Port A as the most significant byte (word) of
the long-word; the byte (word) written to Port C last will be
transferre d to Port A as the le ast si gni fic an t by te (w ord) o f th e
long-word.
A LOW on the BE/FW FT input when the Master Reset (MRS1
and MRS2) inputs go from LOW to HIGH will select a Little
Endian arrangement. When data is moving in the direction
from Port A to Port B, the least signific ant byte (word) of the
long word written to Port A will be transferred to Port B first; the
most significant byte (word) of the long word written to Port A
will be transferred to Port B last. When data is moving in the
direction from Port C to Port A, the byte (word) written to Port
C first will be tra nsf erred to port A as the least signific an t by te
(word) of the long-word; the byte (word) written to Port C last
will be transferred to Port A as the most significant byte (word)
of the long- word.
After Mast er Reset, the F WF T selec t function is active, permi t-
ting a choice between two possible timing modes: CY Stan-
dard Mode or First-Word Fall-Through (FWFT) Mode. Once
the Ma ster Reset (MRS1, MRS2) input is HIGH, a HIGH on the
BE/FWFT input at the second LOW-to-HIGH transition of
CLKA (for FIFO1) and CLKC (for FIFO2) will select CY Stan-
dard Mode. This mode uses the Empty Flag function (EFA,
EFB) to ind icate whether or not ther e are any words pres ent in
the FIFO m em ory. It use s the Fu ll Fla g f unc tio n (FFA, FFC) to
indicate whether or not the FIFO memory has any free space
for writing. In CY Standard Mode, every word read from the
FIFO, including the first, must be requested using a formal
read operation.
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW
on the BE/FWFT input at the second LOW-to-HIGH transition
of CLKA (for FIFO1) and CLKC (for FIFO2) will select FWFT
Mode. This mode uses the Output Ready function (ORA,
ORB) to indic ate whether or not there is val id da ta at th e da ta
outputs (A 0–35 or B0–17). It also use s the In put R eady f unctio n
(IRA, IRC) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT Mode, the first word
written to an empty FIFO goes directly to data outputs, no read
request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Master Reset, the level applied to the BE/FWFT in-
put to choose the desired timing mode must remain static
throughout the FIFO operation.
Programming the Almost Empty and Almost Full Flags
Four registers in the CY7C436X6A V are used to hold the offset
values for the Almost Em pty a nd Alm ost Full fla gs. The Po rt B
Almost Empty flag (AEB) offset register is labeled X1 and the
Port A Almos t Empty flag (AEA) offset register is labeled X2.
The Port A Almost Full flag (AFA) offset register is labeled Y1
and the Po rt C Al most F ull fla g (AFC) offset register is labeled
Y2. The index of each register name corresponds with preset
values during the reset of a FIFO, programmed in parallel us-
ing the FIFO’s Port A data inputs, or programmed in serial
using the Serial Data (SD) input (see Table 1).
To load a FIFO’s Almost Empty fl ag and Almos t Full flag of fset
registers with one of the three preset values listed in Ta bl e 1 ,
the Serial Program Mode (SPM) and at least one of the flag-
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Document #: 38-06026 Rev. ** Page 30 of 40
select inputs must be HIGH during the LOW-to-HIGH transition
of its Master Reset input (MRS1 and MRS2). For example, to
load the preset value of 64 into X1 and Y1, SPM, FS0 and FS1
must be HIG H when FIFO 1 reset (MRS1) retur ns HIGH. Flag-
offset registers associated with FIFO2 are loaded with one of
the preset values in the same way with Master Reset (MRS2).
When using one of the preset values for the flag offsets, the
FIFOs can be reset simultaneously or at different times.
To program the X1, X2, Y1, and Y2 registers in parallel from
Port A, perfo rm a Mas ter Rese t on both F IFOs simul taneousl y
with SPM HIGH and FS0 and FS1 LOW during the LOW-to-
HIGH transition of MRS1 and MRS 2. After this reset is com-
plete, th e first fou r writes do not store data in RAM but load the
offset registers in the order Y1, X1, Y2, X2. The Port A data
inputs used by the offset registers are (A0–9), (A0–11), or
(A0–13), for the CY7C436X6A V , respectively . The highest num-
bered input is used as the most significant bit of the binary
number in each ca se. Valid programm ing val ues for the regis-
ters range from 0 to 1023 fo r the CY7C436 46AV ; 0 to 4095 for
the CY7C43666AV; 0 to 16383 for the CY7C43686AV. (See
footnote #50) After all the offset registers are programmed
from Port A, the Port C Full/Input Ready (FFC/IRC) is set HIGH
and both FIFOs begin normal operation.
To program the X1, X2, Y1, and Y2 registe rs serial ly, initiate a
Master Reset with SPM LOW, FS0/SD LOW, and FS1/SEN
HIGH during the LOW-t o-HIGH transition of MRS1 and MRS2.
After this reset is complete, the X and Y register values are
loaded bit-wise through the FS0/SD input on each LOW-to-
HIGH transi tio n of CLKA th at th e FS1 /SEN input is LOW. 40-,
48-, or 5 6-bi t w ri tes are needed to com pl ete th e p r ogra mmin g
for the CY7C436X6AV, respectively. The four registers are
written in the order Y1, X1, Y2, and, finally, X2. The first-bit
write stores the most significant bit of the Y1 register and the
last-bit write stores the least significant bit of the X2 register.
When the opt ion to p rogram th e of fset re gisters serially is ch o-
sen, th e Po rt A Ful l/In put R ea dy (FFA/IRA) flag remains LO W
until all register bits are written. FFA/IRA is set HIGH by the
LOW -to -HIGH trans itio n of CLKA af ter the last bit is lo ade d to
allow normal FIFO operation. The Port C Full/Input ready
(FFC/IRC) flag also remains LOW throughout the serial pro-
gramming process, until all register bits are written. FFC/IRC
is set HIGH by the LOW-to-HIGH transition of CLKC after the
last bit is loaded to allow normal FIFO2 operation.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard and FWFT modes.
FIFO Write/Read Operation
The state of the Port A data (A0–35) lines is controlled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-impedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when both CSA and W/RA are LOW.
Data is loa ded into FIFO1 from the A0–35 inputs o n a LOW - to-
HIGH transition of CLKA when CSA is LOW, W/RA is HIGH,
ENA is HIGH, MBA is LOW, and FFA/IRA is HIGH. Data is read
from FIFO2 to the A0–35 outputs by a LOW -to-HIGH transitio n
of CLKA when CSA is LOW, W/RA is LOW , ENA is HIGH, MBA
is LOW, and EF A/ORA is HIGH (see Table 2). FIFO reads and
writes on Port A are independent of any concurrent Port B
operation.
The state of the Port B data (B0–17) lines is controlled by the
Port B Chip Select (CSB) and Port B Read select (RENB). The
B0–17 lines are in the high-impedance state when either CSB
is HIGH or RENB is LOW. The B0–17 lines are active outputs
when CSB is LOW and RENB is HIGH.
Data is loaded i nto FIF O2 from the C0–17 inputs on a LOW -t o-
HIGH transition of CLKC when WENC is HIGH, MBC is LOW,
and FFC/IRC i s HIGH (see Table 4). Data is read from FIFO1
to the B0–17 outputs by a LOW-to-HIGH transition of CLKB
when CSB is LOW, RENB is HIGH, MBB is LOW, and
EFB/ORB is HIGH (see Table 3). FIFO reads on Port B and
writes to Port C are inde pen de nt of an y c onc urre nt Por t A op-
eration.
The set-up and hold tim e co ns trai nts to the port c loc ks for th e
port Ch ip Selects and Writ e/Read sel ects are on ly for enab ling
write and read operations and are not related to high-imped-
ance control of the data outputs. If a port enable is LOW during
a clock cycle, the port’s Chip Select and Write/Read select
may ch an ge s ta t es du ring th e s et-u p a nd hold time w in dow of
the cycle.
When operating the FIFO in FWFT Mode with the Output
Ready flag LOW , the nex t word written is automa tically sent to
the FIFO’s output register by the LOW-to-HIGH transition of
the port clock that sets the Output Ready flag HIGH, data re-
siding in the FIFO’s memory array is clocked to the output reg-
ister only when a read is selected using the port’s Chip Sele ct,
Write/Read selec t, Enable, and Mailbox select.
When opera ting the FIFO in CY Standard M ode, regardless of
whether the Empty Flag is LOW or HIGH, data residing in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select,
Write/Read selec t, Enable, and Mailbox select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least
two fli p-flop stages. Th is is done to improve flag-si gnal reliabi l-
ity by reducing the probability of the metastable events when
CLKA, CLKB, and CLKC operate asynchronously to one an-
other. EF A/ORA, AE A, FF A/IRA, and AF A are synch ronized to
CLKA. EFB/ORB and AEB are synchronized to CLKB.
FFC/IRC and AFC are synchronized to CLKC. Tabl e 5 and
Ta ble 6 show the relationship of each port flag to FIFO1 and
FIFO2.
Empty/Output Ready Flags (EFA/ORA, EFB/ORB)
These are dual -purpose flags. In the FWFT Mode, the Outp ut
Ready (ORA, ORB) function is selected. When the Output
Ready flag is HIGH, new data is present in the FIFO output
register. When the Output Ready flag is LOW, the previous
data word remains in the FIFO output register, and any FIFO
reads are ignored.
In the CY Standard Mode, the Empty Flag (EF A, EFB) function
is sele cted. When the Empt y Flag is HIGH, dat a is avail able in
the FIFO’s RAM memory for reading to the output register.
When Em pty Flag is LOW, the previous data word remains in
the FIFO output register, and any FIFO reads are ignored.
The Empt y/Ou tput read y fla g of a FIFO is sy nchron ized to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is increment-
ed each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write poi nter and read poin ter comp arator that indicat es whe n
the FIFO SRAM status is empty, empty+1, or empty+2.
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Document #: 38-06026 Rev. ** Page 31 of 40
In FWFT Mode, from the time a word is written to a FIFO, it can
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. There-
fore, an Output Ready flag is LOW if a word in memory is the
nex t dat a to be se nt to t he FI FO out p ut reg i st er and th r e e cy -
cles have not elapsed since the time the word was written. The
Output Ready flag of the FIFO remains LOW until the third
LOW -to-HIGH transi tio n o f the synchron iz ing c lo ck oc curs , s i-
multane ously fo rcing t he Output Ready flag H IGH and s hifting
the word to the FIFO output register.
In the CY Standard Mod e, from the time a word is writte n to a
FIFO, the Empty Flag will indicate the presence of data avail-
able for reading in a minimum of two cycles of the Empty Flag
synchronizing clock. Therefore, an Empty Flag is LOW if a
word i n mem ory i s t he nex t d ata to be se nt to the FIFO o utp ut
register and two cycles have not elapsed since the time the
word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forcing the Empty Flag HIGH; only then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synch ronizi ng cl ock beg ins the fir st sync hroniz ation cy cle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle will be
the first synchronization cycle.
Full/Input Ready Flags (FFA/IRA, FFC/IRC)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IRA and IRC ) fu nc tio n i s s el ected. In CY Standa rd M ode , th e
Full Flag (FFA and FF C) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
any writes to the FIFO are ignored.
The Full /Input Ready fl ag of a FIFO i s synchronized t o the port
clock that writes data to its array. For both FWFT and CY Stan-
dard modes, each time a word is written to a FIFO, its write
pointer is incremented. The state machine that controls a
Full/Inp ut Ready flag mo nitors a wri te pointer and read po inter
compar ator tha t indi cates when the FIFO SRAM st atus is ful l,
full–1, or full–2. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a mini-
mum of two cycles of the Full/Input Ready flag synchronizing
clock. Therefore, a Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock
have elapsed since the next memory write location has been
read. The second LOW-to-HIGH transition on the Full/Input
Ready flag synchronizing clock after the read sets the Full/In-
put Ready flag HIGH.
A LOW -to-HIGH tra nsition o n a Full/Inpu t Ready flag s ynchro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time tSKEW1 or greater after the
read. Otherwise, the subsequent clock cycle will be the first
sync hronization cycle.
Almost Empty Flags (AEA, AE B)
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
stat us is al most empt y, a lmost e mpty+1, or almost empty +2.
The Almost Empty state is defined by the contents of register
X1 for AE B and register X2 for AEA . These regist ers are loa d-
ed with pres et values during a FIFO reset, programmed from
Port A, or programmed serially (see Almost Empty flag and
Almost Full fl ag of fse t p rogram ming abo ve). An Almos t Empt y
flag is LOW when its FIFO contains X or less words and is
HIGH when i ts FIF O conta ins (X+2 ) or more words . (See foot-
note #50)
The Almost Empty flag is set HIGH by the first LOW-to-HIGH
transition of its synchronizing clock after two FIFO writes that
fills memory to the (X+2) level. A LOW-to-HIGH transition of an
Almost Empty flag synchronizing clock begins the first syn-
chronization cycle if it occurs at time tSKEW2 or greater after
the write that fills the FIFO to (X+2) words. Otherwise, the sub-
sequent synchronizing clock cycle will be the first synchroni-
zation cycle.
Almost Full Flags (AFA, AFC)
The Almost Full flag of a FIFO is synchronized to the port clock
that write s data to its array. The state ma chine that contro ls an
Almost Full flag monitors a write pointer and read pointer com-
parator that indicates when the FIFO SRAM status is almost
full, almost full–1, or almost full–2. The Almost Full state is
defined by t he contents o f re gi ste r Y1 fo r AFA and register Y2
for AFC. These registers are loaded with preset values during
a FIFO reset, programmed from Port A, or programmed seri-
ally (see Almost Empty flag and Almost Full flag offset pro-
grammi ng above). An Almost Fu ll fl ag is LO W whe n th e num -
ber of words in its FIFO is greater than or equal to (1024–Y)
(4096 – Y) or (1638 4 – Y) fo r the CY7C 436X 6AV respectivel y.
An Almost Full flag is HIGH when the number of words in its
FIFO is less than or equal to [1024–(Y+2)] [4096–(Y+2)], or
[16384–(Y+2)],for the CY7C436X6AV respectively. (See foot-
note #50)
The Almost Full flag is set HIGH by the first LOW-to-HIGH
transition of its synchronizing clock after two FIFO reads that
reduces the number of words in memory to
[1024/4096/16384–(Y+2)]. A LOW-to-HIGH transition of an Al-
most F ull flag synchr onizing c lock be gins th e first synchroni -
zation cycle if it occurs at time tSKEW2 or grea ter after the rea d
that reduces the number of words in memory to
[1024/4096/16384–(Y+2)]. Otherwise, the subsequent syn-
chronizing clock cycle will be the first synchronization cycle.
Mailbox Registers
Each FI FO has a 36-b it bypass register to pas s com mand and
control information between Port A and Port B/Port C without
putting it in queue. The Mailbox Select (MBA, MBB, MBC) in-
puts choose between a mail register and a FIFO for a port data
transfer operation. The usable width of both the Mail1 and
Mail2 reg isters match es the selecte d bus size of Port B and C.
A LOW-to-HIGH transition on CLKA writes A0−35 data to the
Mail1 Reg ister wh en a Port A write i s select ed by CSA, W /RA,
and ENA with MBA HIGH.
When se nd ing data from Port C to Port A via the M ail 2 Re gis -
ter, the following is the case: A LOW-to-HIGH transition on
CLKC writes C0−17 data to the Mail2 Register when a Port C
write is selected by WENC with MBC HIGH. If the selected
Port C bus size is 18 bits, then the usable width of the Mail2
Register employs data lines C0–17. If the selected Port C bus
size is 9 bits, then the usable width of the Mail2 Register em-
ploys data lines C0−8. (In this case, C9−17 are don’t care in-
puts.)
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Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LO W . Attempt ed writes to a mail regi ster are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register if the port Mailbox Select
input is LOW, and from the mail register if the port Mailbox
Select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-
HIGH transition on CLKB when a Port B read is selected by
CSB, RENB, and MBB HIGH. For a 18-bit bus siz e, 18 bi ts of
mailbox data are placed on B0–17. For a 9-bit bus size, 9 bits
of mailbox data are placed on B0–8. (In this case, B9–17 are
indeterminate.)
The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH
transition on CLKA when a Port A read is selected by CSA,
W/RA, and ENA with MBA HIGH.
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B and Port C buses can be configured in a 18-bit word
or 9-bit byte format for data read from FIFO1 or written to
FIFO2. The levels applied to the Port B Bus Size Select
(SIZEB) and the Port C Bus Size Select (SIZEC) determine
the widt h of the buses . The bus size can be se lected ind epen-
dently for Ports B and C. These levels should be static through-
out FIFO ope ration. Both bus siz e selections are im plemented
at the completion of Master Reset, by the time the Full/Input
Ready flag is set HIGH.
Two different methods for sequencing data transfer are avail-
able for Port B when the bus size selection is either byte-or
word-size . They are referred to as Big Endian (most significant
byte first) and Little Endian (least significant byte first). The
level applied to the Big Endian Select (BE) input during the
LOW -to-HIGH transition o f MRS1 and M RS2 selects the endi-
an method that will be active during FIFO operation. The en-
dian method is implemented at the completion of Master Re-
set, by the time the Full/Input Ready flag is set HIGH.
Only 36 -bit long-word d ata i s w rit ten to o r read from Po rt A for
the CY7C436X6AV FIFO. Bus-matching operations are done
after data is read fro m the FIFO1 RAM and before da ta is writ-
ten to FIFO2 RAM. These bus-matching operations are not
available when transferring data via mailbox registers. Further-
more, both the word- and byte-size bus selections limit the
width of the data bus that can be used for ma il regis ter opera-
tions. In this case, only those byte lanes belonging to the se-
lected word- or byte-size bus can carry mailbox data. The re-
maining data outputs will be indeterminate. The remaining
data inputs will be don’t care inputs. For example, when a
wor d-size bus i s selected, then mailbox data can be tran s mit-
ted only between A0–17 and B0–17. When a byte-size bus is
selec ted , then mail box data ca n be t ransm itt ed onl y bet ween
A0–8 and B0–8.
Bus-Matching FIFO1 Reads
Data is written to the FIFO1 RAM in 36-bit long-word incre-
ments. I f byte or word size is i mp lem en ted on Port B, o nl y th e
first one or two bytes appear on the selected portion of the
FIFO1 output register, with the rest of the long-word stored in
auxiliary registers. In this case, subsequent FIFO1 reads out-
put the rest of the long word to the FIFO1 output register.
When read ing data f rom FIFO1 as by te, the unuse d B9–17 out-
puts are indeterminate.
Bus-Matching FIFO2 Writes
Data is written to the FIFO2 RAM in 18-bit word increments.
Data written to FIFO2 with a byte or word bus si ze stores the
initial bytes or words in auxiliary registers. The CLKC rising
edge that writes th e word to FI FO2 also st ores the en tire long-
word in FIFO2 RAM.
When writing data into FIFO2 in byte format, the unused C8–17
inputs will be don’t care inputs.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Retransmit func-
tion applies to CY standard mode only.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have oc-
curred and at least one word has been read since the last reset
cycle. A LOW pulse on RT1, (RT2) resets the internal read
pointer to the first physical location of the FIFO. CLKA CLKB
and CLKC may be free running bu t RENB (ENA) must be dis -
abled during and tRTR after the retransmit pulse. With every
valid read cycle after retransmit pulse, previously accessed
data is read and t he read p ointer can b e inc remen ted un til i t is
equal to the write pointer. Flags are governed by the relative
locations of the read and write pointers and are updated during
a retransmit cycle. Data written to the FIFO after activation of
RT1, (RT2) are transmitted also. The full depth of the FIFO can
be repeatedly retransmitted.
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.
AB
B0–8
C
B9–17 D
B0–8
CD
AB
A
B
C
D
(A) WORD SIZE - BIG ENDIAN
(B) WORD SIZE - LITTLE ENDIAN
(C) BYTE SIZE - BIG ENDIAN
BE SIZEB
HL
BE SIZEB
LL
BE SIZEB
HH
1st: Read from
FIFO1
2nd: Read from
FIFO1
1st: Read from
FIFO1
2nd: Read from
FIFO1
1st: Read from
FIFO1
2nd: Read from
FIFO1
3rd: Read from
FIFO1
4th: Read from
FIFO1
BYTE OR DER ON
PORT A:
D
C
B
A
(D) BYTE SIZE - LITTLE ENDIAN
BE SIZEB
LH
1st: Read from
FIFO1
2nd: Read from
FIFO1
3rd: Read from
FIFO1
4th: Read from
FIFO1
PORT B BUS SIZING
A
A27–35 B
A18–26 C
A9–17 D
A0–8Wr ite to FIFO1
B9–17
B0–8
B9–17 B0–8
B9–17
B0–8
B9–17 B0–8
B9–17
B0–8
B9–17 B0–8
B9–17
B0–8
B9–17 B0–8
B9–17
B0–8
B9–17 B0–8
B9–17
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A
C9–17 B
C0–8
C
C9–17 D
C0–8
CD
AB
A
B
C
D
(A) WORD SIZE - BIG ENDIAN
(B) WORD SIZE - LITTLE ENDIAN
(C) BYTE SIZE - BIG ENDIAN
BE SIZEC
HL
BE SIZEC
LL
BE SIZEC
HH
1st: Write to
FIFO2
2nd: Write to
FIFO2
1st: Writ e to
FIFO2
2nd: Write to
FIFO2
1st: Write to
FIFO2
2nd: Writ e to
FIFO2
3rd: Write to
FIFO2
4th: Write to
FIFO2
D
C
B
A
(D) BYTE SIZE - LITTLE ENDIAN
BE SIZEC
LH
1st: Write to
FIFO2
2nd: Write to
FIFO2
3rd: Write to
FIFO2
4th: Writ e to
FIFO2
PORT C BUS SIZING
BYTE ORDER ON
PORT A: A
A27–35 B
A18–26 C
A9–17 D
A0–8Read from
FIFO2
C9–17 C0–8
C9–17 C0–8
C9–17 C0–8
C9–17 C0–8
C9–17 C0–8
C9–17 C0–8
C9–17 C0–8
C9–17 C0–8
C9–17 C0–8
C9–17 C0–8
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Notes:
63. X1 register holds th e offset for AEB; Y1 register holds the offset for AFA.
64. X2 register holds th e offset for AEA; Y2 register holds the offset for AFC.
Table 1. Flag Programming
SPM FS1/SEN FS0/SD MRS1 MRS2 X1 and Y1 Registers[63] X2 and Y2 Registers[64]
H H H ↑X64 X
H H H X ↑X64
H H L ↑X16 X
H H L X ↑X16
H L H ↑X 8 X
H L H X ↑X 8
H L L ↑ ↑ Parallel programming via Port A Parallel programming via Port A
L H L ↑ ↑ Serial prog rammi ng vi a SD Serial programming via SD
L H H↑ ↑ Reserved Reserved
L L H ↑ ↑ Reserved Reserved
L L L ↑ ↑ Reserved Reserved
Table 2. Port A Enable Function
CSA W/RA ENA MBA CLKA A0–35 Port Function
H X X X X In high-impedance state None
L H L X X In high-impedance state None
LHHL↑In high-impedance state FIFO1 write
LHHH↑In high-im pedance state Mail1 write
L L L L X Active, FIFO 2 outp ut regi ste r None
LLHL↑Active, FIFO2 output regi ste r FIFO2 read
L L L H X Active, Mail2 register None
LLHH↑Active, Mail2 register Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function
CSB RENB MBB CLKB B0–17 Port Function
H X X X In high-impedance state None
L H L X Active, FIFO1 output register None
LH L↑Active, FIFO1 output register FIFO1 read
L H H X Active, Mail1 register None
LHH↑Active, Mail1 register Mail1 read (set MBF1 HIGH)
Table 4. Port C Enable Function
WENC MBC CLKC C0–17 Port Function
HL ↑In high-impedance state FIFO2 write
HH ↑In high-impedance state Mail2 write
L L X In high-impedance state None
L H X Active, Mail1 register None
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Table 5. FIFO1 Flag Operation (CY Standard and FWFT modes)
Number of Words in FIFO Memory [50, 65, 66, 67, 68] Synchronized to CLKB Synchronized to CLKA
CY7C43646AV CY7C43666AV CY7C43686AV EFB/ORB AEB AFA FFA/IRA
0 0 0 L L H H
1 TO X1 1 TO X1 1 TO X1 H L H H
(X1+1) to
[1024–(Y1+1)] (X1+1) to
[4096–(Y1+1)] (X1+1) to
[16384–(Y1+1)] H H H H
(1024–Y1) to 1023 (4096–Y1) to 4095 (16384–Y1) to
16383 H H L H
1024 4096 16384 H H L L
Table 6. FIFO2 Flag Operation (CY Standard and FWFT modes)
Number of Words in FIFO Memory [50, 66, 67, 69, 70] Synchronized to CLKA Synchronized to CLKC
CY7C43646AV CY7C43666AV CY7C43686AV EFA/ORA AEA AFC FFC/IRC
0 0 0 L L H H
1 TO X2 1 TO X2 1 TO X2 H L H H
(X2+1) to
[1024–(Y2+1)] (X2+1) to
[4096–(Y2+1)] (X2+1) to
[16384–(Y2+1)] H H H H
(1024–Y2) to 1023 (4096–Y2) to 4095 (16384–Y2) to
16383 H H L H
1024 4096 16384 H H L L
Table 7. Data Size Table for Word Writes to FIFO2
Size Mode[71] Write No. Data Written to FIFO2 Data Read From FIFO2
SIZE BE C9–17 C0–8A27–35 A18–26 A9–17 A0–8
LH1ABABCD
2CD
LL1CDABCD
2AB
Notes:
65. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the al m o st - ful l o ffset fo r FI FO1 u s ed by AFA. Both X1 and Y1 are selected during a FIFO1 reset
or port A programming.
66. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
67. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT Mode, the first word written to an empty FIFO goes unrequested to
the output register (no read operation necessary), it is not included in the FIFO memory count.
68. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in CY Standard Mode.
69. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset
or port A programming.
70. The ORA and IRC functions are active during FWFT mode; the EFA and FF C functions are active in CY Standard Mode.
71. BE is selected at Master Reset. SIZEC must be static throughout device operation.
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Table 8. Data Size Table for Byte Writes to FIFO2
Size Mode[71] Write No. Data Written to
FIFO2 Data Read From FIFO2
SIZE BE C0–8A27–35 A18–26 A9–17 A0–8
HH1 A ABCD
2B
3C
4D
HL1 D ABCD
2C
3B
4A
Table 9. Data Size Table for Word Reads from FIFO1
Size Mode[72] Data Written to FIFO1 Read No. Data Read From FIFO1
SIZE BE A27–35 A18–26 A9–17 A0–8B9–17 B0–8
LHABCD1AB
2CD
LLABCD1CD
2AB
Table 10. Data Siz e Ta ble f or Byte Reads from FIFO1
Size Mode[72] Data Written to FIFO1 Read No. Data Read From
FIFO1
SIZE BE A27–35 A18–26 A9–17 A0–8B0–8
HHABCD1 A
2B
3C
4D
HLABCD1 D
2C
3B
4A
Note:
72. BE is selected at Master Reset. SIZEB must be static throughout device operation.
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3.3V 1K x36/18x2 Tri Bus Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43646AV-7AC A128 128-Lead Thin Quad Flat Package Commercial
10 CY7C43646AV-10AC A128 128-Lead Thin Quad Flat Package Commercial
15 CY7C43646AV-15AC A128 128-Lead Thin Quad Flat Package Commercial
3.3V 4K x36/18x2 Tri Bus Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C43666AV-7AC A128 128-Lead Thin Quad Flat Package Commercial
10 CY7C43666AV-10AC A128 128-Lead Thin Quad Flat Package Commercial
15 CY7C43666AV-15AC A128 128-Lead Thin Quad Flat Package Commercial
3.3V 16Kx36/18x2 Tri Bus Synchronous FIFO
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
7 CY7C436 86AV-7AC A128 128-Lead Thin Qu ad Fla t Packa ge Commercial
10 CY7 C43686AV-10AC A128 128-Lea d Thin Qu ad Fla t Packa ge Commercial
15 CY7 C43686AV-15AC A128 128-Lea d Thin Qu ad Fla t Packa ge Commercial
15 CY7C43686AV-15AI A128 128-Lea d Thin Qu ad Fla t Packa ge Industrial
Shaded area contains advance information.
PRELIMINARY
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Document #: 38-06026 Rev. ** Page 39 of 40
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
51-85101-A
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Document #: 38-06026 Rev. ** Page 40 of 40
Document Title: CY7C43646AV, CY7C43666AV, CY7C43686AV 3.3V 1K/4K/16K x 36/x18x2 TriBus FIFO
Document Numbe r: 38-060 26
REV. ECN NO. Issue Date Orig. of Change Description of Change
** 107314 05/23/01 SZV Change from Spec #: 38-00778 to 38-06026
