Data Sheet January 1998 T7288 CEPT/E1 Line Interface Features Fully integrated 2.048 Mbits/s line interface Intended for use in systems that must comply with ITU-T specifications G.703, G.823, I.431, G.732, G.735--G.739 Pin-selectable 75 or 120 operation Monolithic clock recovery Low power dissipation: -- 100 mW for 120 twisted pair, typical -- 108 mW for 75 coaxial, typical Minimal external circuitry required Robust frequency acquisition/phase-locked loop Pin-selectable HDB3 encoder and decoder Loopback modes for fault isolation Multiple link-status and alarm features Single-rail/dual-rail interface Pin compatible with the LC1135B device Description The Lucent Technologies Microelectronics Group T7288 CEPT/E1 Line Interface is an integrated circuit that provides a 2.048 Mbits/s line interface to either twisted-pair or coaxial cable as specified in ITU-T requirements G.703, G.823, I.431, G.732, and G.735--G.739. The device performs receive pulse regeneration, timing recovery, and transmit pulse driving functions. The T7288 device is manufactured by using low-power CMOS technology and is available in a 28-pin, plastic DIP or in a 28-pin, plastic SOJ package for surface mounting. The T7288 device is functionally compatible with the LC1135B device. The digital circuitry is shown in Figure 1; the analog circuitry is shown in Figure 6. HDB3/TNDATA MUX BLUE (AIS) SIGNAL GENERATOR LP2 TBC RCLK TDATA/ TPDATA HDB3/ TNDATA TCLK ALL ANALOG FUNCTIONS ZS VIO/ RNDATA MUX MUX R2 HD3 ENCODER MUX MUX MUX TRANSMIT MUX T2 SINGLE-TODUALRAIL CONVERTER MUX HDB3/TNDATA SR/DR MUX MUX MUX BLUE SIGNAL (AIS) GENERATOR RDATA/ RPDATA MUX LOSS OF CLOCK DETECTION RECEIVE R1 MUX T1 HDB3 DECODER FLM MUX DUAL-TOSINGLERAIL CONVERTER RBC SR/DR MUX MUX BIPOLAR VIOLATION DETECTION HDB3 CODE VIOLATION DETECTION MUX LP3 MUX LDC LOS LP1 MUX SD +5 V BCLK ALMT VDDA OUPUT DRIVERS AND LOGIC +5 V VDD OUPUT DRIVERS AND LOGIC GND GNDD Figure 1. Digital Block Diagram ALL ANALOG FUNCTIONS GND GNDA 5-4343(C) Data Sheet January 1998 T7288 CEPT/E1 Line Interface Pin Information LOS 1 28 T1 LOC 2 27 R1 HDB3/TNDATA 3 26 SD VIO/RNDATA 4 25 GNDA RCLK 5 24 VDDA RDATA/RPDATA TCLK 6 23 7 ZS T2 TDATA/TPDATA 8 T7288-PL 22 T7288-EL 21 LP1 9 20 R2 LP2 10 19 GNDD LP3 11 18 NC ALMT 12 17 FLM RBC 13 16 SR/DR TBC 14 15 BCLK VDDD 5-4344(C) Figure 2. Pin Diagram Table 1. Pin Descriptions 2 Pin Symbol Type Name/Function 1 LOS O Loss of Signal (Active-Low). This pin is cleared (0) upon loss of the data signal at the receiver inputs. 2 LOC O Loss of Clock (Active-Low). This pin is cleared when SD = 1 and LOS = 0, indicating that a loss of clock has occurred. When LOS = 0, no transitions occur on the RCLK and on either RDATA (for single-rail operation) or RPDATA and RNDATA (for dual-rail operation) outputs. A valid clock must be present at BCLK for this function to operate properly. 3 HDB3/ TNDATA I HDB3 Enable/N-Rail Transmit Data. If SR/DR = 0, this pin is set (1) to insert an HDB3 substitution code on the transmit side and to remove the substitution code on the receive side. If SR/DR = 1, this pin is used as the n-rail transmit input data (internal pull-down is included). 4 VIO/RNDATA O Violation/N-Rail Receive Data. If SR/DR = 0 and HDB3 = 0, bipolar violations on the receive-side input are detected, causing VIO to be set; if HDB3 = 1, HDB3 code violations cause VIO to be set. If SR/DR = 1, this pin is used as the n-rail receive output data. 5 RCLK O Receive Clock. Output receive clock signal to the terminal equipment. 6 RDATA/ RPDATA O Receive Data/P-Rail Receive Data. If SR/DR = 0, this pin is used for 2.048 Mbits/s unipolar output data with a 100% duty cycle. If SR/DR = 1, this pin is used as the p-rail receive output data. 7 TCLK I Transmit Clock. Input clock signal (2.048 MHz 80 ppm). 8 TDATA/ TPDATA I Transmit Data/P-Rail Transmit Data. If SR/DR = 0, this pin is used as 2.048 Mbits/s unipolar input data. If SR/DR = 1, this pin is used as the p-rail transmit input data. Lucent Technologies Inc. Data Sheet January 1998 T7288 CEPT/E1 Line Interface Pin Information (continued) Table 1. Pin Descriptions (continued) Pin Symbol Type Name/Function 9 LP1 I Loopback 1 Enable (Active-Low). This pin is cleared for a full local loopback (transmit converter output to receive converter input). Most of the transmit and receive analog circuitry is exercised in this loopback (internal pull-up is included). 10 LP2 I Loopback 2 Enable (Active-Low). This pin is cleared for a remote loopback. In loopback 2, a high on TBC (pin 14) inserts the blue signal (AIS) on the transmit side (internal pull-up is included). 11 LP3 I Loopback 3 Enable (Active-Low). This pin is cleared for a digital local loopback. Only the transmit and receive digital sections are exercised in this loopback (internal pull-up is included). 12 ALMT I Alarm Test Enable (Active-Low). This pin is cleared, forcing LOS = 0, LOC = 0, and VIO = 1 for testing without affecting data transmission (internal pullup is included). 13 RBC I Receive Blue Control. This pin is set to insert the blue signal (AIS) on the receive side (internal pull-down is included). 14 TBC I Transmit Blue Control. This pin is set to insert the blue signal (AIS) on the transmit side. This control has priority over a loopback 2 if both are operated (internal pull-down is included). 15 BCLK I Blue Clock. Blue clock (AIS) input signal (2.048 MHz 80 ppm). This clock can be independent of the transmit clock. 16 SR/DR I Single-Rail (Active-Low)/Dual-Rail Operation. If SR /DR = 0 (internal pulldown is included), single-rail operation is selected; if SR/DR = 1, dual-rail operation is selected (see Tables 4--6). 17 FLM I Framer Logic Mode. If FLM = 0 (internal pull-down is included), logic mode 1 operation occurs. If FLM = 1, logic mode 2 operation occurs (see Tables 4--6). 18 NC 19 GNDD 20 R2 21 VDDD 22 T2 O Transmit Bipolar Tip. Positive bipolar transmit output. 23 ZS I Impedance Select. This pin is cleared for 75 coaxial cable operation and set for 120 shielded twisted-pair operation (internal pull-down is included). 24 VDDA 5 V Analog Supply (10%). 25 GNDA Analog Ground. 26 SD I Shutdown Enable. If this pin is high, a loss-of-signal detection (LOS = 0) forces LOC low and causes the following (see Table 4): For single-rail operation: RCLK high, RDATA low. For dual-rail, logic mode 1 operation: RCLK high, RPDATA and RNDATA low. For dual-rail, logic mode 2 operation: RCLK low, RPDATA and RNDATA high (internal pull-down included). 27 R1 I Receive Bipolar Ring. Negative bipolar receive input. 28 T1 I Receive Bipolar Tip. Positive bipolar receive input. Lucent Technologies Inc. No Connection. Test pin for manufacturing purposes only. This pin must be left floating or tied to GNDD. Digital Ground. O Transmit Bipolar Ring. Negative bipolar transmit output. 5 V Digital Supply (10%). 3 Data Sheet January 1998 T7288 CEPT/E1 Line Interface Overview The T7288 device is a fully integrated line interface that requires only two transformers, three input termination resistors, and two output impedance-matching resistors to provide a bidirectional line interface between a 2.048 Mbits/s CEPT/E1 data link and terminal equipment. Typical application diagrams are shown in Figure 3 and Figure 4 for 75 coaxial cable and 120 shielded twisted-pair operation, respectively. The circuit is divided into three main blocks: transmit converter, receive converter, and logic. The transmit and receive converters process information signals through the device in the transmit and receive directions, respectively; the logic is the control and status interface for the device. Figure 3 and Figure 4 include a matched-impedance transmit-interface section in order to match the output impedance of the transmitter to the line. See Table 2 for the G.703/CH-PTT specifications for transmit-interface return loss. RECEIVED DATA T1 270 RDATA/RPDATA VIO/RNDATA RECEIVE INPUT 200 270 RCLK R1 1:2 VDDD TRANSMITTED DATA T7288 CEPT/E1 LINE INTERFACE MATCHED-IMPEDANCE TRANSMIT INTERFACE +5 V VDDA 1 F ZS GNDD GNDA 15.4 T2 75 TRANSMIT OUTPUT LOAD 15.4 R2 TDATA/TPDATA HDB3/TNDATA TCLK 1.36:1 5-4345(C)r.2 Note: Lucent 2741 family pulse transformers are recommended. Figure 3. Typical Application Diagram for Coaxial Environment 4 Lucent Technologies Inc. Data Sheet January 1998 T7288 CEPT/E1 Line Interface Overview (continued) RECEIVED DATA T1 866 RDATA/RPDATA VIO/RNDATA RECEIVE INPUT 200 866 RCLK R1 1:2 VDDD TRANSMITTED DATA T7288 CEPT/E1 LINE INTERFACE MATCHED-IMPEDANCE TRANSMIT INTERFACE +5 V VDDA ZS 1 F GNDD GNDA 26.1 T2 120 TDATA/TPDATA TRANSMIT OUTPUT LOAD HDB3/TNDATA 26.1 TCLK R2 1.36:1 5-4346(C)r.2 Note: Lucent 2741 family pulse transformers are recommended. Figure 4. Typical Application Diagram for Shielded Twisted-Pair Environment Table 2. Return Loss (Resistor Tolerance: 1% on Transmit Side, 2% on Receive Side) Interference Min Typ Max Unit Transmit: 51 kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz 8 14 10 28 26 24 -- -- -- dB dB dB Receive: 51 kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz 12 18 14 32 31 30 -- -- -- dB dB dB Lucent Technologies Inc. 5 Data Sheet January 1998 T7288 CEPT/E1 Line Interface Overview (continued) Transmit Converter The line-interface transmission format is return-to-zero, bipolar alternate mark inversion (AMI), requiring transmission and sensing of alternately positive and negative pulses. The transmit converter accepts unipolar data and clock and converts the signal to a balanced bipolar data signal. Binary 1s in the data stream become pulses of alternating polarity transmitted between the two output rails, T2 and R2. Binary 0s are transmitted as null pulses. The output pulse waveform is nominally rectangular. The pulses are produced by a high-speed D/A converter and are driven onto the line by low-impedance output buffers. The positive and negative pulses meet ITU-T specification G.703 template requirements. The normalized pulse template is shown in Figure 5. A block diagram of the analog circuitry is shown in Figure 6. The clock multiplier shown in Figure 6 uses a phase-locked loop (PLL) to produce the high-speed timing waveforms needed to produce a well-controlled pulse width. The clock multiplier also eliminates the need for the tightly controlled transmit clock duty cycle usually required in discrete implementations. Transmitter specifications are given in Table 10. 269 ns (244 + 25) 20% 10% V = 100% 194 ns (244 - 50) 10% NOMINAL PULSE 20% 50% 244 ns 219 ns (244 - 25) 10% 10% 0% 10% 10% 20% 488 ns (244 + 244) 5-3145(C) Note: V corresponds to the nominal peak value. Figure 5. ITU-T G.703 Pulse Template 6 Lucent Technologies Inc. Data Sheet January 1998 T7288 CEPT/E1 Line Interface Overview (continued) Transmit Converter (continued) LOS LP1 DIGITAL SIGNAL DETECTOR ANALOG SIGNAL DETECTOR RECEIVER ANALOG INPUT T1 R1 PDATA NDATA RP DATA/CLOCK RN RECOVERY RCLK M U X RDATA/RPDATA VIO/RNDATA RCLK TRANSMIT AND RECEIVE LOGIC TP T2 R2 TRANSMIT OUTPUT DRIVERS SD TN HIGH-SPEED D/A 2 CLOCK MULTIPLIER TCLK TDATA/TPDATA HDB3/TNDATA TCLK TIMING SIGNALS ZS 5-4347(C) Figure 6. T7288 Analog Block Diagram Lucent Technologies Inc. 7 T7288 CEPT/E1 Line Interface Overview (continued) Receive Converter The receive converter accepts bipolar input signals (T1, R1), with a maximum of 6 dB loss at 1024 kHz, through the interconnection cable. The received signal is rectified while the amplitude and rise time are restored. These input signals are peak-detected and sliced by the receiver front end, producing the digital signals PDATA and NDATA (see Figure 6). Receive decision levels are automatically adjusted to be 50% of peak-to-zero signal levels. The timing is extracted by means of PLL circuitry that locks an internal, freerunning, current-controlled oscillator (ICO) to the 2.048 MHz component. The PLL employs a 3-state phase detector and a lowvoltage/temperature coefficient ICO. The ICO freerunning frequency is trimmed to within 2.5% of the data rate at wafer probe, with VDD = 5.0 V and TA = 25 C. For all operating conditions, the free-running oscillator frequency deviates from the data rate by less than 7%, alleviating the problem of harmonic lock. For robust operation, the PLL is augmented with a frequency-acquisition capability. This feature detects if the recovered PLL clock (RCLK) deviates by more than +1.7%/-1.6% in frequency from a 2.048 MHz reference clock, which must be provided at BCLK. If the RCLK frequency is not within the prescribed range of the BCLK frequency, the T7288 device enters a training mode in which receive input data is disconnected from the PLL, and the RCLK frequency is steered to equal the BCLK frequency. After frequency acquisition is completed, the PLL reconnects to receive input data to acquire proper phase-lock and timing of RCLK with respect to the incoming T1, R1 data. Valid data is available when proper phase-lock has been achieved. The frequency acquisition circuitry is intended to avoid improper harmonic locking during start-up situations, such as powerup or data interruption. Once the T7288 device is phase-locked to data, the frequency-acquisition mode will not be activated. 8 Data Sheet January 1998 A continuously present (i.e., ungapped, unswitched) 2.048 MHz reference clock must be present at BCLK to enable the frequency-acquisition circuitry. However, the receive PLL will operate even in the absence of a 2.048 MHz clock at BCLK. The 2.048 MHz clock at TCLK can also be used to provide the 2.048 MHz reference at BCLK. Because the clock output of the receive converter is derived from the ICO, a free-running clock can be present at the output of the receive converter without data being present at the input. A shutdown pin (SD) is provided to block this clock, if desired, to eliminate the free-running clock upon loss of the input signal. Both analog and digital methods of loss-of-signal detection are used in the T7288 device. The analog signal detector shown in Figure 6 uses the output of the receiver peak detector to determine if a signal is present at T1 and R1. If the input amplitude drops below 0.25 V, typical, the analog detector output becomes active. Analog loss of signal is registered, at most, several milliseconds after a drop in signal level, depending on a variety of factors, such as initial signal amplitude. Hysteresis (140 mV, typical) is provided in the analog detector to eliminate LOS chattering. The digital signal detector counts 0s in the recovered data. If more than 32 consecutive 0s occur, the digital signal detector becomes active. In normal operation, the detector outputs are ORed together to form LOS; however, in loopback 1, only the digital signal detector is used to monitor the looped signal. Table 3 describes the operation of the shutdown, LOS, and LOC functions in normal operation and in loopback 1. The PLL is designed to accommodate large amounts of input jitter with high power supply rejection for operation in noisy environments. Low jitter sensitivity to power supply noise allows compact line-card layouts that employ many line interfaces on one board. The minimum input jitter tolerance, as specified in ITU-T specification G.823, and the measured T7288 device jitter tolerance are shown in Figure 7. Receiver specifications are shown in Table 11. The T7288 device satisfies the ITU-T jitter transfer function requirement of recommendations G.735--G.739 (see Figure 8). Lucent Technologies Inc. Data Sheet January 1998 T7288 CEPT/E1 Line Interface Overview (continued) Receive Converter (continued) Table 3. Shutdown, LOS, and LOC Truth Table x = don't care. Inputs Outputs LP1 SD ALMT Input Signal Loopback 1 LOS LOC 1 1 1 1 0 0 0 0 x 0 0 1 1 0 0 1 1 x at T1, R1 Active No signal Active No signal x x x x x 1 1 1 1 1 1 1 1 0 Signal x x x x Active No signal Active No signal x 1 0 1 0 1 0 1 0 0 1 1 1 0 1 1 1 0 0 Receive RCLK* Data* Normal Normal Low Free-running ICO Normal Normal Low High Normal loopback Normal loopback Free-running ICO Low Normal loopback Normal loopback Low High Unaffected Unaffected Active LOS Detectors Analog & digital Analog & digital Analog & digital Analog & digital Digital only Digital only Digital only Digital only x * These values apply for single-rail or dual-rail/logic mode 1. For dual-rail/logic mode 2, all logic-level outputs except for looped-back data are the inverse of that shown above. Activated by analog loss-of-signal detection. Digital LOS detection forces receive data low. Analog LOS detection merely forces receive data to stop transitions; receive data will be forced either high or low with analog LOS detection. All-0s looped-back data, no HDB3 operation. Sufficiently sparse looped-back data (not HDB3 encoded) also causes the receive ICO to freerun; therefore, properly timed loopback data is not guaranteed. 10.0 MEASURED T7288 PERFORMANCE BER = 10-6 INPUT JITTER AMPLITUDE (U.I. PEAK-TO-PEAK) (1, 2.9) G.823 SPECIFICATION (2.4k, 1.5) (20, 1.5) 1.0 (18k, 0.2) 0.1 (100k, 0.2) MEASURED DATA POINTS JITTER JITTER JITTER JITTER FREQUENCY AMPLITUDE FREQUENCY AMPLITUDE (kHz) (U.I.pp) (kHz) (U.I.pp) 4.0 1.9 40 0.45 8.0 1.1 50 0.44 10 0.9 60 0.43 15 0.67 70 0.43 20 0.52 100 0.43 30 0.46 0.01 0.1 1.0 10 JITTER FREQUENCY (kHz) 100 5-4354(C) Note: Measurement conditions--random data, TA = 25 C, VDD = 5 V, 6 dB cable loss, BCLK clock present. Figure 7. Random Input Data Jitter Tolerance (HDB3 Encoded) Lucent Technologies Inc. 9 Data Sheet January 1998 T7288 CEPT/E1 Line Interface Overview (continued) Receive Converter (continued) G.735-G.739 SPECIFICATION (36k, 0.5 dB) 0 20 LOG (JOUT/JIN) (dB) T7288 MEASURED -5 -20 dB/DECADE -10 (100k, -8.4 dB) -15 -20 0.1 10 1 36 100 FREQUENCY (kHz) Notes: Equivalent binary content of input signal: 1000. Jitter input amplitude = 0.1 U.I. peak-to-peak. Figure 8. Receive Jitter Transfer Function Digital Logic The logic provides alarms, optional HDB3 coding, blue signal (AIS) insertion circuits, and maintenance loopbacks. It also optionally performs dual-rail to single-rail conversion of the data and provides an alternate logic polarity (logic mode 2) in dual-rail mode for receive clock and receive and transmit data. Single-Rail/Dual-Rail Interface and Alternate Logic Mode The T7288 device supports either single-rail or dual-rail operation by setting the control pin SR/DR. In the single-rail mode (SR /DR = 0), the T7288 receiver converts bipolar input signals (T1, R1) to a unipolar output signal on RDATA. The T7288 transmitter converts a unipolar input signal on TDATA to a balanced bipolar data signal on pins T2 and R2. If desired, the HDB3 control pin can be used to set HDB3 encoding/decoding. Violation information is available on output pin VIO. 10 In the dual-rail mode (SR /DR = 1), the T7288 receiver converts bipolar input signals (T1, R1) to p-rail and n-rail, nonreturn-to-zero output data on pins RPDATA and RNDATA, respectively. The T7288 transmitter converts nonreturn-to-zero p-rail and n-rail input data on pins TPDATA and TNDATA, respectively, to a balanced bipolar data signal on pins T2 and R2. In the dual-rail mode, HDB3 encoding/decoding and bipolar violation output functions are unavailable. In the dual-rail mode, an alternate-logic polarity mode is available via control pin FLM. If FLM = 1, the T7288 device operates in logic mode 2; RCLK is inverted with respect to logic mode 1, and input and output data (TPDATA, TNDATA, RPDATA, and RNDATA) are activelow (see Figures 10--13). Internal pull-downs on signals SR/DR and FLM set default operation to single-rail, logic mode 1 (see Table 4). Lucent Technologies Inc. Data Sheet January 1998 T7288 CEPT/E1 Line Interface Overview (continued) Digital Logic (continued) Table 4. Rail Interface and Logic Mode Options FLM SR /DR Single-/Dual-Rail Logic Mode 0* 0* Single 1 0 1 Dual 1 1 0 X X 1 1 Dual 2 * Default operation (identical with LC1135B) if both pins are unconnected. X = illegal option. Table 5. Single-Rail Operation (Default State) SR/DR = 0 (or left unconnected internal pull-down circuitry). Pin Name Function 3 HDB3/TNDATA HDB3 enable as in the LC1135B device 4 VIO/RNDATA VIO violation as in the LC1135B device 6 RDATA/RPDATA RDATA receive data as in the LC1135B device 8 TDATA/TPDATA TDATA transmit data as in the LC1135B device Table 6. Dual-Rail Operation SR/DR = 1. Pin Name Function 3 HDB3/TNDATA N-rail transmit input data 4 VIO/RNDATA N-rail receive output data 6 RDATA/RPDATA P-rail receive output data 8 TDATA/TPDATA P-rail transmit input data Alarms An independent loss of clock (LOC) output is provided so that loss of clock is detected when the shutdown option is in effect. LOS and LOC can be wire-ORed to produce a single alarm. A bipolar violation output is included if HDB3 = 0, giving an alarm (VIO) each time a violation occurs (two or more successive 1s on a rail). The violation alarm output is held in a latch for one cycle of the internal clock (RCLK). In the HDB3 mode, HDB3 code violations are detected and an alarm is produced. An alarm test pin (ALMT) is provided to test the alarm outputs, LOS, LOC, and VIO. Clearing this pin forces the alarm outputs to the alarm state without affecting data transmission. Lucent Technologies Inc. 11 Data Sheet January 1998 T7288 CEPT/E1 Line Interface Overview (continued) Digital Logic (continued) HDB3 Option The T7288 device contains an HDB3 encoder and decoder (for single-rail mode only, i.e., SR/DR = 0) that can be selected by setting the HDB3 pin. This allows the encoder to substitute a zero-substitution code for four consecutive 0s detected in the data stream, as illustrated in Table 7. A V represents a violation of the HDB3 code, and a B represents a bipolar pulse of correct polarity. The decoder detects the zero-substitution code and reinserts four 0s in the data stream. Case 1: Preceding mark has a polarity opposite the polarity of the preceding violation and is not a violation itself. Case 2: Preceding mark has a polarity the same as the polarity of the preceding violation or is a violation itself. Table 7. HDB3 Substitution Code Case 1 Case 2 Before HDB3 0000 0000 After HDB3 000V B00V Blue Signal (AIS) Generators There are two blue signal (AIS) generators in this device. One (RBC = 1) substitutes an all-1s signal on RDATA output (SR/DR = 0) or RPDATA and RNDATA (SR/DR = 1) toward the terminal equipment. The other (TBC = 1) substitutes a bipolar, all-1s signal for the bipolar data out of the transmit converter that can be used to keep line repeaters active. Loopback Paths The T7288 device has three independent loopback paths that are activated by clearing the respective control inputs, LP1, LP2, or LP3. Loopback 1 bridges the data stream from the transmit converter (transmit converter included) to the input of the receive converter. This maintenance loop includes most of the internal circuitry. Loopback 2 provides a loopback of data and recovered clock from the bipolar inputs (T1, R1) to the bipolar outputs of the transmit converter (T2, R2). The receive front end, receive PLL, and transmit driver circuitry are all exercised. The loop can be used to isolate failures between systems. TBC = 1 overrides this function. Loopback 3 loops the data stream as in loopback 1 but bypasses the transmit and receive converters. The blue signal (AIS) can be transmitted to the line when in this loopback. Loopbacks 2 and 3 can be operated simultaneously to provide transmission loops in both directions. Current Pulses With all other pins grounded, current pulses of maximum value and time widths are allowed on the T1/R1 and T2/R2 pins without damaging the device, as shown in the table below. Also, to help ensure long-term reliability, the average value of a current-pulse train is specified. Table 8. Current Pulses 12 Pin Maximum Value Width Average Value T1, R1 20 mA 1 s to 1 s 6 mA T2, R2 200 mA 1 s to 1 s 40 mA Lucent Technologies Inc. Data Sheet January 1998 T7288 CEPT/E1 Line Interface Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Symbol Min Max Unit dc Supply Voltage VDD -0.5 6.5 V Power Dissipation PD -- 500 mW Storage Temperature Tstg -65 125 C Maximum Voltage (any pin) with Respect to VDD -- -- 0.5 V Minimum Voltage (any pin) with Respect to GND -- -0.5 -- V Maximum Allowable Voltages (T1, R1) with Respect to GND -- -5.0 5.0 V Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: Human-Body Model ESD Threshold Device Voltage T7288 >2500 V RL1 R1 R2 FOR DEVICE TESTING P1 REGULATED HIGH-VOLTAGE POWER SUPPLY C1 SOCKET 5-2263(C).a Notes: P1--0 kV to 5 kV dc power supply. R1--At least 10 M, high-voltage, 1 W carbon composition. RL1--High-voltage (5 kV) relay of a bounceless type (mercury-wetted or equivalent). C1--100 pF, 5 kV capacitor. R2--1500 5%, 1 W carbon composition < 1 pF shunt capacitance. Figure 9. Circuit Schematic of Human-Body ESD Simulator Lucent Technologies Inc. 13 Data Sheet January 1998 T7288 CEPT/E1 Line Interface Electrical Characteristics TA = -40 C to +85 C; VDD = 5 V 10%. Table 9. Logic Interface Electrical Characteristics Parameter Symbol Conditions Min Max Unit Input Voltage: Low High VIL VIH -- -- GNDD 2.0 0.8 VDDD V V Output Voltage*: Low High VOL VOH 2.0 mA sink 80 A source GNDD 2.4 0.4 VDDD V V Input Capacitance CI -- -- 20 pF Load Capacitance CL -- -- 40 pF * Digital outputs drive purely capacitive loads to full output levels (VDDD, GNDD). Internal pull-up resistors are provided on the following input leads: LP1, LP2, LP3, and ALMT. Internal pull-down devices are provided on the following leads: SD, RBC, HDB3/TNDATA, TBC, SR/DR, FLM, and ZS. The internal pull-up or pull-down devices require the input to source or sink to be no more than 20 A. Table 10. Transmitter Specifications Parameter Min Typ Max Unit Output Pulse Amplitude: 75 (ZS = 0) 120 (ZS = 1) 2.14 2.70 2.37 3.0 2.60 3.30 V V Pulse Width (50%) 219 244 269 ns Positive/Negative Pulse Imbalance -- -- 5 % Zero Level -- -- 10 %* Output Transformer Turns Ratio 1:1.33 1:1.36 1:1.39 -- * Percentage of the nominal pulse amplitude. 14 Lucent Technologies Inc. Data Sheet January 1998 T7288 CEPT/E1 Line Interface Electrical Characteristics (continued) Table 11. Receiver Specifications Parameter Min Typ Max Unit 0.7 -- 4.2 Vp Allowed Cable Loss at BER = No Interference Interfering PBRS, 18 dB Below Transmitted PBRS -- -- 10 -- 7 6 dB dB PLL: 3 dB Bandwidth Peaking -- -- 28 0.24 -- 0.5 kHz dB ICO Free-running Frequency Error -- -- 7 % 1:1.9 1:2.0 1:2.1 -- 0.9 -- 3.0 k Receiver Sensitivity* 10-9 Input Transformer Turns Ratio Input Resistance, R1 or T1, Each Input to Ground * Measured at T1, R1 (V peak-to-zero, GND reference). Transfer characteristics (1/4 input). Table 12. Jitter 20 Hz--100 kHz Parameter Min Typ Max Unit Receive Plus Transmit Jitter at T2/R2 -- 0.06 0.09 U.I. peak-to-peak Transmit Jitter at T2/R2 -- 0.012 0.04 U.I. peak-to-peak Table 13. Power Dissipation TA = -40 C to +85 C, VDD = 5.0 V 10%. Parameter Symbol Conditions Min Typ Max Unit Power Dissipation: 75 (ZS = 0) 120 (ZS = 1) Pdis Pdis All 1s transmit and receive data, VDD = 5.5 V -- -- 190 170 290 260 mW mW Power Dissipation: 75 (ZS = 0) 120 (ZS = 1) Pdis Pdis All 1s transmit and receive data, VDD = 5.0 V -- -- 170 150 -- -- mW mW Power Dissipation: 75 (ZS = 0) 120 (ZS = 1) Pdis Pdis PRBS (50% 1s) transmit and receive data, VDD = 5.0 V -- -- 108 100 -- -- mW mW Note: All measurements are with a matched-impedance transmit interface (see Figure 3 and Figure 4) and with VDD or GND applied to digital input leads. Lucent Technologies Inc. 15 Data Sheet January 1998 T7288 CEPT/E1 Line Interface Timing Characteristics All duty-cycle and timing relationships are in reference to a TTL, 1.4 V threshold level. Loss-of-Clock Indication Timing The clock must be absent 6.4 s to guarantee a loss-of-clock indication. However, a loss-of-clock indication can occur if the clock is absent for as little as 1.95 s, depending on the timing relationship of the interruption with respect to the timing cycle. The returning clock must be present 3.91 s to guarantee a normal condition on the loss-of-clock pin (LOC). However, the loss-of-clock indication can return to normal immediately, depending on the timing relationship of the signal return with respect to the timing cycle. Table 14. Clock Timing Relationships TA = -40 C to +85 C, VDD = 5.0 V 10%; load capacitance = 40 pF. Symbol Description tTCLTCL TCLK Clock Period tTCHTCL TCLK Duty Cycle tTDVTCL tTCLTDV Data Setup Time, TDATA Data Hold Time, TCLK to to TCLK TDATA Min Typ Max Unit * 488 * ns 40 50 60 % 50 -- -- ns 40 -- -- ns tr Clock Rise Time (10%--90%) -- -- 40 ns tf Clock Fall Time (10%--90%) -- -- 40 ns tRCLRCL tRCHRDV tRDVRCH tRCLRDV RCLK Duty Cycle 40 50 60 % VIO 171 -- -- ns RCLK 131 -- -- ns -- -- 40 ns Data Hold Time, RCLK to RDATA, Data Setup Time, RDATA, VIO to Propagation Delay, RCLK to RDATA, VIO * A tolerance of 80 ppm. TDATA for single-rail mode; TPDATA and TNDATA for dual-rail mode. RDATA and VIO for single-rail mode; RPDATA and RNDATA for dual-rail mode. 16 Lucent Technologies Inc. Data Sheet January 1998 T7288 CEPT/E1 Line Interface Timing Characteristics (continued) Timing Diagrams (Single-Rail or Dual-Rail, Logic Mode 1) tTCLTCL tr tf TCLK TDATA OR TPDATA TNDATA tTDVTCL tTCLTDV 5-4357(C) Figure 10. Transmit Timing tr tRCLRDV tf RCLK tRDVRCH RDATA VIO OR RPDATA RNDATA tRCHRDV 5-4358(C) Figure 11. Receive Timing Lucent Technologies Inc. 17 Data Sheet January 1998 T7288 CEPT/E1 Line Interface Timing Characteristics (continued) Timing Diagrams (Dual-Rail, Logic Mode 2) tTCLTCL tr tf TCLK ACTIVELOW TPDATA TNDATA tTDVTCL tTCLTDV 5-4359(C) Figure 12. Transmit Timing tRCLRDV tr tf RCLK tRDVRCH ACTIVELOW RPDATA RNDATA tRCHRDV 5-4360(C) Figure 13. Receive Timing 18 Lucent Technologies Inc. Data Sheet January 1998 T7288 CEPT/E1 Line Interface Outline Diagrams 28-Pin, Plastic DIP Dimensions are in millimeters. L N B 1 W PIN #1 IDENTIFIER ZONE H SEATING PLANE 0.38 MIN 2.54 TYP Number of Pins (N) 28 0.023 MAX 5-4410.R1 Package Dimensions (DIP) Maximum Length Including Leads (L) Maximum Width Without Leads (B) Maximum Width Including Leads (W) Maximum Height Above Board (H) 37.34 13.97 15.49 5.59 Lucent Technologies Inc. 19 Data Sheet January 1998 T7288 CEPT/E1 Line Interface Outline Diagrams (continued) 28-Pin, Plastic SOJ Dimensions are in millimeters. L N B 1 PIN #1 IDENTIFIER ZONE W H SEATING PLANE 0.10 1.27 TYP 0.020 MAX 0.64 MIN 5-4413.R1 Number of Pins (N) Package Dimensions (SOJ) Maximum Length Including Leads (L) Maximum Width Without Leads (B) Maximum Width Including Leads (W) Maximum Height Above Board (H) 18.03 7.62 8.81 3.18 28 Ordering Information 20 Device Code Package Temperature T - 7288 - - - PL T - 7288 - - - EL 28-Pin DIP 28-Pin SOJ -40 C to +85 C -40 C to +85 C Comcode (Ordering Number) 105742597 105742605 Lucent Technologies Inc. Data Sheet January 1998 T7288 CEPT/E1 Line Interface DS97-195TIC Replaces DS92-071SMOS Catalog CA95-003TIC Version to Incorporate the Following Updates 1. Data sheet format. Lucent Technologies Inc. 21 T7288 CEPT/E1 Line Interface Interactive Terminal Transmission Convergence Preliminary Data Sheet January 1998 For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 For data requests in Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148 For technical inquiries in Europe: CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 865 900 (Bracknell UK), FRANCE: (33) 1 41 45 77 00 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright (c) 1997 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. January 1998 DS97-195TIC (Replaces DS92-071SMOS) Printed On Recycled Paper