NJU3712A
-1-
Ver.2012-03-15
8-BIT SERIAL TO PARALLEL CONVERTER
GENERAL DESCRIPTION
The NJU3712A is a n 8-bit se rial to parallel c onverter
especially applying to MPU outport expander. It can
operate from 2.4V to 5.5V.
The effec tive outport ass ignment of MPU is availa ble
as the con nection between NJU3712A and M PU using
only 4 lines.
The serial data synchronizing with 5MHz or more
clock can be input to the serial data input terminal and
the data are output from parallel output buffer through
serial in parallel out shift register and parallel data
latches.
Furthermore, the NJU3712A outputs the serial data
from SO terminal through t he s hift regis te r. Theref or e, it
connects with other SIPO ICs like as NJU3711A in
cascade for expanding the parallel conversion outputs.
The hysteresis input circuit realizes wide noise
margin and the high drive-ability output buffer (25mA)
can drive LED directly.
FEATURES
8-Bit Serial In Parallel Out
Cascade Connection
Hysteresis Input 0.5V typ at 5V
Operating Voltage 2.4 to 5.5V
Maximum Operating Frequency 5MHz
Output Current 25mA at 5V, 5mA at 3V
C-MOS Technology
Package Outline SSOP16
BLOCK DIAG RAM
PACKAGE OUTLI NE
PIN CONFIGURATION
NJU3712AV
P3 1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
P2
P1
V
SS
CLR
STB
CLK
DATA
P4
P5
V
SS
P6
P7
P8
SO
NJU3712AV
P1
Shift Register
Co
n
t
r
o
ll
e
r
C
ir
cu
i
t
Latch Circuit
P2
P3
P7
P8
DAT
A
CL
K
STB
CLR
SO
NJU3712A
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Ver.2012-03-15
TERMINAL DESCRIPTION
No.
SYMBOL I/O FUNCTION
1 P3 O
2 P4 O
3 P5 O
Parallel Conversion Data Output Terminals
4 V
SS
- GND
5 P6 O
6 P7 O
7 P8 O
Parallel Conversion Data Output Terminals
8 SO O Serial Data Output Terminal
9 DATA I Serial Data Input Terminal
10 CLK I Clock Signal Input Terminal
11 STB I Strobe Signal Input Terminal
12 CLR I Clear Signal Input Terminal
13 V
SS
- GND
14 P1 O
15 P2 O
Parallel Conversion Data Output Terminals
16 V
DD
- Power Supply Terminal (2.4 to 5.5V)
NJU3555NJU3555NJU3712A
-3-
Ver .2012-03-15
FUNCTIONAL DESCRIPTION
(1) Reset
When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion
output are "L" level.
Norma l ly, the CL R t erminal should be "H" lev el.
(2) Data Transmission
In the STB term inal is "H" level and the clock signals are inputted to the CLK terminal, the serial data
into the DATA terminal are shif t ed in the shif t register synchronizin g at a rising edge o f the clock sig nal.
When the STB terminal is changed to "L" level, the data in the shift register are transferred to the
latches.
Even if the STB t ermina l is "L" level, the input clock signal sh if t s the dat a in t he shif t register, therefore,
the clock signal should be control led for data order.
(3) Cascade Connection
The serial data input from DATA term inal is output from the SO terminal through internal shift register
unrelated wit h t he CLR and STB status.
Furthermor e, t he 4 input circuit s provide a hyst eresi s charact eri st ics using the schmit t t r igger st ruct ure
to protect the noise.
CLK
STB CLR OPERATION
X X L
All of latches are reset (t he data in the shift register is no change).
All of p arallel c onversion output s are "L".
H H
The serial data into the DATA terminal are inputt ed to the shif t register.
In this stage, the data in the latch is not chang ed.
L
H
The data in the shift register is transferred to the latch. And the data in the
latch is output from the parall e l conversion output terminals.
L H
When the clock signal is inputted into the CLK terminal in state of the
STB="L" and CLR="H", the data is shifted in the shift register and latched
data is a lso change d in accordance w it h t he shift register.
Note 1)
X: Don’t care
NJU3712A
- 4 -
Ver.2012-03-15
TIMING CHART
CL
K
CLR
STB
DATA
P1
P2
P3
P4
P5
P6
P7
P8
SO
NJU3555NJU3555NJU3712A
-5-
Ver .2012-03-15
ABSOLUTE MAXIMUM RATING S
(Ta=25°C)
PARAMETER SYMBOL RATINGS UNIT
Suppl y Voltage R ang e V
DD
-0.5 ~ +7.0 V
Input Voltage Range V
I
V
SS
-0.5 ~ V
DD
+0.5 V
Output Voltage Ran ge V
O
V
SS
-0.5 ~ V
DD
+0.5 V
Output Current I
O
±25 mA
V
O
=7V, V
I
=0V 10 (max)
Output Short Curren t
(SO Terminal)
(Note 5)
I
OS
V
O
=0V, V
I
=7V -10 (max) mA
V
O
=7V, V
I
=0V 20 (max)
Output Short Curren t
(P1~P8 Terminals)
(Note 5)
I
OSD
V
O
=0V, V
I
=7V -20 (max) mA
Power Dissipation P
D
595 (SSOP)
(Note 6)
mW
Operating Temperature Range Topr -25 ~ +85 °C
Storage Temperature Range Tstg -65 ~+150 °C
Note 2)
All voltage are relative to V
SS
=0V reference.
Note 3)
Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also
recommended that the IC be used in the range specified in the DC electrical characteristics, or the electrical stress may cause
malfunctions and impact on the reliability.
Note 4)
To stabilize the IC operation, place decoupli ng capacitor between V
DD
and V
SS
.
Note 5)
V
DD
=7V, V
SS
=0V, less than 1 second per pin.
Note 6)
EIA/JEDEC Standard Test Board (76.2 x 114.3 x 1.6mm, 2layers, FR-4) m ounting.
DC ELECTRICAL CHARACTERIS TICS
(V
DD
=2.4~5.5V, V
SS
=0V, Ta=25°C, unless otherwise noted)
PARAMETER
SYMBOL
CONDITION MIN TYP MAX UNIT
Operating Voltage V
DD
2.4 -
5.5
V
Operating Current I
DDS
V
IH
=V
DD
, V
IL
=V
SS
- -
0.1
mA
High-level Output Voltage V
OH
I
OH
=-0.4mA V
DD
-0.4 - V
DD
V
Low-level Output Voltage V
OL
I
OL
=+3.2mA
SO
Terminal
V
SS
- 0.4 V
High-level Input Voltage V
IH
0.7V
DD
- V
DD
V
Low-level Input Voltage V
IL
V
SS
- 0.3V
DD
V
Input Leakage Current I
LI
V
I
=0
~
V
DD
-10 - 10 µA
I
OH
=-25mA
V
DD
-1.5 - V
DD
I
OH
=-15mA
V
DD
-1.0 - V
DD
V
DD
=5V
I
OH
=-10mA
V
DD
-0.5 - V
DD
High-level Output Voltage
(Note 6)
V
OHD
V
DD
=3V I
OH
=-5mA
P1~P8
Terminals
V
DD
-0.5 - V
DD
V
I
OL
=+25mA
V
SS
- 1.5
I
OL
=+15mA
V
SS
- 0.8
V
DD
=5V
I
OL
=+10mA
V
SS
- 0.4
Low-level Output Voltage
(Note 6)
V
OLD
V
DD
=3V I
OL
=+5mA
P1~P8
Terminals
V
SS
- 0.5
V
Note 7)
Specified value represent output current per pin. When use, total current consideration and less than power dissi pation in rating
operation shoul d be required.
NJU3712A
- 6 -
Ver.2012-03-15
NJU3555NJU3555NJU3712A
-7-
Ver .2012-03-15
SWITCHING CHARACTERISTICS
(V
DD
=2.4~5.5V, V
SS
=0V, Ta=25°C, unless otherwise noted)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT
Set-Up Time t
SD
DATA-CLK 20 -
-
ns
Hold T ime t
HD
CLK-DATA 20 - - ns
Set-Up Time t
SSTB
STB-CLK 30 - - ns
Hold T ime t
HSTB
CLK-STB 30 - - ns
t
pd O
CLK-SO - - 70 ns
t
pd PCK
CLK-P1~P8 - - 100 ns
t
pd PSTB
STB-P1~P8
- - 80 ns
Output Delay Time
t
pd PCLR
CLR-P1~P8 - - 80 ns
Maximum Operating Frequency
f
MAX
5 - - MHz
Note 8)
C
OUT
=50pF
NJU3712A
- 8 -
Ver.2012-03-15
SWITCHING CHARACTERISTICS TES T WAVEFORM
f
MAX
t
pd O
CL
K
t
SSTB
t
SD
t
HD
t
HSTB
DAT
A
STB
CL
K
SO
CL
K
P1~P8
STB
t
pd PCK
L
H
P1~P8
t
pd PSTB
CL
K
STB
H
P1~P8
t
pd PCLR
CLR
DAT
A
NJU3555NJU3555NJU3712A
-9-
Ver .2012-03-15
APPLICATION CIRCUIT (1)
APPLICATION CIRCUIT (2) ( Combi ned with NJU3711 A)
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
MPU
NJU3712A
DATA
CLK
STB
CLR
SO
P1 P2 P3 P4 P5 P6 P7 P8
MPU
NJU3712A
DATA
CLK
STB
CLR
SO
NJU3711A
DATA
CLK
STB
CLR
P1
P2
P3
P4
P5
P6
P7
P8
MOTOR
DRIVER
M
P1 P2 P3 P4 P5 P6 P7 P8
