73S1210F-IM68 EB - Maxim Integrated

73S1210F

Self-Contained Smart Card Reade r

with PINpad and Power Manage ment

Simplifying System Integration™

DATA SHEET

May 2009

GENERAL DESCRIPTION

The 73S1210F is a versatile and economical CMOS

System-on-Chip device intended for smart car d reader

applications. The circuit is built ar ound an 80515 hi gh-

performance core; it features primar il y an ISO-7816 / EMV

interface and a generic asynchronous se rial interface.

Delivered with turnkey Teridian embedded firm ware, it

forms a ready-to-use smart car d r eader solution that can be

seamlessly incorporated into any micropr oce ssor-based

system where a serial line is available.

The solution is scalable, thanks to a buil t-in I2

In addition, the cir cuit features an ON /OFF mode which

operates directly with an ON/OFF syst em switch: A ny

activity on the ON/O FF button is debounced i nternally

and controls the power generation circuit accordingly,

under the supervision of the firmware (OFF request /

OFF acknowledgement at firm ware level). The OFF

mode can be alternatively initiat ed from the controller

(firmware action instead of ON/OFF switch).

C interface

that allows to drive external electrica l smart card interfaces

such as Teridian 73S 8010 ICs. This makes the solution

immediately able to support multi-card slots or multi-SAM

architectures.

In addition, the 73S1210 features a 5x6 PINpad interface, 8

user I/Os, multiple interrupt options and an analog voltage

input (for DC volt age monitoring such as battery level

detection) that make it suitable for l ow-cost PINpad reader

devices.

The 80515 CPU core instruction set is compatible with the

industry standard 8051, while offering one clock-cycle per

instruction processing power (most instructions) . With a

CPU clock running up to 24MH z, it results in up to 24MIPS

available that meets the requirements of va r i ous encryption

needs such as AES, DES / 3-DES and even RSA (for PIN

encryption for instance).

The circuit r equi r es a single 6MHz to 12MHz crystal.

The respective 73S1210F embedded memories are 32KB

Flash program memory, 2KB use r XRAM memory, and

256B IRAM memory. Dedicated FIFOs f or the ISO 7816

UART are independent from the user XRAM and IRAM.

Alternatively to the turnkey firmware offered by Teridian,

customers can develop their own embedded firmware

directly within their application or using Teridian 73S1210F

Evaluation Board through a JTAG-like i nterface.

The chip incorporates an inductor-based DC -D C converter

that generates all t he nece ssary voltages to the various

73S1210F function blocks (smart card interface, digital

core, etc.) from any of two distinct power supply sources:

the +5V bus (VBUS, 4.4 to 6.5V), or a main battery (VBAT,

4.0V to 6.5V). The chip automatically powers-up the DC-

DC converter with VBUS if it is prese nt, or uses VBAT as the

supply input if VBUS is not present. Alternatively, t he pin VPC

can support a wider power supply input range (2.7V to

6.5V), when using a single system supply source.

In OFF mode, the circuit typically draws less than 1µA,

which makes it ideal for applications where battery life

must be maximized.

Embedded Flash memory is in-system progr ammable

and lockable by means of on-silicon fuses. This makes

the 73S1210F suitable f or both development and

production phases.

Teridian Semiconductor Corporation offers with its

73S1210F a very comprehensive set of software

libraries for EMV . Refer to the 73S12xxF Software

User’s Guide for a complete description of the

Application Programm i ng Interface (API Libraries) and

related software modules.

A complete array of development and pr ogramming

tools, libraries and dem onstration boards enable rapid

development and certif i ca tion of readers that meet

most demanding smart card standards.

APPLICATIONS

• PINpad smart car d readers:

o With serial connectivity

o Ideal for low-cost POS Terminals and Digital

Identification ( Secure Login, Gov’t ID, ...)

• SIM Readers in Perso nal Wireless devices

• Payphones & Vending machines

• General purpose smart card readers

ADVANTAGES

• Reduced BOM

• Versatile power supply options

o 2.7V to 6.5V ranges

• Higher performance CPU core (up to 24MIPS)

• Built-in EMV/IS O slot, expandable to multi-slots

• Flexible power supply options

o On-chip DC-DC converter

o CMOS switches between supply inputs

• Sub-µA Power Down mode with ON/OFF switch

• Powerful In-Circuit Emulation and P r ogramming

• A complete set of E MV4.1 / ISO7816 li br aries

• Turnkey PC/SC firmware and host drivers

o Multiple OS supported

73S1210F Data Sheet DS_1210F_001

2 Rev. 1.4

FEATURES

80515 Core:

• 1 clock cycle per instruction (most instructions)

• CPU clocked up to 24MHz

• 32KB Flash memory (lockable)

• 2kB XRAM (User Data Memory)

• 256 byte IRAM

• Hardware watchdog timer

Oscillators:

• Single low-cost 6MHz to 12MHz crystal

• An Internal PLL provides all the necessary clocks to

each block of the system

Interrupts:

• Standard 80C515 4-priority level structure

• 9 different source s of interrupt to t he core

Power Down Modes:

• 2 standard 80C515 Power Down and IDLE modes

• Sub-µA OFF mode

• ON/OFF Main System Power Switch:

• Input for an SPST momentary switch to ground

Timers:

• (2) Standard 80C52 timers T0 and T1

• (1) 16-bit timer

Built-in ISO-7816 Card Interface:

• Linear regulator produces V CC for the card

(1.8V, 3V or 5V)

• Full compliance with EMV 4.1

• Activation/Deactivation sequencers

• Auxiliary I/O lines (C4 and C8 signals)

• 7kV ESD protect i on on all interface pins

Communication with Smart Cards:

• ISO 7816 UART 9600 to 115kbps for T=0, T=1

• (2) 2-Byte FIFOs for transmit and receive

• Configured to drive multiple external Teridian

73S8010x interfaces (for multi-SAM architectures)

Voltage Detection:

• Analog Input (detection range: 1.0V to 2.5V)

Communication Interfaces:

• Full-duplex serial interface (1200 to 115kbps

UART)

• I2

• Man-Machine Interf ace and I/Os:

C Master Inter face (400kbps)

• 6x5 Keyboard (hardware scanning, debouncing

and scrambling)

• (8) User I/Os

• Single programmable current output (LED )

• Operating Voltage:

• Single supply 2.7V to 6.5V operat ion (VPC)

• 5V supply (VBUS 4.4V to 5.5V) with or without

battery back up operation (VBAT 4.0V to 6.5V)

• Automated detect i on of voltage presence - Priority

on VBUS over VBAT

DC-DC Converter:

• Requires a single 10µH Inductor

• 3.3V / 20mA supply available for ext er nal circuits

Operating Temperature:

• -40°C to 85°C

Package:

• 68-pin QFN, 44 pin QF N

Turnkey Firmware:

• Compliant with PC/SC, ISO 7816 and EMV4.1

specifications

• Features a Power Down mode accessible from the

host

• Supports Plug & Play over seri al i nterface

• Windows®

• Windows CE / Mobile driver available (*)

XP driver available (*)

• Linux and other OS: Upon request

• Or for custom developments:

o A complete set of ISO-7816, EMV4.1 and

low-level libraries are available for T =0 / T=1

o Two-level A ppli ca tion Programming Interface

(ANSI C-language libraries)

(*) Contact Teridian Semiconductor for conditions and

availability.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 3

Table of Contents

1 Hardware Description ......................................................................................................................... 8

1.1 Pin Description ............................................................................................................................. 8

1.2 Hardware Overview ................................................................................................................... 11

1.3 80515 MPU Core ....................................................................................................................... 11

1.3.1 80515 Overview ............................................................................................................. 11

1.3.2 Memory Organization .................................................................................................... 11

1.4 Program Security ....................................................................................................................... 16

1.5 Special Function Registers (SFRs) ........................................................................................... 18

1.5.1 Internal Data Special Function Registers (SFRs) .......................................................... 18

1.5.2 IRAM Special Function Registers (Generic 80515 SFRs) ............................................ 19

1.5.3 External Data Special Function Registers (SFRs) ........................................................ 20

1.6 Instruction Set ............................................................................................................................ 22

1.7 Peripheral Descriptions .............................................................................................................. 22

1.7.1 Oscillator and Clock Generation .................................................................................... 22

1.7.2 Power Supply Management .......................................................................................... 25

1.7.3 Power ON/OFF .............................................................................................................. 26

1.7.4 Power Control Modes .................................................................................................... 27

1.7.5 Interrupts ........................................................................................................................ 33

1.7.6 UART ............................................................................................................................. 40

1.7.7 Timers and Counters ..................................................................................................... 45

1.7.8 WD Timer (Software Watchdog Timer) ......................................................................... 47

1.7.9 User (USR) Ports ........................................................................................................... 49

1.7.10 Analog Voltage Comparator .......................................................................................... 51

1.7.11 LED Driver ..................................................................................................................... 53

1.7.12 I2 C Master Interface ....................................................................................................... 54

1.7.13 Keypad Interf ace ............................................................................................................ 61

1.7.14 Emulator Port ................................................................................................................. 68

1.7.15 Smart Card Interface Function ...................................................................................... 69

1.7.16 VDD Fault Detect Functi on .......................................................................................... 103

2 Typical Application Schematic ...................................................................................................... 104

3 Electrical Specification ................................................................................................................... 105

3.1 Absolute Maximum Ratings ..................................................................................................... 105

3.2 Recommended Operating Conditions ..................................................................................... 105

3.3 Digital IO Characteristics ......................................................................................................... 106

3.4 Oscillator Interface Requirements ........................................................................................... 107

3.5 DC Characteristics: Analog Input ............................................................................................. 107

3.6 Smart Card Interface Requirements ........................................................................................ 108

3.7 DC Characteristics ................................................................................................................... 110

3.8 Current Fault Detection Circuits ............................................................................................... 111

4 Equivalent Circuits ......................................................................................................................... 112

5 Package Pin Designation ............................................................................................................... 120

5.1 68-pin QFN Pinout ................................................................................................................... 120

5.2 44-pin QFN Pinout ................................................................................................................... 121

6 Packaging Information ................................................................................................................... 122

6.1 68-Pin QFN Package Outline .................................................................................................. 122

6.2 44-Pin QFN Package Outline .................................................................................................. 123

7 Ordering Information ...................................................................................................................... 124

8 Related Documentation .................................................................................................................. 124

9 Contact Information ........................................................................................................................ 124

Revision History ...................................................................................................................................... 125

73S1210F Data Sheet DS_1210F_001

4 Rev. 1.4

Figures

Figure 1: IC Functional Block Diagram ......................................................................................................... 7

Figure 2: Memory Map ................................................................................................................................ 15

Figure 3: Clock Generation and Control Circuits ........................................................................................ 22

Figure 4: Oscillator Circuit ........................................................................................................................... 24

Figure 5: Detailed Power Management Logi c B l ock Diagram .................................................................... 25

Figure 6: Power Down Control .................................................................................................................... 27

Figure 7: Detail of Power Down I nterrupt Logic .......................................................................................... 28

Figure 8: Power Down Sequencing ............................................................................................................ 29

Figure 9: External I nterrupt Configuration ................................................................................................... 33

Figure 10: I2 C Write Mode Operation .......................................................................................................... 55

Figure 11: I2 C Read Operation ................................................................................................................... 56

Figure 12: Simplified K eypad Block Diagram ............................................................................................. 61

Figure 13: Keypad Interface Flow Chart ..................................................................................................... 63

Figure 14: Smart Card Interface Block Diagram ......................................................................................... 69

Figure 15: External Sm art Card I nterface Block Diagram .......................................................................... 70

Figure 16: Asynchronous Activati on Sequence Timing .............................................................................. 73

Figure 17: Deactivation S equence .............................................................................................................. 73

Figure 18: Smart Card CLK and ETU Generation ...................................................................................... 74

Figure 19: Guard, Block, Wait and A T R Tim e Def i nitions .......................................................................... 75

Figure 20: Synchronous Activat ion ............................................................................................................. 77

Figure 21: Example of Sync Mode Operation: Generating/Reading AT R S i gnal s ..................................... 77

Figure 22: Creation of Synchronous Clock Start/Stop Mode Start Bi t in Sync Mode ................................. 78

Figure 23: Creation of Synchronous Clock Start/Stop Mode Stop Bit i n Sync Mode ................................. 78

Figure 24: Operation of 9-bit M ode in Sync Mode ...................................................................................... 79

Figure 25: 73S1210F Typical Appl i cat ion S chematic ............................................................................... 104

Figure 26: 12 MHz Oscillator Circuit ......................................................................................................... 112

Figure 27: 32KHz Oscillator Circuit ........................................................................................................... 112

Figure 28: Digital I/O Circuit ...................................................................................................................... 113

Figure 29: Digital Output Circuit ................................................................................................................ 113

Figure 30: Digital I/O with Pull Up Circuit .................................................................................................. 114

Figure 31: Digital I/O with Pull Down Circuit ............................................................................................. 114

Figure 32: Digital Input Circuit ................................................................................................................... 115

Figure 33: OFF_REQ Interf ace Circuit ..................................................................................................... 115

Figure 34: Keypad Row Circuit ................................................................................................................. 115

Figure 35: Keypad Column Circuit ............................................................................................................ 116

Figure 36: LED Circuit ............................................................................................................................... 116

Figure 37: Test and Security P i n Circuit ................................................................................................... 117

Figure 38: Analog Input Circuit ................................................................................................................. 117

Figure 39: Smart Card Output Circuit ....................................................................................................... 117

Figure 40: Smart Card I/O Circuit ............................................................................................................. 118

Figure 41: PRES Input Circuit ................................................................................................................... 118

Figure 42: PRESB Input Circuit ................................................................................................................ 118

Figure 43: ON_OFF Input Circuit .............................................................................................................. 119

Figure 44: 73S1210F 68 QFN Pinout ....................................................................................................... 120

Figure 45: 73S1210F 44 QFN Pinout ....................................................................................................... 121

Figure 46: 73S1210F 68 QFN Mechanical Drawing ................................................................................. 122

Figure 47: 73S1210F 44 QFN Package Drawing ..................................................................................... 123

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 5

Tables

Table 1: 73S1210 Pinout Description ........................................................................................................... 8

Table 2: MPU Data Memory M ap ............................................................................................................... 11

Table 3: Flash Special Function Registers ................................................................................................. 13

Table 4: Internal Data M em ory M ap ........................................................................................................... 14

Table 5: Program Security Regist ers .......................................................................................................... 17

Table 6: IRAM Special Functi on Regist ers Locations ................................................................................ 18

Table 7: IRAM Special Functi on Regist ers Reset Values .......................................................................... 19

Table 8: XRAM Special Function Regist ers Reset Values ......................................................................... 20

Table 9: PSW Register ................................................................................................................................ 21

Table 10: Port Registers ............................................................................................................................. 21

Table 11: Frequencies and Mcount Values for MCLK = 96M Hz ................................................................ 23

Table 12: The MCLKCtl Register ................................................................................................................ 23

Table 13: The TCON Register .................................................................................................................... 24

Table 14: The INT5Ctl Register .................................................................................................................. 30

Table 15: The MISCtl0 Regist er .................................................................................................................. 30

Table 16: The MISCtl1 Register .................................................................................................................. 31

Table 17: The MCLKCtl Register ................................................................................................................ 31

Table 18: The PCON Register .................................................................................................................... 32

Table 19: The IEN0 Register ...................................................................................................................... 34

Table 20: The IEN1 Register ...................................................................................................................... 35

Table 21: The IEN2 Register ...................................................................................................................... 35

Table 22: The TCON Register .................................................................................................................... 36

Table 23: The T2CON Register .................................................................................................................. 36

Table 24: The IRCON Register ................................................................................................................... 37

Table 25: External MP U Interrupts .............................................................................................................. 37

Table 26: Control Bits for External Interrupts .............................................................................................. 38

Table 27: Priority Lev el Groups .................................................................................................................. 38

Table 28: The IP0 Register ......................................................................................................................... 38

Table 29: The IP1 Register ......................................................................................................................... 39

Table 30: Priority Lev el s .............................................................................................................................. 39

Table 31: Interrupt Poll ing S equence .......................................................................................................... 39

Table 32: Interrupt Vectors ......................................................................................................................... 39

Table 33: UART Modes .............................................................................................................................. 40

Table 34: Baud Rate Generation ................................................................................................................ 40

Table 35: The PCON Register .................................................................................................................... 41

Table 36: The BRCON Register ................................................................................................................. 41

Table 37: The MISCtl0 Regist er .................................................................................................................. 42

Table 38: The S0CON Register .................................................................................................................. 43

Table 39: The S1CON Register .................................................................................................................. 44

Table 40: The TMOD Register .................................................................................................................... 45

Table 41: Timers/Counters Mode Description ............................................................................................ 45

Table 42: The TCON Register .................................................................................................................... 46

Table 43: The IEN0 Register ...................................................................................................................... 47

Table 44: The IEN1 Register ...................................................................................................................... 48

Table 45: The IP0 Register ......................................................................................................................... 48

Table 46: The WDTREL Register ............................................................................................................... 48

Table 47: Direction Registers and Internal Resources for DIO Pi n Groups ............................................... 49

Table 48: UDIR Control Bit ......................................................................................................................... 49

Table 49: Selectable Controls Using the UxIS Bits ..................................................................................... 49

Table 50: The USRIntCtl1 Register ............................................................................................................ 50

Table 51: The USRIntCtl2 Register ............................................................................................................ 50

Table 52: The USRIntCtl3 Register ............................................................................................................ 50

Table 53: The USRIntCtl4 Register ............................................................................................................ 50

Table 54: The ACOMP Register ................................................................................................................. 51

Table 55: The INT6Ctl Register .................................................................................................................. 52

Table 56: The LEDCtl Register ................................................................................................................... 53

73S1210F Data Sheet DS_1210F_001

6 Rev. 1.4

Table 57: The DAR Register ....................................................................................................................... 57

Table 58: The WDR Register ...................................................................................................................... 57

Table 59: The SWDR Register ................................................................................................................... 58

Table 60: The RDR Register ....................................................................................................................... 58

Table 61: The SRDR Register .................................................................................................................... 59

Table 62: The CSR Register ....................................................................................................................... 59

Table 63: The INT6Ctl Register .................................................................................................................. 60

Table 64: The KCOL Register ..................................................................................................................... 64

Table 65: The KROW Register ................................................................................................................... 64

Table 66: The KSCAN Register .................................................................................................................. 65

Table 67: The KSTAT Register ................................................................................................................... 65

Table 68: The KSIZE Regist er .................................................................................................................... 66

Table 69: The KORDERL Register ............................................................................................................. 67

Table 70: The KORDERH Register ............................................................................................................ 67

Table 71: The INT5Ctl Register .................................................................................................................. 68

Table 72: The SCSel Register .................................................................................................................... 80

Table 73: The SCInt Register ..................................................................................................................... 81

Table 74: The SCIE Register ...................................................................................................................... 82

Table 75: The VccCtl Register .................................................................................................................... 83

Table 76: The VccTmr Register .................................................................................................................. 84

Table 77: The CRDCtl Register .................................................................................................................. 85

Table 78: The STXCtl Register ................................................................................................................... 86

Table 79: The STXData Register ................................................................................................................ 87

Table 80: The SRXCtl Register ................................................................................................................... 87

Table 81: The SRXData Register ............................................................................................................... 88

Table 82: The SCCtl Register ..................................................................................................................... 89

Table 83: The SCECtl Register ................................................................................................................... 90

Table 84: The SCDIR Register ................................................................................................................... 91

Table 85: The SPrtcol Register ................................................................................................................... 92

Table 86: The SCCLK Register .................................................................................................................. 93

Table 87: The SCECLK Register ................................................................................................................ 93

Table 88: The SParCtl Register .................................................................................................................. 94

Table 89: The SByteCtl Register ................................................................................................................ 95

Table 90: The FDReg Register ................................................................................................................... 96

Table 91: The FDReg Bit Functions ............................................................................................................ 96

Table 92: Divider Ratios Provided by the ETU Counter ............................................................................. 96

Table 93: Divider Values for t he E T U Clock ............................................................................................... 97

Table 94: The CRCMsB Register ............................................................................................................... 98

Table 95: The BGT Register ....................................................................................................................... 99

Table 96: The EGT Register ....................................................................................................................... 99

Table 97: The BWTB0 Register ................................................................................................................ 100

Table 98: The BWTB1 Register ................................................................................................................ 100

Table 99: The BWTB2 Register ................................................................................................................ 100

Table 100: The BWTB3 Register .............................................................................................................. 100

Table 101: The CWTB0 Register .............................................................................................................. 100

Table 102: The CWTB1 Register .............................................................................................................. 100

Table 103: The ATRLsB Register ............................................................................................................. 101

Table 104: The ATRMsB Register ............................................................................................................ 101

Table 105: The STSTO Register .............................................................................................................. 101

Table 106: The RLength Register ............................................................................................................. 101

Table 107: Smart Card SFR Table ........................................................................................................... 102

Table 108: The VDDFCtl Register ............................................................................................................ 103

Table 109: Order Numbers and Packaging Marks ................................................................................... 124

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 7

SMART

CARD

ISO

INTERFACE

SCLK

SIO

EXTERNAL

SMART

CARD

INTERFACE

POWER

REGULATION

AND VCC

CONTROL

LOGIC

GND

VDD

TBUS1

TBUS2

TBUS3

TBUS0

RXTX

ERST

ISBR

TCLK

TXD

RXD

ICE INTERFACE

SEC

SMART CARD LOGIC

ISO UART and CLOCK GENERATOR

FLASH/ROM

PROGRAM

MEMORY

32KB

DATA

XRAM

2KB

CORE

SERIAL

INT2

INT3

GND

PERIPHERAL

INTERFACE

and SFR LOGIC

FLASH

INTERFACE

TEST

OCDSI

ISR

WATCH-

DOG

TIMER

PMU

PORTS

TIMER_0_1

MEMORY_

CONTROL CONTROL

UNIT

RAM_

SFR_

CONTROL

ALU

RESET

VOLTAGE REFERENCE

AND FUSE TRIM

CIRCUITRY

VPD REGULATOR

ANA_IN

PLL

and

TIMEBASES

VDD

SCRATCH

IRAM

256B

12MHz

OSCILLATOR

X12OUT

X12IN

COL4

COL3

COL2

COL1

COL0

ROW5

ROW4

ROW3

ROW2

ROW1

ROW0

KEYPAD

INTERFACE

MASTER

INT.SDA

SCL

USR(8:0)

DRIVERS

USR7

USR6

USR5

USR4

USR3

USR1

USR2

USR0

VCC

RST

CLK

I/O

AUX2

AUX1

PRES

VPC

GND

VBUS

VBAT

VDD

LIN

OFF_REQ

ON_OFF

GND

LED

DRIVER

LED0

Pins available on both 68 and 44-pin packages.

Pins only available on 68-pi n package.

Figure 1: IC Functional Block Diagram

73S1210F Data Sheet DS_1210F_001

8 Rev. 1.4

1 Hardware Description

1.1 Pin Description

Table 1: 73S1210 Pinout Descriptio n

Pin Name

Pin (68 QFN)

Pin (44 QFN)

Type

Equivalent

Circuit*

Description

X12IN 10 9 I Figure 26 MPU clock crystal oscillator input pin. A 1MΩ resistor is

required between pins X12IN and X12OUT.

X12OUT 11 10 O Figure 26 MPU clock crystal oscillator output pin.

ROW(5:0)

I Figure 34 Keypad row input sense.

COL(4:0)

O Figure 35 Keypad column output scan pins.

USR(7:0)

IO Figure 30 General-purpose user pins, individually configurable as

inputs or outputs or as external input interrupt ports.

SCL 5 6 O Figure 29 I2C (master mode) compatible Clock signal. Note: the pin

is configured as an open drain output. When t he I2C

interface is being used, an external pul l up resistor is

required. A value of 3K is recommended.

SDA 6 7 IO Figure 28 I

C (master mode) compatible data I/ O . Not e: this pin is bi-

directional. When the pin is configured as out put, it is an

open drain output. When the I 2C i nterface is being used,

an external pull up resistor is required. A value of 3K is

recommended.

RXD 17 11 I Figure 32 Serial UART Receive data pin.

TXD 18 12 O Figure 29 Serial UART Transmit data pin.

INT3 48 30 I Figure 32 General purpose interrupt input.

INT2 49 31 I Figure 32 General purpose interrupt input.

SIO 47 29 IO Figure 28 IO data signal for use with external Smart Card interface

circuit such as 73S8010.

SCLK 45 28 O Figure 29 Clock signal for use with external Smart Card interface

circuit.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 9

Pin Name

Pin (68 QFN)

Pin (44 QFN)

Type

Equivalent

Circuit*

Description

PRES 53 34 I Figure 41 Smart Card presence. Active high. Not e: the pin has a

very weak pull down resistor. In noisy environments, an

external pull down may be desired to i nsure against a

false card event.

CLK 55 36 O Figure 39 Smart Card clock signal.

RST 57 38 O Figure 39 Smart Card reset signal.

IO 61 42 IO Figure 40 Smart Card Data IO signal.

AUX1 60 41 IO Figure 40 Auxiliary Smart Card IO signal (C4).

AUX2 59 40 IO Figure 40 Auxiliary Smart Card IO signal (C8).

VCC 58 39 PSO Smart Card VCC supply voltage output. A 0.47µF

capacitor is required and should be located at the smart

card connector. The capacitor should be a ceramic type

with low ESR.

GND 56 37 GND S m art Card Ground.

VPC 65 44 PSI P ower supply source for m ai n voltage converter circuit. A

10µF and a 0.1µF capacitor are requi red at the VPC input.

The 10µF capacitor should be a ceramic type with low

ESR.

VBUS 62 PSI Alternate power source input from external power supply.

VBAT 64 PSI Alternate power source input, typically from two series

cells, V > 4V.

VP 54 35 PSO Intermediate output of main converter circuit. Requi res an

external 4.7µF low E SR filter capacitor to GND.

LIN 66 1 PSI Connection to 10µH inductor for internal step up

converter. Note: inductor must be rat ed for 400 mA

maximum peak current.

ON_OFF 63 43 I Figure 43 Power control pin. Connected to normally open SPST

switch to ground. Closing switch for duration great er than

debounce period will turn 73S1210F on. If 73S1210F is

on, closing switch will flag the 73S1210F t o go to the off

state. Firmware will control when the power i s shut down.

OFF_REQ 52 33 O Figure 33 Digital output. I f ON_OFF switch is closed (to ground) for

debounce duration and circuit is “on,” OFF_REQ will go

high (Request to turn OFF). This out put should be

connected to an interrupt pin to signal the CPU core that a

request to shut down power has been initiated. The

firmware can then perform all of its shut down

housekeeping duties before shutting down VDD.

TBUS(3:0)

Trace bus signals for ICE.

73S1210F Data Sheet DS_1210F_001

10 Rev. 1.4

Pin Name

Pin (68 Qfn)

Pin (44 QFN)

Type

Equivalent

Circuit*

Description

RXTX 43 27 IO ICE control.

ERST 38 23 IO ICE control.

ISBR 3 IO ICE control.

TCLK 39 24 I ICE control.

ANA_IN 15 AI Figure 38 Analog input pin. T hi s signal goes t o a programm abl e

comparator and is used to sense the value of an ex ternal

voltage.

SEC 2 I Figure 37 Input pin for use in programming security fuse. It should be

connected to ground when not in use.

TEST 51 32 DI Figure 37 Test pin, should be connected to ground

LED0 4 5 IO Figure 36 Special output driver, programm abl e pull-down current to

drive LED. May also be used as an input .

VDD 68

PSO

VDD supply output pin. A 0.1µF capacitor is recommended

at each VDD pin.

N/C 7

No connect.

GND

General ground supply pins for all IO and logi c circuits.

RESET 1 4 I Figure 32 Reset input, positiv e asserti on. Resets logic and registers

to default condition. Not e: to insure proper reset operation

after VDD is turned on by application of VBUS power or

activation of the O N/ O FF swit ch, external reset circuitry

must generate a proper reset signal to the 73S 1210F. This

can be accomplished via a simple RC network.

* See the figures in the Equivalent Circuits section.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 11

1.2 Hardware O ver view

The 73S1210F single smart card controller integrates all pri m ary functional blocks required to implement

a smart card reader. Included on chip are an 8051-compatible microprocessor (MPU) which executes up

to one instruction per clock cycle (80515), a fully i ntegrated IS0 7816 compliant smart card interf ace,

expansion smart card interface, serial interf ace, I2C interface, 6 x 5 keypad interface, RAM , FLASH

memory, and a variety of I/O pins.

The power management circuitry provides a 3.3V voltage output (VDD, pin #68) t hat must be connected

to the power supply inputs of the digital core of the circuit, pins # 28 and 40 (these are not i nternally

connected). Should external circuitry require a 3.3V digital power supply, the V DD out put is capable of

supplying additional current.

Figure 1 shows a functional block diagram of the 73S 1210F.

1.3 80515 MPU Core

1.3.1 80515 Overview

The 73S1210F includes an 80515 MPU (8-bit, 8051-compatible) that performs most instructions in one

clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution

of fetch and execution phases. Normal l y a machine cycle is aligned with a memory fetch, therefore, most

of the 1-byte instructions are perf orm ed i n a singl e cy cle. This leads to an 8x performance (average)

improvement (in terms of M IPS) over the Intel 8051 device running at the same clock frequency.

Actual processor clocking speed can be adjusted to the total processing demand of the application

(cryptographic calculations, key management, m em ory management, and I/O management) using the

XRAM special function register MPUCKCtl.

Typical smart card, serial, keyboard and I 2C managem ent functions are available for the MP U as part of

the Teridian standard library. A st andard A NS I “C” 80515-application programming interface library is

available to help reduce design cycle. Ref er to the 73S12xxF Software User’s Guide.

1.3.2 Memory Organization

The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.

Memory organization in the 80515 is simi l ar to that of the industry st andard 8051. There are three

memory areas: Program memory (Flash), ex ternal data memory (XRAM), and int ernal data memory

(IRAM). Data bus address space is allocated to on-chip memory as shown Table 2

Table 2: MPU Data Memory Map

Address

(hex) Memory

Technology Memory Type Typi cal Usage Memory Size

(bytes)

0000-7FFF Flash Memory Non-volatile Program and non-volatile data 32KB

0000-07FF Static RAM Volatile MPU data XRAM 2KB

FC00-FFFF External SFR Volatile Peripheral control 1KB

Note: The IRAM is part of the core and is addressed differently.

Program Memory : The 80515 can address up to 32K B of program memory space from 0x0000 to

0xFFFF. Program memory i s read when t he M P U fetches instructions or performs a MOVC operation.

After reset, the MPU starts program execution from location 0x0000. The l ower part of the program

memory includes reset and interrupt v ect ors. T he i nterrupt vectors are spaced at 8-byte intervals, st arting

from 0x0003. Reset is located at 0x0000.

Flash Memory: The program m em ory consists of flash memory. The flash memory i s intended to

primarily contain MPU program code. F lash erasure is initiated by writing a specific data pattern to

73S1210F Data Sheet DS_1210F_001

12 Rev. 1.4

specific SFR registers in the proper sequence. These special pattern/sequence requirement s prev ent

inadvertent erasure of the flash m em ory .

The mass erase sequence is:

1. Write 1 to the FLSH_MEEN bit in the FLSHCTL register (SFR address 0xB2[ 1] ).

2. Write pattern 0xAA to ERASE (SFR address 0x94).

Note: The mass erase cycle can only be init iated when the ICE port is enabled.

The page erase sequence is:

1. Write the page address to PGADDR (SFR address 0xB7[7:1]).

2. Write pattern 0x55 t o ERASE (SFR address 0x94).

The PGADDR register denotes the page address for page erase. The page size is 512 (200h) bytes and

there are 128 pages within the flash memory. The PGADDR denotes the upper seven bits of the flash

memory address such that bit 7:1 of the PGADDR corresponds to bit 15:9 of t he flash memory address.

Bit 0 of the PGADDR is not used and is ignored. The MPU may write to the f lash m em ory . This is one of

the non-volatile storage opt i ons av ai l able to the user. The FLSHCTL SFR bit FLSH_PWE (flash program

write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and X RA M

writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL = 1. Table 3 shows

the location and description of t he 73S1210 flash-specific SFR s.

Any flash modifications must set the CPUCLK to operate at 3.6923 MHz (MPUCLKCtl = 0x0C)

before any flash memory operat i ons are ex ecut ed to insure the proper timing when modifying the

flash memory.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 13

Table 3: Flash Special Function Registers

Address R/W Description

ERASE 0x94 W This register is used to initiate eit her the Flash Mass Erase cycle or the

Flash Page Erase cycle. Specific pat terns are expected for ERASE in

order to initiate the appropriat e E rase cycle (defaul t = 0x00).

0x55 –

Initiate Flash Page Erase cycle. Must be proceeded by a write

to PGADDR @ SFR 0xB7.

0xAA – Initiate Flash Mass Erase cycle. M ust be proceeded by a write

to FLSH_MEEN @ SFR 0xB2 and the debug port must be

enabled.

Any other pattern written to ERASE will have no effect.

PGADDR 0xB7 R/W Flash Page Erase Address register containing the flash memory page

address (page 0 through 127) that will be erased during the Page Erase

cycle (default = 0x00). Note: the page address is shifted left by one bit

(see detailed description above).

Must be re-written for each new Page Erase cycle.

FLSHCTL 0xB2 R/W

Bit 0 (FLSH_PWE): Program Write Enable:

0 – MOVX commands refer to XRAM Space, normal operation (default).

1 – MOVX @DPTR,A m oves A to Program Space (Flash) @ DPTR.

This bit is automatically reset after each byte written to fl ash. Writes to

this bit are inhibited when interrupts are enabled.

W Bit 1 (FLSH_MEEN): Mass Erase Enable:

0 – Mass Erase disabled (default).

1 – Mass Erase enabled.

Must be re-written for each new Mass Erase cycle.

R/W Bit 6 (SECURE):

Enables security provisions that prev ent external reading of flash

memory and CE program RAM. Thi s bit is reset on chip reset and may

only be set. Attempts to write zero are ignored.

Internal Data Memory: The Int ernal data memory provides 256 bytes (0x00 t o 0xFF) of data memory.

The internal data memory address is always one byte wide and can be accessed by either direct or

indirect addressing. The Special Function Registers occupy t he upper 128 bytes. This SFR area is

available only by direct addressing. Indirect addressing accesses the upper 128 bytes of Internal

RAM.

The lower 128 bytes contain working registers and bit-addressable memory. T he l ower 32 bytes form

four banks of eight registers (R0-R7). Two bits on t he program m em ory status word (PSW) select which

bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addresses 0x00-

0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. Table 4

shows the internal data memory map.

73S1210F Data Sheet DS_1210F_001

14 Rev. 1.4

Table 4: Internal Data Memory Map

Address Direct Addressing Indirect Addressing

0xFF Special Function

Registers (SFRs) RAM

0x80

0x7F Byte-addressable area

0x30

0x2F Byte or bit-addressable area

0x20

0x1F Register banks R0…R7 (x4)

0x00

External Data Memory: While the 80515 can address up to 64KB of external data memory in the space

from 0x0000 to 0xFFFF, only the memory ranges shown in Figure 2 contain physical m em ory. The

80515 writes into external data m em ory when the MPU executes a MOVX @Ri,A or M O V X @DPTR,A

instruction. The MPU reads ext ernal data memory by executing a MOV X A,@Ri or MOVX A,@DPTR

instruction.

There are two types of instructions, di ffering in whether they provide an eight-bit or six teen-bit indirect

address to the external data RAM .

In the first ty pe (MO V X A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight

lower-ordered bits of address. This method allows the user access to the first 256 bytes of the 2KB of

external data RAM. In the second type of MOVX inst ruct i on (M OVX A,@DPTR), the data pointer

generates a sixteen-bit address.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 15

Address Use

0xFFFF Peripheral Control

Registers (128b)

0XFF80

0xFF7F Smart Card Control

(384b)

0XFE00

Address Use

0xFBFF

–

0x7FFF

Flash

Program

Memory

32K

Bytes

0x0800

Address Use

0x07FF

XRAM

Indirect Access Direct Access

0xFF Byte RAM SFRs

0x80

0x7F Byte RAM

0x48

0x47 Bit/Byte RAM

0x20

0x1F Register bank 3

0x18

0x17 Register bank 2

0x10

0x0F Register bank 1

0x08

0x07 Register bank 0

0x0000

0x00

Program Memory External Data Memory Internal Data Memory

Figure 2: Memory Map

Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a

16-bit register that is used to address external m em ory. In the 80515 core, the standard dat a poi nter is

called DPTR, the second data pointer is called DPT R1. T he data pointer select bit chooses the active

pointer. The data pointer select bi t is located at the LSB of t he DPS IRAM special function register

(DPS.0). DPTR is selected when DPS. 0 = 0 and DP T R1 is select ed when DP S .0 = 1.

The user switches between pointers by toggling the LS B of the DPS register. All DPTR-related

instructions use the currently selected DPTR for any activity.

The second data pointer may not be supported by certain compilers.

73S1210F Data Sheet DS_1210F_001

16 Rev. 1.4

1.4 Program Security

Two levels of program and data security are available. Each level requires a specific fuse to be bl own in

order to enable or set the specific security m ode. Mode 0 security is enabled by setting the SECURE bit

(bit 6 of SFR register FLSHCTL 0xB2). M ode 0 li m i ts the ICE interface to only al l ow bulk erase of the

flash program memory. All ot her ICE operations are blocked. This guarantees the security of the user’s

MPU program code. Security (Mode 0) is enabled by MPU code that sets the SECURE bit. The MPU

code must execute the setting of the SECURE bit immediat ely after a reset to properly enable Mode 0.

This should be the first instruction after the reset vector jump has been executed. If the “startup.a51”

assembly file is used in an application, then it must be modified to set the SECURE bit after the reset

vector jump. If not using “startup.a51”, then this should be the fi rst i nst ructi on in m ain(). O nce security

Mode 0 is enabled, the only way to disable it is to perform a global erase of t he flash followed by a full

circuit reset. Once the flash has been erased and the reset has been executed, security Mode 0 is

disabled and the ICE has full cont rol of the core. The flash can be reprogrammed after t he bul k erase

operation is completed. Global erase of the flash will also clear the data XRAM mem ory.

The security enable bit (SECURE) is reset whenever the MPU is reset. Hardware associated with the bit

only allows it to be set. As a result, the code may set the SECURE bit to enable the security Mode 0

feature but may not reset i t. Once the SECURE bit is set, the code is protected and no external read of

program code in flash or data (in XRAM) is possible. In order to invoke the security Mode 0, the

SECSET0 (bit 1 of the XRAM SFR register SECReg 0xFFD7) fuse must be blown beforehand or the

security mode 0 will not be enabled. The S ECSET0 and SECSET1 fuses once blown, cannot be

overridden.

Specifically, when SECURE is set:

• The ICE is limited t o bul k flash erase only.

• Page zero of flash memory, the preferred location for the user’s preboot code, may not be page-

erased by either MPU or ICE. Page zero may only be erased with global flash erase. Not e that

global flash erase erases XRAM whether the SE CURE bi t is set or not.

• Writes to page zero, whether by MPU or I CE , are inhibited.

Security mode 1 is in effect when the SECSET1 fuse has been programmed (blown open). In security

mode 1, the ICE is complet el y and permanently disabled. The Flash program mem ory and the MPU are

not available for alteration, observation, nor control. A s soon as the fuse has been blown, the ICE is

disabled. The testing of the SECSET1 fuse will occur during the reset and bef ore the start of pre-boot

and boot cycles. This mode is not rev ersible, nor recoverable. In order to blow the SECS E T 1 fuse, the

SEC pin must be held high for the fuse burning sequence to be executed properly. The f i rmware can

check to see if this pin is held high by reading the SECPIN bit (bit 5 of X RA M SFR register SECReg

0xFFD7). If this bit is set and the firmware desires, it can blow the SECS ET1 fuse. The burning of the

SECSET0 does not require the S E C pin to be held high.

In order to blow the fuse for S E CS ET1 and SECSET0, a particular set of regist er writ es in a specif ic order

need to be followed. There are two additional registers that need to have a specific v al ue written to them

in order for the desired fuse to be blown. These regist ers are FUSECtl (0xFFD2) and TRIMPCtl

(0xFFD1). The sequence for blowing the fuse is as f ol l ows:

1. Write 0x54H to FUSECtl.

2. Write 0x81H for security mode 0. Note: only program one security mode at a time.

Write 0x82H for security mode 1. Note: SEC pin must be high for security m ode 1.

3. Write 0xA6 to TRIMPCtl.

4. Delay about 500 µs.

5. Write 0x00 to TRIMPCtl and FUSECtl.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 17

Table 5: Program Security Registers

Address R/W Description

FLSHCTL 0xB2 R/W Bit 0 (FLSH_PWE): Program Write Enable:

0 – MOVX commands refer to XRAM Space, normal operation (default).

1 – MOVX @DPTR,A m oves A to Program Space (Flash) @ DPTR.

This bit is automatically reset after each byte written to fl ash. Writes to

this bit are inhibited when interrupts are enabled.

W Bit 1 (FLSH_MEEN): Mass Erase Enable:

0 – Mass Erase disabled (default).

1 – Mass Erase enabled.

Must be re-written for each new Mass Erase cycle.

R/W Bit 6 (SECURE):

Enables security provisions that prevent external reading of flash

memory and CE program RAM. Thi s bit is reset on chip reset and may

only be set. Attempts to write zero are ignored.

TRIMPCtl 0xFFD1 W 0x54 value will set up f or security fuse control. All other val ues are

reserved and should not be used.

FUSECtl 0xFFD2 W 0xA6 value will cause the selected fuse to be blown. All other values

will stop the burning process.

SECReg 0xFFD7 W Bit 7 (PARAMSEC):

0 – Normal operation.

1 – Enable permanent programming of the security fuses.

R Bit 5 (SECPIN):

Indicates the state of the SEC pin. The SEC pin is held low by a

pull-down resistor. The user can force this pin high during boot

sequence time to indicate to fi rmware t hat sec mode 1 is desired.

R/W Bit 1 (SECSET1):

See the Program Security secti on.

R/W Bit 0 (SECSET0):

See the Program Security secti on.

73S1210F Data Sheet DS_1210F_001

18 Rev. 1.4

1.5 Special Function Register s ( SFRs)

The 73S1210F utilizes numerous SFRs to communicate with the 73S1210Fs many peripherals. This

results in the need for more SFR locati ons outside the direct address IRAM space (0x80 to 0xFF). Whil e

some peripherals are mapped to unused IRAM SFR locati ons, addi tional SFRs for the smart card and

other peripheral functions are mapped to the top of the XRAM data space (0xFC00 to 0xFFFF).

1.5.1 Internal Data Special Function Registers (SFRs)

A map of the Special Funct i on Registers is shown in Table 6.

Table 6: IRAM Special Function Registers Locations

Hex\Bin X000 X001 X010 X011 X100 X101 X110 X111 Bin/

Hex

F8 FF

F0 B F7

E8 EF

E0 A E7

D8 BRCON DF

D0 PSW

KCOL

KROW

KSCAN

KSTAT

KSIZE

KORDERL

KORDERH

C8 T2CON CF

C0 IRCON C7

B8 IEN1 IP1 S0RELH S1RELH BF

B0 FLSHCTL PGADDR B7

A8 IEN0 IP0 S0RELL AF

A0 A7

98 S0CON S0BUF IEN2 S1CON S1BUF S1RELL 9F

USR70

UDIR70

DPS

ERASE

88 TCON TMOD TL0 TL1 TH0 TH1

MCLKCtl

80 SP DPL DPH DPL1 DPH1 WDTREL PCON 87

Only a few addresses are used, the others are not implement ed. SFRs specific to the 73S1210F are

shown in bold print (gray background). Any read access to unimplem ented addresses will return

undefined data, while most write access will have no effect. However, a f ew l ocat i ons are reserved and

not user configurable in the 73S1210F. Writes to the unused SFR locations can affect the operation

of the core and therefore must not be written to. This applies to all the SFR areas in both the

IRAM and XRAM spaces. In addition, all unused bit locations within valid SFR registers must be

left in their default (power on default) states.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 19

1.5.2 IRAM Special Function Registers (Generic 80515 SFRs)

Table 7 shows the location of the S F Rs and t he value they assume at reset or power-up.

Table 7: IRAM Special Functi o n Regi sters Reset V alues

Name Location Reset Value Description

SP 0x81 0x07 Stack Pointer

DPL 0x82 0x00 Data Pointer Low 0

DPH 0x83 0x00 Data Pointer High 0

DPL1 0x84 0x00 Data Pointer Low 1

DPH1 0x85 0x00 Data Pointer High 1

WDTREL 0x86 0x00 Watchdog Timer Reload register

PCON 0x87 0x00 Power Control

TCON 0x88 0x00 Timer/Counter Control

TMOD 0x89 0x00 Timer Mode Control

TL0 0x8A 0x00 Timer 0, low byte

TL1 0x8B 0x00 Timer 1, high by te

TH0 0x8C 0x00 Timer 0, low byte

TH1 0x8D 0x00 Timer 1, high byte

MCLKCtl 0x8F 0x0A Master Clock Control

USR70 0x90 0xFF User Port Data (7: 0)

UDIR70 0x91 0xFF User Port Direction (7: 0)

DPS 0x92 0x00 Data Pointer Select Register

ERASE 0x94 0x00 Flash Erase

S0CON 0x98 0x00 Serial Port 0, Cont rol Regist er

S0BUF 0x99 0x00 Serial Port 0, Data Buffer

IEN2 0x9A 0x00 Interrupt Enable Register 2

S1CON 0x9B 0x00 Serial Port 1, Control Register

S1BUF 0x9C 0x00 Serial Port 1, Data Buffer

S1RELL 0x9D 0x00 Serial Port 1, Reload Register, low byte

IEN0 0xA8 0x00 Interrupt Enable Register 0

IP0 0xA9 0x00 Interrupt Priority Register 0

S0RELL 0xAA 0xD9 Serial Port 0, Reload Register, low byte

FLSHCTL 0xB2 0x00 Flash Control

PGADDR 0xB7 0x00 Flash Page Address

IEN1 0xB8 0x00 Interrupt Enable Register 1

IP1 0xB9 0x00 Interrupt Priority Register 1

S0RELH 0xBA 0x03 Serial Port 0, Reload Register, high byte

S1RELH 0xBB 0x03 Serial Port 1, Reload Register, high byte

IRCON 0xC0 0x00 Interrupt Request Control Register

T2CON 0xC8 0x00 Timer 2 Control

PSW 0xD0 0x00 Program Status Word

KCOL 0XD1 0x1F Keypad Column

73S1210F Data Sheet DS_1210F_001

20 Rev. 1.4

Name Location Reset Value Description

KROW 0XD2 0x3F Keypad Row

KSCAN 0XD3 0x00 Keypad Scan Time

KSTAT 0XD4 0x00 Keypad Control/Status

KSIZE 0XD5 0x00 Keypad Size

KORDERL 0XD6 0x00 Keypad Column LS Scan Order

KORDERH 0XD7 0x00 Keypad Column MS Scan Order

BRCON 0xD8 0x00 Baud Rate Control Register (only BRCON.7 bit used)

A 0xE0 0x00 Accumulator

B 0xF0 0x00 B Register

1.5.3 External Data Special Function Registers (SFRs)

A map of the XRAM Special Function Registers is shown in Table 8. The smart card registers are listed

separately in Table 107.

Table 8: XRAM Special Functi on Registers Reset Values

Name Location Reset Value Description

DAR 0x FF80 0x00 Device Address Register (I2C)

WDR 0x FF81 0x00 Write Data Register (I2C)

SWDR 0x FF82 0x00 Secondary Write Data Register (I2C)

RDR 0x FF83 0x00 Read Data Register (I2C)

SRDR 0x FF84 0x00 Secondary Read Data Register (I2C)

CSR 0x FF85 0x00 Control and Status Register (I2C)

USRIntCtl1 0x FF90 0x00 External Interrupt Control 1

USRIntCtl2 0x FF91 0x00 External Interrupt Control 2

USRIntCtl3 0x FF92 0x00 External Interrupt Control 3

USRIntCtl4 0x FF93 0x00 External Interrupt Control 4

INT5Ctl 0x FF94 0x00 External Interrupt Control 5

INT6Ctl 0x FF95 0x00 External Interrupt Control 6

MPUCKCtl 0x FFA1 0x0C MPU Clock Control

ACOMP 0x FFD0 0x00 Analog Compare Register

TRIMPCtl 0x FFD1 0x00 TRIM Pulse Control

FUSECtl 0x FFD2 0x00 FUSE Control

VDDFCtl 0x FFD4 0x00 VDDFault Cont rol

SECReg 0x FFD7 0x00 Security Register

MISCtl0 0x FFF1 0x00 Miscellaneous Control Register 0

MISCtl1 0x FFF2 0x10 Miscellaneous Control Register 1

LEDCtl 0x FFF3 0xFF LED Control Register

Accumulator (ACC, A): A CC i s t he accumulator register. Most instructions use the accumulator to hold

the operand. The mnemonics for accumulator-specific instructions ref er to accumulator as “A”, not ACC.

B Register: The B register is used during multipl y and divide instructions. It can also be used as a

scratch-pad register to hold t em porary data.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 21

Program Status Word (PSW):

Table 9: PSW Register

MSB LSB

CV AC F0 RS1 RS OV – P

Bit Symbol Function

PSW.7 CV Carry flag.

PSW.6 AC Auxiliary Carry flag for BCD operations.

PSW.5 F0 General purpose Flag 0 available for user.

PSW.4 RS1 Register bank select control bits. The contents of RS1 and RS0 select the

working register bank:

RS1/RS0 Bank Selected Location

00 Bank 0 (0x00 – 0x07)

01 Bank 1 (0x08 – 0x0F)

10 Bank 2 (0x10 – 0x17)

11 Bank 3 (0x18 – 0x1F)

PSW.3 RS0

PSW.2 OV Overflow flag.

PSW.1 F1 General purpose Flag 1 available for user.

PSW.0 P Parity flag, affect ed by hardware to indicate odd / even number of “one” bi ts

in the Accumulator, i.e. even parity.

Stack Pointer: The stack pointer (SP) is a 1-byte register init i al i zed t o 0x07 after reset. This register is

incremented before PUSH and CALL instructions, causing t he st ack t o begi n at location 0x08.

Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part i s DPL, and the highest is DPH.

It can be loaded as a 2-byte register (MOV DPTR,#data16) or as two registers (e.g. MOV DPL,#data8). It

is generally used to access external code or data space (e.g. M OVC A,@A+DPTR or MOVX A,@DPTR

respectively).

Program Counter: The program counter (PC) is 2 bytes wide initiali zed to 0x0000 after reset. This

memory. Note: The program count er i s not m apped to the SFR area.

Port Registers: The I/O ports are controlled by S pecial Funct i on Regi st er USR70. The cont ents of the

SFR can be observed on corresponding pins on the chip. Writing a 1 to any of the ports (see Table 10)

causes the corresponding pin to be at high level (3. 3V ), and writing a 0 causes the corresponding pin to

be held at low level (GND). The data direct i on regist er UDIR70 define individual pins as input or output

pins (see the User (USR) Ports section for details).

Table 10: Port Registers

Address R/W Description

USR70 0x90 R/W Register for User port bit 7:0 read and write operat i ons (pins USR0…

USR7).

UDIR70 0x91 R/W Data direction register for User port bits 0:7. Setting a bit to 0 means

that the corresponding pin is an output.

73S1210F Data Sheet DS_1210F_001

22 Rev. 1.4

All ports on the chip are bi-directional. Each consists of a Latch (SFR ‘USR70’), an output driv er, and an

input buffer, therefore t he M P U can output or read data through any of these port s if they are not used for

alternate purposes.

1.6 Instruction Set

All instructions of the generic 8051 m i crocontroller are support ed. A complete list of the inst ruct i on set

and of the associated op-codes is contained in the 73S12xxF Software User’s Guide.

1.7 Peripheral Descripti ons

1.7.1 Oscillator and Clock Generation

The 73S1210F has one oscillator circuit for the m ai n CP U clock. The m ai n oscillator circuit is designed to

operate with various crystal or ext ernal clock frequencies. A n i nternal divider working in conjunction with a

PLL and VCO provides a 96MHz internal clock within the 73S1210F. 96 MHz is the recommended

frequency for proper operation of specific peripheral bl ocks such as the specific timers, ISO 7816 UART

and interfaces, Step-up converter, and keypad. The clock generation and control circuits are shown in

Figure 3.

VCO

Phase

Freq

DET

CPU CLOCK

DIVIDER

6 bits

MCLK

96MHz

1.5-48MHz

MPU CLOCK - CPCLK

SMART CARD L OGIC

BLOCK CLOCK

SCCLK

SCLK

CLOCK

Prescaler 6bits

SC/SCE

CLOCK

Prescaler 6bits SEL

ETU CLOCK

DIVIDER

12 bits

CPUCKDiv

See SC Clock descriptions f or more accurat e di agram

ETUCLK

MCount(2:0)

KEYCLK

I2CCLK

1kHz

400kHz

DIVIDE

by 120

DIVIDER

/93760

HIGH

XTAL

OSC

X12IN

X12OUT

M DIVIDER

/(2*N + 4)

HCLK

HOSCen

12.00MHz

div 2

ICLK

SCCKenb

SELSC

DIVIDE

by 96 CLK1M

1MHz

7.386MHz 7.386MHz

3.6923MHz

I2C_2x

800kHz

div 2

SCECLK

div 2 div 2

Figure 3: Clock Generation and Control Circuits

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 23

The master clock control register enables different secti ons of the clock circuitry and specifies the value

of the VCO Mcount divi der. The MCLK must be configured to operate at 96MHz to ensure proper

operation of some of the peripheral bl ocks according to t he following formula:

MCLK = (Mcount * 2 + 4) * FXTAL = 96MHz

Mcount is configured in the MCLKCtl regist er m ust be bound between a value of 1 to 10. The possible

crystal or external clock frequencies for getting M CLK = 96M Hz are shown in Table 11.

Table 11: Frequencies and Mcount Values for MCLK = 96MHz

FXTAL (MHz) Mcount (N)

12.00 2

9.60 3

8.00 4

6.86 5

6.00 6

Master Clock Control Regi s ter (M CL KCtl): 0x8F  0x0A

The MPU clock that drives the CPU core def aul ts to 3.6923MHz after reset. The MPU clock is scalable

by configuring the MPU Clock Control register.

Table 12: The MCLKCtl Register

MSB LSB

HSOEN KBEN SCEN – – MCT.2 MCT.1 MCT.0

Bit

Symbol

Function

MCLKCtl.7 HSOEN High-speed oscillator disable. When set = 1, disables the high-speed

crystal oscillator and VCO/PLL syst em . Do not set this bit = 1.

MCLKCtl.6 KBEN 1 = Disable the keypad logic clock.

MCLKCtl.5 SCEN 1 = Disable the smart card logic clock.

MCLKCtl.4 –

MCLKCtl.3 –

MCLKCtl.2 MCT.2 This value determines the ratio of the VCO frequency (MCLK) to the

high-speed crystal oscillator frequency such that:

MCLK = (MCount*2 + 4)* FXTAL. The default v al ue is M Count = 2h such

that MCLK = (2*2 + 4)*12.00MHz = 96MHz.

MCLKCtl.1 MCT.1

MCLKCtl.0 MCT.0

73S1210F Data Sheet DS_1210F_001

24 Rev. 1.4

MPU Clock Control Register (MPUCKCtl): 0xFF A1  0x0C

Table 13: The TCON Register

MSB LSB

– – MDIV.5 MDIV.4 MDIV.3 MDIV.2 MDIV.1 MDIV.0

Bit

Symbol

Function

MPUCKCtl.7 –

MPUCKCtl.6 –

MPUCKCtl.5 MDIV.5 This value determines the ratio of the MPU master clock frequency to the

VCO frequency (MCLK) such that

MPUClk = MCLK/(2 * (M PUCKDiv(5:0) + 1)).

Do not use values of 0 or 1 for MP UCKDiv(n).

Default is 0Ch to set CPCLK = 3.6923MHz.

MPUCKCtl.4 MDIV.4

MPUCKCtl.3 MDIV.3

MPUCKCtl.2 MDIV.2

MPUCKCtl.1 MDIV.1

MPUCKCtl.0 MDIV.0

The oscillator circuits are designed to connect directly to standard parallel resonant crystal in a Pierce

oscillator configuration. Each side of the crystal should include a 22pF capacitor to ground for both

oscillator circuits and a 1MΩ resistor is required across the 12MHz crystal.

73S1210F

X12IN

X12OUT

12MHz

22pF 22pF

1MΩ

Note: The crystal should be placed as close as possible to the I C, and vias should be avoided.

Figure 4: Oscillator Circuit

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 25

1.7.2 Power Supply Management

The detailed power supply management logic block diagram i s shown in Figure 5.

BUS

BAT

BUSTH

SET

CLR

Debounce

Circuit

ON_OFF

DC-DC

Converter

/ Pass

Through*

Delay

Circuit

(POR)

VPC

VCC

Regulator

LIN

OFF_REQ

INT3

MPU

INT

PWRDN*

*PWRDN bit in MISCtl0

VDD

VCC

Power

Control

VCC Voltage

Select

VCC Enable

Pass Through

Mode Enable

PTEN

SET

CLR

*Pass Through -> VP = VPC

Smart

Card

Power

To optional

external

circuits

20mA max.

VDD

Regulator

VDD to

Internal

Circuits

Figure 5: Detailed Power Management Logic Block Diagram

The 73S1210F contains a power supply and converter circuit that takes power from any one of three

sources; VPC, VBUS, or VBAT.

VPC is specified to range from 2.7 to 6.5 volts. It can typically be supplied by a single cell battery with a

voltage range of 2.7 t o approximately 3.1 volts or by a st andard supply of 3.3 or 5 volts.

VBUS is typically supplied by an external power supply and ranges in value from 4.4 to 5.5 volts (6.5V maximum).

73S1210F Data Sheet DS_1210F_001

26 Rev. 1.4

VBAT is expected to be supplied from a bat tery of three to four series connected cells with a voltage value

of 4.0 to 6.5 vol ts.

VBAT and VBUS are internally switched to VPC by two separate FET switches configured as a SPDT swit ch

(break-before-make). They will not be enabled at the same time. VBUS is automatically selected in lieu of

VBAT when VBUS is present (i.e. VBUS always has t he priority).

If VPC is provided and either VBAT or VBUS is also used, the source of VPC must be diode isolated from t he

VPC pin to prevent current f low from VBAT or VBUS into the VPC source.

The power that is supplied to the VPC pi n (externally or internally, i .e. through VBAT or VBUS – see above) is

up-converted to the intermedi ate voltage VP utilizing an inductiv e, step-up converter. A series power

inductor (nominal value = 10 µH) must be connected from VPC to the pin LIN, and a 10µF low ESR filter

capacitor must be connected to VPC.

VP requires a 4.7µF filter capacitor and will have a nominal value of 5.5 volts during normal operation. VP

is used internally by the smart card electri cal i nterface circuit and is regulated to the desired smart card

supply VCC voltage (can be programmed for values of 5V, 3V, or 1.8V ).

VP is also used internally to generat e a 3.3V nominal, regulated power supply VDD. VDD is out put on pin

68 and must be directly tied to all other VDD pins on the 73S1210F (pins 28 and 40). VDD powers all the

digital logic, input/ output buffering, and analog funct i ons. It can also be used for external circuitry: up to

20mA current can be supplied to external devices simultaneously to the 73S1210F’s digital core

maximum consumption.

1.7.3 Power ON/OFF

The 73S1210F features an ON_OFF input pi n for a momentary contact, main-syst em O N/ O FF swit ch. T he

purpose of this switch is to place the circuit in a very low-power mode – the “OFF” mode – where all circuits

are no longer powered, therefore allowing the lowest possible current consumpt ion.

When in “OFF” mode, an action on the O N/ OF F swit ch will turn-on the power supply of the digital core

(VDD) and apply a power-on-reset condition. Alt ernatively, entering the “OFF ” m ode from the “ON” mode

requires firmware action.

When in “ON” mode, an action on the ON/OFF swit ch wil l send a request to the controller that will have to

be acknowledged (firmware action required) in order to enter the “OFF” state.

When placed into the “OFF” state, the 73S1210F will consume minimum current from VPC and VBAT; VP

and VDD will be unavailable (VDD out = 0V and VP = 0V).

When in “ON” mode, the 73S1210F will operate normal l y, with all the features described in t his document

available. VP and VDD will be available (VDD out = 3.3V and VP = 5.5V nominal).

Whenever VBUS power is supplied, the circuit will be automatically in the “ON” state. The functions of the

ON/OFF switch and circuitry are overridden and t he 73S 1210F i s i n the “ON” state with VP and VDD available.

Without VBUS applied, t he circuit i s by default in the “OFF” state, and will respond only to the ON_OFF pin.

The ON_OFF pin should be connected to an SPS T swit ch t o ground. If the circuit is OFF and the switch

is closed for a debounce period of 50-100ms, the circuit wi ll go i nto the “ON” state wherein all functions

are operating in normal fashion. If the circuit is in the “ON” state and the ON/OFF pin i s connected to

ground for a period greater than the debounce period, O FF _RE Q will be asserted hi gh and hel d

regardless of the state of ON/OF F. The OFF_REQ signal should be connected to one of the interrupt

pins to signal the CPU core that a request to shutdown has been initiated. The firmware will

acknowledge this request by setting the S CP WRDN bit in the Smart Card VCC Control/Status Register

(VccCtl) high after it has completed all shutdown activit i es. When SCP WRDN is set high, the circuit will

deactivate the smart card int erf ace if required and turn off all analog functi ons and the VDD supply for the

logic and companion circuits. The default st ate upon application of power is the “OFF” state unless

power is supplied to the VBUS supply. Not e that at any time, the firmware may assert SCPWRDN and the

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 27

73S1210F will go into the “OFF ” st ate (when VBUS is not present). If the ON/ O FF swit ch function is not

desired and the application does not need to shut down power on V DD, the ON_OFF input can be

permanently grounded which will automat icall y turn on VDD when power is supplied on any of the VP C,

VBAT or VBUS power supply inputs.

If power is applied to both VBAT and VBUS, the circuit will automatically consume power from onl y the VBUS

source. The 73S1210F will be unconditionally “ON” when VBUS is applied. If the VBUS source is removed,

the 73S1210F will switchover to the VBAT input supply and remain i n the “ON” state. The firmware

should assert SCPWRDN based on no activity or VBUS removal to reduce battery power consumption.

When operating from VBUS, and not calli ng for VCC, the step-up converter becomes a simple switch

connecting VBUS to VP in order to save power.

Note: When the ON_OFF switch functi on i s not needed, i.e. when the 73S1210F must be in an al way s-ON

state when using another supply than V B US (VPC or V BAT), some external discrete components are needed.

1.7.4 Power Control Modes

The 73S1210F contains circuitry to disable portions of the device and place it into a lower power standby

mode or power down the 73S1210F into its “OFF” m ode. The standby mode will stop the core, clock

subsystem and the peripherals connected to it. Thi s i s accomplished by ei ther shutting off the power or

disabling the clock going to the block. The M i scellaneous Cont rol regi st ers MISCtl0, MISCtl1 and the

Master Clock Control register (MCLKCtl) provide control over the power modes. The PWRDN bit in

MISCtl0 will setup the 73S1210F for standby or “OFF” m odes. Depending on the state of the ON/OFF

circuitry and power applied to the VB US i nput, the 73S1210F will go into either standby mode or power

“OFF” mode. If system power is provi ded by, VBUS or the ON/OFF circuitry is i n the “ON” state, the MPU

core will placed into standby mode. If the VBUS input is not sourcing power and t he ON/ O FF circuit ry is

in the “OFF” state, setting the PWRDN bit will shut down the converter and VP will turn off. The power

down mode should only be initiated by setting the PWRDN bit in the MISCtl0 register and not by

manipulating individual cont rol bi ts in various registers. Figure 6 shows how the PWRDN bit controls the

various functions that comprise power down state.

VDDFAULT

Analog functions

(VCO, PLL,

reference and bias

circuits, etc.)

ANALOG

COMPARE

High Speed OSC

MISCtl0 - PWRDN

VDDFCtl - VDDFEN

ACOMP - CMPEN

MCLCKCtl - HOSEN

Smart Card Power

SCVCCCtl - SCPRDN

These are the registers and

the names of the control bits. These are the block

references.

PWRDN Signal

Note: the PWRDN Signal is not the direct version of the PWRDN Bit. Ther e ar e delays f rom assertion of the PWRDN

bit to the assertion of the PWRDN Signal (32 MPU clocks). Ref er to the Power Down sequence diagram.

Flash Read Pulse

one-shot circuit

MISCtl1 - FRPEN

Figure 6: Power Down Control

73S1210F Data Sheet DS_1210F_001

28 Rev. 1.4

When the PWRDN bit is set, the clock subsystem wil l prov i de a del ay of 32 MPUCLK cycles to allow the

program to set the STOP bi t in the PCON register. This delay will enable the program to properly halt the

core before the analog circuits shut down (high speed oscillator, V CO/PLL, voltage reference and bias

circuitry, etc.). The PDMUX bit in SFR INT5Ctl should be set prior to setting the PWRDN bit in order to

configure the wake up interrupt logic. T he power down mode is de-asserted by any of the interrupts

connected to external interrupts 0, 4 and 5 (external USR[0:7], smart card and Keypad). These interrupt

sources are OR’ed together and routed through some delay logic into INT0 to provide this functi onal i ty.

The interrupt will turn on the power t o al l secti ons t hat were shut off and start the clock subsystem. After

the clock subsystem clocks start running, the MPUCLK begi ns t o clock a 512 count delay counter. When

the counter times out, the interrupt will then be active on INT0 and the program can resume. Figure 7

shows the detailed logic for waking up the 73S1210F from a power down state using these specific

interrupt sources. Figure 8 shows the timing associated wit h the power down mode.

USR[7:0] Control

USRxINTSrc set to

4(ext INT0 high)

6(ext INT0 low) 1

INT5

INT4

RESETB

CLR

9 BIT CNTR

RESETB

PDMUX

(FF94h:bit7)

MPU

INT0

PWRDN_analogQ

CLR

PWRDN

(FFF1h:bit7)

USR0

USR6

USR1

USR2

USR3

USR4

USR5

USR7

CLR

5 BIT CNTR

Notes:

1. The counters are clocked by the MPUCLK

2. TC - Terminal count (high at ov er flow)

3. CE - Count enable

RESETB

Figure 7: Detail of Power Down Interrupt Logic

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 29

PWRDN BIT

PWRDN SIG

EXT. EVENT

INT0 to MPU

MPU STOP

ANALOG Enable

PLL CLOCKS

t0: MPU sets PWRDN bit.

t1: 32 MPU clock cycles after t0, the PWRDN SIG is asserted, turning all analog functions OFF.

t2: MPU executes STOP instruction, must be done prior t o t 1.

t3: Analog functions go to OFF condition. No Vref, PLL/VCO, Ibias, etc.

text

text: An external event (RTC, Keypad, Card event, USB) occu rs.

t4: PWRDN bit and PWRDN signal are cleared by external event.

t5: High-speed oscillator/PLL/VCO operating.

t6: After 512 MPU clock cycles, INT0 to MPU is assert ed.

t7: INT0 causes MPU to exit STOP condition.

Figure 8: Power Down Sequencing

73S1210F Data Sheet DS_1210F_001

30 Rev. 1.4

External Interrupt Control Register (INT5Ctl): 0xFF94  0x00

Table 14: The INT5Ctl Register

MSB LSB

PDMUX – – – – – KPIEN KPINT

Bit Symbol Function

INT5Ctl.7 PDMUX

When set = 1, enables interrupts from Keypad (normally going to int5),

Smart Card interrupts (normally going to int4), or USR(7:0) pins (int0) to

cause interrupt on int0. The assertion of the interrupt to int0 is delayed by

512 MPU clocks to allow the analog circuits, including the clock system, to

stabilize. This bit must be set prior to asserting the PWRDN bit in order to

properly configure the interrupts that will wake up the circuit. This bit is

reset = 0 when this register is read.

INT5Ctl.6 –

INT5Ctl.5 –

INT5Ctl.4 –

INT5Ctl.3 –

INT5Ctl.2 –

INT5Ctl.1 KPIEN Keypad interrupt enable.

INT5Ctl.0 KPINT Keypad interrupt flag.

Miscellaneous Control Register 0 (MISCtl0): 0xFFF1  0x00

Table 15: The MISCtl0 Register

MSB LSB

PWRDN – – – – – SLPBK SSEL

Bit Symbol Function

MISCtl0.7 PWRDN

This bit sets the circuit into a low-power conditi on. All analog (high-speed

oscillator and VCO/PLL) functions are disabled 32 MPU clock cycles after

this bit is set = 1. This allows t i m e for the next instruction to set the STOP

bit in the PCON register to stop the CPU core. The M P U is not operative in

this mode. When set, thi s bi t overrides the individual control bits that

otherwise control power consumption.

MISCtl0.6 –

MISCtl0.5 –

MISCtl0.4 –

MISCtl0.3 –

MISCtl0.2 –

MISCtl0.1 SLPBK UART loop back testing mode.

MISCtl0.0 SSEL Serial port pins select.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 31

Miscellaneous Control Register 1 (MISCtl1): 0xFFF2  0x10

Table 16: The MISCtl1 Register

MSB LSB

– – FRPEN FLSH66 – – – –

Bit Symbol Function

MISCtl1.7 –

MISCtl1.6 –

MISCtl1.5 FRPEN

Flash Read Pulse enable (low). If FRPEN = 1, the Flash Read signal is

passed through with no change. When FRPEN = 0 a one-shot circuit that

shortens the Flash Read signal is enabled to save power. T he F l ash Read

pulse will shorten to 40 or 66ns (approximate based on t he set ting of the

FLSH66 bit) in duration, regardless of the MPU clock rate. For MPU clock

frequencies greater than 10MHz, this bit should be set hi gh.

MISCtl1.4 FLSH66 When high, creates a 66ns Flash read pulse, otherwise creates a 40ns

read pulse when FRPEN is set.

MISCtl1.3 –

MISCtl1.2 –

MISCtl1.1 –

MISCtl1.0 –

Master Clock Control Regi s ter (M CL KCtl): 0x8F  0x0A

Table 17: The MCLKCtl Register

MSB LSB

HSOEN KBEN SCEN – – MCT.2 MCT.1 MCT.0

Bit Symbol Function

MCLKCtl.7 HSOEN* High-speed oscillator enable. When set = 1, disables the high-speed

crystal oscillator and VCO/PLL syst em . This bit is not changed when the

PWRDN bit is set but the oscillator/VCO/PLL is disabled.

MCLKCtl.6 KBEN 1 = Disable the keypad logic clock. This bit is not changed in PWRDN

mode but the function is disabled.

MCLKCtl.5 SCEN 1 = Disable the smart card logic clock. This bit is not changed in P WRDN

mode but the function is disabled. Interrupt logic for card insertion/remov al

remains operable even with smart card clock disabled.

MCLKCtl.4 –

MCLKCtl.3 –

MCLKCtl.2 MCT.2 This value determines the ratio of the VCO frequency (MCLK) to the

high-speed crystal oscillator frequency such that:

MCLK = (MCount*2 + 4)*Fxtal. T he default value is MCount = 2h such

that MCLK = (2*2 + 4)*12.00MHz = 96MHz.

MCLKCtl.1 MCT.1

MCLKCtl.0 MCT.0

*Note: The HSOEN bit should never be set under normal circumstances. Power down control should

only be initiated via use of the PWRDN bit in MISCtl0.

73S1210F Data Sheet DS_1210F_001

32 Rev. 1.4

Power Control Register 0 (PCON): 0x87  0x00

The SMOD bit used for the baud rate generator is set up via this register.

Table 18: The PCON Register

MSB LSB

SMOD – – – GF1 GF0 STOP IDLE

Bit Symbol Function

PCON.7 SMOD If SM0D = 1, the baud rate is doubled.

PCON.6 –

PCON.5 –

PCON.4 –

PCON.3 GF1 General purpose flag 1.

PCON.2 GF0 General purpose flag 1.

PCON.1 STOP Sets CPU to Stop mode.

PCON.0 IDLE Sets CPU to Idle mode.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 33

1.7.5 Interrupts

The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request

flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the

corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and

IEN2. Some of the 10 sources are multiplex ed i n order to expand the number of interrupt sources.

These are described in more detail in the respectiv e secti ons.

External interrupts are the i nterrupts external to the 80515 core, i. e. signals that originate in other parts of

the 73S1210F, for exampl e the USR I/O, smart card interface, analog comparators, etc. The external

interrupt configuration is shown in Figure 9.

USR

Int

Ctl

USR

Int

Ctl

USR

Int

Ctl

SCInt

W ai t T i meout

Card Event

RxData

TX_Event

Tx_Sent

TX_Error

RX_Error

Card_Det

VCC_OK

CRDCtl

VccCTL

SCIE

VCC_TMR

Analog

Comp

KeyPad

USR

Int

Ctl

int0

int1

USR

Pads

USR0

USR7

USR6

USR5

USR4

USR3

USR2

USR1

INT2

INT3

INT

Pads

int2

int3

Serial

Ch 0

Serial

Ch 1

SerChan 0 int

SerChan 1 int

int4

INT5

Ctl

INT6

Ctl

int5

int6

During STOP, I DLE

when PWRDN bit i s set

MPU

CORE

VDD_Fault

Delay

Clear PWRDN bit

PDMUXCtl

Figure 9: External Interrupt Configuration

73S1210F Data Sheet DS_1210F_001

34 Rev. 1.4

1.7.5.1 Interrupt Overview

When an interrupt occurs, the MPU will vect or to the predetermined address as shown in Table 32. Once

the interrupt service has begun, it can only be interrupted by a higher priority interrupt. The interrupt

service is terminated by a return from the RETI instruction. When a RETI is performed, the processor will

return to the instruction t hat would have been next when the interrupt occurred.

When the interrupt condition occurs, the processor will also indicat e this by setting a flag bit. T hi s bit is

set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per

machine cycle, then samples are polled by the hardware. If the sample indicates a pending i nterrupt

when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the

interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address.

Interrupt response will require a varying am ount of time depending on the state of t he M PU when the

interrupt occurs. If the MPU is performing an interrupt service with equal or greater priori ty, the new

interrupt will not be invoked. In other cases, the response time depends on the current instruction. T he

fastest possible response to an interrupt is 7 machine cycles. T hi s includes one m achine cy cle for

detecting the interrupt and six cy cles to perform the LCALL.

1.7.5.2 Special Function Registers for Interrupts

Interrupt Enable 0 Register (I EN0): 0xA8  0x00

Table 19: The IEN0 Register

MSB LSB

EAL WDT – ES0 ET1 EX1 ET0 EX0

Bit Symbol Function

IEN0.7 EAL EAL = 0 – disable all interrupts.

IEN0.6 WDT Not used for interrupt control.

IEN0.5 –

IEN0.4 ES0 ES0 = 0 – disable serial channel 0 interrupt.

IEN0.3 ET1 ET1 = 0 – disable timer 1 overflow interrupt.

IEN0.2 EX1 EX1 = 0 – disable external interrupt 1.

IEN0.1 ET0 ET0 = 0 – disable timer 0 overflow interrupt.

IEN0.0 EX0 EX0 = 0 – disable external interrupt 0.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 35

Interrupt Enable 1 Register (I EN1): 0xB8  0x00

Table 20: The IEN1 Register

MSB LSB

– SWDT EX6 EX5 EX4 EX3 EX2 –

Bit Symbol Function

IEN1.7 –

IEN1.6 SWDT Not used for interrupt control.

IEN1.5 EX6 EX6 = 0 – disable external interrupt 6.

IEN1.4 EX5 EX5 = 0 – disable external interrupt 5.

IEN1.3 EX4 EX4 = 0 – disable external interrupt 4.

IEN1.2 EX3 EX3 = 0 – disable external interrupt 3.

IEN1.1 EX2 EX2 = 0 – disable external interrupt 2.

IEN1.0 –

Interrupt Enable 2 Register (I EN2): 0x9A  0x00

Table 21: The IEN2 Register

MSB LSB

– – – – – – – ES1

Bit Symbol Function

IEN2.0 ES1 ES1 = 0 – disable serial channel interrupt.

73S1210F Data Sheet DS_1210F_001

36 Rev. 1.4

Timer/Counter Control Register (TCON): 0x88  0x00

Table 22: The TCON Register

MSB LSB

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Bit Symbol Function

TCON.7 TF1 Ti m er 1 overflow flag.

TCON.6 TR1 Not used for interrupt control.

TCON.5 TF0 Ti m er 0 overflow flag.

TCON.4 TR0 Not used for interrupt control.

TCON.3 IE1 Interrupt 1 edge fl ag i s set by hardware when the falling edge on external

interrupt int1 is observed. Cleared when an i nterrupt is processed.

TCON.2 IT1 Interrupt 1 type cont rol bi t. 1 selects falling edge and 0 selects low level f or

input pin to cause an interrupt.

TCON.1 IE0 Interrupt 0 edge flag is set by hardware when the fal li ng edge on external

interrupt int0 is observed. Cleared when an i nterrupt is processed.

TCON.0 IT0 Interrupt 0 type cont rol bi t. 1 selects falling edge and 0 sets low level for input

pin to cause interrupt.

Timer/Interrupt 2 Control Register (T2CON): 0xC8  0x00

Table 23: The T2CON Register

MSB LSB

– I3FR I2FR – – – – –

Bit Symbol Function

T2CON.7 –

T2CON.6 I3FR External interrupt 3 faili ng/rising edge flag.

I3FR = 0 external interrupt 3 negative transition active.

I3FR = 1 external interrupt 3 positive transition active.

T2CON.5 I2FR External interrupt 3 faili ng/rising edge flag.

I2FR = 0 external interrupt 3 negative transition active.

I2FR = 1 external interrupt 3 positi ve transition active.

T2CON.4 –

T2CON.3 –

T2CON.2 –

T2CON.1 –

T2CON.0 –

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 37

Interrupt Request Re g ister (IRCON): 0xC0  0x00

Table 24: The IRCON Regis ter

MSB LSB

– – EX6 IEX5 IEX4 IEX3 IEX2 –

Bit Symbol Function

IRCON.7 –

IRCON.6 –

IRCON.5 IEX6 External int errupt 6 flag.

IRCON.4 IEX5 External int errupt 5 flag.

IRCON.3 IEX4 External int errupt 4 flag.

IRCON.2 IEX3 External int errupt 3 flag.

IRCON.1 IEX2 External int errupt 2 flag.

IRCON.0 –

1.7.5.3 External Interrupts

The external interrupts (external to the CPU core) are connected as shown in Table 25. Interrupts with

multiple sources are OR’ed together and indivi dual interrupt source control is provided in XRAM SFRs to

mask the individual interrupt sources and provide the corresponding interrupt flags. Multifunct i on US R

[7:0] pins control Int errupt s 0 and 1. Dedicated external interrupt pins INT2 and INT3 control interrupts 2

and 3. The polarity of i nterrupts 2 and 3 is programmable in the MPU. I nterrupts 4, 5 and 6 have multiple

peripheral sources and are multiplexed to one of these three interrupts. The peripheral functions will be

described in subsequent sections. Generic 80515 MPU literature st ates that interrupts 4 through 6 are

defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 4, 5 and 6 are

converted to rising edge level by the hardware.

SFR (special function register) enable bits must be set to permit any of these interrupt s t o occur.

Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset aut om atically

by the MPU interrupt handl er.

Table 25: External MPU Interrupts

External

Interrupt Connection Polarity Flag Reset

0 USR I/O High Priority see USRIntCtlx Automatic

1 USR I/O Low Priority see USRIntCtlx Automatic

2 External Int errupt Pin INT2 Edge selectable Automatic

3 External Int errupt Pin INT3 Edge selectable Automatic

4 Smart Card Interrupts N/A Automatic

5 Keypad N/A Automatic

6 I2N/A C, VDD_Fault, Analog Comp Automatic

Note: Interrupts 4, 5 and 6 have multiple interrupt sources and the flag bits are cleared upon reading of

the corresponding register. To prevent any interrupts from being ignored, the register containing m ultiple

interrupt flags should be stored temporary to allow each interrupt flag to be test ed separat el y to see which

interrupt(s) is/are pending.

73S1210F Data Sheet DS_1210F_001

38 Rev. 1.4

Table 26: Control Bits for External Interrupts

Enable Bit Description Flag Bit Description

EX0 Enable external interrupt 0 IE0 External interrupt 0 flag

EX1 Enable external interrupt 1 IE1 External interrupt 1 flag

EX2 Enable external interrupt 2 IEX2 External interrupt 2 flag

EX3 Enable external interrupt 3 IEX3 External interrupt 3 flag

EX4 Enable external interrupt 4 IEX4 External interrupt 4 flag

EX5 Enable external interrupt 5 IEX5 External interrupt 5 flag

EX6 Enable external interrupt 6 IEX6 External interrupt 6 flag

1.7.5.4 Power Down Interrupt Logic

The 73S1210F contains special interrupt logic t o al l ow INT0 to wake up the CPU from a power down

(CPU STOP) state. See the Power Control Modes section for details.

1.7.5.5 Interrupt Priority Level Structure

All interrupt sources are combined in groups, as shown in Table 27.

Table 27: Priority Level Groups

Group

0 External interrupt 0 Serial channel 1 interrupt

1 Timer 0 interrupt – External interrupt 2

2 External interrupt 1 – External interrupt 3

3 Timer 1 interrupt – External interrupt 4

4 Serial channel 0 interrupt – External interrupt 5

5 – – External interrupt 6

Each group of interrupt sources can be programmed individually to one of four priority lev el s by set ting or

clearing one bit in the special function regist er IP0 and one in IP1. If requests of the same priority level

are received simultaneously, an int ernal pol li ng sequence as per Table 31 determines which request is

serviced first.

IEN enable bits must be set t o permi t any of these interrupts to occur. Likewise, each interrupt has its

own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler.

Interrupt Priority 0 Register (IP0): 0xA9  0x00

Table 28: The IP0 Register

MSB LSB

– WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0

Note: WDTS is not used for interrupt cont rols.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 39

Interrupt Priority 1 Register (IP1): 0xB9  0x00

Table 29: The IP1 Register

MSB LSB

– – IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0

Table 30: Priority Levels

IP1.x IP0.x Priority Lev el

0 0 Level0 (lowest)

0 1 Level1

1 0 Level2

1 1 Level3 (highest)

Table 31: Interrupt Polling Sequence

External interrupt 0

Polling sequence

Serial channel 1 interrupt

Timer 0 interrupt

External interrupt 2

External interrupt 1

External interrupt 3

Timer 1 interrupt

Serial channel 0 interrupt

External interrupt 4

External interrupt 5

External interrupt 6

1.7.5.6 Interrupt Sources and Vectors

Table 32 shows the interrupts with t hei r associated flags and vector addresses.

Table 32: Interrupt Vectors

Interrupt Request Flag Description Interrupt Vector Address

N/A Chip Reset 0x0000

IE0 External interrupt 0 0x0003

TF0 Timer 0 interrupt 0x000B

IE1 External interrupt 1 0x0013

TF1 Timer 1 interrupt 0x001B

RI0/TI0 Serial channel 0 interrupt 0x0023

RI1/TI1 Serial channel 1 interrupt 0x0083

IEX2 External interrupt 2 0x004B

IEX3 External interrupt 3 0x0053

IEX4 External interrupt 4 0x005B

IEX5 External interrupt 5 0x0063

IEX6 External interrupt 6 0x006B

73S1210F Data Sheet DS_1210F_001

40 Rev. 1.4

1.7.6 UART

The 80515 core of the 73S1210F includes two separate UARTs that can be programmed to communicate

with a host. The 73S1210F can only connect one UART at a time since there is only one set of TX and

Rx pins. The MISCtl0 register is used to select which UART is connected to the TX and RX pins. Each

UART has a different set of operat i ng m odes t hat the user can select according to their needs. The

UART is a dedicated 2-wire serial interface, which can communicat e with an external host processor at

up to 115,200 bits/s. The T X and RX pins operat e at the VDD supply voltage levels and should never

exceed 3.6V. The operation of each pin is as follows:

RX: Serial input dat a i s appli ed at this pin. Conforming to RS-232 standard, the bytes are input LSB first.

The voltage applied at RX m ust not exceed 3.6V.

TX: This pin is used to output the serial data. The bytes are output LSB first.

The 73S1210F has several UART-related read/write regist ers. A l l UA RT transfers are programmable for

parity enable, parity select, 2 stop bits/1 stop bit and XON/ XOFF options for variable communication baud

rates from 300 to 115200 bps. Table 33 shows the selectabl e UART operation modes and Table 34

shows how the baud rates are calculated.

Table 33: UART Modes

UART 0 UART 1

Mode 0 N/A Start bit, 8 data bi ts, parity, stop bit, variable

baud rate (internal baud rate generator).

Mode 1 Start bit, 8 dat a bi ts, stop bit, variable

baud rate (internal baud rate generator

or timer 1).

Start bit, 8 data bits, stop bit, variabl e baud

rate (internal baud rate generator).

Mode 2 Start bit, 8 data bits, parity, stop bit, fixed

baud rate 1/32 or 1/64 of fCKMPU. N/A

Mode 3 Start bit, 8 data bits, parity, stop bit,

variable baud rate (internal baud rate

generator or timer 1). N/A

Note: Parity of serial data is available through the P flag of the accumulator. Seven-bit serial m odes with

parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit

output data. Sev en-bi t serial modes without parity can be simulat ed by setting bit 7 to a constant 1. 8-bit

serial modes with parity can be simulated by setting and reading the 9th bit, using the control bi ts

S0CON3 and S1CON3 in the S0COn and S1CON SFRs.

Table 34: Baud Rate Generation

Using Timer 1 Using Internal Baud Rate Generator

Serial Interface 0 2smod 2 * fCKMPU/ (384 * (256-TH1)) smod * f CKMPU/(64 * (210-S0REL))

Serial Interface 1 N/A fCKMPU/(32 * (210-S1REL))

Note: S0REL (9:0) and S1REL (9: 0) are 10-bi t values derived by combining bits f rom the respective timer

reload registers SxRELH (bits 1:0) and SxRELL (bits 7:0). TH1 is the high byte of timer 1. The SMOD bit

is located in the PCON SFR.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 41

Power Control Register 0 (PCON): 0x87  0x00

The SMOD bit used for the baud rate generator is set up via this register.

Table 35: The PCON Register

MSB LSB

SMOD – – – GF1 GF0 STOP IDLE

Bit Symbol Function

PCON.7 SMOD If SM0D = 1, the baud rate is doubled.

PCON.6 –

PCON.5 –

PCON.4 –

PCON.3 GF1 General purpose flag 1.

PCON.2 GF0 General purpose flag 1.

PCON.1 STOP Sets CPU to Stop mode.

PCON.0 IDLE Sets CPU to Idle mode.

Baud Rate Control Register 0 (BRCON): 0xD8  0x00

The BSEL bit used to enabl e the baud rate generator is set up via this register.

Table 36: The BRCON Register

MSB LSB

BSEL – – – – – – –

Bit Symbol Function

BRCON.7 BSEL If BSEL = 0, the baud rate is derived using timer 1. If BSEL = 1 the

baud rate generator circuit is used.

BRCON.6 –

BRCON.5 – .

BRCON.4 –

BRCON.3 –

BRCON.2 –

BRCON.1 –

BRCON.0 –

73S1210F Data Sheet DS_1210F_001

42 Rev. 1.4

Miscellaneous Control Register 0 (MISCtl0): 0xFFF1  0x00

Transmit and receive (TX and RX) pin selection and l oop back t est conf i gurat i on are set up via this

Table 37: The MISCtl0 Register

MSB LSB

PWRDN – – – – – SLPBK SSEL

Bit Symbol Function

MISCtl0.7 PWRDN This bit places the 73S1210F into a power down state.

MISCtl0.6 –

MISCtl0.5 –

MISCtl0.4 –

MISCtl0.3 –

MISCtl0.2 –

MISCtl0.1 SLPBK

1 = UART loop back testing mode. The pins TX D and RXD are to be

connected together externally (wit h SLPBK =1) and t herefore:

SLPBK SSEL Mode

0 0 normal using Serial_0

0 1 normal using Serial_1

1 0 Serial_0 TX feeds Serial_1 RX

1 1 Serial_1 TX feeds Serial_0 RX

MISCtl0.0 SSEL Selects either Serial_1 if set =1 or Serial_0 if set = 0 to be connected to

RXD and TXD pins.

1.7.6.1 Serial Interface 0

The Serial Interface 0 can operate in 4 m odes:

• Mode 0

Pin RX serves as input and output. T X outputs the shift clock. 8 bits are transmitted with LSB first.

The baud rate is fixed at 1/12 of the crystal frequency. Reception is initialized in Mode 0 by setting

the flags in S0CON as follows: RI0 = 0 and RE N0 = 1. In other modes, a start bit when REN0 = 1

starts receiving serial data.

• Mode 1

Pin RX serves as input, and TX serves as serial out put. No external shift clock is used, 10 bit s are

transmitted: a start bi t (always 0), 8 data bits (LSB first ), and a st op bi t (always 1). On receive, a start

bit synchronizes the transmission, 8 data bits are available by reading S0BUF, and st op bi t sets the

flag RB80 in the Special Funct ion Regist er S0CON. In mode 1 either internal baud rate generator or

timer 1 can be use to specify baud rate.

• Mode 2

This mode is similar to Mode 1, wit h two differences. The baud rate is fixed at 1/32 or 1/64 of

oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 dat a bi ts (LSB first), a

programmable 9th bit, and a stop bit (1). The 9th bit can be used to control the parity of the serial

interface: at transmission, bit TB80 in S0CON is output as the 9th bit, and at receive, the 9th bit

affects RB80 in Special Function Register S0CON.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 43

• Mode 3

The only difference between Mode 2 and M ode 3 i s t hat in Mode 3 either internal baud rate generat or

or timer 1 can be use to specify baud rate.

The S0BUF register is used to read/write data to/ from the serial 0 interface.

Serial Interface 0 Control Regi ster (S0CON): 0x9B  0x00

Transmit and receive data are transferred v i a this register.

Table 38: The S0CON Register

MSB LSB

SM0 SM1 SM20 REN0 TB80 RB80 TI0 RI0

Bit Symbol Function

S0CON.7 SM0 These two bits set the UART0 mode:

Mode Description SM0 SM1

0 N/A 0 0

1 8-bit UART 0 1

2 9-bit UART 1 0

3 9-bit UART 1 1

S0CON.6 SM1

S0CON.5 SM20 Enables the inter-processor communication feature.

S0CON.4 REN0 If set, enables serial reception. Cleared by soft ware t o disable recept i on.

S0CON.3 TB80 The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,

depending on the function it performs (parity check, multiprocessor

communication etc.).

S0CON.2 RB80 In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM20 is 0,

RB80 is the stop bit. In Mode 0 this bit is not used. Must be cleared by

software.

S0CON.1 TI0

Transmit interrupt flag, set by hardware after completion of a serial transfer.

Must be cleared by software.

S0CON.0 RI0 Receive interrupt flag, set by hardware after completion of a serial

reception. Must be cleared by soft ware.

73S1210F Data Sheet DS_1210F_001

44 Rev. 1.4

1.7.6.2 Serial Interface 1

The Serial Interface 1 can operate in 2 modes:

• Mode A

This mode is similar to Mode 2 and 3 of Serial interface 0, 11 bits are transmit ted or received: a start bit

(0), 8 data bits (LSB fi rst), a programmable 9th bit, and a stop bit (1). The 9th bit can be used to control

the parity of the serial i nterface: at transmission, bit TB81 in S1CON is out putted as the 9th bit, and at

receive, the 9th bit affects RB81 in Special Function Register S1CON. The only difference between

Mode 3 and A is that in Mode A onl y the internal baud rate generator can be use to specify baud rat e.

• Mode B

This mode is similar to Mode 1 of S erial i nterface 0. Pin RX serves as input, and TX serves as serial

output. No external shif t clock is used, 10 bits are transmitted: a start bi t (always 0), 8 data bits (LSB

first), and a stop bit (alway s 1). On receiv e, a start bit synchronizes the transmission, 8 data bits are

available by reading S1BUF, and st op bit sets the flag RB81 in the Special F unct i on Regist er

S1CON. In mode 1, the internal baud rate generator is use to specify the baud rate.

The S1BUF register is used to read/write data to/ from the serial 1 interface.

Serial Interface Control Register (S1CON): 0x9B  0x00

The function of the serial port depends on the setting of the Serial P ort Cont rol Register S1CON.

Table 39: The S1CON Register

MSB LSB

SM – SM21 REN1 TB81 RB81 TI1 RI1

Bit Symbol Function

S1CON.7 SM Sets the UART operation mode.

SM Mode Description Baud Rate

0 A 9-bit UART variable

1 B 8-bit UART variable

S1CON.6 –

S1CON.5 SM21 Enables the inter-processor communication feature.

S1CON.4 REN1 If set, enables serial reception. Cleared by soft ware t o disable recept i on.

S1CON.3 TB81 The 9th transmitted data bit in Mode A . Set or cleared by the MPU, dependi ng

on the function it performs (parit y check, multiprocessor communication, etc.).

S1CON.2 RB81 In Mode B, if sm21 is 0, rb81 is the stop bit. Must be cleared by sof tware.

S1CON.1 TI1 Transmit interrupt flag, set by hardware after complet i on of a serial transfer.

Must be cleared by software.

S1CON.0 RI1 Receive interrupt flag, set by hardware after completion of a serial reception.

Must be cleared by software.

Multiprocessor operation mode: The feature of receiving 9 bi ts in Modes 2 and 3 of Serial Interface 0 or in

Mode A of Serial Interface 1 can be used for multiprocessor communication. In t hi s case, the slave

processors have bit SM20 in S0CON or SM21 in S 1CON set to 1. When the master processor outputs

slave’s address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. The slave

processors compare the received byte with their network address. If there is a match, the addressed slave

will clear SM20 or SM21 and receive the rest of the message, while other slaves will leave the SM20 or

SM21 bit unaffected and ignore this message. After addressing the slave, t he host wil l output the rest of the

message with the 9th bit set to 0, so no serial port receiv e interrupt will be generated in unselected slaves.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 45

1.7.7 Timers and Counters

The 80515 has two 16-bit timer/count er regi st ers: Ti m er 0 and T im er 1. These registers can be

configured for counter or timer operations.

In timer mode, the regist er i s increment ed every machine cycle, meaning that it counts up after every 12

periods of the MPU clock signal.

In counter mode, the register is i ncrement ed when t he falling edge is observed at the corresponding input

signal T0 or T1 (T0 and T1 are the timer gating inputs derived from USR[0:7] pi ns, see t he User (USR)

Ports section). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count

rate is 1/2 of the oscillat or frequency. There are no restrictions on the duty cycle, however to ensure

proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.

Four operating modes can be selected for Timer 0 and Tim er 1. Two Special Function Registers (TMOD

and TCON) are used to select the appropriate mode.

The Timer 0 load registers are designated as TL0 and TH0 and the Timer 1 l oad regist ers are designat ed

as TL1 and TH1.

Timer/Counter Mode Control Register (TMOD): 0x89  0x00

Table 40: The TMOD Register

MSB LSB

GATE C/T M1 M0 GATE C/T M1 M0

Timer 1 Timer 0

Bits TR1 and TR0 in the TCON register start their associated timers when set.

Bit Symbol Function

TMOD.7

TMOD.3 Gate If set, enables external gate cont rol (USR pin(s) connected t o T0 or T1 for

Counter 0 or 1, respectively). When T 0 or T1 is high, and T Rx bi t is set (see

the TCON register), a counter is incremented every falling edge on T0 or T1

input pin. If not set, the TRx bit controls t he corresponding t i m er.

TMOD.6

TMOD.2 C/T Selects Timer or Counter operation. When set to 1, the counter operation is

performed based on the falling edge of T 0 or T 1. When cleared to 0, the

corresponding register will function as a timer.

TMOD.5

TMOD.1 M1 Selects the mode for Timer/Counter 0 or Timer/Count er 1, as shown in the

TMOD description.

TMOD.4

TMOD.0 M0 Selects the mode for Timer/Counter 0 or Timer/Count er 1, as shown in the

TMOD description.

Table 41: Timers/Counters Mode Description

M1 M0 Mode Function

0 0 Mode 0 13-bit Counter/Timer.

0 1 Mode 1 16-bit Counter/Timer.

1 0 Mode 2 8-bit auto-reload Counter/Timer.

1 1 Mode 3 If Timer 1 M1 and M0 bits are set to '1', Ti m er 1 st ops. If Timer 0 M1

and M0 bits are set to '1', Tim er 0 act s as t wo i ndependent 8-bit

Timer/Counters.

73S1210F Data Sheet DS_1210F_001

46 Rev. 1.4

Mode 0

Putting either tim er/counter into mode 0 configures it as an 8-bit t i m er/counter with a divide-by-32

prescaler. In this mode, the t i m er regist er i s confi gured as a 13-bi t register. As the count rolls over from

all 1’s to all 0’s, it set s the timer overflow flag TF0. The overf l ow flag TF0 then can be used to request an

interrupt. The counted input i s enabl ed to the timer when TRx = 1 and either GA TE = 0 or TX = 1 (setting

GATE = 1 allows the timer to be controlled by external input TX, to facilitate pulse width measurements).

TRx are control bits in the special f unct i on regist er TCON; GATE is in TMOD. The 13-bit register consists

of all 8 bits of TH1 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be

ignored. Setting the run flag (TRx) does not clear the registers. Mode 0 operation i s the same for timer 0

as for timer 1.

Mode 1

Mode 1 is the same as mode 0, except that the timer register is run with all 16 bits.

Mode 2

Mode 2 configures the timer register as an 8-bit counter (TLx) with automatic reload. T he overflow from

TLx not only sets TFx, but also reloads TLx with the content s of THx, which is preset by software. The

reload leaves THx unchanged.

Mode 3

Mode 3 has different effect s on timer 0 and timer 1. Timer 1 in mode 3 simply hol ds its count. The effect

is the same as setting TR1 = 0. Timer 0 in m ode 3 est abl ishes TL0 and T H0 as t wo separate count ers.

TL0 uses the timer 0 control bits: C/ T , GATE, TR0, INT0, and TF 0. TH0 is locked into a timer function

(counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls

the "timer 1" int errupt . Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When

timer 0 is in mode 3, ti m er 1 can be turned on and off by switching it out of and into its own mode 3, or

can still be used by the serial channel as a baud rate generator, or in fact, in any applicati on not requiring

an interrupt from timer 1 i tself.

Timer/Counter Control Register (TCON): 0x88  0x00

Table 42: The TCON Register

MSB LSB

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Bit Symbol Function

TCON.7 TF1 Timer 1 ov erf l ow flag.

TCON.6 TR1 Not used for interrupt control.

TCON.5 TF0 Timer 0 ov erf l ow flag.

TCON.4 TR0 Not used for interrupt control.

TCON.3 IE1 Interrupt 1 edge fl ag i s set by hardware when the falling edge on external

interrupt int1 is observed. Cleared when an i nterrupt is processed.

TCON.2 IT1 Interrupt 1 type cont rol bi t. 1 selects falling edge and 0 selects low level for

input pin to cause an interrupt.

TCON.1 IE0 Interrupt 0 edge fl ag i s set by hardware when the falling edge on external

interrupt int0 is observed. Cleared when an i nterrupt is processed.

TCON.0 IT0 Interrupt 0 type cont rol bi t. 1 selects falling edge and 0 sets low level for

input pin to cause interrupt.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 47

1.7.8 WD Timer (Software Watchdog Timer)

The software watchdog timer is a 16-bit count er that is incremented once every 24 or 384 clock cycles.

After a reset, the wat chdog timer is disabled and all registers are set to zero. The watchdog consists of a

16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once

the watchdog starts, it cannot be st opped unl ess t he i nternal reset signal becomes active.

WD Timer Start Procedure: The WDT is started by setting t he SWDT flag. When the WDT register

enters the state 0x7CFF, an asy nchronous WDTS signal wil l become act i ve. The signal WDTS sets bit 6

in the IP0 register and requests a reset stat e. WDTS is cleared either by the reset signal or by changing

the state of the WDT t im er.

Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request

signal from becoming active. Thi s requirement imposes an obligation on the programmer to issue two

instructions. The first instruct i on set s WDT and the second instruction sets SWDT. The maximum del ay

allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has

not been set, WDT is automati call y reset, otherwise the watchdog timer is reloaded with the content of

the WDTREL register and WDT is automatically reset.

Interrupt Enable 0 Register (I EN0): 0xA8  0x00

Table 43: The IEN0 Register

MSB LSB

EAL WDT ET2 ES0 ET1 EX1 ET0 EX0

Bit Symbol Function

IEN0.7 EAL EAL = 0 – disable all interrupts.

IEN0.6 WDT Watchdog timer refresh flag.

Set to initiate a refresh of the watchdog timer. Must be set di rectl y before

SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT

is reset by hardware 12 clock cycle s after it has been set.

IEN0.5 –

IEN0.4 ES0 ES0 = 0 – disable serial channel 0 interrupt.

IEN0.3 ET1 ET1 = 0 – disable timer 1 overflow interrupt.

IEN0.2 EX1 EX1 = 0 – disable external interrupt 1.

IEN0.1 ET0 ET0 = 0 – disable timer 0 overflow interrupt.

IEN0.0 EX0 EX0 = 0 – disable external interrupt 0.

73S1210F Data Sheet DS_1210F_001

48 Rev. 1.4

Interrupt Enable 1 Register (I EN1): 0xB8  0x00

Table 44: The IEN1 Register

MSB LSB

– SWDT EX6 EX5 EX4 EX3 EX2 –

Bit Symbol Function

IEN1.7 –

IEN1.6 SWDT Watchdog timer start/refresh flag. Set to activate/refresh t he watchdog timer.

When directly set after sett i ng WDT, a wat chdog timer refresh is performed. Bit

SWDT is reset by the hardware 12 clock cycles after it has been set.

IEN1.5 EX6 EX6 = 0 – disable external interrupt 6.

IEN1.4 EX5 EX5 = 0 – disable external interrupt 5.

IEN1.3 EX4 EX4 = 0 – disable external interrupt 4.

IEN1.2 EX3 EX3 = 0 – disable external interrupt 3.

IEN1.1 EX2 EX2 = 0 – disable external interrupt 2.

IEN1.0 –

Interrupt Priority 0 Register (IP0): 0xA9  0x00

Table 45: The IP0 Register

MSB LSB

– WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0

Bit Symbol Function

IP0.6 WDTS Watchdog timer status flag. Set when the watchdog timer has expired. The

internal reset will be generated, but this bit will not be cleared by the reset.

This allows the user program to determine if the watchdog timer caused the

reset to occur and respond accordingly. Can be read and cleared by software.

Note: The remaining bits in t he IP0 register are not used for watchdog control.

Watchdog Timer Reload Register (WDTREL): 0x86  0x00

Table 46: The WDTREL Register

MSB LSB

WDPSEL WDREL6 WDREL5 WDREL4 WDREL3 WDREL2 WDREL1 WDREL0

Bit Symbol Function

WDTREL.7 WDPSEL Prescaler select bit. When set, t he wat chdog is clocked through an

additional divide-by-16 prescaler.

WDTREL.6

WDTREL.0 WDREL6-0 Seven bit reload value f or the high-byte of the watchdog ti m er. T hi s v al ue is

loaded to the WDT when a refresh is triggered by a consecutive setting of

bits WDT and SWDT.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 49

1.7.9 User (USR) Ports

The 73S1210F includes 8 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins

are inputs until they are confi gured for the desired direction. The pins are configured and controlled by

the USR70 and UDIR70 SFRs. Each pin declared as USR can be configured independently as an input

or output with the bit s of the UDIR70 register. Table 47 lists the directi on regist ers and confi gurabi li ty

associated with each group of USR pins. USR pins 0 to 7 are m ultiple use pins that can be used for

general purpose I/O, external interrupts and timer control. Table 48 shows the configuration for a USR

pin through its associated bit in i ts UDIR register. Values read from and written into the GPIO ports use

the data registers USR70. Note: A fter reset, all USR pins are defaulted as inputs and pulled up to VDD

until any write to t he corresponding UDIR register i s perf ormed. This insures all USR pins are set to a

known value until set by t he firmware. Unused USR pins can be set for output if unused and

unconnected to prevent them f rom floating. Alternativ el y, unused USR pins can be set for input and tied

to ground or VDD.

Table 47: Direction Registers and Internal Resources for DIO Pin Groups

USR Pin Group Type Direction

Name

Direction

(SFR)

Location

Data

Name

Data

(SFR)

Location

USR_0…USR_7 Multi-use UDIR70 0x91 [7:0] USR70 0x90 [7:0]

Table 48: UDIR Control Bit

UDIR Bit

0 1

USR Pin Function output input

Four XRAM SFR registers (USRIntTCtl0, USRIntTCtl1, USRIntTCtl2, and USRIntTCtl3) control the use of

the USR [7:0] pins. E ach of the USR [7:0] pins can be configured as GPIO or i ndi vidually be assigned an

internal resource such as an interrupt or a timer/counter control. Each of the four registers contains two

3-bit configuration words named UxIS (where x corresponds to t he USR pin). The control resources

selectable for the USR pins are listed i n Table 50 through Table 53. If more t han one i nput is connected

to the same resource, the resources are combined using a logical OR.

Table 49: Selectable Controls Using the UxIS Bits

UxIS Value Resource Selected for USRx Pin

0 None

1 None

2 T0 (counter0 gate/clock)

3 T1 (counter1 gate/clock)

4 Interrupt 0 rising edge/hi gh l evel on USRx

5 Interrupt 1 rising edge/hi gh l evel on USRx

6 Interrupt 0 falling edge/low level on USRx

7 Interrupt 1 fall ing edge/low level on USRx

Note: x denotes the corresponding USR pin. Interrupt edge or level control is assigned in the IT0 and IT1

bits in the TCON register.

73S1210F Data Sheet DS_1210F_001

50 Rev. 1.4

External Interrupt Control Register (USRIntCtl1) : 0xFF90  0x00

Table 50: The USRIntCtl 1 Reg ister

MSB LSB

– U1IS.6 U1IS.5 U1IS.4 – U0IS.2 U0IS.1 U0IS.0

External Interrupt Control Register (USRIntCtl2) : 0xFF91  0x00

Table 51: The USRIntCtl 2 Reg ister

MSB LSB

– U3IS.6 U3IS.5 U3IS.4 – U2IS.2 U2IS.1 U2IS.0

External Interrupt Control Register (USRIntCtl3) : 0xFF92  0x00

Table 52: The USRIntCtl 3 Reg ister

MSB LSB

– U5IS.6 U5IS.5 U5IS.4 – U4IS.2 U4IS.1 U4IS.0

External Interrupt Control Register (USRIntCtl4) : 0xFF93  0x00

Table 53: The USRIntCtl 4 Reg ister

MSB LSB

– U7IS.6 U7IS.5 U7IS.4 – U6IS.2 U6IS.1 U6IS.0

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 51

1.7.10 Analog Voltage Comparator

The 73S1210F includes a programmable comparator that i s connected to the ANA_IN pin. The

comparator can be configured to trigger an interrupt i f the input voltage rises above or fal l s below a

selectable threshold voltage. T he comparator control register should not be modified when the anal og

interrupt (ANAIEN bit in the INT6Ctl register) is enabled to guard against any false i nterrupt that might be

generated when modifying the threshold. The comparator has a built-in hysteresis to prevent the

comparator from repeatedly responding to low-amplitude noise. This hysteresis is approximately 20m V.

Interrupt control is handled in the INT6Ctl register.

Analog Compare Control Register (ACOMP): 0xFFD0  0x00

Table 54: The ACOMP Register

MSB LSB

ANALVL – ONCHG CPOL CMPEN TSEL.2 TSEL.1 TSEL.0

Bit Symbol Function

ACOMP.7 ANALVL When read, indicates whether the input level is above or below the

threshold. This is a real time value and is not latched, so it may change

from the time of the interrupt trigger until read.

ACOMP.6 –

ACOMP.5 ONCHG If set, the Ana_interrupt i s invoked on any change above or below the

threshold, bit 4 is ignored.

ACOMP.4 CPOL If set = 1, Ana_interrupt is invoked when signal rises above selected

threshold. If set = 0, A na_i nterrupt is invoked when signal goes below

selected threshold (default).

ACOMP.3 CMPEN Enables power to the analog comparator. 1 = Enabled. 0 = Disabled

(default).

ACOMP.2 TSEL.2 Sets the voltage threshold for comparison to the voltage on pi n ANA_IN.

Thresholds are as follows:

TSEL.2 TSE L.1 TSEL.0 Voltage Threshold

0 0 1.00V

0 0 1 1.24V

0 1 0 1.40V

1 1 1.50V

1 0 0 1.75V

1 0 1 2.00V

1 1

0 2.30V

1 1 1 2.50V

ACOMP.1 TSEL.1

ACOMP.0 TSEL.0

73S1210F Data Sheet DS_1210F_001

52 Rev. 1.4

External Interrupt Control Register (INT6Ctl): 0xFF95  0x00

Table 55: The INT6Ctl Reg ister

MSB LSB

– – VFTIEN VFTINT I2CIEN I2CINT ANIEN ANINT

Bit Symbol Function

INT6Ctl.7 –

INT6Ctl.6 –

INT6Ctl.5 VFTIEN VDD fault interrupt enable.

INT6Ctl.4 VFTINT VDD fault interrupt flag.

INT6Ctl.3 I2CIEN I

C interrupt enabled.

INT6Ctl.2 I2CINT I

C interrupt flag.

INT6Ctl.1 ANIEN If ANIEN = 1 Analog Compare event interrupt is enabled. When masked

(ANIEN = 0), ANINT (bit 0) may be set, but no interrupt is generated.

INT6Ctl.0 ANINT (Read Only) Set when the selected ANA_IN signal changes with respect to

the selected threshold if Compare_Enable is asserted. Cleared on read of

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 53

1.7.11 LED Driver

The 73S1210F provides a single dedicated output pi n for driving an LED. The LED driver pin can be

configured as a current source that will pull to ground to drive an LED that is connected to VDD without

the need for an external current li m i ting resistor. This pin may be used as general purpose output wit h

the programmed pull-down current and a strong (CMOS) pull-up, if enabl ed. The analog block must be

enabled when this output is being used to drive the selected output current.

This pin may be used as an input with consideration of the programmed output current and level. The

LED Control Register (LEDCtl): 0xFFF3  0xFF

Table 56: The LEDCtl Reg ister

MSB LSB

– LPUEN ISET.1 ISET.0 – – – LEDD0

Bit Symbol Function

LEDCtl.7 –

LEDCtl.6 LPUEN 0 = Pull-ups are enabled for all of the LED pins.

LEDCtl.5 ISET.1 These two bits control the drive current (to ground) for the LED driver pin.

Current levels are:

00 = 0ma(off)

01 = 2ma

10 = 4ma

11 = 10ma

LEDCtl.4 ISET.0

LEDCtl.3 –

LEDCtl.2 –

LEDCtl.1 –

LEDCtl.0 LEDD0 Write data controls output level of pi n LED0. Read will report level of pin LE D0.

73S1210F Data Sheet DS_1210F_001

54 Rev. 1.4

1.7.12 I2C Master Interface

The 73S1210F includes a dedicated fast mode, 400kHz I2C Mast er i nterface. The I2C interface can read

or write 1 or 2 bytes of data per dat a transfer frame. The MPU communicates with the interface through

six dedicated SFR registers:

• Device Address (DAR)

• Write Data (WDR)

• Secondary Write Data (SWDR)

• Read Data (RDR)

• Secondary Read Data (SRDR)

• Control and Status (CSR)

The DAR register is used to set up the slave address and specify if the transaction is a read or write

operation. The CSR register sets up, starts the transaction and reports any errors that may occur. When

the I2C transaction is complete, the I2C interrupt is reported via external int errupt 6. The I2C interrupt is

automatically de-asserted when a subsequent I2C transaction is started. The I2C interface uses a 400kHz

clock from the time-base circuits.

1.7.12.1 I2C Write Sequence

To write data on the I2C Master B us, the 80515 has to program the following registers according to the

following sequence:

1. Write slave device address to Device Address register (DAR). The data contains 7 bi ts for the slave

device address and 1 bit of op-code. The op-code bit should be written with a 0 to indicate a writ e

operation.

2. Write data to Write Dat a regist er (WDR). This data will be transferred to the slave devi ce.

3. If writing 2 bytes, set bit 0 of the Control and S tatus register (CSR) and load the second data byte to

Secondary Write Data register (SWDR).

4. Set bit 1 of the CSR register to start I2C Master Bus.

5. Wait for I2C interrupt to be asserted. It indicates t hat the write on I2C Master Bus is done. Refer to

information about the INT6Ctl, IEN1 and IRCON register for masking and flag operation.

Figure 10 shows the timing of t he I2C write mode:

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 55

1-7 8 9 10-17 18

ACK bit ACK bit STOP

condition

START

condition

SCL

SDA

LSBMSB LSBMSB

Device Address

[7:0] Write Data [7:0

I2C_Interrupt

Start I2C

(CSR bit1)

Transfer length

(CSR bit0)

1-7 8 9 10-17 18

ACK bit ACK bit STOP

condition

START

condition

SCL

SDA

LSBMSB LSBMSB

Device Address

[7:0] Write Data [7:0]

I2C_Interrupt

Start I2C

(CSR bit1)

Transfer length

(CSR bit0)

Secondary Write

Data [7:0]

ACK bit

19-26 27

LSBMSB

Figure 10: I2C Write Mode Operation

1.7.12.2 I2C Read Sequence

To read data on the I2C Master Bus from a slave device, the 80515 has to program the f ol l owing regist ers

in this sequence:

1. Write slave device address to Device Address register (DAR). The data contains 7 bi ts device

address and 1 bit of op-code. The op-code bit should be written with a 1.

2. Write control data to Control and Status register. Write a 1 to bit 1 to start I2C Master Bus. Also write

a 1 to bit 0 if t he S econdary Read Data register (SRDR) is to be captured from the I2C Slave devi ce.

3. Wait for I2C interrupt to be asserted. It indicates that the read operation on the I2C bus is done.

Refer to information about the INT6Ctl, IEN1 and IRCON registers for masking and flag operation.

4. Read data from the Read Data regist er (RDR).

5. Read data from Secondary Read Data register (SRDR) if bit 0 of Control and Stat us regist er (CSR) is

written with a 1.

73S1210F Data Sheet DS_1210F_001

56 Rev. 1.4

Figure 11 shows the timing of the I2C read mode:

1-7 8 9 10-17 18

ACK bit No ACK bit STOP

condition

START

condition

SCL

SDA

LSBMSB LSBMSB

Device Address

[7:0] Read Data [7:0

I2c_Interrupt

Start I2C

(CSR bit1)

Transfer lengt h

(CSR bit0)

1-7 8 9 10-17 18

ACK bit No ACK bit STOP

condition

START

condition

SCL

SDA

LSBMSB LSBMSB

Device Address

[7:0] Read Data [7:0]

I2c_Interrupt

Start I2C

(CSR bit1)

Transfer lengt h

(CSR bit0)

Secondary Read

Data[7:0]

ACK bit

19-26 27

Figure 11: I2C Read Operation

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 57

Device Address Register (DAR): 0xFF80  0x00

Table 57: The DAR Register

MSB LSB

DVADR.6 DVADR.5 DVADR.4 DVADR.3 DVADR.2 DVADR.1 DVADR.0 I2CRW

Bit Symbol Function

DAR.7

DVADR

[0:6] Slave device address.

DAR.6

DAR.5

DAR.4

DAR.3

DAR.2

DAR.1

DAR.0 I2CRW If set = 0, the transaction is a write operat i on. If set=1, read.

I2C Write Data Regi s ter (WDR): 0XFF81  0x00

Table 58: The WDR Register

MSB LSB

WDR.7 WDR.6 WDR.5 WDR.4 WDR.3 WDR.2 WDR.1 WDR.0

Bit Function

WDR.7

Data to be written to the I2C slave device.

WDR.6

WDR.5

WDR.4

WDR.3

WDR.2

WDR.1

WDR.0

73S1210F Data Sheet DS_1210F_001

58 Rev. 1.4

I2C Secondary Write Data Register (SWDR): 0XFF82  0x00

Table 59: The SWDR Registe r

MSB LSB

SWDR.7 SWDR.6 SWDR.5 SWDR.4 SWDR.3 SWDR.2 SWDR.1 SWDR.0

Bit Function

SWDR.7

Second Data byte to be written to the I2C slave device if bit 0 (I2CLEN) of the

Control and Status register (CSR) is set = 1.

SWDR.6

SWDR.5

SWDR.4

SWDR.3

SWDR.2

SWDR.1

SWDR.0

I2C Read Data Register (RDR): 0 XFF83  0x00

Table 60: The RDR Register

MSB LSB

RDR.7 RDR.6 RDR.5 RDR.4 RDR.3 RDR.2 RDR.1 RDR.0

Bit Function

RDR.7

Data read from the I2C slave devi ce.

RDR.6

RDR.5

RDR.4

RDR.3

RDR.2

RDR.1

RDR.0

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 59

I2C Secondary Read Data Register (SRDR): 0XFF84  0x00

Table 61: The SRDR Register

MSB LSB

SRDR.7 SRDR.6 SRDR.5 SRDR.4 SRDR.3 SRDR.2 SRDR.1 SRDR.0

Bit Function

SRDR.7

Second Data byte to be read from the I2C slave device if bit 0 (I2CLE N) of the Control

and Status register (CSR) is set = 1.

SRDR.6

SRDR.5

SRDR.4

SRDR.3

SRDR.2

SRDR.1

SRDR.0

I2C Control and Status Register (CSR): 0xFF85  0x00

Table 62: The CSR Register

MSB LSB

– – – – – AKERR I2CST I2CLEN

Bit Symbol Function

CSR.7 –

CSR.6 –

CSR.5 –

CSR.4 –

CSR.3 –

CSR.2 AKERR Set to 1 if acknowledge bit from Slave Device is not 0. Automatically reset

when the new bus transaction is started.

CSR.1 I2CST

Write a 1 to start I2C transaction. Automatically reset to 0 when t he bus

transaction is done. This bit should be t reat ed as a “busy” i ndi cat or on

reading. If it is high, the serial read/write operations are not completed and

no new address or data should be written.

CSR.0 I2CLEN Set to 1 for 2 byte read or write operations. Set to 0 for 1-byte operations.

73S1210F Data Sheet DS_1210F_001

60 Rev. 1.4

External Interrupt Control Register (INT 6 Ctl): 0xFF95  0x00

Table 63: The INT6Ctl Reg ister

MSB LSB

– – VFTIEN VFTINT I2CIEN I2CINT ANIEN ANINT

Bit Symbol Function

INT6Ctl.7 –

INT6Ctl.6 –

INT6Ctl.5 VFTIEN VDD fault interrupt enable.

INT6Ctl.4 VFTINT VDD fault interrupt f lag.

INT6Ctl.3 I2CIEN When set = 1, the I

C interrupt is enabled.

INT6Ctl.2 I2CINT When set = 1, the I

C transaction has completed. Cleared upon the start

of a subsequent I2C transaction.

INT6Ctl.1 ANIEN Analog compare interrupt enable.

INT6Ctl.0 ANINT Analog compare interrupt flag.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 61

1.7.13 Keypad Interface

The 73S1210F supports a 30-button (6 rows x 5 columns) keypad (SPST Mechanical Contact Switches)

interface using 11 dedicated I/O pi ns. Figure 12 shows a simplified block diagram of the keypad

interface.

Scan

pull-up

Debouncing

Debounce Time

76543210

KSIZE Register

(1) KCOL is normally used as Read only

is disabled, this register is to be used by

firmware to write the column data to

handle firmware scanning.

Key_Detect

Hardware Scan Enable

Column

Scan Order

Column Value

Row Value

Key_Detect_Enable

KORDERL / H Registers

76543210

KCOL Register

(1)

76543210

KROW Register

Dividers 1kHz

Scan

Time

KSCAN Register

76543210

KSTAT Register

Keypad Clock

VDD

pull-

COL4:0

ROW5:0

73S1210F

If smaller keypad than 6 x 5 is to be

implemented, unused row inputs

should be connected to VDD. Unused

column outputs should be left

unconnected.

VDD

Figure 12: Simplified Keypad Block Diagram

There are five drive lines (output s) corresponding to columns and 6 sense lines (inputs) corresponding to

rows. Hysteresis and pull-ups are provided on all inputs (rows), which eliminate the need for external

resistors in the keypad. Key scanning happens by asserting one of the 5 column lines low and looking for

a low on a sense line indicating that a key i s pressed (switch closed) at t he intersection of the drive/sense

(column/row) line in the keypad. K ey detection is performed by hardware with an incorporated debounce

timer. Debouncing time is adjust able through the KSCAN register. Internal hardware circuitry performs

column scanning at an adjustable scanning rate and column scanning order through registers KSCAN

and KORDERL / KORDERH. Key scanning is disabled at reset and must be enabled by firmware. When

a valid key is detected, an i nterrupt is generated and the valid value of the pressed key is automatically

73S1210F Data Sheet DS_1210F_001

62 Rev. 1.4

written into the KCOL and KROW registers. The keypad interface uses a 1kHz clock derived from the

12MHz crystal. The clock is enabled by setting bit 6 – KBEN – in the MCLKCtl register (see the Oscillator

and Clock Generation section) to carry out scanning and debouncing. T he key pad size can be adjusted

within the KSIZE register.

Normal scanning is performed by hardware when the SCNEN bit is set at 1 in the KSTAT register. Figure

13 shows the flowchart of how the hardware scanning operates. I n order t o m i nim i ze power, scanning

does not occur until a key-press is detected. Once hardware key scanning is enabled, t he hardware

drives all column outputs low and waits f or a l ow t o be detected on one of the inputs. When a low i s

detected on any row, and before key scanning starts, the hardware checks that the low level is still

detected after a debounce time. The debounce time is defined by fi rm ware in the KSCAN register (bits

7:0, DBTIME). Debounce t i m es from 4ms to 256ms in 4ms increments are supported. If a key is not

pressed after the debounce time, t he hardware will go back t o l ooking for any input to be low. If a key is

confirmed to be pressed, key scanning begins.

Key scanning asserts one of the 5 drive lines (COL 4:0) low and looks for a low on a sense line indicating

that a key is pressed at the int ersection of the drive/sense line in the keypad. A fter all sense lines have

been checked without a key-press being detected, the nex t column line is asserted. The time between

checking each sense line is the scan time and is defined by fi rmware in the KSCAN register (bits 0:1 –

SCTIME). Scan ti m es f rom 1m s to 4ms are supported. Scanning order does not affect t he scan t im e.

This scanning continues until the entire keypad i s scanned. If only one key is pressed, a valid key is

detected. Simultaneous key presses are not considered as val i d (If two keys are pressed, no key is

reported to firmware).

Possible scrambling of the column scan order is provided by m eans of the KORDERL and KORDERH

registers that define the order of column scanning. Values in these registers must be updated every t i m e

a new keyboard scan order is desired. It is not possible to change the order of scanning the sense lines.

The column and row intersection for the det ect ed valid key are stored in the KCOL and KROW registers.

When a valid key is detected, an i nterrupt is generated. Firmware can then read those registers to

determine which key had been pressed. After reading the KCOL and KROW registers, the firmware can

update the KORDERL / KORDERH registers if a new scan order is needed. When the SCNEN bit is

enabled in the KSTAT register, the KCOL and KROW registers are only updated after a val i d key has

been identified. The hardware does not wait for the firmware to service the interrupt in order to proceed

with the key scanning process. Once the valid key (or invalid key – e.g. two keys pressed) is detected,

the hardware waits for the key to be released. O nce t he key i s released, the debounce timer is started. If

the key is not still released after the debounce time, the debounce counter starts again. After a key

release, all columns will be driven low as before and the process will repeat waiting for any key to be

pressed. When the SCNEN bit is disabled, al l dri ve outputs are set to the value in the KCOL register. If

firmware clears the SCNEN bit in the mi ddl e of a key scan, the KCOL register contains the last value

stored in there which will then be reflect ed on the output pins. A bypass mode is provided so that the

firmware can do the key scanning manual ly (SCNEN bit must be cleared). In bypass mode, the firmware

writes/reads the Column and Row registers to perform the key scanning.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 63

Figure 13: Keypad Interface Flow Chart

Any

Row

Input = 0 ?

Keypad

Initialization

All Column

Outputs = 0

Deboucing

Timer

Any Row

Input still = 0 ?

Yes No

How Many

keys have been

detected?

Download of the key row and

column values in KROW and

KCOL registers

1 key

Keypad Interrupt

generation

Is (are)

the key(s)

released ?

(*)

Deboucing

Timer Yes

Is (are)

the key(s)

still released ?

(*)

KSCAN Register:

Debouncing Time

KSTAT Register:

Enable HW Scanning

Enable Keypad Interrupt

Keypad Scanning

KORDERL / H Registers:

Column Scan Order

KSTAT Register:

Key Detect Interrupt

Yes

KCOL Register:

Value of the valid key column

KROW Register:

Value of the valid key row

KSCAN Register:

Scanning Rate

KSIZE Register:

Keypad Size Definition

0 key

hardware keypad interface

than

1 key

KSCAN Register:

Debouncing Time

(*) Key release is cheked by looking for a low level on any row.

73S1210F Data Sheet DS_1210F_001

64 Rev. 1.4

Keypad Column Register (KCO L ): 0xD1  0x1F

This register contains the value of the column of a key detected as valid by the hardware. In bypass

mode, this register firmware writes directl y this register to carry out manual scanning.

Table 64: The KCOL Register

MSB LSB

– – – COL.4 COL.3 COL.2 COL.1 COL.0

Bit Symbol Function

KCOL.7 –

KCOL.6 –

KCOL.5 –

KCOL.4 COL.4 Drive lines bit mapped to corresponding with pins COL(4:0). When a key

is detected, firmware reads this register to determine column. In bypass

(S/W keyscan) mode, Firmware writes this register di rectl y. 0x1E =

COL(0) low, all others high. 0x0F = COL(4) low, al l others high. 0x1F =

COL(4:0) all high.

KCOL.3 COL.3

KCOL.2 COL.2

KCOL.1 COL.1

KCOL.0 COL.0

Keypad Row Register (KROW): 0xD2  0x3F

This register contains the value of the row of a key detected as valid by the hardware. In bypass mode,

this register firmware reads directly thi s regist er to carry out manual detection.

Table 65: The KROW Register

MSB LSB

– – ROW.5 ROW.4 ROW.3 ROW.2 ROW.1 ROW.0

Bit Symbol Function

KROW.7 –

KROW.6 –

KROW.5 ROW.6 Sense lines bit mapped to correspond with pins ROW(5:0). When key

detected, firmware reads this register t o determine row. In bypass mode,

firmware reads rows and has to determine if there was a key press or not.

0x3E = ROW(0) low, all others high. 0x1F = ROW(5) low, all others high.

0x3F = ROW(5:0) all high.

KROW.4 ROW.4

KROW.3 ROW.3

KROW.2 ROW.2

KROW.1 ROW.1

KROW.0 ROW.0

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 65

Keypad Scan T ime Register (KSCAN): 0xD3  0x00

This register contains the values of scanning tim e and debouncing time.

Table 66: The KSCAN Register

MSB LSB

DBTIME.5 DBTIME.4 DBTIME.3 DBTIME.2 DBTIME.1 DBTIME.0 SCTIME.1 SCTIME.0

Bit Symbol Function

KSCAN.7 DBTIME.5

Debounce time in 4ms increments. 1 = 4ms de-bounce tim e, 0x3F =

252ms, 0x00 = 256ms. Key presses and key releases are debounced by

this amount of time.

KSCAN.6 DBTIME.4

KSCAN.5 DBTIME.3

KSCAN.4 DBTIME.2

KSCAN.3 DBTIME.1

KSCAN.2 DBTIME.0

KSCAN.1 SCTIME.1 Scan time in ms. 01 = 1ms, 02 = 2ms, 00 = 3ms, 00 = 4ms. Tim e between

checking each key during keypad scanning.

KSCAN.0 SCTIME.0

Keypad Control/Status Register (KSTAT): 0xD4  0x00

This register is used to control the hardware keypad scanning and detection capabili ties, as well as the

keypad interrupt control and status.

Table 67: The KSTAT Register

MSB LSB

– – – – KEYCLK HWSCEN KEYDET KYDTEN

Bit Symbol Function

KSTAT.7 –

KSTAT.6 –

KSTAT.5 –

KSTAT.4 –

KSTAT.3 KEYCLK The current state of the keyboard clock can be read from this bit.

KSTAT.2 HWSCEN Hardware Scan Enable – When set, the hardware will perform automatic

key scanning. When cleared, the firmware must perf orm the key scanning

manually (bypass mode).

KSTAT.1 KEYDET

Key Detect – When HWSCEN = 1, this bit is set causing an interrupt that

indicates a valid key press was detected and the key locat i on can be read

from the Keypad Column and Row regist ers. When HWS CE N = 0, this bit

is an interrupt which indicates a falling edge on any Row input if all Row

inputs had been high previously (note: m ultiple Key Detect interrupts may

occur in this case due to the keypad switch bouncing). In al l cases, this bit

is cleared when read. When HWSCEN = 0 and the keypad interface 1kHz

clock is disabled, a key press will still set this bit and cause an interrupt.

KSTAT.0 KYDTEN Key Detect Enable – When set, the KEY DE T bit can cause an interrupt and

when cleared the KEYDET cannot cause an interrupt . KEYDET can still

get set even if the i nterrupt is not enabled.

73S1210F Data Sheet DS_1210F_001

66 Rev. 1.4

Keypad Scan Time Register (KSIZE): 0xD5  0x00

This register is not applicable when HWSCEN is not set. Unused row inputs should be connected to

VDD.

Table 68: The KSIZE Register

MSB LSB

– – ROWSIZ.2 ROWSIZ.1 ROWSIZ.0 COLSIZ.2 COLSIZ.1 COLSIZ.0

Bit Symbol Function

KSIZE.7 –

KSIZE.6 –

KSIZE.5 ROWSIZ.2 Defines the number of rows in the keypad. Maximum num ber is 6 gi ven

the number of row pins on the package. All ows f or a reduced keypad size

for scanning.

KSIZE.4 ROWSIZ.1

KSIZE.3 ROWSIZ.0

KSIZE.2 COLSIZ.2 Defines the number of columns in the keypad. Maxim um num ber i s 5

given the number of column pins on the package. Allows for a reduced

keypad size for scanning.

KSIZE.1 COLSIZ.1

KSIZE.0 COLSIZ.0

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 67

Keypad Column LS Scan Order Register (KORDERL): 0xD6  0x00

In the KORDERL and KORDERH registers, Column Scan Order(14:0) is grouped into 5 set s of 3 bi ts

each. Each set determines which column (COL(4:0) pin) to act i vate by loading the column number into

the 3 bits. When in HW_Scan_Enable mode, the hardware will step through the sets from 1Col t o 5Col

(up to the number of columns in Colsize) and scan the column defi ned i n the 3 bits. To scan in sequential

order, set a counting pattern with 0 in set 0, and 1 in set 1,and 2 in set 2, and 3 in set 3, and 4 in set 4.

The firmware should update this as part of the interrupt service routine so that t he new scan order is

loaded prior to the next key bei ng pressed. For example, to scan COL(0) first, 1Col(2:0) should be

loaded with 000’b. To scan COL(4) fift h, 5Col(2:0) should be loaded with 100’b.

Table 69: The KORDERL Register

MSB LSB

3COL.1 3COL.0 2COL.2 2COL.1 2COL.0 1COL.2 1COL.1 1COL.0

Bit Symbol Function

KORDERL.7 3COL.1 Column to scan 3rd (lsb’s).

KORDERL.6 3COL.0

KORDERL.5 2COL.2 Column to scan 2nd. KORDERL.4 2COL.1

KORDERL.3 2COL.0

KORDERL.2 1COL.2 Column to scan 1st. KORDERL.1 1COL.1

KORDERL.0 1COL.0

Keypad Column MS Scan Order Register (KORDERH): 0xD7  0x00

Table 70: The KORDERH Register

MSB LSB

– 5COL.2 5COL.1 5COL.0 4COL.2 4COL.1 4COL.0 3COL.2

Bit Symbol Function

KORDERH.7 –

KORDERH.6 5COL.2 Column t o scan 5th. KORDERH.5 5COL.1

KORDERH.4 5COL.0

KORDERH.3 4COL.2 Column t o scan 4th. KORDERH.2 4COL.1

KORDERH.1 4COL.0

KORDERH.0 3COL.2 Column t o scan 3

(msb).

73S1210F Data Sheet DS_1210F_001

68 Rev. 1.4

External Interrupt Control Register (INT5Ctl): 0xFF94  0x00

Table 71: The INT5Ctl Reg ister

MSB LSB

PDMUX – – – – – KPIEN KPINT

Bit Symbol Function

INT5Ctl.7 PDMUX Power down multiplexer control.

INT5Ctl.6 –

INT5Ctl.5 –

INT5Ctl.4 –

INT5Ctl.3 –

INT5Ctl.2 –

INT5Ctl.1 KPIEN Enables Keypad interrupt when set = 1.

INT5Ctl.0 KPINT This bit indicates the Keypad logic has set Key_Detect bit and a key

location may be read. Cleared on read of regist er.

1.7.14 Emulator Port

The emulator port, consisting of the pins E_RST, E_TCLK and E_RXTX, prov i des control of the MPU

through an external in-circuit emulator. The E_TBUS[3:0] pi ns, together with the E_ISYNC/ B RK RQ, add

trace capability to the em ul ator. The emulator port is compatible with the ADM51 emulators

manufactured by Signum S ystems™.

The signals of the emulator port have weak pull-ups. Adding resistor footprints for signals E_RST,

E_TCLK and E_RXTX on the P CB is recommended. If necessary, adding 10kΩ pull-up resistors on

E_TCLK and E_RXTX and a 3kΩ on E_RST will help the emulator operate normal l y if a problem arises.

If code trace capability is needed on this interface, 20pF capacitors ( (to ground) need to be added to

allow the trace function capabilit y to run properly. These capacitors should be attached to the TBUS0:3

and ISBR signals.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 69

1.7.15 Smart Card Interface Function

The 73S1210F integrates one ISO-7816 (T=0, T =1) UART, one complete ICC electrical interface as well

as an external smart card interface to al l ow mul tiple smart cards to be connected using the Teridian 8010

family of int erface devices. Figure 14 shows the simplified block diagram of t he card circuitry (UART +

interfaces), with detail of dedi cat ed XRAM registers.

Figure 14: Smart Card Interface Block Diagram

Card interrupts are managed through two dedicated registers: SCIE (Interrupt E nabl e to define which

interrupt is enabled) and SCInt (Interrupt status). They allow the firmware to determine the source of an

interrupt, that can be a card inserti on / removal, card power fault, or a transmission (TX ) or recepti on (RX)

event / fault. It should be noted that ev en when card clock is disabled, an ICC interrupt can be generated

Direct

Mode

Card

Insertion

Activation /

Deactivation

Sequencer VCC

Buffer / Level

Shifter RST

Buffer / Level

Shifter CLK

I/O

Buffer / Level

Shifter

Buffer / Level

Shifter

Buffer / Level

Shifter

VCC Card

Generation

ICC Event

ICC Pwr_event

I/O ICC#1

I/OExt. ICC

CLK ICC

CLKExt. I CC

Card Clock

Management

7.2MHz

SCCLK/

SCSCLK

PRES

Serial

UART

Internal ICC Interface

SCSel

UART

T=0 T=1

RLength

STSTO

ATRMsB/LsB

BGT/EGT

SRXData

SRXCtl

STXData

STXCtl

SCPrtcol

SCCtl

FDReg

SByteCtl

SParCtl

Card Interrupt

Management

SCInt

SCIE

External ICC Interface

Bypass

Mode

XRAM Registers

VccCtl/

VccTMR

SCCLK/SCSCLK

Timers

2-Byte

Tx FIFO

2-Byte

Rx FIFO

Card and

Mode

Selection

SCDir

SCECtl

BGT0/1/2/3/

CWT0/1

SIO

SCLK

SCCLK

SCSCLK

73S1210F Data Sheet DS_1210F_001

70 Rev. 1.4

on a card insertion / removal to al low power savi ng m odes. Card insert ion / removal is generated from

the respective card switch detection inputs (whose polarit y is programmable).

The built-in ICC Interf ace has a li near regulator (VCC generator) capable of driving 1.8, 3.0 and 5.0V smart

cards in accordance with the ISO 7816-3 and EMV4. 1 st andards. Thi s converter uses the VP (5.5V

nominal) input supply source. See t he power supply m anagem ent section above for more detail.

Auxiliary I/O li nes C4 and C8 are only prov i ded for the built-in interface. If support for the auxiliary lines is

necessary for the external smart card int erf ace, they need to be handled manually through the USR GPIO

pins. The external 73S8010x devices directly connect the I/O (SI O) and clock (SCLK) signals and cont rol

is handled via the I2C interf ace.

Figure 15 shows how multiple 8010 devices can be connected t o the 73S1210F.

73S1210F

73S8010

73S8010 SC3

SC2

73S8010 SC(n)

SC1

INT3

SDA

SCL

INT

SCL

SDA

INT

SCL

SDA

INT

SCL

SDA

SAD(0:2)

I/O

RST

CLK

VPC

PRES

IOUC

XTALIN

GND

PRES

VPC

PRES

SIO

SCLK

VCC

Figure 15: External Smart Card Interface Block Diagram

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 71

1.7.15.1 ISO 7816 UART

An embedded ISO 7816 (hardware) UART is provided to cont rol comm unicat i ons between a smart card

and the 73S1210F MPU. The UART can be shared bet ween the one built-in ICC interface and the

external ICC interface. Selection of the desired interface is made by regist er SCSel. Control of the

external interface is handled by the I2C interface for any external 73S 8010x device. The following is a list

of features for the ISO 7816 UART:

• Two-byte FIFO for temporary data storage on both TX and Rx dat a.

• Parity checking in T=0. This feat ure can be enabl ed/disabled by firmware. Parity error reporti ng to

firmware and Break generation to ICC can be controlled independently.

• Parity error generation for test purposes.

• Retransmission of last byte if ICC indicates T=0 parity error. This feat ure can be enabl ed/disabled by

firmware.

• Deletion of last byte receiv ed i f ICC indicates T=0 parity error. This feature can be enabl ed/disabled

by firmware.

• CRC/LRC generation and checking. CRC/LRC is automat icall y inserted into T=1 data stream by t he

hardware. This feature can be enabled/disabled by firmware.

• Support baud rates: 115200, 57600, 38400, 28800, 19200, 14400, 9600 under firmware control

(assuming 12MHz crystal) with various F/D settings.

• Firmware manages F/D. All F/D combi nations are supported in which F/D is directly divisible by 31 or

32 (i.e. F/D is a multi ple of either 31 or 32).

• Flexible ETU clock generation and control.

• Detection of convention (direct or indirect) character TS . This affects both polarity and order of bits in

byte. Convention can be ov erridden by firmware.

• Supports WTX Timeout with an expanded Wait Time Counter (28 bits).

• A Bypass Mode is provided to by pass t he hardware UART in order for the sof tware to emulate the

UART (for non-standard operating m odes). In such a case, the I/O line value is refl ect ed i n S F R

SCCtl or SCECtl respectively for the built-in or external i nterfaces. This mode is appropriate for some

synchronous and non T=0 / T=1 cards.

The single integrated smart card UART is capable of supporti ng T =0 and T=1 cards in hardware

therefore offloading the bit manipulation tasks from the firmware. The em bedded firmware instructs the

hardware which smart card it should communicate with at any point in time. Firmware reconfigures the

UART as required when switching between smart cards. When the 73S1210F has transmitted a

message with an expected response, the firmware should not swit ch t he UART to another smart card

until the first smart card has responded. If the smart card responds while another smart card is selected,

that first smart card’s response will be ignored.

73S1210F Data Sheet DS_1210F_001

72 Rev. 1.4

1.7.15.2 Answer to Reset Processing

A card insertion event generates an interrupt to the firmware, which is then responsible for the

configuration of the electrical i nterface, the UART and activation of the card. The activation sequencer

goes through the power up sequence as defined in the IS O 7816-3 specif icat i on. An asynchronous

activation timing di agram i s shown in

Figure 16. After the card reset is de-asserted, the firmware instructs the hardware to look for a TS by te

that begins the ATR response. If a response is not provided within the pre-programmed tim eout period,

an interrupt is generated and the fi rmware can t hen take appropriate action, including instructing the

73S1210F to begin a deactivat i on sequence. O nce commanded, the deactivation sequencer goes

through the power down sequence as defined in the IS O 7816-3 specif i cat ion. If an ATR response is

received, the hardware looks for a TS byte that determines direct/inverse convention. The hardware

handles the indirect convention conversion such that the embedded firmware only receives direct

convention. This feature can be di sabled by firmware within SByteCtl register. Parity checking and

break generation is performed on the TS by te unless disabled by firmware. If during t he card session, a

card removal, over-current or other error event is detected, the hardware will automatically perform the

deactivation sequence and then generate an interrupt to the firmware. The firmware can then perform

any other error handling required for proper system operation. Smart card RST, I/O and CLK , C4, C8

shall be low before the end of the deact i vation sequence. Figure 17 shows the timing for a deactivation

sequence.

VCCSEL

bits

VCC

VCCOK bit

RSTCRD bit

RST

CLK

t1 t2 t3 t4 t5

tto

See Note

ATR starts

SELSC

bits

t1: SELSC.1 bit set (selects internal ICC interface) and a non-zero value in VCCSEL bits (calling for a

value of Vcc of 1.8, 3.0, or 5.0 volts) will begin the activation sequence. t1 is the time for Vcc to rise

to acceptable level, declared as Vcc OK (bit VCCOK gets set). This time depends on filter capacitor

value and card Icc load.

tto: The time al l owed for Vcc to rise to Vcc OK status after set ting of the VCCSEL bits. Thi s t i m e i s

generated by the VCCTMR counter. If Vcc OK is not set, (bit VCCOK) at this time, a deactivation will

be initiated. VCCSEL bi ts are not automatically cleared. The firmware must clear the VCCSEL bits

before starting a new activati on.

t2: Time from VccTmr timeout and VCC OK to IO reception (high), typically 2-3 CLK cycles if RDYST

= 0. If RDYST = 1, t2 starts when VCCOK = 1.

t3: Time from I O = high to CLK start, typically 2-3 CLK cy cles.

t4: Time allowed for start of CLK to de-assertion of RST. P rogramm abl e by the RLength register.

t5: Time allowed for A TR timeout, set by the STSTO register.

Note: If the RST CRD bit i s set, RST is asserted (low). Upon clearing RSTCRD bit, RST will be

de-asserted after t4.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 73

Figure 16: Asynchronous Activation Sequence Timing

VCC

RST

CLK

t1 t2

Firmware sets

VCCSEL to 00

CMDVCCnB

t5 delay or

Card Event

t1: Time after ei ther a “card event” occurs or firmware sets the VCCSela and VCCSelb bit s t o 0

(see t5, VCCOff_tmr) occurs until RS T is asserted l ow.

t2: Time after RS T goes low until CLK stops.

t3: Time after CLK st ops until IO goes low.

t4: Time after IO goes low until VCC is powered down.

t5: Delayed VCC off time (in ETUs per VCCOff_tmr bits). O nl y in effect due to firmware

deactivation.

Figure 17: Deactivation Sequence

1.7.15.3 Data Reception/Transmission

When a 12Mhz crystal is used, the smart card UART will generat e a 3.69Mhz (default) clock to both

smart card interfaces. This will allow approxi m ately 9600bps (1/ETU) communication during ATR (IS O

7816 default). As part of the PPS negotiation between the smart card and the reader, the firmware may

determine that the smart card paramet ers F & D may be changed. After this negotiation, the firmware

may change the ETU by writi ng to the SFR FDReg to adjust the ETU and CLK. The firmware may also

change the smart card clock frequency by writing to the SFR SCCLK (SCECLK for external interface).

Independent clock frequency control is provided t o each smart card int erface. Clock stop high or Clock

stop low is supported in asynchronous mode. Figure 18 shows the ETU and CLK cont rol circuit s. T he

firmware determines when clock stop is supported by the smart card and when it i s appropriat e to go into

that mode (and when to come out of it). The smart card UART is clocked by the same clock that i s

provided to the selected smart card. T he transition between smart card clocks is handled in hardware to

eliminate any glitches for the UA RT during swit chov er. T he external smart card clock is not affected

when switching the UART to communicate with the internal smart card.

73S1210F Data Sheet DS_1210F_001

74 Rev. 1.4

PLL

ETU Divider

12 bits

FI Decoder

DIV

ETUCLK

CLK

DIV

SCLK

Pre-Scaler

6 bits

Pre-Scaler

6 bits

F/D Register

SCCLK(5:0)

SCSCLK(5:0) MSCLK

MSCLKE

MCLK =

96MHz

FDReg(3:0)

FDReg(7:4)

9926

1/744

3.69M

1/13

7.38M

3.69M

7.38M

Defaults

in Italics

SCSel(3:2)

1/13

SYNC

CENTER

EDGE

Figure 18: Smart Card CLK and ETU Generation

There are two, two-byte FIFOs that are used to buffer transmit and receive data. During a T=0 processing,

if a parity error is detected by the 73S1210F during message reception, an error signal (BREAK) wil l be

generated to the smart card. The byt e receiv ed wil l be di scarded and the firmware notified of the error.

Break generation and receive byte dropping can be disabled under f irm ware control . During the

transmission of a byte, if an error signal (BREAK) is detected, t he l ast byte is retransmitted again and the

firmware notified. Retransmission can be disabled by firmware. When a correct byte is received, an

interrupt is generated to the firmware, which then reads the byte from the receive FIFO. Receive overruns

are detected by the hardware and reported vi a an interrupt. During transmission of a message, the

firmware will write bytes into the transmit FIFO. The hardware will send t hem to the smart card. When the

last byte of a message has been writt en, the firmware will need to set the LA STTX bit in the STXCtl SFR.

This will cause the hardware to insert the CRC/LRC if in a T =1 prot ocol m ode. CRC/LRC

generation/checking is only provided during T=1 processing. Firmware will need to instruct the smart

function to go into receive m ode after this last transmit data by te if it expects a response from the smart

card. At the end of t he smart card response, t he firmware will put the interface back into transmit mode if

appropriate.

The hardware can check for the following card-related timeouts:

• Character Waiting Time (CWT)

• Block Waiting Time (BWT)

• Initial Waiting Time (IWT)

The firmware will load the Wait Ti m e with the appropriate value for the operat ing m ode at the appropriate

time. Figure 19 shows the guard, block, wait and ATR t i m e definitions. If a tim eout occurs, an interrupt

will be generated and the firmware can take appropriat e recovery steps. Support is provided for adding

additional guard times between characters using the Ex tra Guard Time register (EGT), and between the

last byte received by t he 73S 1210F and the first byte transmitt ed by the 73S1210F using the Block Guard

Time register (BGT). Other than the protocol checks described above, the firmware is responsible for all

protocol checking and error recovery.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 75

> EGT

< WWT

CHAR 1 CHAR 2

CHAR

N+1 CHAR

N+2 CHAR

N+3

BLOCK1 BLOCK2

> BWT < CWT

RECEPTION

TRANSMISSION

T = 1 Mode

CHAR 1 CHAR 2 CHAR N

RST

TSTO(7:0) ATRTO(15:0)

VCC_OK

RLen(7:0)

CHAR 1 CHAR 2 CHAR N

ATR Timing Parameters

IWT(15:0)

BGT(4:0)

T = 0 Mode

EGT

(By seting Last_TXByte and

TX/RXB=0 during CHAR N,

RX mode will start after last

TX byte)

WWT is set by the value in the BWT registers.

Figure 19: Guard, Block, Wait and ATR Time Definitions

1.7.15.4 Bypass Mode

It is possible to bypass the smart card UART i n order for the firmware to support non-T=0/T=1 smart

cards. This is called Bypass mode. In t his m ode the embedded firmware will communicate directly with

the selected smart card and drive I/O during transmit and read I/O during receive in order to comm unicat e

with the smart card. In t hi s mode, ATR processing is under firmware control. The firmware must

sequence the interface signals as required. Firmware must perform T S processing, parity checking,

break generation and CRC/LRC calculation (if required).

1.7.15.5 Synchronous Operation Mode

The 73S1210F supports synchronous operation. When sync mode is selected f or ei ther interface, the

CLK signal is generated by the ETU counter. The values in c, SCCLK, and SCECLK must be set to

obtain the desired sync CLK rate. There i s only one ETU counter and therefore, in sync mode, the

interface must be selected to obt ai n a smart card clock signal. In sync mode, input data is sampled on

the rise of CLK, and output data is changed on the fall of CLK.

73S1210F Data Sheet DS_1210F_001

76 Rev. 1.4

Special Notes Regarding Synchronous Mode Operation

When the SCISYN or SCESNC bits (SPrtcol, bit 7, bit 5, respectively) are set , the selected smart card

interface operates in synchronous mode and there are changes in the definition and behavior of pertinent

1. The source for the smart card clock (CLK or SCLK) is the E TU count er. O nly the actively selected

interface can have a running synchronous clock. In contrast, an unselected interface may have a

running clock in the asynchronous mode of operation.

2. The control bits CLKLVL, SCLKLVL, CLKOFF, and SCLKOFF are f unct i onal i n sy nchronous mode.

When the CLKOFF bit is set, i t will not truncate either the logi c l ow or logi c high period when the (stop

at) level is of opposite pol arity. The CLK/SCLK signal wil l compl ete a correct logic low or logic high

duty cycle before stopping at the selected level. The CLK “start” is a result of the falling edge of the

CLKOFF bit. Set ting clock to run when it is stopped low will result in a half period of low before going

high. Setting clock to run when it is stopped high will result in the clock going low immediately and

then running at the selected rate with 50% duty cycle (within the l im i tations of the ETU divisor value).

3. The Rlen(7:0) is configured to count t he falling edges of the ETU clock (CLK or SCLK) after i t has

been loaded with a value from 1 to 255. A value of 0 disables the count i ng function and RLen

functions such as I/O source selection (I/O signal bypasses the FIFOs and is controlled by the

SCCLK/SCECLK SFRs). When the RLen counter reaches the “max” (loaded) v al ue, it sets the

WAITTO interrupt (SCInt, bit 7), which is m askable v i a WTO IEN (SCIE, bit 7). It must be reloaded in

order to start the counting/clocking process again. This al lows t he processor to select the number of

CLK cycles and hence, the number of bit s to be read or written to/from the card.

4. The FIFO is not clocked by t he first CLK (falling) edge resulting from a CLKOFF de-asserti on (a clock

start event) when the CLK was stopped in t he hi gh st ate and RLen has been loaded but not yet

clocked.

5. The state of the pi n IO or SIO is sampled on the rising edge of CLK /SCLK and stored in bit 5 of the

SCCtl/SCECtl register.

6. When Rlen = max or 0 and I2CMODE= 1 (STXCtl, b7), the IO or SIO signal is directl y controlled by the

data and direction bits in the respective SCCtl and SCECtl register. The state of the data in the TX

FIFO is bypassed.

7. In the SPrtcol register, bit 6 (MODE9/ 8B ) becomes act i ve. When set, the RXData FIF O wil l read

nine-bit words with the state of the ninth bit being readable in SRXCtl, bit 7 (B9DAT). The RXDAV

interrupt will occur when the ninth bit has been clocked in (rising edge of CLK or SCLK).

8. Care must be taken to clear the RX and TX FIFOs at the start of any transaction. The user shall read

the RX FIFO until i t indicates empty status. Reading the TX FIFO twice will reset the i nput byte

pointer and the next write to the TX FIFO will load the byte to the “first out” posit ion. Note that the bit

pointer (serializer/deserializer) is reset to bit 0 on any change of the TX/RXD bit.

Special bits that are only act i ve for sync mode include: SRXCtl, b7 “BIT9DAT”, SPrtcol, b6 “MODE9/8B”,

STXCtl, b7 “I2CMODE”, and the definition of SCInt, b7, which was “WAITTO”, becomes RLenINT i nterrupt,

and SCIE, b7, which was “WTOIEN”, becomes RLenIEN.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 77

VCC

VCCOK

RSTCRD

RST

CLK

t1 t2

tto

VCCSEL

bits

t1: The ti m e from setting VCCSEL bits until VCCOK = 1.

tto: The time from setting VCCSEL bits until VCCTMR times out. At t1 (if RDYST = 1) or tto (if RDYST = 0),

activation star ts. It is suggested to have RDYST = 0 and use the VCCTMR interrupt to let MPU know when

sequence is starting.

t2: time from start of activat ion (no exter nal indication) unt il IO goes i nto recepti on mode (= 1). This is approximately

4 SCCLK (or SCECLK) clock cycles.

t3: minimum one half of ETU period.

t4: ETU per i od.

Note that in Sync mode, IO as input is sampled on the r i sing edge of CLK. IO ch anges on the falling edge of CLK,

either from the ca r d or from the 73S1210F. The RST signal to the card is directly controlled by the RSTCRD bit

(non-inverted) via the MPU and is shown as an example of a possible RST pat tern.

Figure 20: Synchronous Activation

IO reception on

RST

CLK

CLKOFF

CLKLVL

Rlength Interrupt

RLength Count

RLenght = 1

TX/RXB Mode bit

(TX = '1')

1. Clear CLKOFF after Card is in reception mode.

2. Set RST bit.

3. Interrupt is generated when Rlength counter is MAX.

4. Read and clear Interrupt.

5. Clear RST bit.

6. Toggle TX/RXB to reset bit counter.

7. Reload RLength Counter.

Count MAX

t1. CLK wll start at least 1/2 ETU after CLKOFF is set low

when CLKLVL = 0

Figure 21: Example of Sync Mode Operation: Generating/Reading ATR Signals

73S1210F Data Sheet DS_1210F_001

78 Rev. 1.4

RLength Count - was set for length of ATR

CLK

RLength Interrupt

CLK Stop

CLK Stop Level

IO Bit

IODir Bit

TX/RX Mode Bit

TX = '1'

Data from Card -end of ATR Data from TX FIFO

RLength

Count MAX

1. Interrupt generated when Rlength counter is MAX.

2. Read and clear Interrupt.

3. Set CLK Stop and CLK Stop level high in Interrupt routine.

4. Set TX/RX Bit to TX mode.

5. Reload Rlength Counter.

6. Set IO Bit low and IODir = Output. Since Rlen=(MAX or 0) and TX/RX =1, IO pin is controlled by IO bit.

7. Clear CLK Stop and CLK Stop level.

Note: Data in TX fifo should not be Empty here.

START Bit

Synchronous Clock Start/Stop Mode style Start bit procedure. This procedure should be used to

generate the start bit insertion in Synchronous mode for Synchronous Clock Start/Stop Mode protocol.

RLen=0 Rlen=1

Figure 22: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync M ode

RLength Count

(Rlength = 9)

CLK

RLength Interrupt

CLK Stop

CLK Stop Level

IO Bit

IODir Bit

TX/RX Mode Bit

TX = '1'

I2CMode = 1: Data to/from Card

I2CMode = 0: Data from TX fifo I2CMode = 1:ACK Bit (to/from card)

I2CMode = 0: Data from TX fifo

RLength Count MAX

1. Interrupt generated when Rlength counter is MAX.

2. Read and clear Interrupt.

3. Set CLK Stop and CLK St op l evel high.

4. Set IO Bit low and I O Dir = Output.

5. Set TX/RX Bit to TX mode.

6. Reload Rlength Counter.

7. Set IO Bit High and IODir = Output.

8. Clear CLK Stop and CLK Stop lev el .

Note: Data in TX fifo should not be Empty here.

STOP Bit

TX/RX mode

Synchronous Clock Start/Stop Mode Stop bi t procedure. This procedure should be used to

generate the Stop bit in Sy nchronous Mode. S YCKST is bit 7 of STXCTL register.

Figure 23: Creation of Synchronous Clock Start/Stop Mode Stop Bit in S ync Mode

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 79

RLength Count

RLength = 9

CLK

RLength Interrupt

RX data

TX/RX Mode Bit

TX = '1'

Data from Card

(Bit 8) Data from Card

(Bit 1)

RLength Count MAX

Rlen=9

Protection Bit

(Bit 9)

RX FIFO

(Data from Card is ready for CPU read)

Protection Bit is ready for CPU read

Rlen=8 Rlen=0 Rlen =1

Protection Bit Data

(Bit 9)

1._ Interrupt generated

when Rlength counter is

Max

2._ Read and clear

Interrupt 3._ Reload RLength

counter

RLength Count

RLength = 9 RLength Count MAX

Rlen=9

Rlen=8

RLength Interrupt

CLK

CLK Stop

CLK Stop Level = 0

1._ Interrupt generated

when Rlength counter is Max 2._Stop CLK after the last

byte and protection bit

Stop CLK after receiving the last byte and protection bit.

Receive data in 9 bit m ode

Figure 24: Operation of 9-bit Mode in Sy nc M ode

Synchronous card operation is broken down into three primary t ypes. These are commonly referred to as

2-wire, 3-wire and I2C synchronous cards. Each card type requires different control and timing and

therefore requires different algorit hm s to access. Teridian has created an application note to provide

detailed algorithms for each card ty pe. Refer to the application note titled “73S12xxF Synchronous Card

Design Application Note”.

73S1210F Data Sheet DS_1210F_001

80 Rev. 1.4

1.7.15.6 Smart Card SFRs

Smart Card Select Register (SCSel): 0xFE00  0x00

The Smart Card Select register is used t o determine which smart card interface is using the ISO UART.

The internal Smart Card has integrated 7816-3 compl i ant sequencer circuitry to drive an external smart

card interface. The external smart card interface relies on 73S8010 parts to generate the ISO 7816-3

compatible signals and sequences. Multiple 73S8010 devices can be connected to the external smart

card interface.

Table 72: The SCSel Register

MSB LSB

– – – – SELSC.1 SELSC.0 BYPASS –

Bit Symbol Function

SCSel.7 –

SCSel.6 –

SCSel.5 –

SCSel.4 –

SCSel.3 SELSC.1 Select Smart Card Interface - These bits select the interface t hat is using

the IS0 UART. These bits do not activate the interface. A ct i vation is

performed by the VccCtl register.

00 = No smart card interface selected.

01 = External Smart Card Interface selected (using SCLK, SIO).

1X = Internal Smart Card I nterface selected.

SCSel.2 SELSC.0

SCSel.1 BYPASS 1 = Enabled, 0 = Disabled. When enabled, ISO UART is bypassed and the

I/O line is controlled vi a the SCCtl and SCECtl registers.

SCSel.0 –

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 81

Smart Card Interrupt Register (SCInt): 0xFE01  0x00

When the smart card interrupt is asserted, the firmware can read this register to determine the actual

cause of the interrupt. The bi ts are cleared when this register is read. Each interrupt can be disabled by

the Smart Card Interrupt E nabl e regi st er. Error processing must be handled by the firmware. This

Table 73: The SCInt Reg ister

MSB LSB

WAITTO CRDEVT VCCTMRI RXDAV TXEVT TXSENT TXERR RXERR

Bit Symbol Function

SCInt.7 WAITTO

Wait Timeout - An ATR or card wait timeout has occurred. In sync mode,

this interrupt is asserted when the RLen counter (it advances on falling

edges of CLK/ETU) reaches the loaded (max) val ue. This bit is cleared

when the SCInt register is read. When running i n S ynchronous Clock

Stop Mode, this bit becomes RLenINT interrupt (set when the Rlen

counter reaches the terminal count).

SCInt.6 CRDEVT

Card Event - A card event i s signaled via pin DETCARD either when the

Card was inserted or removed (read the CRDCtl register to det ermi ne

card presence) or there was a fault condition in the int erface circuitry.

This bit is functional even if the smart card logic clock is disabled and

when the PWRDN bit is set. This bit i s cleared when t he SCInt register is

read.

SCInt.5 VCCTMRI VCC Timer - This bit i s set when the VCCTMR times out. This bit is

cleared when the SCInt register is read.

SCInt.4 RXDAV

Rx Data Available - Data was received from the smart card because the

Rx FIFO is not empty. In bypass mode, this interrupt i s generat ed on a

falling edge of the smart card I /O line. After receiving this interrupt in

bypass mode, firmware should disable it unti l the firmware has received

the entire byte and is wait i ng for the next start delimit er. T hi s bit is

cleared when there is no RX data available i n the RX FIFO.

SCInt.3 TXEVNT TX Event - Set whenever the TXEMTY or TXFULL bits are set i n the

SRXCtl SFR. This bit is cleared when the STXCtl register is read.

SCInt.2 TXSENT

TX Sent - Set whenever the ISO UART has successfully transmitted a

byte to the smart card. Also set when a CRC/LRC byte is sent in T=1

mode. Will not be set in T=0 when a break is det ect ed at the end of a

byte (when break detection is enabled). Thi s bit is cleared when the

SCInt register is read.

SCInt.1 TXERR

TX Error - An error was detected during t he transmission of data to the

smart card as indicated by either BREA K D or TXUNDR bit being set in

the STXCtl SFR. Additional inf orm ation can be found in that register

description. This bit is cleared when the STXCtl register is read.

SCInt.0 RXERR

RX Error - An error was detected during the recepti on of data from the

smart card. Additional information can be found in the SRXCtl register.

This interrupt will be asserted for RXOV RR, or RX Parity error events.

This bit is cleared when the SRXCtl register is read.

73S1210F Data Sheet DS_1210F_001

82 Rev. 1.4

Smart Card Interrupt Enable Register (SCIE): 0xFE02  0x00

When set to 1, the respective condition can cause a smart card interrupt. When set to a 0, the respective

condition cannot cause an interrupt. When disabled, the respective bit in the Smart Card I nterrupt

Table 74: The SCIE Register

MSB LSB

WTOIEN CDEVEN VTMREN RXDAEN TXEVEN TXSNTEN TXEREN RXEREN

Bit Symbol Function

SCIE.7 WTOIEN Wait Timeout Interrupt Enable - Enable for ATR or Wait Timeout Interrupt.

In sync mode, function is RLI E N (RLen = max .) interrupt enable.

SCIE.6 CDEVEN Card Event Interrupt Enable.

SCIE.5 VTMREN VCC Timer Interrupt Enable.

SCIE.4 RXDAEN Rx Data Available Interrupt Enable.

SCIE.3 TXEVEN TX Event Interrupt Enable.

SCIE.2 TXSNTEN TX Sent Interrupt Enable.

SCIE.1 TXEREN TX Error Interrupt Enable.

SCIE.0 RXEREN RX Error Interrupt Enable.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 83

Smart Card VCC Control/Status Register (VccCtl ): 0xFE03  0x00

This register is used to control the power up and power down of the integrated smart card interface. It i s

used to determine whether to apply 5V, 3V, or 1.8 to the smart card. Perform the voltage selection wit h

one write operation, setting both VCCSEL.1 and VCCSEL.0 bits simultaneously. The VDDFLT bit (if

enabled) will provide an emergency deactivat i on of the internal smart card slot. See the VDD Fault

Detect Function section for more det ai l.

Table 75: The VccCtl Register

MSB LSB

VCCSEL.1 VCCSEL.0 VDDFLT RDYST VCCOK – – SCPWRDN

Bit Symbol Function

VccCtl.7 VCCSEL.1

Setting non-zero value for bits 7,6 will begin activation sequence with target

Vcc as given below:

State VCCSEL.1 VCCSEL.0 VCC

1 0 0 0V

2 0 1 1.8V

3 1 0 3.0V

4 1 1 5V

A card event or VCCOK going low will i ni tiate a deactivation sequence.

When the deactivation sequence for RST, CLK and I/O is complete, VCC will

be turned off. When this type of deactivation occurs, the bits must be reset

before initiating another acti vation.

VccCtl.6 VCCSEL.0

VccCtl.5 VDDFLT When there is a VDD Fault event, this bi t will be set = 0. This causes

VCCSEL.1 and VCCSEL.0 bits to be immediately set = 0 to begin

deactivation.

VccCtl.4 RDYST If this bit is set = 1, the activation sequence will start when bit VCCOK is set =

1. If not set, the deactivation sequence shall start when the VCCTMR times

out.

VccCtl.3 VCCOK (Read only). Indicates that VCC output voltage is stable.

VccCtl.2 –

VccCtl.1 –

VccCtl.0 SCPWRDN

This bit controls the power-off mode of the 73S1210F circuit.

1 = power off, 0 = normal operation. When i n power down mode,

VDD = 0V. VDD can only be turned on by pressing the ON/O FF swit ch or by

application of 5V to VBUS. If VBUS power is available and SCPWRDN bit is set,

it has no effect until VBUS is removed and VDD will shut off.

73S1210F Data Sheet DS_1210F_001

84 Rev. 1.4

VCC Stable Timer Register (VccTmr): 0xFE04  0x0F

A programmable timer is provided to set the time from activation start (setting the VCCSEL.1 and

VCCSEL.0 bits to non-zero) to when VCC_OK is evaluated. V CC_OK m ust be true at the end of this

timers programmed interval (tt o i n Figure 16) in order for the activation sequence to continue. If VCC_OK

is not true and the end of t he interval (tto), the Card Event interrupt will be set, and a deactivation

sequence shall begin including clearing of the VCCSEL bits.

Table 76: The VccTmr Register

MSB LSB

OFFTMR.3 OFFTMR.2 OFFTMR.1 OFFTMR.0 VCCTMR.3 VCCTMR.2 VCCTMR.1 VCCTMR.0

Bit Symbol Function

VccTmr.7 OFFTMR.3 VCC Off Timer - The bits set the delay (in number of ETUs) for

deactivation after t he V CCSEL.1 and VCC SEL.0 have been set

to 0. The time v al ue is a count of the 32768Hz clock and is given

by tto = OFFTMR(7:4) * 30.5µs. This delay does not affect

emergency deactivations due to VDD Fault or card events. A

value of 0000 results in no additi onal delay.

VccTmr.6 OFFTMR.2

VccTmr.5 OFFTMR.1

VccTmr.4 OFFTMR.0

VccTmr.3 VCCTMR.3 VCC Timer - VCCOK must be true at the time set by the value i n

these bits in order for the activ ation sequence to continue. If not,

the VCCSEL bits will be cleared. T he time value is a count of the

32768Hz clock and is given by tto = VCCTMR(3:0) * 30.5µs. A

value of 0000 results in no tim eout, not zero time, and activ ation

requires that RDYST is set and RDY goes high.

VccTmr.2 VCCTMR.2

VccTmr.1 VCCTMR.1

VccTmr.0 VCCTMR.0

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 85

Card Status/Contro l Register (CRDCtl): 0xFE05  0x00

This register is used to configure the card detect pin (DETCA RD) and monit or card det ect st atus. This

up/down enable before setting CDETEN. The card det ect l ogi c is f unct i onal even without smart card logic

clock. When the PWRDN bit i s set = 1, no debounce i s prov i ded but card presence is operable.

Table 77: The CRDCtl Registe r

MSB LSB

DEBOUN CDETEN – – DETPOL PUENB PDEN CARDIN

Bit Symbol Function

CRDCtl.7 DEBOUN

Debounce - When set = 1, this will enable hardware debounce of

the card detect pin. The debounce funct ion shall wait for 64ms of

stable card detect assertion before setting the CARDIN bit. This

counter/timer uses the keypad clock as a source of 1kHz signal.

De-assertion of the CARDIN bit is im m edi ate upon de-assertion

of the card detect pin(s).

CRDCtl.6 CDETEN Card Detect Enable - When set = 1, activates card detection

input. Default upon power-on reset is 0.

CRDCtl.5 –

CRDCtl.4 –

CRDCtl.3 DETPOL Detect Polarity - When set = 1, the DETCARD pin shall i nterpret

a logic 1 as card present.

CRDCtl.2 PUENB Enable pull-up current on DETCARD pin (active low).

CRDCtl.1 PDEN Enable pull-down current on DETCARD pin.

CRDCtl.0 CARDIN

Card Inserted - (Read only). 1 = card inserted, 0 = card not

inserted. A change in the val ue of this bit is a “card event.” A

read of this bit indicates whether smart card is inserted or not

inserted in conjunction with the DETPOL setting.

73S1210F Data Sheet DS_1210F_001

86 Rev. 1.4

TX Control/Status Register (STXCtl): 0xFE06  0x00

This register is used to control transmission of data to the smart card. Some control and some stat us bi ts

are in this register.

Table 78: The STXCtl Reg ister

MSB LSB

I2CMODE – TXFULL TXEMTY TXUNDR LASTTX TX/RXB BREAKD

Bit Symbol Function

STXCtl.7 I2CMODE

I2C Mode - When in sync mode and this bit is set , and when the RLen count

value = max or 0, the source of the smart card data for IO pin (or SIO pi n) wil l

be connected to the IO bit i n SCCtl (or SCECtl) register rather than the TX

FIFO. See the description for the Protocol Mode Register for more detail.

STXCtl.6 –

STXCtl.5 TXFULL TX FIFO is full. Additional writes may corrupt the contents of t he F IFO. This

bit it will remain set as long as the TX FIFO is full. Generates a TX_Event

interrupt upon going full.

STXCtl.4 TXEMTY

1 = TX FIFO is empty, 0 = TX FIFO is not empty . If there is data in the TX

FIFO, the circuit will transmit it to the smart card if i n transmit mode. In T=1

mode, if the LAST TX bit is set and the hardware is configured to transmit the

CRC/LRC, the TXEMTY will not be set until the CRC/LRC is transmitted. In

T=0, if the LASTTX bit is set, TXEMTY will be set after the last word has

been successfully transmitted to t he smart card. G enerat es a T X EVNT

interrupt upon going empty.

STXCtl.3 TXUNDR

TX Underrrun - (Read only) Asserted when a transmit under-run condition

has occurred. An under-run condition is defined as an empty T X FIFO when

the last data word has been successfully transmit ted to the smart card and

the LASTTX bit was not set . No special processing is performed by the

hardware if this condition occurs. Cleared when read by fi rmware. T his bi t

generates a TXERR interrupt.

STXCtl.2 LASTTX

Last TX Byte - Set by firmware (in both T=0 and T=1) when the last byte in

the current message has been written into the transmit FIFO. In T=1 mode,

the CRC/LRC will be appended to the message. S houl d be set after the last

byte has been written into the transmit FIFO. Should be cleared by firmware

before writing first byt e of next message into the transmit F IFO. Used in T=0

to determine when to set TXEMTY.

STXCtl.1 TX/RXB

1 = Transmit mode, 0 = Receive mode. Conf i gures t he hardware to be

receiving from or transmitti ng to the smart card. Determines which counters

should be enabled. This bit should be set to receiv e m ode prior to switching

to another interface. S etting and resetting this bit shall i ni tialize the CRC

logic. If LASTTX is set, this bit can be reset to RX mode and UART logi c will

automatically change mode to RX when TX operation is completed

(TX_Empty = 1).

STXCtl.0 BREAKD Break Detected - (Read only) 1 = A break has been detected on the I/O line

indicating that the smart card detected a parit y error. Cleared when read.

This bit generates a TXERR interrupt.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 87

STX Data Register (STXData): 0xFE07  0x00

Table 79: The STXData Register

MSB LSB

STXDAT.7 STXDAT.6 STXDAT.5 STXDAT.4 STXDAT.3 STXDAT.2 STXDAT.1 STXDAT.0

Bit Function

STXData.7

Data to be transmitted to smart card. Gets stored in the TX FIFO and then extracted by

the hardware and sent to the selected smart card. When the MPU reads this register,

the byte pointer is changed to ef fectively “read out” the data. Thus, two reads will

always result in an “empty” FI FO condition. The contents of the FI F O regist ers are not

cleared, but will be overwritten by writes.

STXData.6

STXData.5

STXData.4

STXData.3

STXData.2

STXData.1

STXData.0

SRX Control/ Status Register (SRXCtl ): 0x F E08  0x00

This register is used to monitor reception of data from the smart card.

Table 80: The SRXCtl Reg ister

MSB LSB

BIT9DAT – LASTRX CRCERR RXFULL RXEMTY RXOVRR PARITYE

Bit Symbol Function

SRXCtl.7 BIT9DAT Bit 9 Data - When in sync mode and with MODE9/8B set, this bit will contain

the data on IO (or SIO) pi n that was sampled on the ninth CLK (or SCLK)

rising edge. This is used to read data in synchronous 9-bit formats.

SRXCtl.6 –

SRXCtl.5 LASTRX

Last RX Byte - User sets this bit during the reception of the last byte. When

byte is received and this bit i s set, logic checks CRC to match 0x1D0F (T=1

mode) or LRC to match 00h (T=1 mode), otherwise a CRC or LRC error i s

asserted.

SRXCtl.4 CRCERR (Read only) 1 = CRC (or LRC) error has been detected.

SRXCtl.3 RXFULL (Read only) RX FIFO is full. S tatus bit to indicate RX FIFO i s f ul l .

SRXCtl.2 RXEMTY (Read only) RX FIFO is empty. This is only a status bit and does not generate

an RX interrupt.

SRXCtl.1 RXOVRR

RX Overrun - (Read Only) Asserted when a receive-over-run conditi on has

occurred. An over-run is defined as a byte was received f rom the smart card

when the RX FIFO was full. Invalid data may be in the receiv e FIFO.

Firmware should take appropriate action. Cleared when read. Additional

writes to the RX FIFO are di scarded when a RXOV RR occurs until the overrun

condition is cleared. Will generate an RXE RR interrupt.

SRXCtl.0 PARITYE Parity Error - (Read only) 1 = The logic detected a parity error on incoming

data from the smart card. Cleared when read. Wil l generate an RXERR

interrupt.

73S1210F Data Sheet DS_1210F_001

88 Rev. 1.4

SRX Data Register (SRXData): 0xFE09  0x00

Table 81: The SRXData Register

MSB LSB

SRXDAT.7 SRXDAT.6 SRXDAT.5 SRXDAT.4 SRXDAT.3 SRXDAT.2 SRXDAT.1 SRXDAT.0

Bit Function

SRXData.7

(Read only) Data received from the smart card. Dat a receiv ed from the smart

card gets stored in a FIFO that i s read by the firmware.

SRXData.6

SRXData.5

SRXData.4

SRXData.3

SRXData.2

SRXData.1

SRXData.0

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 89

Smart Card Contr o l Register (SCCtl): 0xFE 0 A  0x21

This register is used to monitor reception of data from the smart card.

Table 82: The SCCtl Register

MSB LSB

RSTCRD – IO IOD C8 C4 CLKLVL CLKOFF

Bit Symbol Function

SCCtl.7 RSTCRD

1 = Asserts the RST (set RST = 0) to the smart card int erface, 0 = De-assert

the RST (set RST = 1) to the smart card interface. Can be used to extend

RST to the smart card. Refer to RLength register description. This bi t is

operational in all modes and can be used to ex tend RST during activation or

perform a “Warm Reset” as required. In auto-sequence mode, this bit should

be set = 0 to allow the sequencer to de-assert RST per the RLength

parameters.

In sync mode (see the SPrtcol register) the sense of this bit is non-inv ert ed, if

set = 1, RST = 1, if set = 0, RS T = 0. Rlen has no effect on Reset i n sy nc

mode.

SCCtl.6 –

SCCtl.5 IO

Smart Card I/O. Read is state of I/O signal (Caution, t hi s signal i s not

synchronized to the MPU clock). In By pass mode, write value is state of

signal on I/O. In sy nc m ode, this bit will contain the value of I/O pin on the

latest rising edge of CLK.

SCCtl.4 IOD Smart Card I/O Direction control Bypass mode or sync mode. 1 = i nput

(default), 0 = output.

SCCtl.3 C8

Smart Card C8. When C8 is an output, the value written to this bit will appear

on the C8 line. The value read when C8 is an output is the value stored in

the register. When C8 is an input, the value read is the value on the C8 pin

(Caution, this signal is not synchronized to the MPU clock). When C8 is an

input, the value writ ten will be stored in the register but not presented to the

C8 pin.

SCCtl.2 C4

Smart Card C4. When C4 is an output, the value written to this bit will appear

on the C4 line. The value read when C4 is an output is the value stored in

the register. When C4 is an input, the value read is the value on the C4 pin

(Caution, this signal is not synchronized to the MPU clock). When C4 is an

input, the value writ ten will be stored in the register but not presented to the

C4 pin.

SCCtl.1 CLKLVL 1 = High, 0 = Low. If CLKOFF is set = 1, the CLK to smart card will be at the

logic level indicated by thi s bit. If in bypass mode, t his bit directly controls the

state of CLK.

SCCtl.0 CLKOFF 0 = CLK is enabled. 1 = CLK is not enabled. When asserted, t he CLK wil l

stop at the level selected by CLKLVL. This bit has no effect i f in bypass

mode.

73S1210F Data Sheet DS_1210F_001

90 Rev. 1.4

External Sm a r t Ca r d Co n tr o l Register (SCECtl): 0xF E0B  0x00

This register is used to directly set and sample signals of E xternal Smart Card interface. There are three

modes of asynchronous operation, an “automati c sequence” mode, and bypass mode. Clock stop per

the ISO 7816-3 interface is also supported but firmware must handle the protocol for SIO and SCLK for

I2C clock stop and start. Control for Reset (t o m ake RST signal ), activation control, voltage select, etc.

should be handled via the I2C interface when using external 73S8010 devices. USR(n) pins shall be

used for C4, C8 functions if necessary.

Table 83: The SCECtl Reg ister

MSB LSB

– – SIO SIOD – – SCLKLVL SCLKOFF

Bit Symbol Function

SCECtl.7 –

SCECtl.6 –

SCECtl.5 SIO

External Smart Card I/O. Bit when read indicates state of pin S IO for SIOD

= 1 (Caution, this signal is not synchronized to the MPU clock), when

written, sets the stat e of pin SIO for SIOD = 0. Ignored if not in bypass or

sync modes. In sync mode, thi s bit will contain the value of I O pi n on the

latest rising edge of SCLK.

SCECtl.4 SIOD 1 = input, 0 = output. External Sm art Card I /O Direction control. Ignored if

not in bypass or sync modes.

SCECtl.3 –

SCECtl.2 –

SCECtl.1 SCLKLVL Sets the state of SCLK when disabled by SCLKOFF bit . If in bypass mode,

this bit directly controls the state of SCLK.

SCECtl.0 SCLKOFF 0 = SCLK enabled, 1 = SCLK disabled. When di sabled, SCLK level is

determined by SCLKLVL. This bit has no effect i f in bypass mode.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 91

C4/C8 Data Directio n Reg ister (SCDIR): 0xFE0C  0x00

This register determines the direction of the internal interface C4/C8 lines. After reset, all signals are

tri-stated.

Table 84: The SCDIR Regis ter

MSB LSB

– – – – C8D C4D – –

Bit Symbol Function

SCDIR.7 –

SCDIR.6 –

SCDIR.5 –

SCDIR.4 –

SCDIR.3 C8D 1 = input, 0 = output. Smart Card C8 direction.

SCDIR.2 C4D 1 = input, 0 = output. Smart Card C4 direction.

SCDIR.1 –

SCDIR.0 –

73S1210F Data Sheet DS_1210F_001

92 Rev. 1.4

Protocol Mode Register (SPrtcol): 0xFE0D  0x03

This register determines the protocol to be use when communi cat i ng with the selected smart card. This

Table 85: The SPrtcol Register

MSB LSB

SCISYN MOD9/8B SCESYN 0 TMODE CRCEN CRCMS RCVATR

Bit Symbol Function

SPrtcol.7 SCISYN

Smart Card Internal Sy nchronous mode - Configures internal smart card

interface for synchronous mode. This mode rout es the internal interface

buffers for RST, IO, C4, C8 to the SCCtl register bits for direct firmware

control. CLK is generated by t he ETU counter.

SPrtcol.6 MOD9/8B Synchronous 8/9 bit mode select - For sync mode, i n protocols with 9-bit

words, set this bit. The f i rst ei ght bits read go into the RX FIFO and the

ninth bit read will be stored in the IO (or SIO) data bit of the SRXCtl register.

SPrtcol.5 SCESYN

Smart Card External Synchronous mode - Configures External Smart Card

interface for synchronous mode. This mode rout es the external smart card

interface buffers for SI O to SCECtl register bits for direct firmware control.

SCLK is generated by the ET U count er.

SPrtcol.4 0 Reserved bit , must always be set to 0.

SPrtcol.3 TMODE Protocol mode select - 0: T=0, 1: T=1. Determines which smart card

protocol is to be used during message processing.

SPrtcol.2 CRCEN

CRC Enable – 1 = Enabled, 0 = Disabled. Enables the checking/generation

of CRC/LRC while in T=1 mode. Has no effect i n T=0 m ode. If enabled and

a message is being transmitted to t he smart card, the CRC/LRC will be

inserted into the message stream after the last TX byte is transmitt ed to the

smart card. If enabled, CRC/LRC will be checked on incoming messages

and the value made available to the firmware via the CRC LS/MS regi st ers.

SPrtcol.1 CRCMS CRC Mode Select – 1 = CRC, 0 = LRC. Determines type of checking

algorithm to be used.

SPrtcol.0 RCVATR Receive ATR – 1 = Enable ATR timeout , 0 = Disable ATR timeout. Set by

firmware after the smart card has been turned on and the hardware is

expecting ATR.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 93

SC Clock Configuration Register (SCCLK): 0xFE0F  0x0C

This register controls the internal smart card (CLK) clock generation.

Table 86: The SCCLK Regi ste r

MSB LSB

– – ICLKFS.5 ICLKFS.4 ICLKFS.3 ICLKFS.2 ICLKFS.1 ICLKFS.0

Bit Symbol Function

SCCLK.7 –

SCCLK.6 –

SCCLK.5 ICLKFS.5 Internal Smart Card CLK Frequency Select - Division factor t o determine

internal smart card CLK frequency. MCLK clock is div i ded by (register

value + 1) to clock the ETU divider, and then by 2 to generate CLK.

Default ratio is 13. The programm ed value in this register is applied to the

divider after this val ue i s writ ten, in such a manner as to produce a

glitch-free output, regardless of the selection of act ive interface. A

SCCLK.4 ICLKFS.4

SCCLK.3 ICLKFS.3

SCCLK.2 ICLKFS.2

SCCLK.1 ICLKFS.1

SCCLK.0 ICLKFS.0

External SC Clock Configuration Register (SCECLK): 0xFE10  0x0C

This register controls the external smart card (SCLK) clock generati on.

Table 87: The SCECLK Register

MSB LSB

– – ECLKFS.5 ECLKFS.4 ECLKFS.3 ECLKFS.2 ECLKFS.1 ECLKFS.0

Bit Symbol Function

SCECLK.7 –

SCECLK.6 –

SCECLK.5 ECLKFS.5 External Smart Card CLK Frequency Select - Division factor to determine

external smart card CLK frequency. M CLK clock is div i ded by (register

value + 1) to clock the ETU divider, and then by 2 to generate SCLK.

Default ratio is 13. The programm ed value in this register is applied to the

divider after this val ue i s writ ten, in such a manner as to produce a

glitch-free output, regardless of the selection of act ive interface. A

SCECLK.4 ECLKFS.4

SCECLK.3 ECLKFS.3

SCECLK.2 ECLKFS.2

SCECLK.1 ECLKFS.1

SCECLK.0 ECLKFS.0

73S1210F Data Sheet DS_1210F_001

94 Rev. 1.4

Parity Control Register (SParCtl): 0xFE11  0x00

This register provides the ability to configure the parity circuitry on t he smart card interface. The settings

apply to both integrated smart card int erfaces.

Table 88: The SParCtl Register

MSB LSB

– DISPAR BRKGEN BRKDET RETRAN DISCRX INSPE FORCPE

Bit Symbol Function

SParCtl.7 –

SParCtl.6 DISPAR Disable Parity Check – 1 = disabled, 0 = enabled. If enabled, the UA RT wil l

check for even parity (the number of 1’s including the parity bit is even) on

every character. This also applies to t he TS during ATR.

SParCtl.5 BRKGEN

Break Generation Disable – 1 = disabled, 0 = enabled. If enabled, and T=0

protocol, the UART will generate a Break to the smart card if a parity e rror i s

detected on a receive character. No Break will be generat ed i f parity

checking is disabled. This also applies to TS during ATR.

SParCtl.4 BRKDET Break Detection Disable – 1 = disabled, 0 = enabled. If enabled, and T=0

protocol, the UART will detect the generation of a Break by the smart card.

SParCtl.3 RETRAN Retransmit Byte – 1 = enabled, 0 = disabled. If enabl ed and a Break is

detected from the smart card (Break Detect i on m ust be enabl ed), the last

character will be transmitted again. This bit applies to T=0 protocol.

SParCtl.2 DISCRX Discard Received Byte – 1 = enabled, 0 = disabled. If enabled and a parity

error is detected (Parity checking must be enabled), the last character

received will be discarded. This bit applies t o T=0 protocol.

SParCtl.1 INSPE Insert Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If

enabled, the UART will insert a parity error in every character transmitted by

generating odd parity instead of even parity for the character.

SParCtl.0 FORCPE Force Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If

enabled, the UART will generate a parity error on a character received from

the smart card.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 95

Byte Contr o l Register (SByteCtl): 0xFE12  0x2C

This register controls the processing of characters and the detection of the TS byte. When receiving, a

Break is asserted at 10.5 ETU after the beginning of the start bit. Break from the card is sampled at 11

ETU.

Table 89: The SByteCtl Register

MSB LSB

– DETTS DIRTS BRKDUR.1 BRKDUR.0 – – –

Bit Symbol Function

SByteCtl.7 –

SByteCtl.6 DETTS

Detect TS Byte – 1 = Next Byte is TS, 0 = Next byte is not TS. When set, the

hardware will treat the next character receiv ed as t he TS and determine if

direct or indirect convention is being used. Direct conv ention is the default

used if firmware does not set this bit prior to transmission of TS by the smart

card to the firmware. The hardware will check parity and generate a break as

defined by the DISP A R and B RK G E N bi ts in the parity control register. T hi s

bit is cleared by hardware after TS i s received. TS is decoded prior to the

FIFO and is stored in the receive FIFO.

SByteCtl.5 DIRTS

Direct Mode TS Select – 1 = direct mode, 0 = indirect mode. Set/cleared by

hardware when TS is processed indicating either direct/indirect mode of

operation. When switching between smart cards, t he firmware should write

the bit appropriately since thi s regist er i s not uni que to an individual smart

card (firmware should keep track of this bit).

SByteCtl.4 BRKDUR.1 Break Duration Select – 00 = 1 ETU, 01 = 1.5 ETU, 10 = 2 ETU,

11 = reserved. Determines the length of a B reak signal which is generat ed

when detecting a parity error on a character reception in T =0 mode.

SByteCtl.3 BRKDUR.0

SByteCtl.2 –

SByteCtl.1 –

SByteCtl.0 –

73S1210F Data Sheet DS_1210F_001

96 Rev. 1.4

FD Control Register (FDReg): 0xFE13  0x11

This register uses the transmission factors F and D to set the ETU (baud) rate. The values in this register

are mapped to the ISO 7816 conv ersion factors as described below. The CLK signal for each interface is

created by dividing a high-frequency , intermediate signal (MSCLK) by 2. The ETU baud rate is created

by dividing MSCLK by 2 times the Fi/Di ratio specified by the codes below. For example, if FI = 0001 and

DI = 0001, the ratio of F i/Di is 372/1. Thus the ETU divider i s confi gured to divide by 2 * 372 = 744. The

maximum supported F/D ratio i s 4096.

Table 90: The FDReg Register

MSB LSB

FVAL.3 FVAL.2 FVAL.1 FVAL.0 DVAL.3 DVAL.2 DVAL.1 DVAL.0

Table 91: The FDReg Bit Functions

Bit Symbol Function

FDReg.7 FVAL.3 Refer to the Table 93 above. T his value is converted per the table to

set the divide ratio used to generat e the baud rate (ETU). Default,

also used for ATR, is 0001 (Fi = 372). This val ue is used by the

selected interface.

FDReg.6 FVAL.2

FDReg.5 FVAL.1

FDReg.4 FVAL.0

FDReg.3 DVAL.3 Refer to Table 93 above. This val ue i s used t o set the divide ratio

used to generate the smart card CLK. Def ault, also used for ATR, is

0001 (Di = 1).

FDReg.2 DVAL.2

FDReg.1 DVAL.1

FDReg.0 DVAL.0

Table 92: Divider Ratios Provided by the ETU Counter

FI (code) 0000 0001 0010 0011 0100 0101 0110 0111

Fi (ratio) 372 372 558 744 1116 1488 1860 1860⊕

FCLK max 4 5 6 8 12 16 20 20⊕

FI(code) 1000 1001 1010 1011 1100 1101 1110 1111

Fi(ratio) 512⊕ 512 768 1024 1536 2048 2048⊕ 2048⊕

FCLK max 5⊕ 5 7.5 10 15 20 20⊕ 20⊕

DI(code) 0000 0001 0010 0011 0100 0101 0110 0111

Di(ratio) 1⊕ 1 2 4 8 16 32 32⊕

DI(code) 1000 1001 1010 1011 1100 1101 1110 1111

Di(ratio) 12 20 16⊕ 16⊕ 16⊕ 16⊕ 16⊕ 16⊕

Note: values marked with ⊕ are not i ncluded in the ISO definition and arbitrary values have been

assigned.

The values given below are used by the ETU divider to create the ETU clock. The entries that are not

shaded will result in precise CLK/ETU per ISO requirem ents. Shaded areas are not precise but are

within 1% of the t arget value.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 97

Table 93: Divider Values for the ETU Clock

Fi code 0000 0001 0010 0011 0100 0101

code F→

D↓ 372 372 558 744 1116 1488

0001 1 744 744 1116 1488 2232 2976

0010 2 372 372 558 744 1116 1488

0011 4 186 186 279 372 558 744

0100 8 93 93 138 186 279 372

1000 12 62 62 93 124 186 248

0101 16 47 47 70 93 140 186

1001 20 37 37 56 74 112 149

0110 32 23 23 35 47 70 93

Fi code 0110 1001 1010 1011 1100 1101

code F→

D↓ 1860 512 768 1024 1536 2048

0001 1 3720 1024 1536 2048 3072 4096

0010 2 1860 512 768 1024 1536 2048

0011 4 930 256 384 512 768 1024

0100 8 465 128 192 256 384 512

1000 12 310 85 128 171 256 341

0101 16 233 64 96 128 192 256

1001 20 186 51 77 102 154 205

0110

116

128

73S1210F Data Sheet DS_1210F_001

98 Rev. 1.4

CRC MS Value Registers (CRCMsB): 0xFE14  0xFF, (CRCLsB): 0xFE15  0xFF

Table 94: The CRCMsB Register

MSB LSB

CRC.15 CRC.14 CRC.13 CRC.12 CRC.11 CRC.10 CRC.9 CRC.8

MSB LSB

CRC.7 CRC.6 CRC.5 CRC.4 CRC.3 CRC.2 CRC.1 CRC.0

The 16-bit CRC value forms the TX CRC word in TX m ode (writ e value) and the RX CRC in RX mode

(read value). The initial v al ue of CRC to be used when generating a CRC to be transmitted at the end of

a message (after the last TX byt e is sent ) when enabled i n T =1 mode. Should be reloaded at the

beginning of every message to be t ransmi tted. When using CRC, both CRC registers should be

initialized to FF. When using LRC, the CRCLsB value register should be loaded to 00. When receiving a

message, the firmware should load this wit h the initial value and then read this regist er to get the final

value at the end of the message. These registers need to be reloaded for each new message to be

received. When in LRC mode, bits (7:0) are used and bit s (15: 8) are undefined. During LRC/CRC

checking and generation, this register is updated with the current value and can be read to aid in

debugging. This information wil l be transmitted to the smart card using the t i m i ng specif i ed by the Guard

Time register. When checking CRC/LRC on an incoming message (CRC/LRC is checked against the

data and CRC/LRC), the firmware reads the f inal value after the message has been received and

determines if an error occurred (= 0x1D0F (CRC) no erro r, else error; = 0 (LRC) no error, else error).

When a message is received, the CRC/LRC is stored in the FIFO. The polynomial used to generate and

check CRC is x16 + x12+ x5 +1. When in indirect convention, the CRC is generated prior to the conversion

into indirect convention. When in indirect conv ention, the CRC is checked after the conversion out of

indirect convention. For a given message, the CRC generated (and readable from this register) will be

the same whether indirect or direct conventi on is used t o transmit the data to the smart card. T he

CRCLsB / CRCMsB registers will be updated with CRC/LRC whenever bits are being receiv ed or

transmitted from/t o the smart card (even if CRCEN is not set and in mode T1). T hey are available to the

firmware to use if desired.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 99

Block Guard Time Register (BGT): 0xFE 16  0x10

This register contains the Extra Guard Ti m e V al ue (E G T) m ost-signif i cant bi t. The Extra Guard Time

indicates the minimum ti m e between the leading edges of the start bit of consecutive characters. The

delay is depends on the T=0/T=1 mode. Used in transmit mode. This register also contains the Block

Guard Time (BGT) value. B l ock Guard Tim e i s t he m i nim um time between the leading edge of the st art

bit of the last character received and the leading edge of the start bit of the first character transmitted.

This should not be set less than the character length. The transmission of the first character will be hel d

off until BGT has elapsed regardless of the TX data and TX/RX control bit timing.

Table 95: The BGT Register

MSB LSB

EGT.8 – – BGT.4 BGT.3 BGT.1 BGT.2 BGT.0

Bit Symbol Function

BGT.7 EGT.8 Most-significant bit for 9-bit EGT tim er. See the EGT register.

BGT.6 –

BGT.5 –

BGT.4 BGT.4

Time in ETUs between the start bi t of the last received character to

start bit of the first character transmitted to the smart card. Def aul t

value is 22.

BGT.3 BGT.3

BGT.2 BGT.2

BGT.1 BGT.1

BGT.0 BGT.0

Extra Guard Time Register (E G T): 0xFE17  0x0C

This register contains the Extra Guard Ti m e V al ue (E G T) l east-signif i cant byte. The Extra Guard Time

indicates the minimum ti m e between the leading edges of the start bit of consecutive characters. The

delay depends on the T=0/T=1 mode. Used in t ransmit mode.

Table 96: The EGT Register

MSB LSB

EGT.7 EGT.6 EGT.5 EGT.4 EGT.3 EGT.1 EGT.2 EGT.0

Bit Function

EGT.7

Time in ETUs between start bits of consecutive characters. In T=0

mode, the minimum is 1. In T=0, the leading edge of t he next start bit

may be delayed if t here is a break det ect ed from the smart card.

Default value is 12. In T=0 mode, regardless of the value loaded, the

minimum value is 12, and for T=1 mode, the minimum value i s 11.

EGT.6

EGT.5

EGT.4

EGT.3

EGT.2

EGT.1

EGT.0

73S1210F Data Sheet DS_1210F_001

100 Rev. 1.4

Block Wait Time Registers (BWTB0): 0xFE1B  0x00, (BWTB1): 0xFE1A  0x00,

(BWTB2): 0xFE19  0x00, (BWTB3): 0xFE18  0x00

These registers are used to set the Block Waiting Tim e(27: 0) (B WT). All of these parameters define t he

maximum time t he 73S1210F will have to wait for a character from the smart card. These registers serve

a dual purpose. When T=1, these registers are used to set up t he block wait time. The block wait time

defines the time in ETUs bet ween t he beginni ng of the last character sent to smart card and the start bit

of the first character received f rom smart card. It can be used to detect an unresponsive card and should

be loaded by firmware prior to writi ng the last TX byte. When T=0, these registers are used to set up the

work wait time. The work wait ti m e i s def i ned as the time between the leading edge of two consecutive

characters being sent to or from the card. I f a timeout occurs, an interrupt is generated t o the firmware.

The firmware can then take appropriate action. A Wait Time Extension (WTX) is supported with the 28-

bit BWT.

Table 97: The BWTB0 Register

MSB LSB

BWT.7 BWT.6 BWT.5 BWT.4 BWT.3 BWT.1 BWT.2 BWT.0

Table 98: The BWTB1 Register

MSB LSB

BWT.15 BWT.14 BWT.13 BWT.12 BWT.11 BWT.10 BWT.9 BWT.8

Table 99: The BWTB2 Register

MSB LSB

BWT.23 BWT.22 BWT.21 BWT.20 BWT.19 BWT.18 BWT.17 BWT.16

Table 100: The BWTB3 Register

MSB LSB

– – – – BWT.27 BWT.26 BWT.25 BWT.24

Character Wait Time Registers (CWTB0): 0xFE1D  0x00, (CWTB1): 0xFE1C  0x00

These registers are used to hold the Character Wait Time(15: 0) (CWT) or I ni tial Waiting Time(15:0) (IWT)

depending on the situation. B oth the IWT and the CWT measure the tim e i n ETUs between the leading

edge of the start of t he current character receiv ed from the smart card and the leading edge of the st art of

the next character received from the smart card. The only difference is the mode in which the card is

operating. When T=1 these registers are used to configure t he CWT and these registers configure the IWT

when the ATR is being received. These registers should be l oaded prior to receiving characters from the

smart card. Firmware must manage which time is stored i n the register. If a timeout occurs, an interrupt is

generated to the firmware. The firmware can then take appropriate action.

Table 101: The CWTB0 Register

MSB LSB

CWT.7 CWT.6 CWT.5 CWT.4 CWT.3 CWT.1 CWT.2 CWT.0

Table 102: The CWTB1 Register

MSB LSB

CWT.15 CWT.14 CWT.13 CWT.12 CWT.11 CWT.10 CWT.9 CWT.8

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 101

ATR Timeout Regi s ter s (AT RL sB): 0 xF E20  0x00, (ATRMsB): 0xFE1F  0x00

These registers form the ATR timeout (A T RTO [15:0]) parameter. Time in ETU between t he l eadi ng

edge of the first character and leading edge of the last character of the ATR response. Tim er is enabl ed

when the RCVATR is set and starts when leading edge of the first start bit is received and disabled when

the RCVATR is cleared. An ATR t i m eout is generated if this time is exceeded.

Table 103: The ATRLsB Registe r

MSB LSB

ATRTO.7 ATRTO.6 ATRTO.5 ATRTO.4 ATRTO.3 ATRTO.1 ATRTO.2 ATRTO.0

Table 104: The ATRMsB Register

MSB LSB

ATRTO.15 ATRTO.14 ATRTO.13 ATRTO.12 ATRTO.11 ATRTO.10 ATRTO.9 ATRTO.8

TS Timeout Register (STSTO): 0xFE21  0x00

The TS timeout is the time in ETU between the de-assertion of smart card reset and the leading edge of

the TS character in the ATR (when DETTS is set ). T he timer is started when smart card reset is

de-asserted. An ATR timeout i s generat ed if this time is exceeded (MUTE card).

Table 105: The STSTO Register

MSB LSB

TST0.7 TST0.6 TST0.5 TST0.4 TST0.3 TST0.1 TST0.2 TST0.0

Reset Time Register (RLength): 0xFE22  0x70

Time in ETUs that the hardware delays the de-assertion of RST. If set to 0 and RSTCRD = 0, the hardware

adds no extra delay and the hardware will release RS T after VCCOK is asserted during power-up. If set to 1,

it will delay the release of RST by the time in this register. When the firmware sets the RSTCRD bit, the

hardware will assert reset (RST = 0 on pin). When firmware clears the bit, the hardware will release RST

after the delay specified in Rlen. If firmware sets the RSTCRD bit prior t o inst ruct ing the power to be applied

to the smart card, the hardware will not release RST after power-up until RLen after the firm ware clears the

RSTCRD bit. This prov ides a m eans to power up the smart card and hold it in reset until the firmware wants

to release the RST to the select ed smart card. Works with the selected smart card interface.

Table 106: The RLength Register

MSB LSB

RLen.7 RLen.6 RLen.5 RLen.4 RLen.3 RLen.1 RLen.2 RLen.0

73S1210F Data Sheet DS_1210F_001

102 Rev. 1.4

Shaded locations indicate functions t hat are not provided in the synchronous mode.

Table 107: Smart Card SFR Table

Name Address b7 b6 b5 b4 b3 b2 b1 b0

SCSel FE00 SelSC(1:0) BYPASS

SCInt FE01 WAITTO/

RLIEN CRDEVT VCCTMR RXDAVl TXEVNT TXSENT TXERR RXERR

SCIE FE02 WTOI/

RLIEN CDEVNT VTMREN RXDAEN TXEVEN TXSNTEN TXERR RXERR

VccCtl FE03 VCCSEL.1

VCCSEL.0 VDDFLT RDYST VCCOK SCPWRDN

VCCTmr FE04 OFFTMR(3:0) VCCTMR(3:0)

CRDCtl FE05 DEBOUN CDETEN DETPOL PUENB PDEN CARDIN

STXCtl FE06 I2CMODE TXFULL TXEMTY TXUNDR LASTTX TX/RXB BREAKD

STXData FE07 TXDATA(7:0)

SRXCtl FE08 BIT9DAT LASTRX CRCERR RXFULL RXEMTY RXOVRR PARITYE

SRXData FE09 RXDATA(7:0)

SCCtl FE0A RSTCRD IO IOD C8 C4 CLKLVL CLKOFF

SCECtl FE0B SIO SIOD SCLKLVL SCLKOFF

SCDIR FE0C C8D C4D

SPrtcol FE0D SCISYN MOD9/8B SCESYN 0 TMODE CRCEN CRCMS RCVATR

SCCLK FE0F ICLKFS(5:0)

SCECLK FE10 ECLKFS(5:0)

SParCtl FE11 DISPAR BRKGEN BRKDET RTRAN DISCRX INSPE FORCPE

SByteCtl FE12 DETTS DIRTS BRKDUR (1:0)

FDReg FE13 FVAL(3:0) DVAL (3:0)

CRCMsB FE14 CRC(15:8)

CRCLsB FE15 CRC(7:0)

BGT FE16 EGT8 BGT(4:0)

EGT FE17 EGT(7:0)

BWTB3 FE18 BWT(27:24)

BWTB2 FE19 BWT(23:16)

BWTB1 FE1A BWT(15:8)

BWTB0 FE1B BWT(7:0)

CWTB1 FE1C CWT(15:8)

CWTB0 FE1D CWT(7:0)

ATRMsB FE1F ATRTO(15:8)

ATRLsB FE20 ATRTO(7:0)

STSTO FE21 TSTO(7:0)

RLength FE22 RLen(7:0)

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 103

1.7.16 VDD Fault Detect Function

The 73S1210F contains a circuit to detect a low-vol tage condition on the supply voltage VDD. If enabled,

it will deactivate the active internal smart card interface when VDD falls below t he V DD Fault threshold. The

The user’s code may load a different v al ue using the FOVRVDDF bit = 1 after the power-up cycle has

completed.

VDDFault Control Register (VDDFCtl): 0xFFD4  0x00

Table 108: The VDDFCtl Register

MSB LSB

– FOVRVDDF VDDFLTEN – STXDAT.3 VDDFTH.2 VDDFTH.1 VDDFTH.0

Bit Symbol Function

VDDFCtl.7 –

VDDFCtl.6 FOVRVDDF S etting this bit high will allow t he V DDFLT(2: 0) bi ts set in this register to control

the VDDFault threshold. When thi s bit is set low, the VDDFault threshold will

be set to the factory default setting of 2.3V*.

VDDFCtl.5 VDDFLTEN Set = 1 will disable VDD Fault operation.

VDDFCtl.4 –

VDDFCtl.3 –

VDDFCtl.2 VDDFTH.2 V DD Faul t Threshold.

Bit Value(2:0) V DDFault Voltage

000 2.3 (nominal def aul t)

001 2.4

010 2.5

011 2.6

100 2.7

101 2.8

110 2.9

111 3.0

VDDFCtl.1 VDDFTH.1

VDDFCtl.0 VDDFTH.0

* Note: The VDD Fault factory default can be set to any threshold as defined by bits VDDFTH(2:0). The

73S1210F has the capability t o burn fuses at the factory to set t he factory default to any of these

voltages. Contact Teridian f or further details.

73S1210F Data Sheet DS_1210F_001

104 Rev. 1.4

2 Typical Application Schematic

SMARTCARD

SLOT #1

C5 0.1uF

12.000MHz

VDD

ON/CE

CLR

OPTIONAL LCD DISPLAY SYSTEM

16 CHARACTER BY 2 LINES

DOWN

30-SWITCH

KEYPAD

LCD

BRIGHTNESS

ADJUST

ON_OFF

SMARTCARD

SLOT #2

C19

0.1uF

C15

1uF

4.7uF

GND

VPC

PRES

I/O

NC 9

AUX2 10

AUX1 11

GND 12

CLK 13

RST 14

VCC 15

NC 16

VDDF_ADJ 17

SCL 18

SDA 19

VDD 20

GND 21

INT 22

XTALIN 23

XTALOUT 24

I/OUC

AUX1UC

AUX2UC

SAD0

SAD1

SAD2

73S8010R

L1 10uH

VDD

C16

27p

C18

1.0uF

C17

27p

+C4

10uF

C6 10uF

VDD 68

RESET 1

SEC 2

ISBR 3

SCL 5

SDA 6

N/C 7

N/C 8

GND 9

X12IN 10

X12OUT 11

COL0 12

COL1 13

COL2 14

ANAIN 15

COL3 16

RXD 17

TXD

COL4

USR7

ROW0

ROW1

USR6

ROW2

GND

N/C

VDD

USR5

USR4

USR3

USR2

ROW3

USR1

USR0

ROW4

ROW5

ERST

TCLK

VDD

TBUS3

GND

RXTX

TBUS2

SCLK

TBUS1

SIO

INT3

INT2

TBUS0

TEST

OFF_REQ 52

PRES 53

VP 54

CLK 55

GND 56

RST 57

VCC 58

C8/AUX2 59

C4/AUX1 60

I/O 61

VBUS 62

ON_OFF 63

VBAT 64

VPC 65

LIN 66

GND 67

SLUG 69

LED0 4

73S1210F

LED

C11

0.1uF

C10

0.47uF

22pF

C12

0.1uF

C13

0.1uF

C14

0.1uF

VDD

Host Serial RX

Host Serial TX

3VDD

DB0

GND

R/W*

DB7

14 DB6

13 DB5

12 DB4

11 DB3

10 DB2

9DB1

1 2

S11 SW

VDD

1 3

SW_MOM

USR2

USR4

USR1

USR5

USR0

USR3

USR6

Input Power Supply (2.7 - 6.5V)

VDD

27p

SW_MOM

1 3

SW_MOM

27p

20k

10k

1 3

SW_MOM

S12

SW_MOM

S17

SW_MOM

S22

SW_MOM

S27

SW_MOM

100

SW_MOM

S13

SW_MOM

S18

SW_MOM

S23

SW_MOM

1 3

S28

SW_MOM

5.0V Z ener

S14

SW_MOM

1 3

S19

SW_MOM

1 3

S24

SW_MOM

0.1uF

S29

SW_MOM

1 3

S15

SW_MOM

S20

SW_MOM

S25

SW_MOM

S30

SW_MOM

S16

SW_MOM

S10

SW_MOM

1 3

S21

SW_MOM

1 3

S26

SW_MOM

S31

SW_MOM

VCC

RST

CLK

GND

VPP

I/O

SW-1

SW-2

Smart C ard C onnec t or

22pF

ENTER

USR1

USR2

USR6

USR5

USR4

USR3

20k

R5 0

VCC

RST

CLK

GND

VPP

I/O

SW-1

SW-2

Smart C ard C onnec t or

VDD

USR0

3 B

RV1

10K

Figure 25: 73S1210F Typical Application Sch ematic

DS_7310F_001 73S1210F Data Sheet

Rev. 1.4 105

3 Electrical Specification

3.1 Absolute Maximum Ratings

Operation outside these rating lim i ts may cause permanent damage to the device. The smart card

interface pins are protected against short circuits t o VCC, ground, and each other.

Parameter

Rating

DC Supply voltage, VDD -0.5 to 4.0 VDC

Supply Voltage VPC -0.5 to 6.6 VDC

Supply Voltage VBUS -0.5 to 6.6 VDC

Supply Voltage VBAT -0.5 to 6.6 VDC

Storage Temperature -60 to 150°C

Pin Voltage (except card int erf ace) -0.3 to (VDD+0.5) VDC

Pin Voltage (card interface) -0.3 to (VCC+0.5) VDC

ESD tolerance (except card interface) +/- 2KV

ESD tolerance (card interface) +/- 7KV

Pin Current ± 200 mA

Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity ref erenced t o ground.

Note: Smart Card pins are protected agai nst short s bet ween any combinations of Smart Card pins.

3.2 Recommended Operating Conditions

Unless otherwise noted all specifications are valid ov er these temperatures and supply voltage ranges:

Parameter Rating

Supply Voltage VPC 2.7 to 6.5 VDC

Supply Voltage VBUS 4.4 to 5.5 VDC

Supply Voltage VBAT 4.0 t o 6.5 VDC

Ambient Operating Temperat ure (Ta) -40°C to +85°C

73S1210F Data Sheet DS_1210F_001

106 Rev. 1.4

3.3 Digital IO Characteristics

These requirements pertain to digital I/O pin types with consideration of the specific pin function and

configuration. The LED(1:0) pins have pull-ups that m ay be enabled. The Row pins have 100kΩ pull-

ups.

Symbol Parameter Conditions Min. Typ. Max. Unit

Voh Output level, high Ioh = -2mA 0.8 * VDD VDD V

OFF_REQ pin - IOH = -1mA VDD - 0.45 V

Vol Output level, low Iol = 2mA 0 0.3 V

OFF_REQ pin - Iol = 2mA 0.45 V

Vih Input voltage, high 2.7v < VDD <3.6v 1.8 VDD +0.3 V

Vil Input voltage, low 2.7v < VDD <3.6v -0.3 0.6 V

RESET, ON_OFF,PRES pins -0.3 0.8 V

Ileak Leakage current 0 < Vin < VDD

All output modes disabled,

pull-up/downs disabled

-5 5 µA

Ipu Pull-up current If provided and enabled,

Vout < 0.1v -5 µA

Ipd Pull-down current If provided and enabled,

Vout > VDD – 0.1v 5

µA

Symbol Parameter Conditions Min. Typ. Max. Unit

Iled LED drive current Vout = 1.3V,

2.7v < VDD < 3.6v 2

Iolkrow Keypad row output

low current 0.0v < Voh < 0.1v

when pull-up R is enabled 40 100 µA

Iolkcol Keypad column

output high current 0.0v < Voh < 0. 1v

when col. is pulled low 1.5 3 mA

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 107

3.4 Oscillator Interface Requirements

Symbol Parameter Condition Min Typ. Max Unit

High-Frequency Oscillator (Xin) Parameters. Xin I s Used As Input For External Clock For Test

Purposes Only. A Resistor Connecting x12in To x12out Is Required, Value = 1mΩ.

VILX12IN Input Low Voltage –

X12IN -0.3 1.5 0.3*VDD V

VIHX12IN Input High V ol tage – X12IN 0.7*VDD 1.6 Vdd+.0.3 V

IILXTAL Input Current -X12IN GND < Vin < Vdd -10 10 μA

Fxtal Crystal resonant

frequency Fundamental mode 6 12 MHz

3.5 DC Characteristics: Anal og I nput

Symbol Parameter Condition Min Typ. Max Unit

VTHTOL Voltage Threshold

Tolerance Selected Threshold

Value -3% +3% V

73S1210F Data Sheet DS_1210F_001

108 Rev. 1.4

3.6 Smart Card Interf ace Requi r em ent s

Symbol Parameter Condition Min Typ. Max Unit

Card Power Supply (VCC) Regulator

General conditions, -40

C < T < 85

C, 4.75V < VPC < 6.0V, 2.7V < VDD < 3.6V

VCC Card supply Voltage

including ripple and

noise

Inactive mode -0.1 0.1 V

Inactive mode, ICC = 1mA -0.1 0.4 V

Active mode; ICC <65mA ; 5V 4.65 5.25 V

Active mode; ICC < 65mA; 3V 2.85 3.15 V

Active mode; ICC < 40mA; 1.8V 1.68 1.92 V

Active mode; single pulse of

100mA for 2µs; 5V, fixed load =

25mA 4.6 5.25 V

Active mode; single pulse of

100mA for 2µs; 3V, fixed load =

25mA 2.76 3.15 V

Active mode; current pulses of

40nAs with peak |ICC | <200mA, t

<400ns; 5V 4.6 5.25 V

Active mode; current pulses of

40nAs with peak |ICC | <200mA,t

<400ns; 3V 2.7 3.15 V

Active mode; current pulses of

20nAs with peak |ICC | <100mA,t

<400ns; 1.8V 1.62 1.92 V

VCCrip VCC Ripple fRIPPLE = 20kHz – 200MHz 350 mV

ICCmax Card supply output

current

Static load current, VCC>1.65 40 mA

Static load current, VCC>4.6V or

2.7V as selected 65 mA

ICCF ICC fault current Class A, B (5V and 3V) 100 180 mA

Class C (1.8V) 60

130

Isc Maximum current

prior to shut-down

Load current limit prior to Vcc

shut-down 80 150 mA.

Load current limit prior to Vcc

shut-down for Vcc = 1.8V 60 130 mA

VSR Vcc slew rate , rise Rise rate on activate C = 0.47µF 0.12 .30 0.50 V/µs

VSF Vcc slew rate, fall Fall rate on deactivate, C = 0.47µF 0.15 .30 1.20 V/µs

Vrdy Vcc ready voltage

(VCCOK = 1)

5V operation, Vcc rising 4.6

3V operation, Vcc rising 2.75

1.8V operation, Vcc rising 1.65

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 109

Symbol Parameter Condition Min Typ. Max Unit

Interface Requirements – Data Signals: I/O, AUX1 and AUX2

VOH Output level, high IOH = 0 0.9 * VCC VCC+0.1 V

IOH = -40µA 0.75 VCC VCC+0.1 V

VOL Output level, low IOL = 1mA 0.15 *VCC V

VIH Input level, hi gh 0.6 * VCC VCC+0.30 V

VIL Input level, l ow -0.15 0.2 * VCC V

VINACT Output voltage when outside

of session IOL = 0 0.1 V

IOL = 1mA 0.3 V

ILEAK Input leakage VIH = VCC 10 µA

IIL Input current, low VIL = 0 0.65 mA

IIL Input current, low VIL = 0 0.7 mA

ISHORTL Short circuit output current For output low, shorted

to VCC through 33Ω 15 mA

ISHORTH Short circuit output current For output high,

shorted to ground

through 33Ω

15 mA

tR, tF Output rise time, fall times

For I/O, AUX1, AUX2,

CL = 80pF, 10% to

90%. For I/OUC,

AUX1UC, AUX2UC, CL

= 50Pf, 10% to 90% .

100 ns

tIR, tIF Input rise, fall times 1 µs

RPU Internal pull-up resistor Output stable for

>200ns 8 11 14 kΩ

FDMAX Maximum data rate 1 MHz

Reset and Clock for card interface, RST, CLK

VOH Output level, high IOH = -200µA 0.9 * VCC VCC V

VOL Output level, l ow IOL= 200µA 0 0.15 *VCC V

VINACT Output voltage when outside

of session IOL = 0 0.1 V

IOL = 1mA 0.3 V

IRST_LIM Output current limit , RST 30

ICLK_LIM Output current limit , CLK 70 mA

tR, tF Output rise time, fall time

CL = 35pF for CLK,

10% to 90% 8 ns

CL = 200pF for RST,

10% to 90% 100 ns

δ Duty cycle for CLK CL = 35pF, FCLK

≤ 20MHz, CLKIN duty

cycle is 48% to 52%. 45 55 %

73S1210F Data Sheet DS_1210F_001

110 Rev. 1.4

3.7 DC Characteristics

Symbol Parameter Condition Min Typ. Max Unit

IPC

Supply Current @ VPC = 2.7V

(VBUS and VBAT unconnected) CPU clock @ 24MHz 44 55 66 mA

CPU clock @ 12MHz 31 38 46 mA

CPU clock @ 6MHz 23 29 35 mA

CPU clock @ 3.69MHz 20 25 30 mA

Supply Current @ VPC = 3.3V

(VBUS and VBAT unconnected) CPU clock @ 24MHz 34 43 51 mA

CPU clock @ 12MHz 24 30 36 mA

CPU clock @ 6MHz 18 22 27 mA

CPU clock @ 3.69MHz 16 19 23 mA

Supply Current @ VPC = 5.0V

(VBUS and VBAT unconnected) CPU clock @ 24MHz 20 25 30 mA

CPU clock @ 12MHz 14 18 21 mA

CPU clock @ 6MHz 11 13 16 mA

CPU clock @ 3.69MHz 9 12 14 mA

IVBUS

Supply Current @ VVBUS = 4.4V CPU clock @ 24 MHz 16 20 24 mA

CPU clock @ 12MHz 11 14 17 mA

CPU clock @ 6MHz 8 10 13 mA

CPU clock @ 3.69MHz 7 9 11 mA

Supply Current @ VVBUS = 5.0V CPU clock @ 24MHz 16 19 23 mA

CPU clock @ 12MHz 11 14 17 mA

CPU clock @ 6MHz 8 10 13 mA

CPU clock @ 3.69MHz 7 9 11 mA

Supply Current @ VVBUS = 5.5V CPU clock @ 24MHz 16 20 23 mA

CPU clock @ 12MHz 11 14 17 mA

CPU clock @ 6MHz 8 11 13 mA

CPU clock @ 3.69MHz 7 9 11 mA

IVBAT

Supply Current @ VVBAT = 4.0V

(VBUS = 0V) CPU clock @ 24MHz 28 34 41 mA

CPU clock @ 12MHz 19 24 28 mA

CPU clock @ 6MHz 14 18 21 mA

CPU clock @ 3.69MHz 12 15 19 mA

Supply Current @ VVBAT = 5.0V

(VBUS = 0V) CPU clock @ 24MHz 20 26 31 mA

CPU clock @ 12MHz 14 18 21 mA

CPU clock @ 6MHz 11 13 16 mA

CPU clock @ 3.69MHz 9 12 14 mA

Supply Current @ VVBAT = 6.5V

(VBUS = 0V) CPU clock @ 24MHz 16 20 24 mA

CPU clock @ 12MHz 11 14 17 mA

CPU clock @ 6MHz 8 10 13 mA

CPU clock @ 3.69MHz 7 9 11 mA

VDD* VDD Supply Voltage

2.7V < VPC < 6.5V,

IVDD < 40mA. 3.0 3.3 3.6 V

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 111

IDD_IN Supply Current – pins 28 + 40

(internal consumption – digital

core)

CPU clock @ 24MHz 29 33.5 mA

CPU clock @ 12MHz 21 24 mA

CPU clock @ 6MHz 15.5 18 mA

CPU clock @ 3.69MHz 13.5 15.5 mA

Power down

(-40° to 85°C) 8 50 µA

Power down (25°C) 6 15 µA

IDD_OUT Supply Current – pin 68

(available to external circuit ry ) Circuit ON 20 mA

IVBUS Supply Current from VBUS VCC off, IDDINTERNAL <

20µA 0.2 0.4 mA

IVBAT

IVPC Supply Current from VBAT or

VPC Circuit OFF 0.01 1 µA

VBUSON VBUS detection threshold 3.5 V

VBUSIDIS VBUS discharge current 50 μA

External Capacitor Values

CVPC External filter capacit or for VPC 8.0 10.0 12.0 µF

CVP External filter capacit or for VP 2.0 4.7 10.0 µF

CVDD* External filter capacitors for VDD 0.2 1.0 µF

CVCC External filter capacit or for VCC CVCC should be ceramic

with low ESR

(<100MΩ). 0.2 0.47 1.0 µF

*Note: Recommend on 0.1µF f or each VDD pin.

3.8 Current Fault Detection Circuits

Symbol Parameter Condition Min Typ. Max Unit

IVPmax VP over current fault 150 mA

IDDmax VDD over-current limit 40 100 mA

ICCF Card overcurrent fault 80 150 mA

ICCF1P8 Card overcurrent fault VCC = 1.8V 60 130 mA

73S1210F Data Sheet DS_1210F_001

112 Rev. 1.4

4 Equivalent Circuits

VDD

X12LIN X12OUT

ENABLE

TTL

circuit

ESD

Figure 26: 12 MHz Oscillator Circuit

VDD

X32LIN

X32OUT

ENABLEb

TTL

circuit

>1MEG

ESD

Figure 27: 32KHz Oscillator Circui t

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 113

VDD

STRONG

PFET

STRONG

NFET

Data

From

circuit

TTL

circuit

Output

Disable

ESD

Figure 28: Digital I/O Circuit

VDD

STRONG

PFET

STRONG

NFET

Data

From

circuit

Output

Disable

ESD

Figure 29: Digital Output Circuit

73S1210F Data Sheet DS_1210F_001

114 Rev. 1.4

VDD

STRONG

PFET

STRONG

NFET

Data

From

circuit

TTL

circuit

Output

Disable

Pull-up

Disable VERY

WEAK

PFET

ESD

Figure 30: Digital I/O with Pull Up Circuit

VDD

STRONG

PFET

STRONG

NFET

Data

From

circuit

TTL

circuit

Output

Disable

VERY

WEAK

NFET

Pull-down

Enable

ESD

Figure 31: Digital I/O with Pull Down Circuit

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 115

TTL

circuit

ESD

Figure 32: Digital Input Circuit

VDD

STRONG

PFET

STRONG

NFET

Data

From

circuit

TTL

circuit

Output

Disable

Pull-up

Disable

ESD

VERY

WEAK

PFET

VERY

WEAK

NFET

Pull-down

Enable

ESD

Figure 33: OFF_REQ Interface Circui t

VDD

STRONG

PFET

STRONG

NFET

Data

From

circuit

TTL

circuit

Output

Disable

Pull-up

Disable

100k

OHM

ESD

Figure 34: Keypad Row Circuit

73S1210F Data Sheet DS_1210F_001

116 Rev. 1.4

VDD

MEDIUM

PFET

STRONG

NFET

Data

From

circuit

TTL

circuit

Output

Disable

ESD

1200

OHMS

Figure 35: Keypad Column Circui t

VDD

STRONG

PFET

STRONG

NFET

Data

From

circuit

TTL

circuit

Pullup

Disable

0, 2, 4,

10mA

Current Value

Control

ESD

Figure 36: LED Circuit

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 117

Vih>0.7*VDD

To Circuit

Logic

R= 20kΩ

This buffer has a

special input

threshold:

ESD

Figure 37: Test and Security Pi n Circui t

Comparator

Input

ESD

Figure 38: Analog Input Circuit

VCC

STRONG

PFET

STRONG

NFET

From

circuit

ESD

Figure 39: Smart Card Output Circuit

73S1210F Data Sheet DS_1210F_001

118 Rev. 1.4

125ns

DELAY

VCC

STRONG

PFET

STRONG

NFET

RL=11K

From

circuit

CMOS

circuit

ESD

Figure 40: Smart Card I/O Circuit

TTL

circuit

VERY

WEAK

NFET

Pull-down

Enable

ESD

VDD

Figure 41: PRES Input Circuit

VDD

TTL

circuit

Pull-up

Disable

ESD

VERY

WEAK

PFET

Pull-down

Enable

ESD

Figure 42: PRESB Input Circuit

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 119

To Circuit

Logic

R= 24kΩ

ESD

VPC

Figure 43: ON_OFF Input Circuit

73S1210F Data Sheet DS_1210F_001

120 Rev. 1.4

5 Package Pin Designation

5.1 68-pin QFN Pinout

Figure 44: 73S1210F 68 QFN Pinou t

CAUTION: Use handling procedures necessary

for a static sensitive component

TERIDIAN

73S1210F

COL4

USR1

ROW3

USR3

USR4

USR5

VDD

N/C

GND

ROW2

USR6

ROW1

ROW0

USR7

TBUS0

TEST

VBUS

CLK

GND

RST

VCC

AUX2

AUX1

PRES

ON_OFF

VBAT

LIN

GND

VDD

SEC

SCL

SDA

N/C

GND

XI2IN

X12OUT

COL0

COL1

COL2

ANA_IN

COL3

RXD

TXD

INT3

SIO

TBUS1

SCLK

TBUS2

RXTX

GND

TBUS3

VDD

TCLK

ERST

ROW5

ROW4

USR0

ISBR

RESET

USR2

INT2

OFF_REQ

VPC

LED0

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 121

5.2 44-pin QFN Pinout

TERIDIAN

73S1210F

USR1

USR2

USR3

USR4

USR5

VDD

GND

USR6

USR7

TEST

VPC

PRES

CLK

GND

RST

VCC

AUX2

AUX1

ON_OFF

LIN

LED0

SCL

SDA

GND

XI2IN

X12OUT

RXD

TXD

SIO

SCLK

RXTX

VDD

ERST

USR0

VDD

INT3

TCLK

RESET

GNDGND

INT2

OFF_REQ

Figure 45: 73S1210F 44 QFN Pinou t

CAUTION: Use handling procedures necessary

for a static sensitive component.

73S1210F Data Sheet DS_1210F_001

122 Rev. 1.4

6 Packaging Informa tion

6.1 68-Pin QFN Package Outline

Notes: 6.3mm x 6.3mm exposed pad area must remain UNCONNECTED (clear of PCB traces or vias).

Controlling dimensions are in mm.

TOP VIEW

SEATING

PLANE

12°

SIDE VIEW

8.00

7.75

8.00

7.75

0.00/0.05

0.2

0.85

0.65

TERMINAL TIP

FOR ODD TERMINAL/SIDE

C C

0.40

SCALE: NONE

SECTION "C-C"

0.20

0.15/0.25

0.00/0.05

BOTTOM VIEW

PIN#1 ID

R0.20

0.45

8.00

6.30

6.15/6.45

0.42

0.24/0.60

0.42

0.24/0.60

6.40

6.30

6.15/6.45

Figure 46: 73S1210F 68 QFN Mechani cal Drawing

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 123

6.2 44-Pin QFN Package Outline

Notes: 5.1mm x 5.1mm exposed pad area must remain UNCONNECTED (clear of PCB traces or

vias). Controlling dimensions are in mm.

TOP VIEW

SEATING

PLANE

12°

SIDE VIEW

7.00

6.75

7.00

6.75

0.00/0.05

0.2

0.85

0.65

TERMINAL TIP

FOR ODD TERMINAL/SIDE

C C

0.50

SCALE: NONE

SECTION "C-C"

0.23

0.18/0.30

0.00/0.05

BOTTOM VIEW

PIN#1 ID

R0.20

0.45

7.00

5.10

4.95/5.25

0.42

0.24/0.60

0.42

0.24/0.60

5.00

5.10

4.95/5.25

Figure 47: 73S1210F 44 QFN Package Drawing

73S1210F Data Sheet DS_1210F_001

124 Rev. 1.4

7 Ordering Information

Table 109 lists the order numbers and packaging marks used to identi fy 73S1210F products.

Table 109: Order Numbers and Packaging Marks

Part Description Order Number Packaging Mark

73S1210F 68-Pin QFN, Lead Free

73S1210F 68-Pin QFN, Lead Free with Programming 73S1210F-68IM/F

73S1210F-68IM/F/P 73S1210F68IM

73S1210F68IM

73S1210F 68-Pin QFN, Lead Free, Tape and Reel

73S1210F 68-Pin QFN, Lead Free, Tape and Reel with Programming 73S1210F-68IMR/F

73S1210F-68IMR/F/P 73S1210F68IM

73S1210F68IM

73S1210F 44-Pin QFN, Lead Free

73S1210F 44-Pin QFN, Lead Free with Programming 73S1210F-44IM/F

73S1210F-44IM/F/P 73S1210F44IM

73S1210F44IM

73S1210F 44-Pin QFN, Lead Free, Tape and Reel

73S1210F 44-Pin QFN, Lead Free, Tape and Reel with Programming 73S1210F-44IMR/F

73S1210F-44IMR/F/P 73S1210F44IM

73S1210F44IM

8 Related Documentation

The following 73S1210F documents are avai l able f rom T eridi an Semiconductor Corporation:

73S1210F Data Sheet (this document )

73S1210F Development Board Quick St art Gui de

73S1210F Software Development Kit Quick Start Guide

73S1210F Evaluation Board User’s Guide

73S12xxF Software User’s Guide

73S12xxF Synchronous Card Design Application Note

9 Contact Information

For more information about Teridi an Semiconductor products or to check the availability of the 73S1210F,

6440 Oak Canyon Road

Suite 100

Irvine, CA 92618-5201

Telephone: (714) 508-8800

FAX: (714) 508-8878

Email: scr.support@teridian.com

For a complete list of worldwide sales off i ces, go to http://www.teridian.com.

DS_1210F_001 73S1210F Data Sheet

Rev. 1.4 125

Revision History

Revision Date Description

1.0 5/10/2007 First publication.

1.1 11/6/2007 In Table 1, added Equivalent Circuit references.

In Section 1.4, updated program security description to remove pre-boot

and 32-cycle references.

In Section 1.7.1, changed “Mcount is configured i n the MCLKCtl register

must be bound between a value of 1 to 7. The possible crystal or external

clock are shown in Table 12.“ to “Mcount is configured in t he M CLK Ct l

external clock frequencies for getting M CLK = 96M Hz are shown in Table

11.”

In the BRCON description, changed “If BSEL = 1, the baud rate is derived

using timer 1.” to “If BSEL = 0, the baud rate is derived using timer 1.”

In Section 1.7.14, remov ed the following from the emulator port

description: “The signals of the emulat or port have weak pull-ups. Adding

resistor footprints for signals E_RST, E_TCLK and E_RXTX on the PCB is

recommended. If necessary, adding 10KΩ pull-up resistors on E_TCLK

and E_RXTX and a 3KΩ on E _RST wil l hel p the emulator operate

normally if a problem arises.”

In Ordering Information, removed the leaded part numbers.

1.2 12/15/2008

In Table 1, added the “Pin (44 QFN)” column.

In Table 1, added more description to t he SCL, SDA, PRES, VCC, VPC,

SEC, TEST and VDD pins.

In Section 1.3.2, changed “FLSH_E RA S E” to “ERASE” and

“FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes

the page address for page erase. The page size is 512 (200h) bytes and

there are 128 pages within the flash memory. The PGADDR denotes the

upper seven bits of the flash mem ory address such that bit 7:1 of the

PGADDR corresponds to bit 15:9 of the flash memory address. Bit 0 of

the PGADDR is not used and is ignored.” In the description of the

PGADDR register, added “Note: the page address is shift ed l eft by one bit

(see detailed description above).”

In Table 5, changed “FLSHCRL” to “FLSHCTL”.

In Table 5, removed the P RE B O OT bi t description.

In Table 5, moved the TRI M PCtl bit description to FUSECtl and m oved the

FUSECtl bit description to TRIMPCtl.

In Table 6, changed “PGADR” to “PGADDR”.

In Table 7, added PGADDR.

In Table 8, changed the reset value f or RTCCtl from “0x81” to “0x00”.

Added the RTCTrim0 and ACOMP regist ers. Deleted the OMP, VRCtl,

LEDCal and LOCKCtl registers.

In Table 7, removed the Mcount 7 row.

In Table 50 through Table 53, changed t he nam es of regist ers USRI ntCtl0

through USRIntCtl3 to USRI ntCtl1 through USRIntCtl4.

In TCON, corrected the descriptions for TCON.2 and TCON.0.

In Section 1.7.9, added a note about USR pins defaulting as inputs after

reset.

Changed the register address for ATRMsB from FE21 to FE1F.

73S1210F Data Sheet DS_1210F_001

126 Rev. 1.4

In Section 1.7.15.5, del eted “The ETU clock is held in reset condition until

the activation sequence begins (either by VCCOK=1 or VCCTMR timeout)

and will go high ½ the ETU period t hereaf ter.”

In Section 1.7.15.5, added “S ynchronous card operation is broken down

into three primary ty pes. These are comm only referred to as 2-wire,

3-wire and I2C synchronous cards. Each card type requires different

control and timing and therefore requires different algorithms to access.

Teridian has created an application note to provide detailed algorithms for

each card type. Refer to the applicat i on note titled 73S12xxF

Synchronous Card Design Application Note.”

In Table 78 and Table 107, changed t he S YCKST bit to I2CMODE.

In Figure 25, replaced the schematic with a new schemat i c.

In Section 3.4, changed the Fx tal Min from 4 to 6.

Added 44-pin QFN package.

Added Section 8, Related Documentation.

Added Section 9, Contact Information.

Formatted the document per new standard. Added section numbering.

1.3 1/22/2009 Changed the value for the IDD_IN Power Down (25°C) parameter from 13

µA to 15 µA.

1.4 5/12/2009 In Table 1, corrected t he 44 Q FN G ND pin from 37 to 26.

Added the “with Programming” ordering numbers to Table 109.

Teridian Semiconductor Corporation is a registered trademark of Teridi an S em i conductor Corporati on.

Windows is a registered trademark of Microsoft Corporation.

Signum Systems is a trademark of S i gnum S ystems Corporation.

All other trademarks are the property of their respective owners.

Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly

contained in the Company’s warranty det ai l ed in the Teridian Semiconductor Corporation standard Terms

and Conditions. The company assumes no responsibility for any errors which may appear in this

document, reserves the right to change dev i ces or specifi cat ions detailed herein at any time without

notice and does not make any commitm ent to update the information cont ai ned herein. Accordingly, the

reader is cautioned to verify that this document is current by comparing it to the latest version on

http://www.teri dian.com or by checking with your sales representative.

Teridian Semiconductor Corp., 6440 Oak Canyon, S ui te 100, Irvine, CA 92618

TEL (714) 508-8800, FAX (714) 508-8877, ht tp://www.teridian.com

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Maxim Integrated:

73S1210F-44IM/F 73S1210F-44IMR/F 73S1210F-68IM/F 73S1210F-68IMR/F 73S1210F-44M/F/PC 73S1210F-

44MR/F/PC 73S1210F-68M/F/PG 73S1210F-68M/F/PH 73S1210F-68MR/F/PG 73S1210F-68MR/F/PH 73S1210F-

44IMR/F/P 73S1210F-44IM/F/P 73S1210F-IM68 DK 73S1210F-IM68 EB 73S1210F-68MR/F/PJ 73S1210F-68M/F/PJ