ISP1561BMUM - ST-Ericsson Inc

34.807IRELESS

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34.807IRELESS

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1. General description

The ISP1561 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal

Serial Bus (USB) Host Controller. It integrates two Original USB Open Host Controller

Interface (OHCI) cores, one Hi-Speed USB Enhanced Host Controller Interface (EHCI)

core, and four transceivers that are compliant with Hi-Speed USB and Original USB. The

functional parts of the ISP1561 are fully compliant with Ref. 8 “Universal Serial Bus

Speciﬁcation”,Ref. 4 “Open Host Controller Interface Speciﬁcation for USB”,Ref. 2

“Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus”,Ref. 6 “PCI

Local Bus Speciﬁcation”, and Ref. 5 “PCI Bus Power Management Interface

Speciﬁcation”.

Integrated high performance USB transceivers allow the ISP1561 to handle all Hi-Speed

USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed

(1.5 Mbit/s). The ISP1561 provides four downstream ports, allowing simultaneous

connection of USB devices at different speeds.

The ISP1561 provides three downstream port status indicators, GoodLink along with

green and amber LEDs, to allow user-rich messages of the root hub downstream ports

status, without requiring detailed port information to be reﬂected in internal registers.

The ISP1561 is fully compatible with various operating system drivers, such as Microsoft

Windows standard OHCI and EHCI drivers that are present in Windows 98 Second

Edition (SE), Windows Millennium Edition (Me), Windows XP and Windows 2000.

The ISP1561 directly interfaces to any 32-bit, 33 MHz PCI bus. It has 5 V tolerant PCI pins

that can source 3.3 V. The PCI interface fully complies with Ref. 6 “PCI Local Bus

Speciﬁcation”.

The ISP1561 is ideally suited for use in Hi-Speed USB host-enabled motherboards,

Hi-Speed USB host PCI add-on card applications, mobile applications, and embedded

solutions.

To facilitate motherboard development, the ISP1561 can use the available 48 MHz clock

signal to reduce the total cost of a solution. To reduce the ElectroMagnetic Interference

(EMI), however, it is recommended that the 12 MHz clock is used in PCI add-on card

designs.

ISP1561

Hi-Speed Universal Serial Bus PCI Host Controller

Rev. 02 — 5 March 2007 Product data sheet

Product data sheet Rev. 02 — 5 March 2007 2 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

2. Features

nComplies with Ref. 8 “Universal Serial Bus Speciﬁcation”

nSupports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and

low-speed (1.5 Mbit/s)

nTwo Original USB OHCI cores are compliant with Ref. 4 “Open Host Controller

Interface Speciﬁcation for USB”

nOne Hi-Speed USB EHCI core is compliant with Ref. 2 “Enhanced Host Controller

Interface Speciﬁcation for Universal Serial Bus”

nSupports PCI 32-bit, 33 MHz interface compliant with Ref. 6 “PCI Local Bus

Speciﬁcation”, with support for D3cold standby and wake-up modes; all I/O pins are

3.3 V standard, but 5 V tolerant

nCompliant with Ref. 5 “PCI Bus Power Management Interface Speciﬁcation” for all

hosts (EHCI and OHCI), and supports all power states: D0, D1, D2, D3hot and D3cold

nFour downstream ports with support for three types of downstream port indicator

LEDs: GoodLink, amber and green LEDs

nCLKRUN support for mobile applications, such as internal notebook design

nConﬁgurable subsystem ID and subsystem vendor ID through external EEPROM

nConﬁgurable two or four port root hub

nDigital and analog power separation

nSupports hot Plug and Play and remote wake-up of peripherals

nSupports individual power switching and individual overcurrent protection for

downstream ports

nSupports partial dynamic port-routing capability for downstream ports that allows

sharing of the same physical downstream ports between the Original USB Host

Controller and the Hi-Speed USB Host Controller

nSupports legacy PS/2 keyboards and mice

nUses 12 MHz crystal oscillator to reduce system cost and EMI emissions

nOperates at +3.3 V power supply input

nFull industrial operating temperature range from −40 °C to +85 °C

nFull-scan design with high fault coverage (93 % to 95 %) ensures high quality

nLQFP128 package available

3. Applications

nPC motherboard

nNotebook

nPCI add-on card

nSet-Top Box (STB)

nWeb appliance

Product data sheet Rev. 02 — 5 March 2007 3 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

4. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

ISP1561BM LQFP128 plastic low proﬁle quad ﬂat package; 128 leads; body 14 × 14 × 1.4 mm SOT420-1

xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx

xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx

xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

Product data sheet Rev. 02 — 5 March 2007 4 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

5. Block diagram

Fig 1. Block diagram

19 123

92 95 91 90 102 103

ISP1561BM

PCI-bus

XTAL1

XTAL2

RAM

OHCI (FUNCTION 0)

RAM

OHCI (FUNCTION 1)

RAM

EHCI (FUNCTION 2)

ORIGINAL

ATX Hi-SPEED

ATX

ATX1

CONFIGURATION SPACE

PCI CORE

PCI MASTER

PCI SLAVE

CONFIGURATION FUNCTION 0

CONFIGURATION FUNCTION 1

CONFIGURATION FUNCTION 2

XOSC

POR

VDD_DETECT

AD[31:0]

C/BE#[3:0]

REQ#

GNT#

IDSEL

INTA#

FRAME#

DEVSEL#

IRDY#

CLKRUN#

PAR

PERR#

SERR#

TRDY#

STOP#

RST#

GLOBAL CONTROL

PORT ROUTER

SMI# SEL48M SCL SDA

VDD

OC1

AMB1

GRN1

GL1

PWE1 DM1 DP1

OC2

AMB2

GRN2

GL2

PWE2 DM2DP2

OC3

AMB3

GRN3

GL3

PWE3

OC4

AMB4

GRN4

GL4

PWE4

DM3 DP3 DM4 DP4

IRQ1

IRQ12

KBIRQ1

MUIRQ12

A20OUT

legacy keyboard and mouse support

SEL2

PORTS

AVAUX_PLL

AVAUX

VAUX

RREF

CORERESET

96 99 100 98 97 109 110

ORIGINAL

ATX Hi-SPEED

ATX

ATX2

105 113 114 112 106 116 117

ORIGINAL

ATX Hi-SPEED

ATX

ATX3

119

107

101

126127 125 120 122 123

ORIGINAL

ATX Hi-SPEED

ATX

ATX4

PME#

CLK

004aaa156

GND_

RREF

AGND

5, 85

DGND

6, 14, 21, 29, 37, 45, 53,

61, 69, 76, 83, 86, 128

10, 17, 25, 33, 41,

49, 57, 65, 73, 80

23, 24, 26, 27, 28, 30, 31, 32,

36, 38, 39, 40, 42, 43, 44, 46,

62, 63, 64, 66, 67, 68, 70, 71,

74, 75, 77, 78, 79, 81, 82, 84

34, 47, 60, 72

93, 108, 115, 121

104, 111,

118, 124

Product data sheet Rev. 02 — 5 March 2007 5 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin conﬁguration

ISP1561BM

128

004aaa931

Table 2. Pin description

Symbol[1] Pin Type Description

SEL48M 1 I selection between 12 MHz crystal and 48 MHz oscillator

0 — 12 MHz crystal is used

1 — 48 MHz oscillator is used

push-pull; TTL with hysteresis; 5 V tolerant

SCL 2 O I2C-bus clock (open-drain)[2]

SDA 3 I/O I2C-bus data (open-drain)[2]

PME# 4 O PCI power management event; used by a device to request a

change in the device or system power state

push-pull, open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

VAUX 5 - auxiliary voltage (3.3 V)

DGND 6 - digital ground

IRQ1 7 O system keyboard interrupt

push-pull; open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

IRQ12 8 O system mouse interrupt

push-pull; open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

SEL2PORTS 9 I active downstream port selection

0 — all the four ports are active

1 — only port 1 and port 2 are active; port 3 and port 4 are

inactive

push-pull; TTL with hysteresis; 5 V tolerant

VDD 10 - supply voltage (3.3 V)

Product data sheet Rev. 02 — 5 March 2007 6 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

A20OUT 11 O legacy gate 20 output

push-pull; open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

KBIRQ1 12 I legacy keyboard interrupt input

push-pull; TTL with hysteresis; 5 V tolerant[3]

MUIRQ12 13 I legacy mouse interrupt input

push-pull; TTL with hysteresis; 5 V tolerant[3]

DGND 14 - digital ground

SMI# 15 O system management interrupt

open-drain; push-pull; 10 ns slew rate control; CMOS; 5 V

tolerant

INTA# 16 O PCI interrupt

push-pull, open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

VDD 17 - supply voltage (3.3 V)

RST# 18 I PCI reset; used to bring PCI-speciﬁc registers, sequencers and

signals to a consistent state

push-pull; TTL with hysteresis; 5 V tolerant

CLK 19 I PCI system clock (33 MHz)

GNT# 20 I PCI grant; indicates to the agent that access to the bus has been

granted

DGND 21 - digital ground

REQ# 22 O PCI request; indicates to the arbitrator that the agent wants to

use the bus

AD[31] 23 I/O bit 31 of multiplexed PCI address and data

AD[30] 24 I/O bit 30 of multiplexed PCI address and data

VDD 25 - supply voltage (3.3 V)

AD[29] 26 I/O bit 29 of multiplexed PCI address and data

AD[28] 27 I/O bit 28 of multiplexed PCI address and data

AD[27] 28 I/O bit 27 of multiplexed PCI address and data

DGND 29 - digital ground

AD[26] 30 I/O bit 26 of multiplexed PCI address and data

AD[25] 31 I/O bit 25 of multiplexed PCI address and data

AD[24] 32 I/O bit 24 of multiplexed PCI address and data

VDD 33 - supply voltage (3.3 V)

C/BE#[3] 34 I/O byte 3 of multiplexed PCI bus command and byte enable

IDSEL 35 I PCI initialization device select; used as a chip select during

conﬁguration read and write transactions

AD[23] 36 I/O bit 23 of multiplexed PCI address and data

DGND 37 - digital ground

AD[22] 38 I/O bit 22 of multiplexed PCI address and data

AD[21] 39 I/O bit 21 of multiplexed PCI address and data

AD[20] 40 I/O bit 20 of multiplexed PCI address and data

Table 2. Pin description

…continued

Symbol[1] Pin Type Description

Product data sheet Rev. 02 — 5 March 2007 7 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

VDD 41 - supply voltage (3.3 V)

AD[19] 42 I/O bit 19 of multiplexed PCI address and data

AD[18] 43 I/O bit 18 of multiplexed PCI address and data

AD[17] 44 I/O bit 17 of multiplexed PCI address and data

DGND 45 - digital ground

AD[16] 46 I/O bit 16 of multiplexed PCI address and data

C/BE#[2] 47 I/O byte 2 of multiplexed PCI bus command and byte enable

FRAME# 48 I/O PCI cycle frame; driven by the master to indicate the beginning

and duration of an access

VDD 49 - supply voltage (3.3 V)

IRDY# 50 I/O PCI initiator ready; indicates ability of the initiating agent to

complete the current data phase of a transaction

TRDY# 51 I/O PCI target ready; indicates ability of the target agent to complete

the current data phase of a transaction

DEVSEL# 52 I/O PCI device select; indicates if any device has been selected on

the bus

DGND 53 - digital ground

STOP# 54 I/O PCI stop; indicates that the current target is requesting the

master to stop the current transaction

CLKRUN# 55 I/O PCI CLKRUN signal

push-pull input; 3-state output; 5 ns slew rate control; TTL with

hysteresis; 5 V tolerant

PERR# 56 I/O PCI parity error; used to report data parity errors during all PCI

transactions, except a special cycle

VDD 57 - supply voltage (3.3 V)

SERR# 58 O PCI system error; used to report address parity errors, data parity

errors on the Special Cycle command, or any other system error

where the result will be catastrophic

push-pull; open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

PAR 59 I/O PCI parity

C/BE#[1] 60 I/O byte 1 of multiplexed PCI bus command and byte enable

DGND 61 - digital ground

AD[15] 62 I/O bit 15 of multiplexed PCI address and data

AD[14] 63 I/O bit 14 of multiplexed PCI address and data

AD[13] 64 I/O bit 13 of multiplexed PCI address and data

VDD 65 - supply voltage (3.3 V)

AD[12] 66 I/O bit 12 of multiplexed PCI address and data

AD[11] 67 I/O bit 11 of multiplexed PCI address and data

AD[10] 68 I/O bit 10 of multiplexed PCI address and data

DGND 69 - digital ground

AD[9] 70 I/O bit 9 of multiplexed PCI address and data

AD[8] 71 I/O bit 8 of multiplexed PCI address and data

C/BE#[0] 72 I/O byte 0 of multiplexed PCI bus command and byte enable

Table 2. Pin description

…continued

Symbol[1] Pin Type Description

Product data sheet Rev. 02 — 5 March 2007 8 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

VDD 73 - supply voltage (3.3 V)

AD[7] 74 I/O bit 7 of multiplexed PCI address and data

AD[6] 75 I/O bit 6 of multiplexed PCI address and data

DGND 76 - digital ground

AD[5] 77 I/O bit 5 of multiplexed PCI address and data

AD[4] 78 I/O bit 4 of multiplexed PCI address and data

AD[3] 79 I/O bit 3 of multiplexed PCI address and data

VDD 80 - supply voltage (3.3 V)

AD[2] 81 I/O bit 2 of multiplexed PCI address and data

AD[1] 82 I/O bit 1 of multiplexed PCI address and data

DGND 83 - digital ground

AD[0] 84 I/O bit 0 of multiplexed PCI address and data

VAUX 85 - auxiliary voltage (3.3 V)

DGND 86 - digital ground

XTAL1 87 I crystal input; directly connected to a 12 MHz crystal; when this

pin is connected to an external 48 MHz oscillator source,

pin XTAL2 must be left open

Remark: This pin works in conjunction with pin SEL48M.

XTAL2 88 O crystal output; directly connected to a 12 MHz crystal; when

XTAL1 is connected to an external 48 MHz oscillator source, this

pin must be left open

Remark: This pin works in conjunction with pin SEL48M.

OC1 89 I overcurrent sense input for the USB downstream port 1 (digital)

push-pull; TTL with hysteresis; 5 V tolerant

PWE1 90 O power enable for USB downstream port 1 (open-drain)

10 ns slew rate control; TTL; 5 V tolerant

GL1 91 O GoodLink LED indicator output for USB downstream port 1

(open-drain); the LED is off by default, blinks on at USB trafﬁc

10 ns slew rate control; TTL; 5 V tolerant

AMB1 92 O amber LED indicator output for USB downstream port 1

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

AVAUX 93 - analog auxiliary voltage (3.3 V); supply voltage

GND_RREF 94 - reference ground; RREF resistor must be connected to this pin

GRN1 95 O green LED indicator output for USB downstream port 1

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

OC2 96 I overcurrent sense input for USB downstream port 2 (digital)

push-pull; TTL with hysteresis; 5 V tolerant

PWE2 97 O power enable for USB downstream port 2 (open-drain)

10 ns slew rate control; TTL; 5 V tolerant

Table 2. Pin description

…continued

Symbol[1] Pin Type Description

Product data sheet Rev. 02 — 5 March 2007 9 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

GL2 98 O GoodLink LED indicator output for USB downstream port 2

(open-drain); the LED is off by default, blinks on at USB trafﬁc

10 ns slew rate control; TTL; 5 V tolerant

AMB2 99 O amber LED indicator output for USB downstream port 2

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

GRN2 100 O green LED indicator output for USB downstream port 2

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

AVAUX_PLL 101 - analog auxiliary voltage (3.3 V); supply voltage for PLL

DM1 102 AI/O D−; analog connection for USB downstream port 1

DP1 103 AI/O D+; analog connection for USB downstream port 1

AGND 104 - analog ground

OC3 105 I overcurrent sense input for USB downstream port 3 (digital)

push-pull; TTL with hysteresis; 5 V tolerant

PWE3 106 O power enable for USB downstream port 3 (open-drain)

10 ns slew rate control; TTL; 5 V tolerant

RREF 107 AI/O analog connection for the external resistor (12 kΩ± 1%)

AVAUX 108 - analog auxiliary voltage (3.3 V); supply voltage

DM2 109 AI/O D−; analog connection for USB downstream port 2

DP2 110 AI/O D+; analog connection for USB downstream port 2

AGND 111 - analog ground

GL3 112 O GoodLink LED indicator output for USB downstream port 3

(open-drain); the LED is off by default, blinks on at USB trafﬁc

10 ns slew rate control; TTL; 5 V tolerant

AMB3 113 I/O amber LED indicator output for USB downstream port 3

(open-drain); the LED is off by default and can be programmed to

enable it to blink; input as port indicator enable during reset; by

default, pull up is enabled; if no LEDs are used, then connect this

pin to ground, that is, no port indicator support

bidirectional pin; push-pull input; 3-state output; 10 ns slew rate

control; TTL; 5 V tolerant

GRN3 114 O green LED indicator output for USB downstream port 3

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

AVAUX 115 - analog auxiliary voltage (3.3 V); supply voltage

DM3 116 AI/O D−; analog connection for USB downstream port 3

DP3 117 AI/O D+; analog connection for USB downstream port 3

AGND 118 - analog ground

OC4 119 I overcurrent sense input for USB downstream port 4 (digital)

push-pull; TTL with hysteresis; 5 V tolerant

Table 2. Pin description

…continued

Symbol[1] Pin Type Description

Product data sheet Rev. 02 — 5 March 2007 10 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

[1] Symbol names ending with a ‘#’ (for example, NAME#) represent active LOW signals for PCI pins. Symbol

names with an overscore (for example, NAME) represent active LOW signals for USB pins.

[2] The pull-up resistor must always be present even if I2C EEPROM is not used.

[3] If legacy support is not used, connect this pin to ground.

PWE4 120 O power enable for USB downstream port 4 (open-drain)

10 ns slew rate control; TTL; 5 V tolerant

AVAUX 121 - analog auxiliary voltage (3.3 V); supply voltage

DM4 122 AI/O D−; analog connection for USB downstream port 4

DP4 123 AI/O D+; analog connection for USB downstream port 4

AGND 124 - analog ground

GL4 125 O GoodLink LED indicator output for USB downstream port 4

(open-drain); the LED is off by default, blinks on at USB trafﬁc

10 ns slew rate control; TTL; 5 V tolerant

AMB4 126 I/O amber LED indicator output for USB downstream port 4

(open-drain); this pin acts as an input only during the power-up

sequence and thereafter, acts as an output

1 — FF in the PMC register; supports D3cold

0 — EF in the PMC register; does not support D3cold

bidirectional pin; push-pull input; 3-state output; 10 ns slew rate

control; TTL; 5 V tolerant

GRN4 127 O green LED indicator output for USB downstream port 4

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

DGND 128 - digital ground

Table 2. Pin description

…continued

Symbol[1] Pin Type Description

Product data sheet Rev. 02 — 5 March 2007 11 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

7. Functional description

7.1 OHCI Host Controller

An OHCI Host Controller transfers data to devices at the Original USB deﬁned bit rate of

12 Mbit/s or 1.5 Mbit/s.

7.2 EHCI Host Controller

The EHCI Host Controller transfers data to a Hi-Speed USB compliant device at the

Hi-Speed USB deﬁned bit rate of 480 Mbit/s. When the EHCI Host Controller has the

ownership of a port, OHCI Host Controllers are not allowed to modify the port register. All

additional port bit deﬁnitions required for the enhanced Host Controller are not visible to

the OHCI Host Controller.

7.3 Dynamic port-routing logic

The port-routing feature allows sharing of the same physical downstream ports between

the Original USB Host Controller and the Hi-Speed USB Host Controller. This requirement

of Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus”

provides four downstream ports that are multiplexed with the ports of the two OHCIs. The

ﬁrst and third downstream ports are always connected to the ﬁrst OHCI, and the second

and fourth downstream ports are always connected to the second OHCI.

The EHCI is responsible for the port-routing switching mechanism. Two register bits are

used for ownership switching. During power-on and system reset, the default ownership of

all downstream ports is OHCIs. The enhanced Host Controller Driver (HCD) controls the

ownership during normal functionality.

7.4 Hi-Speed USB analog transceivers

The Hi-Speed USB analog transceivers directly interface to the USB cables through

integrated termination resistors. These transceivers can transmit and receive serial data

at all data rates: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed

(1.5 Mbit/s).

7.5 LED indicators for downstream ports

Indication of a good USB connection is provided through the GoodLink technology

(open-drain, a maximum current of 20 mA). During enumeration, LED indicators blink on

momentarily corresponding to the enumeration trafﬁc of ISP1561 downstream ports. The

LED also blinks on whenever there is valid trafﬁc to the downstream port. In suspend

mode, the LED is off.

The GoodLink feature provides a user-friendly indication on the status of the USB trafﬁc

between the host and downstream hubs and devices. It is a useful diagnostics tool to

isolate faulty equipment and helps to reduce ﬁeld support and hotline costs.

The system designer can also program two optional port indicators, a green LED and an

amber LED, to indicate the status of the Host Controller. These port indicators are

implemented as per the USB speciﬁcation.

All LED indicators are open-drain output.

Product data sheet Rev. 02 — 5 March 2007 12 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

7.6 Power management

The ISP1561 provides an advanced power management capabilities interface that is

compliant with Ref. 5 “PCI Bus Power Management Interface Speciﬁcation”. Power is

controlled and managed by the interaction between drivers and PCI registers. For a

detailed description on power management, see Section 10.

7.7 Legacy support

The ISP1561 provides legacy support for a USB keyboard and mouse. This means that

the keyboard and mouse must be able to work even before the OS boot-up, with the

necessary support in the system’s BIOS. Section 11.2 provides detailed description on

legacy support in the ISP1561.

7.8 Phase-Locked Loop (PLL)

A 12 MHz-to-30 MHz and 48 MHz clock multiplier PLL is integrated on-chip. This allows

the use of a low-cost 12 MHz crystal, which also minimizes EMI. No external components

are required for the PLL to operate.

8. PCI

8.1 PCI interface

The PCI interface has three functions. The ﬁrst function (#0) and the second function (#1)

are for OHCI Host Controllers, and the third function (#2) is for the EHCI Host Controller.

All functions supports both master and target accesses and share the same PCI interrupt

signal INTA#. These functions provide memory-mapped, addressable operational

registers as required in Ref. 4 “Open Host Controller Interface Speciﬁcation for USB” and

Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus”.

Additionally, function #0 provides legacy keyboard and mouse support to comply with Ref.

4 “Open Host Controller Interface Speciﬁcation for USB”.

Each function has its own conﬁguration space. The PCI enumerator must allocate the

memory address space for each of these functions. Power management is implemented

in each PCI function and all power states are provided. This allows the system to achieve

low power consumption by switching off the functions which are not required.

8.1.1 PCI conﬁguration space

Ref. 6 “PCI Local Bus Speciﬁcation” requires that each of the three PCI functions of the

ISP1561 provides its own PCI conﬁguration registers, which can vary in size. In addition to

the basic PCI conﬁguration header registers, these functions implement the capability

registers to support power management.

The registers of each of these functions are accessed by the respective driver. Section 8.2

provides a detailed description of various PCI conﬁguration registers.

Product data sheet Rev. 02 — 5 March 2007 13 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.1.2 PCI initiator and target

A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI

transactions as a slave. In the ISP1561, the two open Host Controllers and the enhanced

Host Controller function as both initiators or targets of PCI transactions issued by the host

CPU.

All USB Host Controllers have their own operational registers that can be accessed by the

system driver software. Drivers use these registers to conﬁgure the Host Controller

hardware system, issue commands to it and/or monitor the status of the current hardware

operation. The Host Controller plays the role of a PCI target. All operational registers of

the Host Controllers are the PCI transaction targets of the CPU.

Normal USB transfers require the Host Controller to access system memory ﬁelds, which

are allocated by USB HCDs and PCI drivers. The Host Controller hardware interacts with

the HCD by accessing these buffers. The Host Controller works as an initiator in this case,

and becomes a PCI master.

8.2 PCI conﬁguration registers

OHCI USB Host Controllers and the EHCI USB Host Controller contain two sets of

software-accessible hardware registers: PCI conﬁguration registers and memory-mapped

Host Controller registers.

A set of conﬁguration registers is implemented for each of the three PCI functions of the

ISP1561, see Table 3.

Remark: In addition to the normal PCI header (from offset index 00h to 3Fh),

implementation-speciﬁc registers are deﬁned to support power management and

function-speciﬁc features.

Table 3. PCI conﬁguration space registers of OHCI1, OHCI2 and EHCI

Address

(Hex) Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Bits 7 to 0 Reset Hex Value[1]

Func0 OHCI1 Func1 OHCI2 Func2 EHCI

00 DID[15:0] VID[15:0] 1561 1131 1561 1131 1562 1131

04 Status[15:0] Command[15:0] 0210 0000 0210 0000 0210 0000

08 Class Code[23:0] REVID[7:0] 0C03 1030 0C03 1030 0C03 2030

0C BIST[7:0] Header

Type[7:0] LT[7:0] CLS[7:0] 0080 0000 0080 0000 0080 0000

10 BAR0[31:0] 0000 0000 0000 0000 0000 0000

Base Address Register 1, 2, 3, 4, 5 (Not conﬁgurable to

prevent setting by the driver) 0000 0000 0000 0000 0000 0000

28 Cardbus CIS Pointer[31:0] 0000 0000 0000 0000 0000 0000

2C SID[15:0] SVID[15:0] 1561 1131 1561 1131 1562 1131

30 Expansion ROM Base Address[31:0] 0000 0000 0000 0000 0000 0000

34 Reserved CP[7:0] 0000 00DC 0000 00DC 0000 00DC

38 Reserved 0000 0000 0000 0000 0000 0000

Product data sheet Rev. 02 — 5 March 2007 14 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

[1] Reset values that are highlighted (for example, 0) indicate read and write accesses; and reset values that are not highlighted (for

example, 0) indicate read-only.

[2] XX is 1Fh for four ports or 07h for two ports.

The HCD does not usually interact with the PCI conﬁguration space. The conﬁguration

space is used only by the PCI enumerator to identify the USB Host Controller and assign

appropriate system resources by reading the Vendor ID (VID) and the Device ID (DID).

8.2.1 PCI conﬁguration header registers

The enhanced Host Controller implements normal PCI header register values, except the

values for the memory-mapping base address register, serial bus number and device ID.

8.2.1.1 Vendor ID register (address: 00h)

This read-only register identiﬁes the manufacturer of the device. PCI Special Interest

Group (PCI-SIG) assigns valid vendor identiﬁers to ensure the uniqueness of the

identiﬁer. The bit description is shown in Table 4.

8.2.1.2 Device ID register (address: 02h)

Device ID is a 2-byte read-only register that identiﬁes a particular device. This identiﬁer is

allocated by NXP Semiconductors. Table 5 shows the bit description of the register.

[1] X is 1561h for OHCI1 and OHCI2 and X is 1562h for EHCI.

3C MAX_LAT

[7:0] MIN_GNT

[7:0] Interrupt

Pin[7:0] IL[7:0] 2A01 0100 2A01 0100 1002 0100

40 Reserved Retry Timeout TRDY

Timeout 0000 8000 0000 8000 0000 8000

Enhanced Host Controller-speciﬁc PCI registers

60 PORTWAKECAP[15:0] FLADJ[7:0] SBRN[7:0] - - XX1F 2020[2]

Power management registers

DC PMC[15:0] NEXT_ITEM_

PTR[7:0] CAP_ID[7:0] 5202 0001 5202 0001 FF02 0001

E0 DATA[7:0] PMCSR_BSE

[7:0] PMCSR[15:0] 0000 0000 0000 0000 0000 XX00[2]

Table 3. PCI conﬁguration space registers of OHCI1, OHCI2 and EHCI

…continued

Address

(Hex) Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Bits 7 to 0 Reset Hex Value[1]

Func0 OHCI1 Func1 OHCI2 Func2 EHCI

Table 4. Vendor ID register: bit description

Bit Symbol Access Value Description

15 to 0 VID[15:0] R 1131h Vendor ID: This read-only register value is assigned to NXP Semiconductors

by PCI-SIG as 1131h.

Table 5. Device ID register: bit description

Bit Symbol Access Value Description

15 to 0 DID[15:0] R X[1] Device ID: This register value is deﬁned by NXP Semiconductors to

identify the USB Host Controller IC product. For the ISP1561, NXP

Semiconductors has deﬁned OHCI functions as 1561h, and the EHCI

function as 1562h.

Product data sheet Rev. 02 — 5 March 2007 15 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.1.3 Command register (address: 04h)

This is a 2-byte register that provides coarse control over the ability of a device to

generate and respond to PCI cycles. The bit allocation of the Command register is given

in Table 6. When logic 0 is written to this register, the device is logically disconnected from

the PCI bus for all accesses, except conﬁguration accesses. All devices are required to

support this base level of functionality. Individual bits in the Command register may or may

not support this base level of functionality.

Table 6. Command register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol reserved FBBE SERRE

Reset 00000000

Access ------R/WR/W

Bit 76543210

Symbol SCTRL PER VGAPS MWIE SC BM MS IOS

Reset 00000000

Access R R/W R R/W R R/W R/W R/W

Table 7. Command register: bit description

Bit Symbol Description

15 to 10 - reserved

9 FBBE Fast Back-to-Back Enable: This bit controls whether a master can do

fast back-to-back transactions to various devices. The initialization

software must set this bit if all targets are fast back-to-back capable.

0 — Fast back-to-back transactions are only allowed to the same

agent (value after RST#).

1 — The master is allowed to generate fast back-to-back transactions

to different agents.

8 SERRE SERR# Enable: This bit is an enable bit for the SERR# driver. All

devices that have an SERR# pin must implement this bit. Address

parity errors are reported only if this bit and the PER bit are logic 1.

0 — Disable the SERR# driver.

1 — Enable the SERR# driver.

7 SCTRL Stepping Control: This bit controls whether a device does address

and data stepping. Devices that never do stepping must clear this bit.

Devices that always do stepping must set this bit. Devices that can do

either, must make this bit read/write and initialize it to logic 1 after

RST#.

6 PER Parity Error Response: This bit controls the response of a device to

parity errors. When the bit is set, the device must take its normal

action when a parity error is detected. When the bit is logic 0, the

device sets its Detected Parity Error status bit (bit 15 in the Status

continues normal operation. The state of this bit after RST# is logic 0.

Devices that check parity must implement this bit. Devices are

required to generate parity, even if parity checking is disabled.

Product data sheet Rev. 02 — 5 March 2007 16 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.1.4 Status register (address: 06h)

The Status register is a 2-byte read-only register used to record status information on PCI

bus-related events (bit allocation: see Table 8).

5 VGAPS VGA Palette Snoop: This bit controls how VGA compatible and

graphics devices handle accesses to VGA palette registers. When this

bit is logic 1, palette snooping is enabled (that is, the device does not

respond to palette register writes and snoops data). When the bit is

logic 0, the device must treat palette write accesses like all other

accesses. VGA compatible devices should implement this bit.

4 MWIE Memory Write and Invalidate Enable: This is an enable bit for using

the Memory Write and Invalidate command. When this bit is logic 1,

masters may generate the command. When it is logic 0, Memory

Writes must be used instead. State after RST# is logic 0. This bit must

be implemented by master devices that can generate the Memory

Write and Invalidate command.

3SCSpecial Cycles: Controls the action of a device on special cycle

operations. A value of logic 0 causes the device to ignore all special

cycle operations. A value of logic 1 allows the device to monitor

special cycle operations. State after RST# is logic 0.

2BMBus Master: Controls the ability of a device to act as a master on the

PCI bus. A value of logic 0 disables the device from generating PCI

accesses. A value of logic 1 allows the device to behave as a bus

master. State after RST# is logic 0.

1MSMemory Space: Controls the response of a device to memory space

accesses. A value of logic 0 disables the device response. A value of

logic 1 allows the device to respond to memory space accesses. State

after RST# is logic 0.

0 IOS IO Space: Controls the response of a device to I/O space accesses. A

value of logic 0 disables the device response. A value of logic 1 allows

the device to respond to I/O space accesses. State after RST# is

logic 0.

Table 7. Command register: bit description

…continued

Bit Symbol Description

Table 8. Status register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol DPE SSE RMA RTA STA DEVSELT[1:0] MDPE

Reset 00000010

Access RRRRRRRR

Bit 76543210

Symbol FBBC reserved 66MC CL reserved

Reset 00010000

Access R-RR----

Product data sheet Rev. 02 — 5 March 2007 17 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

Table 9. Status register: bit description

Bit Symbol Description

15 DPE Detected Parity Error: This bit must be set by the device whenever

it detects a parity error, even if the parity error handling is disabled.

14 SSE Signaled System Error: This bit must be set whenever the device

asserts SERR#. Devices that never assert SERR# do not need to

implement this bit.

13 RMA Received Master Abort: This bit must be set by a master device

whenever its transaction, except for special cycle, is terminated with

master abort. All master devices must implement this bit.

12 RTA Received Target Abort: This bit must be set by a master device

whenever its transaction is terminated with target abort. All master

devices must implement this bit.

11 STA Signaled Target Abort: This bit must be set by a target device

whenever it terminates a transaction with target abort. Devices that

never signal target abort do not need to implement this bit.

10 to 9 DEVSELT[1:0] DEVSEL Timing: These bits encode the timing of DEVSEL#. There

are three allowable timing for assertion of DEVSEL#:

00b — for fast

01b — for medium

10b — for slow

11b — is reserved

These bits are read-only and must indicate the slowest time that a

device asserts DEVSEL# for any bus command, except

Conﬁguration Read and Conﬁguration Write.

8 MDPE Master Data Parity Error: This bit is implemented by bus masters.

It is set when the following three conditions are met:

•The bus agent asserted PERR# itself, on a read; or observed

PERR# asserted, on a write.

•The agent setting the bit acted as the bus master for the

operation in which error occurred.

•The Parity Error Response bit (in the Command register) is set.

7 FBBC Fast Back-to-Back Capable: This read-only bit indicates whether

the target is capable of accepting fast back-to-back transactions

when the transactions are not to the same agent. This bit can be set

to logic 1 if the device can accept these transactions; and must be

set to logic 0 otherwise.

6 - reserved

5 66MC 66 MHz Capable: This read-only bit indicates whether this device is

capable of running at 66 MHz. A value of logic 0 indicates 33 MHz,

and a value of logic 1 indicates 66 MHz.

4CL Capabilities List: This read-only bit indicates whether this device

implements the pointer for a new capabilities linked list at offset 34h.

A value of logic 0 indicates that no new capabilities linked list is

available. A value of logic 1 indicates that the value read at offset

34h is a pointer in conﬁguration space to a linked list of new

capabilities.

3 to 0 - reserved

Product data sheet Rev. 02 — 5 March 2007 18 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.1.5 Revision ID register (address: 08h)

This 1-byte read-only register indicates a device-speciﬁc revision identiﬁer. The value is

chosen by the vendor. This ﬁeld is a vendor-deﬁned extension of the device ID. The

Revision ID register bit description is given in Table 10.

8.2.1.6 Class Code register (address: 09h)

Class Code is a 24-bit read-only register used to identify the generic function of the

device, and in some cases, a speciﬁc register-level programming interface. Table 11

shows the bit allocation of the register.

The Class Code register is divided into three byte-size ﬁelds. The upper byte is a base

class code that broadly classiﬁes the type of function the device performs. The middle

byte is a sub-class code that identiﬁes more speciﬁcally the function of the device. The

lower byte identiﬁes a speciﬁc register-level programming interface, if any, so that

device-independent software can interact with the device.

[1] X is 10h for OHCI1 and OHCI2; X is 20h for EHCI.

Table 10. Revision ID register: bit description

Bit Symbol Access Value Description

7 to 0 REVID[7:0] R 30h Revision ID: This byte speciﬁes the design revision number of functions.

Table 11. Class Code register: bit allocation

Bit 23 22 21 20 19 18 17 16

Symbol BCC[7:0]

Reset 0Ch

Access R

Bit 15 14 13 12 11 10 9 8

Symbol SCC[7:0]

Reset 03h

Access R

Bit 76543210

Symbol RLPI[7:0]

Reset X[1]

Access R

Table 12. Class Code register: bit description

Bit Symbol Description

23 to 16 BCC[7:0] Base Class Code: 0Ch is the base class code assigned to this byte,

and it implies a serial bus controller.

15 to 8 SCC[7:0] Sub-Class Code: 03h is the sub-class code assigned to this byte, and

it implies the USB Host Controller.

7 to 0 RLPI[7:0] Register-Level Programming Interface: 10h is the programming

interface code assigned to OHCI, which is USB 1.1 speciﬁcation

compliant. 20h is the programming interface code assigned to EHCI,

which is USB 2.0 speciﬁcation compliant.

Product data sheet Rev. 02 — 5 March 2007 19 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.1.7 CacheLine Size register (address: 0Ch)

The CacheLine Size register is a read/write single-byte register that speciﬁes the system

cacheline size in units of DWORDs. This register must be implemented by master devices

that can generate the Memory Write and Invalidate command. The value in this register is

also used by master devices to determine whether to use the Read, Read Line, or Read

Multiple command to access memory.

Slave devices that want to allow memory bursting using cacheline-wrap addressing mode

must implement this register to know when a burst sequence wraps to the beginning of the

cacheline.

This ﬁeld must be initialized to logic 0 on activation of RST#. Table 13 shows the bit

description of the CacheLine Size register.

8.2.1.8 Latency Timer register (address: 0Dh)

This 1-byte register speciﬁes, in units of PCI bus clocks, the value of the latency timer for

the PCI bus master. The Latency Time register bit description is given in Table 14.

This register must be implemented as writable by any master that can burst more than two

data phases. This register may be implemented as read-only for devices that burst two or

fewer data phases, but the ﬁxed value must be limited to 16 or less. The register must be

initialized to logic 0 at RST#, if programmable.

8.2.1.9 Header Type register (address: 0Eh)

The Header Type register identiﬁes the layout of the second part of the predeﬁned header,

beginning at byte 10h in conﬁguration space. It also identiﬁes whether the device contains

multiple functions (bit allocation: see Table 15).

Table 13. CacheLine Size register: bit description

Bit Symbol Access Value Description

7 to 0 CLS[7:0] R/W 00h CacheLine Size: This byte identiﬁes the system cacheline size.

Table 14. Latency Timer register: bit description

Bit Symbol Access Value Description

7 to 0 LT[7:0] R/W 00h Latency Timer: This byte identiﬁes the latency timer.

Table 15. Header Type register: bit allocation

Bit 76543210

Symbol MFD HT[6:0]

Reset 10000000

Access RRRRRRRR

Table 16. Header Type register: bit description

Bit Symbol Description

7 MFD Multi-Function Device: This bit identiﬁes a multifunction device. If the

bit is logic 0, then the device has a single function. If the bit is logic 1,

then the device has multiple functions.

6 to 0 HT[6:0] Header Type: These bits identify the layout of the part of the

predeﬁned header, beginning at byte 10h in conﬁguration space.

Product data sheet Rev. 02 — 5 March 2007 20 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.1.10 BIST register (address: 0Fh)

This register is used for control and status of Built In Self Test (BIST). Devices that do not

support BIST must always return logic 0, that is, treat it as a reserved register. A device

whose BIST is invoked must not prevent normal operation of the PCI bus. The BIST

8.2.1.11 Base Address registers

Power-up software must build a consistent address map before booting the machine to an

operating system. This means it must determine how much memory is in the system, and

how much address space the I/O controllers in the system require. After determining this

information, power-up software can map the I/O controllers into reasonable locations and

proceed with system boot. To do this mapping in a device-independent manner, base

registers for this mapping are placed in the predeﬁned header portion of conﬁguration

space.

Bit 0 in all Base Address registers is read-only and used to determine whether the register

maps into memory or I/O space. Base Address registers that map to memory space must

return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in

bit 0.

The bit description of the BAR0 register is given in Table 17.

Base Address register 0 (BAR0) — (address: 10h)

Base Address register 1, 2, 3, 4, 5 (BAR1, 2, 3, 4, 5) — (address: 14h, 18h, 1Ch, 20h

and 24h): The BAR1, 2, 3, 4, 5 register spaces are not used in the ISP1561.

8.2.1.12 CardBus CIS Pointer register (address: 28h)

This 4-byte register is used by devices that want to share silicon between CardBus and

PCI. The CardBus CIS Pointer register is used to point to the Card Information Structure

(CIS) for the CardBus card. This register is not implemented in the ISP1561.

8.2.1.13 Subsystem Vendor ID register (address: 2Ch)

The Subsystem Vendor ID register is used to uniquely identify the expansion board or

subsystem where the PCI device resides. This register allows expansion board vendors to

distinguish their boards, even though the boards may have the same vendor ID and device

ID.

Subsystem vendor IDs are assigned by PCI-SIG to maintain uniqueness. The bit

description of the Subsystem Vendor ID register is given in Table 18.

Table 17. BAR0 register: bit description

Bit Symbol Access Value Description

31 to 0 BAR0[31:0] R/W 0000 0000h Base Address to Memory-Mapped Host Controller Register

Space: The memory size required by OHCI and EHCI are 4 kB and

256 bytes, respectively. Therefore, BAR0[31:12] is assigned to the two

OHCI ports, and BAR0[31:8] is assigned to the EHCI port.

Table 18. Subsystem Vendor ID register: bit description

Bit Symbol Access Value Description

15 to 0 SVID[15:0] R 1131h Subsystem Vendor ID: 1131h is the subsystem vendor ID assigned to NXP

Semiconductors.

Product data sheet Rev. 02 — 5 March 2007 21 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.1.14 Subsystem ID register (address: 2Eh)

Subsystem ID values are vendor-speciﬁc. The bit description of the Subsystem ID register

is given in Table 19.

[1] X is 1561h for OHCI1 and OHCI2; X is 1562h for EHCI.

8.2.1.15 Expansion ROM Base Address register (address: 30h)

Some PCI devices, especially those intended for use on expansion boards in the PC

architecture, require local EPROMs for expansion ROM. This 4-byte register at offset 30h

in a type 00h predeﬁned header is deﬁned to handle the base address and size

information for this expansion ROM. The ISP1561 does not support expansion EPROM.

8.2.1.16 Capabilities Pointer register (address: 34h)

The Capabilities Pointer register is used to point to a linked list of new capabilities

implemented by the device. This register is only valid if the CL bit in the Status register is

set. If implemented, bit 1 and bit 0 are reserved and should be set to 00b. Software must

mask these bits off before using this register as a pointer in conﬁguration space to the ﬁrst

entry of a linked list of new capabilities. The bit description of the register is given in

Table 20.

8.2.1.17 Interrupt Line register (address: 3Ch)

The Interrupt Line register is a 1-byte read/write register used to communicate interrupt

line routing information. This register must be implemented by any device or device

function that uses an interrupt pin. The interrupt allocation is done by the BIOS. The

POST software needs to write the routing information into this register because it

initializes and conﬁgures the system. The bit description of the Interrupt Line register is

given in Table 21.

The value in this register speciﬁes which input of the system interrupt controller(s) the

interrupt pin of the device is connected. The device itself does not use this value, rather it

is used by device drivers and operating systems to determine priority and vector

information. Values in this register are system architecture speciﬁc.

Table 19. Subsystem ID register: bit description

Bit Symbol Access Value Description

15 to 0 SID[15:0] R X[1] Subsystem ID: For the ISP1561, NXP Semiconductors has deﬁned OHCI

functions as 1561h, and the EHCI function as 1562h.

Table 20. Capabilities Pointer register: bit description

Bit Symbol Access Value Description

7 to 0 CP[7:0] R DCh Capabilities Pointer: EHCI manages power efﬁciently using this register. This

power management register is allocated at offset DCh. Only one Host

Controller is needed to manage power in the ISP1561.

Table 21. Interrupt Line register: bit description

Bit Symbol Access Value Description

7 to 0 IL[7:0] R/W 00h Interrupt Line: Indicates which IRQ is used to report interrupt from the

ISP1561.

Product data sheet Rev. 02 — 5 March 2007 22 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.1.18 Interrupt Pin register (address: 3Dh)

This 1-byte register is use to specify which interrupt pin the device or device function uses.

The bit description is given in Table 22.

Devices or functions that do not use an interrupt pin must put a logic 0 in this register.

8.2.1.19 MIN_GNT and MAX_LAT registers (address: 3Eh and 3Fh)

The Minimum Grant (MIN_GNT) and Maximum Latency (MAX_LAT) registers are used to

specify the desired settings of the device for latency timer values. For both registers, the

value speciﬁes a period of time in units of 250 ns. Values of 0 indicates that the device has

no major requirements for the settings of latency timers.The MIN_GNT register bit

description is given in Table 23.

[1] X is 01h for OHCI1 and OHCI2; X is 02h for EHCI.

The MAX_LAT register bit description is given in Table 24.

[1] X is 2Ah for OHCI1 and OHCI2; X is 10h for EHCI.

8.2.1.20 TRDY Timeout register (R/W: 40h)

The default and recommended value is 00h, TRDY time-out disabled. This value can,

however, be modiﬁed. It is an implementation-speciﬁc register, and not a standard PCI

conﬁguration register.

The TRDY timer is 13 bits: the lower 5 bits are ﬁxed as logic 0 and the upper 8 bits are

determined by the TRDY time-out register value. The time-out is calculated by multiplying

the 13-bit timer with the PCICLK cycle time.

This register determines the delay for the UE bit setting if a target does not assert its

TDRY signal.

8.2.1.21 Retry Timeout register (R/W: 41h)

The default value is 80h. This value can, however, be modiﬁed. Programming this register

as 00h means that retry time-out is disabled. This is an implementation-speciﬁc register,

and not a standard PCI conﬁguration register.

The time-out is determined by multiplying the register value with the PCICLK cycle time.

This register determines the delay to set the UE bit if a RETRY time-out occurs.

Table 22. Interrupt Pin register: bit description

Bit Symbol Access Value Description

7 to 0 IP[7:0] R/W 01h Interrupt Pin: INTA# is the default interrupt pin used by the ISP1561.

Table 23. MIN_GNT register: bit description

Bit Symbol Access Value Description

7 to 0 MIN_GNT[7:0] R X[1] MIN_GNT: It is used to specify how long a burst period the device needs,

assuming a clock rate of 33 MHz.

Table 24. MAX_LAT register: but description

Bit Symbol Access Value Description

7 to 0 MAX_LAT[7:0] R X[1] MAX_LAT: It is used to specify how often the device needs to gain

access to the PCI bus.

Product data sheet Rev. 02 — 5 March 2007 23 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.2 Enhanced Host Controller-speciﬁc PCI registers

In addition to the PCI conﬁguration header registers, EHCI needs some additional PCI

conﬁguration space registers to indicate the serial bus release number, downstream port

wake-up event capability, and adjust the USB bus frame length for Start-Of-Frame (SOF).

The EHCI-speciﬁc PCI registers are given in Table 25.

8.2.2.1 SBRN register (address: 60h)

The Serial Bus Release Number (SBRN) register is a 1-byte register, and the bit

description is given in Table 26. This register contains the release number of the USB

speciﬁcation with which this USB Host Controller module is compliant.

8.2.2.2 FLADJ register (address: 61h)

This feature is used to adjust any offset from the clock source that generates the clock that

drives the SOF counter. When a new value is written to these six bits, the length of the

frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is

given in Table 27.

Table 25. EHCI-speciﬁc PCI registers

Offset Register

60h Serial Bus Release Number (SBRN)

61h Frame Length Adjustment (FLADJ)

62h to 63h Port Wake Capability (PORTWAKECAP)

Table 26. SBRN register: bit description

Bit Symbol Access Value Description

7 to 0 SBRN[7:0] R 20h Serial Bus Speciﬁcation Release Number: This register value is to identify Ref. 8

“Universal Serial Bus Speciﬁcation”. All other combinations are reserved.

Table 27. FLADJ register: bit allocation

Bit 76543210

Symbol reserved FLADJ[5:0]

Reset 00100000

Access - - R/W R/W R/W R/W R/W R/W

Table 28. FLADJ register: bit description

Bit Symbol Description

7 to 6 - reserved

5 to 0 FLADJ[5:0] Frame Length Timing Value: Each decimal value change to this register

corresponds to 16 high-speed bit times. The SOF cycle time, number of

SOF counter clock periods to generate a SOF micro frame length, is equal

to 59488 + value in this ﬁeld. The default value is decimal 32 (20h), which

gives a SOF cycle time of 60000. See Table 29.

Table 29. FLADJ value as a function of SOF cycle time

FLADJ value SOF cycle time (480 MHz)

0 (00h) 59488

1 (01h) 59504

2 (02h) 59520

Product data sheet Rev. 02 — 5 March 2007 24 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.2.3 PORTWAKECAP register (address: 62h)

The PORTWAKECAP register is a 2-byte register, and the bit description is given in

Table 30. This register is used to establish a policy about which ports are for wake events.

Bit positions 1 to 15 in the mask correspond to a physical port implemented on the current

EHCI controller. Logic 1 in a bit position indicates that a device connected below the port

can be enabled as a wake-up device and the port may be enabled for disconnect or

connect, or overcurrent events as wake-up events. This is an information only mask

Controller. The system-speciﬁc policy can be established by BIOS initializing this register

to a system-speciﬁc value. The system software uses the information in this register when

enabling devices and ports for remote wake-up.

8.2.3 Power management registers

8.2.3.1 CAP_ID register (address: value read from address 34h + 0h)

The Capability Identiﬁer (CAP_ID) register when read by the system software as 01h

indicates that the data structure currently being pointed to is the PCI power management

data structure. Each function of a PCI device may have only one item in its capability list

with CAP_ID set to 01h. The bit description of the register is given in Table 32.

31(1Fh) 59984

32 (20h) 60000

62 (3Eh) 60480

63 (3Fh) 60496

Table 29. FLADJ value as a function of SOF cycle time

…continued

FLADJ value SOF cycle time (480 MHz)

Table 30. PORTWAKECAP register: bit description

Bit Symbol Access Value Description

15 to 0 PORTWAKE

CAP[15:0] R/W 001Fh Port Wake Up Capability Mask: EHCI does not implement this feature.

Table 31. Power management registers

Offset Register

value read from address 34h + 0h Capability Identiﬁer (CAP_ID)

value read from address 34h + 1h Next Item Pointer (NEXT_ITEM_PTR)

value read from address 34h + 2h Power Management Capabilities (PMC)

value read from address 34h + 4h Power Management Control/Status (PMCSR)

value read from address 34h + 6h Power Management Control/Status PCI-to-PCI Bridge

Support Extensions (PMCSR_BSE)

value read from address 34h + 7h Data

Table 32. CAP_ID register: bit description

Bit Symbol Access Value Description

7 to 0 CAP_ID[7:0] R 01h ID: This ﬁeld when 01h identiﬁes the linked list item as being PCI power

management registers.

Product data sheet Rev. 02 — 5 March 2007 25 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.3.2 NEXT_ITEM_PTR register (address: value read from address 34h + 1h)

The Next Item Pointer (NEXT_ITEM_PTR) register (see Table 33) describes the location

of the next item in the function’s capability list. The value given is an offset into the

function’s PCI conﬁguration space. If the function does not implement any other

capabilities deﬁned by the PCI-SIG for inclusion in the capabilities list, or if power

management is the last item in the list, then this register must be set to 00h.

8.2.3.3 PMC register (address: value read from address 34h + 2h)

The Power Management Capabilities (PMC) register is a 2-byte register, and the bit

allocation is given in Table 34. This read-only register provides information on the

capabilities of the function related to power management.

[1] X is 0 for OHCI1, OHCI2 and EHCI S1; X is 1 for EHCI S3.

[2] X is 0 for OHCI1 and OHCI2; X is 1 for EHCI.

Table 33. NEXT_ITEM_PTR register: bit description

Bit Symbol Access Value Description

7 to 0 NEXT_ITEM_

PTR[7:0] R 00h Next Item Pointer: This ﬁeld provides an offset into the function’s

PCI conﬁguration space pointing to the location of the next item in the

function’s capability list. If there are no additional items in the

capabilities list, this register is set to 00h.

Table 34. PMC register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol PME_S[4:0] D2_S D1_S AUX_C[2:0]

Reset X[1] 1X

[2] 1X

[2] X[2] 1X

[2]

Access RRRRRRRR

Bit 76543210

Symbol AUX_C[2:0] DSI reserved PMI VER[2:0]

Reset 00000010

Access RRR-RRRR

Table 35. PMC register: bit description

Bit Symbol Description

15 to 11 PME_S[4:0] PME Support: This 5-bit ﬁeld indicates the power states in which

the function may assert PME#. Logic 0 for any bit indicates that

the function is not capable of asserting the PME# signal while in

that power state.

PME_S[0] — PME# can be asserted from D0

PME_S[1] — PME# can be asserted from D1

PME_S[2] — PME# can be asserted from D2

PME_S[3] — PME# can be asserted from D3hot

PME_S[4] — PME# can be asserted from D3cold

10 D2_S D2 Support: If this bit is logic 1, this function supports the D2

power management state. Functions that do not support D2 must

always return a value of logic 0 for this bit.

9 D1_S D1 Support: If this bit is logic 1, this function supports the D1

power management state. Functions that do not support D1 must

always return a value of logic 0 for this bit.

Product data sheet Rev. 02 — 5 March 2007 26 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

The logic level of the AMB4 pin at power-on determines the default value of PMC

registers. If this pin is connected to VDD as a pull-up, then the ISP1561 supports D3cold (in

the case of notebook design). If this pin is left open or is pulled down, then the ISP1561

does not support D3cold (in the case of PCI add-on card design).

8.2.3.4 PMCSR register (address: value read from address 34h + 4h)

The Power Management Control/Status (PMCSR) register is a 2-byte register used to

manage the power management state of the PCI function, as well as to allow and monitor

Power Management Events (PMEs). The bit allocation of the register is given in Table 36.

8 to 6 AUX_C[2:0] Auxiliary Current: This three-bit ﬁeld reports the VAUX auxiliary

current requirements for the PCI function.

If the Data register is implemented by this function:

•A read from this ﬁeld needs to return a value of 000b.

•The Data register takes precedence over this ﬁeld for VAUX

current requirement reporting.

If the PME# generation from D3cold is not supported by the

function (PMC[15] = 0), this ﬁeld must return a value of 000b when

read.

For functions that support PME# from D3cold and do not implement

the Data register, bit assignments correspond to the maximum

current required for VAUX are:

111b — 375 mA

110b — 320 mA

101b — 270 mA

100b — 220 mA

011b — 160 mA

010b — 100 mA

001b — 55 mA

000b — 0 (self-powered)

5 DSI Device Speciﬁc Initialization: This bit indicates whether special

initialization of this function is required, beyond the standard PCI

conﬁguration header, before the generic class device driver can

use it.

Remark: This bit is not used by some operating systems. For

example, Microsoft Windows and Windows NT do not use this bit

to determine whether to use D3. Instead, it is determined using

the capabilities of the driver.

Logic 1 indicates that the function requires a device-speciﬁc

initialization sequence, following transition to D0 uninitialized state.

4 - reserved

3 PMI PME Clock: When this bit is logic 1, it indicates that the function

relies on the presence of the PCI clock for the PME# operation.

When this bit is logic 0, it indicates that no PCI clock is required for

the function to generate PME#. Functions that do not support the

PME# generation in any state must return logic 0 for this ﬁeld.

2 to 0 VER[2:0] Version: A value of 010b indicates that this function complies with

Ref. 5 “PCI Bus Power Management Interface Speciﬁcation”.

Table 35. PMC register: bit description

…continued

Bit Symbol Description

Product data sheet Rev. 02 — 5 March 2007 27 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

[1] Sticky bit, if the function supports PME# from D3cold, then X is indeterminate at the time of initial operating system boot; X is 0 if the

function does not support PME# from D3cold.

Table 36. PMCSR register: bit allocation

Bit 15 14 13 12 11 10 9 8

Symbol PMES DS[1:0] D_S[3:0] PMEE

Reset X[1] 000000X

[1]

Access R/W R R R/W R/W R/W R/W R/W

Bit 76543210

Symbol reserved PS[1:0]

Reset 00000000

Access ------R/WR/W

Table 37. PMCSR register: bit description

Bit Symbol Description

15 PMES PME Status: This bit is set when the function normally asserts the

PME# signal independent of the state of the PME_EN bit. Writing

logic 1 to this bit clears it and causes the function to stop asserting

PME#, if enabled. Writing logic 0 has no effect. This bit defaults to

logic 0, if the function does not support the PME# generation from

D3cold. If the function supports the PME# generation from D3cold, then

this bit is sticky and must be explicitly cleared by the operating system

each time the operating system is initially loaded.

14 to 13 DS[1:0] Data Scale: This two-bit read-only ﬁeld indicates the scaling factor

when interpreting the value of the Data register. The value and

meaning of this ﬁeld vary, depending on which data value is selected by

the D_S ﬁeld. This ﬁeld is a required component of the Data register

(offset 7) and must be implemented, if the Data register is

implemented. If the Data register is not implemented, this ﬁeld must

return 00b when PMCSR is read.

12 to 9 D_S[3:0] Data Select: This four-bit ﬁeld selects the data that is reported through

the Data register and the D_S ﬁeld. This ﬁeld is a required component

of the Data register (offset 7) and must be implemented if the Data

ﬁeld must return 00b when PMCSR is read.

8 PMEE PME Enabled: Logic 1 allows the function to assert PME#. When it is

logic 0, PME# assertion is disabled. This bit defaults to logic 0 if the

function does not support the PME# generation from D3cold. If the

function supports PME# from D3cold, then this bit is sticky and must

explicitly be cleared by the operating system each time the operating

system is initially loaded. Functions that do not support the PME#

generation from any D-state (that is, PMC[15:11] = 0 0000b), may

hardwire this bit to be read-only always returning logic 0 when read by

system software.

7 to 2 - reserved

Product data sheet Rev. 02 — 5 March 2007 28 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.3.5 PMCSR_BSE register (address: value read from address 34h + 6h)

The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI

bridge-speciﬁc functionality and is required for all PCI-to-PCI bridges. The bit allocation of

this register is given in Table 38.

[1] Internally hardwired.

1 to 0 PS[1:0] Power State: This two-bit ﬁeld is used to determine the current power

state of the EHCI function and to set the function into a new power

state. The deﬁnition of the ﬁeld values is given as:

00b — for D0

01b — for D1

10b — for D2

11b — for D3hot

If the software attempts to write an unsupported, optional state to this

ﬁeld, the write operation must complete normally on the bus; however,

the data is discarded and no status change occurs.

Table 37. PMCSR register: bit description

…continued

Bit Symbol Description

Table 38. PMCSR_BSE register: bit allocation

Bit 76543210

Symbol BPCC_EN B2_B3# reserved

Reset RRRRRRRR

Access 0[1] 0[1] 000000

Table 39. PMCSR_BSE register: bit description

Bit Symbol Description

7 BPCC_EN Bus Power or Clock Control Enable

1 — Indicates that the bus power or clock control mechanism as deﬁned in

Table 40 is enabled.

0 — Indicates that the bus power or control policies as deﬁned in Table 40

are disabled.

When the bus power or clock control mechanism is disabled, the bridge’s

PMCSR PS (Power State) ﬁeld cannot be used by the system software to

control the power or clock of the bridge’s secondary bus.

6 B2_B3# B2 or B3 support for D3hot: The state of this bit determines the action that

is to occur as a direct result of programming the function to D3hot.

1 — Indicates that when the bridge function is programmed to D3hot, its

secondary bus’s PCI clock will be stopped (B2).

0 — Indicates that when the bridge function is programmed to D3hot, its

secondary bus will have its power removed (B3).

This bit is only meaningful if bit 7 (BPCC_EN) is logic 1.

5 to 0 - reserved

Product data sheet Rev. 02 — 5 March 2007 29 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8.2.3.6 Data register (address: value read from address 34h + 7h)

The Data register is an optional, 1-byte register that provides a mechanism for the

function to report state dependent operating data, such as power consumed or heat

dissipated. Table 41 shows the bit description of the register.

Table 40. PCI bus power and clock control

Originating device’s

bridge PM state Secondary bus

PM state Resultant actions by bridge (either direct or

indirect)

D0 B0 none

D1 B1 none

D2 B2 clock stopped on secondary bus

D3hot B2, B3 clock stopped and VCC removed from secondary bus

(B3 only); for deﬁnition of B2_B3#, see Table 39

D3cold B3 none

Table 41. Data register: bit description

Bit Symbol Access Value Description

7 to 0 DATA[7:0] R 00h DATA: This register is used to report the state dependent data requested by

the D_S (Data Select) ﬁeld. The value of this register is scaled by the value

reported by the DS (Data Scale) ﬁeld.

Product data sheet Rev. 02 — 5 March 2007 30 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

9. I2C-bus interface

A simple I2C-bus interface is provided in the ISP1561 to read customized vendor ID,

product ID and some other conﬁguration bits from an external EEPROM.

The I2C-bus interface is for bidirectional communication between ICs using two serial bus

wires: SDA (data) and SCL (clock). Both lines are driven by open-drain circuits and must

be connected to the positive supply voltage through pull-up resistors.

9.1 Protocol

The I2C-bus protocol deﬁnes the following conditions:

•Bus free: both SDA and SCL are HIGH

•START: a HIGH-to-LOW transition on SDA, while SCL is HIGH

•STOP: a LOW-to-HIGH transition on SDA, while SCL is HIGH

•Data valid: after a START condition, data on SDA is stable during the HIGH period of

SCL; data on SDA may only change while SCL is LOW

Each device on the I2C-bus has a unique slave address, which the master uses to select a

device for access.

The master starts a data transfer using a START condition and ends it by generating a

STOP condition. Transfers can only be initiated when the bus is free. The receiver must

acknowledge each byte by means of a LOW level on SDA during the ninth clock pulse on

SCL.

For detailed information, refer to Ref. 7 “The I2C-bus Speciﬁcation”.

9.2 Hardware connections

The ISP1561 can be connected to an external EEPROM through the I2C-bus interface.

The hardware connections are shown in Figure 3.

The slave address that the ISP1561 uses to access the EEPROM is 101 0000b. Page

mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must

be connected to ground (logic 0).

Fig 3. EEPROM connection diagram

004aaa163

SDA

SCL

SDA

SCL

DVAUX

ISP1561

USB HOST 24C01

EEPROM

equivalent

I2C-bus

Product data sheet Rev. 02 — 5 March 2007 31 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

9.3 Information loading from EEPROM

Figure 4 shows the content of the EEPROM memory. If the EEPROM is not present, the

default values of Device ID (DID), Vendor ID (VID), subsystem VID and subsystem DID

assigned to NXP Semiconductors by PCI-SIG will be loaded. See Table 3 for these default

value. For instructions on programming the EEPROM, refer to application note Ref. 1

“Designing a Hi-Speed USB Host PCI Adapter Using the ISP1561” and user manual Ref.

3 “ISP1561 Evaluation Board User’s Guide”.

10. Power management

10.1 PCI bus power states

The PCI bus can be characterized by one of the four power management states: B0, B1,

B2 and B3.

B0 state (PCI clock = 33 MHz, PCI bus power = on) — This corresponds to the bus

being fully operational.

B1 state (PCI clock = intermittent clock operation mode, PCI bus power = on) —

When a PCI bus is in B1, VDD is still applied to all devices on the bus. No bus transactions,

however, are allowed to take place on the bus. The B1 state indicates a perpetual idle

state on the PCI bus.

B2 state (PCI clock = stop, PCI bus power = on) — VDD is still applied on the bus, but

the clock is stopped and held in the LOW state.

B3 state (PCI clock = stop, PCI bus power = off) — VDD is removed from all devices on

the PCI bus segment.

L = LOW; H = HIGH.

Fig 4. Information loading from EEPROM

004aaa930

subsystem vendor ID (L)

subsystem vendor ID (H)

subsystem device ID (L) - OHCI

subsystem device ID (H) - OHCI

subsystem device ID (L) - EHCI

subsystem device ID (H) - EHCI

reserved - FFh

signature 15h - loads subsystem vendor ID, device ID

1Ah - loads default values defined by NXP Semiconductors

address

Product data sheet Rev. 02 — 5 March 2007 32 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

10.2 USB bus states

Reset state — When the USB bus is in the reset state, the USB system is stopped.

Operational state — When the USB bus is in the active state, the USB system is

operating normally.

Suspend state — When the USB bus is in the suspend state, the USB system is

stopped.

Resume state — When the USB bus is in the resume state, the USB system is operating

normally.

11. USB Host Controller registers

Each Host Controller contains a set of on-chip operational registers that are mapped into

uncached memory of the system addressable space. This memory space must begin on a

DWORD (32-bit) boundary. The size of the allocated space is deﬁned by the initial value in

the BAR0 register. HCDs must interact with these registers to implement USB and legacy

support functionality.

After the PCI enumeration driver ﬁnishes the PCI device conﬁguration, the new base

address of these memory-mapped operational registers is deﬁned in BAR0. The HCD can

access these registers by using the address of base address value + offset. Table 42

contains a list of Host Controller registers.

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 02 — 5 March 2007 33 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

Table 42. USB Host Controller registers

Address

(Hex) OHCI register Reset hex value[1] EHCI register

Func0 OHCI1

(2 ports) Func0 OHCI1

(1 port) Func1 OHCI2

(2 ports) Func1 OHCI2

(1 port) Func2 EHCI

(4 ports) Func2 EHCI

(2 ports)

00 HcRevision 0000 0110 0000 0110 0000 0010 0000 0010 0095 000C 0095 000C CAPLENGTH/

HCIVERSION

04 HcControl 0000 0000 0000 0000 0000 0000 0000 0000 0000 2214 0000 2214 HCSPARAMS

08 HcCommandStatus 0000 0000 0000 0000 0000 0000 0000 0000 0000 0012 0000 0012 HCCPARAMS

0C HcInterruptStatus 0000 0000 0000 0000 0000 0000 0000 0000 0008 0000 0008 0000 USBCMD

10 HcInterruptEnable 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 1000 USBSTS

14 HcInterruptDisable 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 USBINTR

18 HcHCCA 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 FRINDEX

1C HcPeriodCurrentED 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CTRLDSSEGMENT

20 HcControlHeadED 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PERIODICLISTBASE

24 HcControlCurrentED 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ASYNCLISTADDR

28 HcBulkHeadED 0000 0000 0000 0000 0000 0000 0000 0000 - - Reserved

2C HcBulkCurrentED 0000 0000 0000 0000 0000 0000 0000 0000 - - Reserved

30 HcDoneHead 0000 0000 0000 0000 0000 0000 0000 0000 - - Reserved

34 HcFmInterval 0000 2EDF 0000 2EDF 0000 2EDF 0000 2EDF - - Reserved

38 HcFmRemaining 0000 0000 0000 0000 0000 0000 0000 0000 - - Reserved

3C HcFmNumber 0000 0000 0000 0000 0000 0000 0000 0000 - - Reserved

40 HcPeriodicStart 0000 0000 0000 0000 0000 0000 0000 0000 - - Reserved

44 HcLSThreshold 0000 0628 0000 0628 0000 0628 0000 0628 - - Reserved

48 HcRhDescriptorA FF00 0902 FF00 0901 FF00 0902 FF00 0901 - - Reserved

4C HcRhDescriptorB 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CONFIGFLAG

50 HcRhStatus 0000 0000 0000 0000 0000 0000 0000 0000 0000 2000 0000 2000 PORTSC1

54 HcRhPortStatus[1] 0000 0000 0000 0000 0000 0000 0000 0000 0000 2000 0000 2000 PORTSC2

58 HcRhPortStatus[2] 0000 0000 - 00000000 - 0000 2000 - PORTSC3

5C Reserved ----0000 2000 - PORTSC4

FF to 60 Reserved -------

100 HceControl 0000 0000 0000 0000 0000 0000 0000 0000 - - -

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Product data sheet Rev. 02 — 5 March 2007 34 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

[1] Reset values that are highlighted (for example, 0) are the ISP1561 implementation speciﬁc reset values, and reset values that are not highlighted (for example, 0) are compliant

with OHCI and EHCI speciﬁcation.

104 HceInput 0000 0000 0000 0000 0000 0000 0000 0000 - - -

108 HceOutput 0000 0000 0000 0000 0000 0000 0000 0000 - - -

10C HceStatus 0000 0000 0000 0000 0000 0000 0000 0000 - - -

Table 42. USB Host Controller registers

…continued

Address

(Hex) OHCI register Reset hex value[1] EHCI register

Func0 OHCI1

(2 ports) Func0 OHCI1

(1 port) Func1 OHCI2

(2 ports) Func1 OHCI2

(1 port) Func2 EHCI

(4 ports) Func2 EHCI

(2 ports)

Product data sheet Rev. 02 — 5 March 2007 35 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

For the OHCI Host Controller, these registers are divided into two types: one set of

operational registers for the USB operation and one set of legacy support registers for the

legacy keyboard and mouse operation.

For the enhanced Host Controller, there are two types of registers: one set of read-only

capability registers and one set of read/write operational registers.

11.1 OHCI USB Host Controller operational registers

OHCI HCDs must communicate with these registers to implement USB data transfers.

Based on their functions, these registers are classiﬁed into four partitions:

•Control and status

•Memory pointer

•Frame counter

•Root hub

11.1.1 HcRevision register (address: content of the base address register + 00h)

[1] X is 1 for OHCI1 (2P) and OHCI1 (1P); X is 0 for OHCI2 (2P) and OHCI2 (1P).

Table 43. HcRevision register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved L

Reset 0000000X

[1]

Access -------R

Bit 76543210

Symbol REV[7:0]

Reset 00010000

Access RRRRRRRR

Product data sheet Rev. 02 — 5 March 2007 36 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.2 HcControl register (address: content of the base address register + 04h)

The HcControl register deﬁnes the operating modes for the Host Controller. All the ﬁelds

in this register, except HCFS and RWC, are modiﬁed only by the HCD. The bit allocation is

given in Table 45.

Table 44. HcRevision register: bit description

Bit Symbol Description

31 to 9 - reserved

8L Legacy:

0 — Does not support legacy devices

1 — Supports legacy keyboard and mouse

7 to 0 REV[7:0] Revision: This read-only ﬁeld contains the BCD representation of the

version of the HCI speciﬁcation that is implemented by this Host

Controller. For example, a value of 11h corresponds to version 1.1. All

of the Host Controller implementations that are compliant with this

speciﬁcation must have a value of 10h.

Table 45. HcControl register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved RWE RWC IR

Reset 00000000

Access -----R/WR/WR/W

Bit 76543210

Symbol HCFS[1:0] BLE CLE IE PLE CBSR[1:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 02 — 5 March 2007 37 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

Table 46. HcControl register: bit description

Bit Symbol Description

31 to 11 - reserved

10 RWE Remote Wake-up Enable: This bit is used by the HCD to enable or

disable the remote wake-up feature on detecting upstream resume

signaling. When this bit and the RD bit in HcInterruptStatus are set, a

remote wake-up is signaled to the host system. Setting this bit has no

impact on the generation of hardware interrupt.

9RWCRemote Wake-up Connected: This bit indicates whether the Host

Controller supports remote wake-up signaling. If remote wake-up is

supported and used by the system, it is the responsibility of the system

ﬁrmware to set this bit during POST. The Host Controller clears the bit on

a hardware reset but does not alter it on a software reset. Remote

wake-up signaling of the host system is host-bus-speciﬁc and is not

described in this speciﬁcation.

8IRInterrupt Routing: This bit determines the routing of interrupts

generated by events registered in HcInterruptStatus. If clear, all

interrupts are routed to the normal host bus interrupt mechanism. If set,

interrupts are routed to the system management interrupt. The HCD

clears this bit on a hardware reset, but it does not alter this bit on a

software reset. The HCD uses this bit as a tag to indicate the ownership

of the Host Controller.

7 to 6 HCFS[1:0] Host Controller Functional State for USB:

00b — USBRESET

01b — USBRESUME

10b — USBOPERATIONAL

11b — USBSUSPEND

A transition to USBOPERATIONAL from another state causes SOF

generation to begin 1 ms later. The HCD may determine whether the

Host Controller has begun sending SOFs by reading the SF ﬁeld of

HcInterruptStatus.

This ﬁeld may be changed by the Host Controller only when in the

USBSUSPEND state. The Host Controller may move from the

USBSUSPEND state to the USBRESUME state after detecting the

resume signaling from a downstream port.

The Host Controller enters USBSUSPEND after a software reset; it

enters USBRESET after a hardware reset. The latter also resets the root

hub and asserts subsequent reset signaling to downstream ports.

5 BLE Bulk List Enable: This bit is set to enable the processing of the bulk list

in the next frame. If cleared by the HCD, processing of the bulk list does

not occur after the next SOF. The Host Controller checks this bit

whenever it wants to process the list. When disabled, the HCD may

modify the list. If HcBulkCurrentED is pointing to an Endpoint Descriptor

(ED) to be removed, the HCD must advance the pointer by updating

HcBulkCurrentED before re-enabling processing of the list.

Product data sheet Rev. 02 — 5 March 2007 38 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.3 HcCommandStatus register (address: content of the base address

The HcCommandStatus register is used by the Host Controller to receive commands

issued by the HCD. It also reﬂects the current status of the Host Controller. To the HCD, it

appears as a “write to set” register. The Host Controller must ensure that bits written as

logic 1 become set in the register while bits written as logic 0 remain unchanged in the

concern for corrupting previously issued commands. The HCD has normal read access to

all bits.

The SOC[1:0] (Scheduling Overrun Count) ﬁeld indicates the number of frames with which

the Host Controller has detected the scheduling overrun error. This occurs when the

periodic list does not complete before EOF. When a scheduling overrun error is detected,

the Host Controller increments the counter and sets the SO (Scheduling Overrun) ﬁeld in

the HcInterruptStatus register. Table 47 shows the bit allocation of the HcCommandStatus

4 CLE Control List Enable: This bit is set to enable the processing of the

control list in the next frame. If cleared by the HCD, processing of the

control list does not occur after the next SOF. The Host Controller must

check this bit whenever it wants to process the list. When disabled, the

HCD may modify the list. If HcControlCurrentED is pointing to an ED to

be removed, the HCD must advance the pointer by updating

HcControlCurrentED before re-enabling processing of the list.

3IEIsochronous Enable: This bit is used by the HCD to enable or disable

processing of isochronous EDs. While processing the periodic list in a

frame, the Host Controller checks the status of this bit when it ﬁnds an

isochronous ED (that is, the Format bit of ED is logic 1; for details, refer

to Ref. 4 “Open Host Controller Interface Speciﬁcation for USB”). If set

(enabled), the Host Controller continues processing EDs. If cleared

(disabled), the Host Controller halts processing of the periodic list, which

now contains only isochronous EDs, and begins processing the bulk or

control lists. Setting this bit is guaranteed to take effect in the next frame

and not the current frame.

2 PLE Periodic List Enable: This bit is set to enable the processing of the

periodic list in the next frame. If cleared by the HCD, processing of the

periodic list does not occur after the next SOF. The Host Controller must

check this bit before it starts processing the list.

1 to 0 CBSR[1:0] Control Bulk Service Ratio: This speciﬁes the service ratio of control

EDs over bulk EDs. Before processing any of the nonperiodic lists, the

Host Controller must compare the ratio speciﬁed with its internal count

on how many nonempty control EDs are processed, in determining

whether to continue serving another control ED or switching to bulk EDs.

The internal count must be retained when crossing the frame boundary.

After a reset, the HCD is responsible for restoring this value.

00b — 1 : 1

01b — 2 : 1

10b — 3 : 1

11b — 4 : 1

Table 46. HcControl register: bit description

…continued

Bit Symbol Description

Product data sheet Rev. 02 — 5 March 2007 39 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

Table 47. HcCommandStatus register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved SOC[1:0]

Reset 00000000

Access ------RR

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset 00000000

Access --------

Bit 76543210

Symbol reserved OCR BLF CLF HCR

Reset 00000000

Access ----R/WR/WR/WR/W

Table 48. HcCommandStatus register: bit description

Bit Symbol Description

31 to 18 - reserved

17 to 16 SOC[1:0] Scheduling Overrun Count: The bit is incremented on each scheduling

overrun error. It is initialized to 00b and wraps around at 11b. It must be

incremented when a scheduling overrun is detected, even if the SO bit in

HcInterruptStatus is already set. This is used by the HCD to monitor any

persistent scheduling problems.

15 to 4 - reserved

3 OCR Ownership Change Request: This bit is set by an OS HCD to request a

change of control of the Host Controller. When set, the Host Controller

must set the OC (Ownership Change) ﬁeld in HcInterruptStatus. After the

changeover, this bit is cleared and remains so until the next request from

the OS HCD.

2 BLF Bulk List Filled: This bit is used to indicate whether there are any

Transfer Descriptors (TDs) on the bulk list. It is set by the HCD whenever

it adds a TD to an ED in the bulk list. When the Host Controller begins to

process the head of the bulk list, it checks Bulk-Filled (BF). If BLF (Bulk

List Filled) is logic 0, the Host Controller does not need to process the

bulk list. If BLF is logic 1, the Host Controller must start processing the

bulk list and set BF to logic 0. If the Host Controller ﬁnds a TD on the list,

then the Host Controller must set BLF to logic 1, causing the bulk list

processing to continue. If no TD is found on the bulk list, and if the HCD

does not set BLF, then BLF is still logic 0 when the Host Controller

completes processing the bulk list and the bulk list processing stops.

Product data sheet Rev. 02 — 5 March 2007 40 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.4 HcInterruptStatus register (address: content of the base address register +

0Ch)

This is a 4-byte register that provides the status of the events that cause hardware

interrupts. The bit allocation of the register is given in Table 49. When an event occurs, the

Host Controller sets the corresponding bit in this register. When a bit becomes set, a

hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register

(see Table 51) and the MIE (Master Interrupt Enable) bit is set. The HCD may clear

speciﬁc bits in this register by writing logic 1 to the bit positions to be cleared. The HCD

may not set any of these bits. The Host Controller does not clear the bit.

1 CLF Control List Filled: This bit is used to indicate whether there are any TDs

on the control list. It is set by the HCD whenever it adds a TD to an ED in

the control list.

When the Host Controller begins to process the head of the control list, it

checks CLF. If CLF is logic 0, the Host Controller does not need to

process the control list. If Control-Filled (CF) is logic 1, the Host Controller

must start processing the control list and set CLF to logic 0. If the Host

Controller ﬁnds a TD on the list, then the Host Controller must set CLF to

logic 1, causing the control list processing to continue. If no TD is found

on the control list, and if the HCD does not set CLF, then CLF is still

logic 0 when the Host Controller completes processing the control list and

the control list processing stops.

0 HCR Host Controller Reset: This bit is set by the HCD to initiate a software

reset of the Host Controller. Regardless of the functional state of the Host

Controller, it moves to the USBSUSPEND state in which most of the

operational registers are reset, except those stated otherwise; for

example, the IR (Interrupt Routing) ﬁeld of HcControl, and no host bus

accesses are allowed. This bit is cleared by the Host Controller on

completing the reset operation. The reset operation must be completed

within 10 µs. This bit, when set, must not cause a reset to the root hub

and no subsequent reset signaling must be asserted to its downstream

ports.

Table 48. HcCommandStatus register: bit description

…continued

Bit Symbol Description

Table 49. HcInterruptStatus register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved OC reserved

Reset 00000000

Access -R/W------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset 00000000

Access --------

Product data sheet Rev. 02 — 5 March 2007 41 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.5 HcInterruptEnable register (address: content of the base address register +

10h)

Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt

bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control

which events generate a hardware interrupt. If the following conditions occur:

•A bit is set in the HcInterruptStatus register.

•The corresponding bit in the HcInterruptEnable register is set.

•The MIE (Master Interrupt Enable) bit is set.

Bit 76543210

Symbol reserved RHSC FNO UE RD SF WDH SO

Reset 00000000

Access - R/W R/W R/W R/W R/W R/W R/W

Table 50. HcInterruptStatus register: bit description

Bit Symbol Description

31 - reserved

30 OC Ownership Change: This bit is set by the Host Controller when HCD

sets the OCR (Ownership Change Request) ﬁeld in

HcCommandStatus. This event, when unmasked, will always

immediately generate a System Management Interrupt (SMI). This bit

is forced to logic 0 when the SMI# pin is not implemented.

29 to 7 - reserved

6 RHSC Root Hub Status Change: This bit is set when the content of

HcRhStatus or the content of any of

HcRhPortStatus[NumberofDownstreamPort] has changed.

5 FNO Frame Number Overﬂow: This bit is set when the Most Signiﬁcant Bit

(MSB) of HcFmNumber (bit 15) changes value, or after the

HccaFrameNumber is updated.

4UEUnrecoverable Error: This bit is set when the Host Controller detects

a system error not related to USB. The Host Controller must not

proceed with any processing nor signaling before the system error is

corrected. The HCD clears this bit after the Host Controller is reset.

3RDResume Detected: This bit is set when the Host Controller detects

that a device on the USB is asserting resume signaling. It is the

transition from no resume signaling to resume signaling causing this

bit to be set. This bit is not set when the HCD sets the USBRESUME

state.

2SFStart-of-Frame: At the start of each frame, this bit is set by the Host

Controller and an SOF token is generated at the same time.

1 WDH Write-back Done Head: This bit is immediately set after the Host

Controller has written HcDoneHead to HccaDoneHead. Further,

updates of HccaDoneHead occur only after this bit is cleared. The

HCD must only clear this bit after it has saved the content of

HccaDoneHead.

0SOScheduling Overrun: This bit is set when USB schedules for current

frame overruns and after the update of HccaFrameNumber. A

scheduling overrun causes the SOC (Scheduling Overrun Count) of

HcCommandStatus to be incremented.

Product data sheet Rev. 02 — 5 March 2007 42 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

Then, a hardware interrupt is requested on the host bus.

Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to

a bit in this register leaves the corresponding bit unchanged. On a read, the current value

of this register is returned.

The bit allocation is given in Table 51.

Table 51. HcInterruptEnable register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol MIE OC reserved

Reset 00000000

Access R/WR/W------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset 00000000

Access --------

Bit 76543210

Symbol reserved RHSC FNO UE RD SF WDH SO

Reset 00000000

Access - R/W R/W R/W R/W R/W R/W R/W

Table 52. HcInterruptEnable register: bit description

Bit Symbol Description

31 MIE Master Interrupt Enable:

0 — Ignore

1 — Enables interrupt generation by events speciﬁed in other bits of

this register

30 OC Ownership Change:

0 — Ignore

1 — Enables interrupt generation because of ownership change

29 to 7 - reserved

6 RHSC Root Hub Status Change:

0 — Ignore

1 — Enables interrupt generation because of root hub status change

5 FNO Frame Number Overﬂow:

0 — Ignore

1 — Enables interrupt generation because of frame number overﬂow

4UEUnrecoverable Error:

0 — Ignore

1 — Enables interrupt generation because of unrecoverable error

Product data sheet Rev. 02 — 5 March 2007 43 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.6 HcInterruptDisable register (address: content of the base address register +

14h)

Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt

bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the

HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the

corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this

read, the current value of the HcInterruptEnable register is returned. The register contains

4 bytes, and the bit allocation is given in Table 53.

3RDResume Detect:

0 — Ignore

1 — Enables interrupt generation because of resume detect

2SFStart-of-Frame:

0 — Ignore

1 — Enables interrupt generation because of Start-of-Frame

1 WDH HcDoneHead Write-back:

0 — Ignore

1 — Enables interrupt generation because of HcDoneHead write-back

0SOScheduling Overrun:

0 — Ignore

1 — Enables interrupt generation because of scheduling overrun

Table 52. HcInterruptEnable register: bit description

…continued

Bit Symbol Description

Table 53. HcInterruptDisable register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol MIE OC reserved

Reset 00000000

Access R/WR/W------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset 00000000

Access --------

Bit 76543210

Symbol reserved RHSC FNO UE RD SF WDH SO

Reset 00000000

Access - R/W R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 02 — 5 March 2007 44 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.7 HcHCCA register (address: content of the base address register + 18h)

The HcHCCA register contains the physical address of Host Controller Communication

Area (HCCA). The bit allocation is given in Table 55. The HCD determines alignment

restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The

alignment is evaluated by examining the number of zeroes in the lower order bits. The

minimum alignment is 256 bytes; therefore, bits 0 through 7 will always return logic 0

when read. This area is used to hold control structures and the Interrupt table that are

accessed by both the Host Controller and the HCD.

Table 54. HcInterruptDisable register: bit description

Bit Symbol Description

31 MIE Master Interrupt Enable:

0 — Ignore

1 — Disables interrupt generation because of events speciﬁed in other

bits of this register.

This ﬁeld is set after a hardware or software reset. Interrupts are

disabled.

30 OC Ownership Change:

0 — Ignore

1 — Disables interrupt generation because of ownership change

29 to 7 - reserved

6 RHSC Root Hub Status Change:

0 — Ignore

1 — Disables interrupt generation because of root hub status change

5 FNO Frame Number Overﬂow:

0 — Ignore

1 — Disables interrupt generation because of frame number overﬂow

4UEUnrecoverable Error:

0 — Ignore

1 — Disables interrupt generation because of unrecoverable error

3RDResume Detect:

0 — Ignore

1 — Disables interrupt generation because of resume detect

2SFStart-of-Frame:

0 — Ignore

1 — Disables interrupt generation because of Start-of-Frame

1 WDH HcDoneHead Write-back:

0 — Ignore

1 — Disables interrupt generation because of HcDoneHead

write-back

0SOScheduling Overrun:

0 — Ignore

1 — Disables interrupt generation because of scheduling overrun

Product data sheet Rev. 02 — 5 March 2007 45 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.8 HcPeriodCurrentED register (address: content of the base address

The HcPeriodCurrentED register contains the physical address of the current isochronous

or interrupt ED. Table 57 gives the bit allocation of the register.

Table 55. HcHCCA register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol HCCA[23:16]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 23 22 21 20 19 18 17 16

Symbol HCCA[15:8]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol HCCA[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol reserved

Reset 00000000

Access --------

Table 56. HcHCCA register: bit description

Bit Symbol Description

31 to 8 HCCA[23:0] Host Controller Communication Area Base Address: This is the base

address of the HCCA.

7 to 0 - reserved

Table 57. HcPeriodCurrentED register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol PCED[27:20]

Reset 00000000

Access RRRRRRRR

Bit 23 22 21 20 19 18 17 16

Symbol PCED[19:12]

Reset 00000000

Access RRRRRRRR

Bit 15 14 13 12 11 10 9 8

Symbol PCED[11:4]

Reset 00000000

Access RRRRRRRR

Product data sheet Rev. 02 — 5 March 2007 46 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.9 HcControlHeadED register (address: content of the base address register +

20h)

The HcControlHeadED register contains the physical address of the ﬁrst ED of the control

list. The bit allocation is given in Table 59.

Bit 76543210

Symbol PCED[3:0] reserved

Reset 00000000

Access RRRR----

Table 58. HcPeriodCurrentED register: bit description

Bit Symbol Description

31 to 4 PCED[27:0] Period Current ED: This is used by the Host Controller to point to the

head of one of the periodic lists that must be processed in the current

Frame. The content of this register is updated by the Host Controller after

a periodic ED has been processed. The HCD may read the content in

determining which ED is currently being processed at the time of reading.

3 to 0 - reserved

Table 59. HcControlHeadED register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol CHED[27:20]

Reset 00000000

Access RRRRRRRR

Bit 23 22 21 20 19 18 17 16

Symbol CHED[19:12]

Reset 00000000

Access RRRRRRRR

Bit 15 14 13 12 11 10 9 8

Symbol CHED[11:4]

Reset 00000000

Access RRRRRRRR

Bit 76543210

Symbol CHED[3:0] reserved

Reset 00000000

Access RRRR----

Table 60. HcControlHeadED register: bit description

Bit Symbol Description

31 to 4 CHED[27:0] Control Head ED: The Host Controller traverses the control list,

starting with the HcControlHeadED pointer. The content is loaded

from HCCA during the initialization of the Host Controller.

3 to 0 - reserved

Product data sheet Rev. 02 — 5 March 2007 47 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.10 HcControlCurrentED register (address: content of the base address

The HcControlCurrentED register contains the physical address of the current ED of the

control list. The bit allocation is given in Table 61.

11.1.11 HcBulkHeadED register (address: content of the base address register +

28h)

This is a 4-byte register, and the bit allocation is given in Table 63. The register contains

the physical address of the ﬁrst ED of the bulk list.

Table 61. HcControlCurrentED register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol CCED[27:20]

Reset 00000000

Access RRRRRRRR

Bit 23 22 21 20 19 18 17 16

Symbol CCED[19:12]

Reset 00000000

Access RRRRRRRR

Bit 15 14 13 12 11 10 9 8

Symbol CCED[11:4]

Reset 00000000

Access RRRRRRRR

Bit 76543210

Symbol CCED[3:0] reserved

Reset 00000000

Access RRRR----

Table 62. HcControlCurrentED register: bit description

Bit Symbol Description

31 to 4 CCED[27:0] Control Current ED: This pointer is advanced to the next ED after serving

the present. The Host Controller must continue processing the list from

where it left off in the last frame. When it reaches the end of the control list,

the Host Controller checks the CLF (Control List Filled) bit of

HcCommandStatus. If set, it copies the content of HcControlHeadED to

HcControlCurrentED and clears the bit. If not set, it does nothing. The

HCD is allowed to modify this register only when the CLE (Control List

Enable) bit of HcControl is cleared. When set, the HCD only reads the

instantaneous value of this register. Initially, this is set to logic 0 to indicate

the end of the control list.

3 to 0 - reserved

Table 63. HcBulkHeadED register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol BHED[27:20]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 02 — 5 March 2007 48 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.12 HcBulkCurrentED register (address: content of the base address register +

2Ch)

This register contains the physical address of the current endpoint of the bulk list.

Endpoints are ordered according to their insertion to the list because the bulk list must be

served in a round-robin fashion. The bit allocation is given in Table 65.

Bit 23 22 21 20 19 18 17 16

Symbol BHED[19:12]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol BHED[11:4]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol BHED[3:0] reserved

Reset 00000000

Access R/WR/WR/WR/W----

Table 64. HcBulkHeadED register: bit description

Bit Symbol Description

31 to 4 BHED[27:0] Bulk Head ED: The Host Controller traverses the bulk list starting

with the HcBulkHeadED pointer. The content is loaded from HCCA

during the initialization of the Host Controller.

3 to 0 - reserved

Table 65. HcBulkCurrentED register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol BCED[27:20]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 23 22 21 20 19 18 17 16

Symbol BCED[19:12]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol BCED[11:4]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol BCED[3:0] reserved

Reset 00000000

Access R/WR/WR/WR/W----

Product data sheet Rev. 02 — 5 March 2007 49 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.13 HcDoneHead register (address: content of the base address register + 30h)

The HcDoneHead register contains the physical address of the last completed TD that

was added to the done queue. In a normal operation, the HCD need not read this register

because its content is periodically written to the HCCA. Table 67 contains the bit allocation

of the register.

Table 66. HcBulkCurrentED register: bit description

Bit Symbol Description

31 to 4 BCED[27:0] Bulk Current ED: This is advanced to the next ED after the Host

Controller has served the present ED. The Host Controller continues

processing the list from where it left off in the last frame. When it reaches

the end of the bulk list, the Host Controller checks the CLF (Control List

Filled) bit of HcControl. If the CLF bit is not set, nothing is done. If the CLF

bit is set, it copies the content of HcBulkHeadED to HcBulkCurrentED and

clears the CLF bit. The HCD can only modify this register when the BLE

(Bulk List Enable) bit of HcControl is cleared. When HcControl is set, the

HCD reads the instantaneous value of this register. This is initially set to

logic 0 to indicate the end of the bulk list.

3 to 0 - reserved

Table 67. HcDoneHead register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol DH[27:20]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 23 22 21 20 19 18 17 16

Symbol DH[19:12]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol DH[11:4]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol DH[3:0] reserved

Reset 00000000

Access R/WR/WR/WR/W----

Table 68. HcDoneHead register: bit description

Bit Symbol Description

31 to 4 DH[27:0] Done Head: When a TD is completed, the Host Controller writes the

content of HcDoneHead to the NextTD ﬁeld of the TD. The Host

Controller then overwrites the content of HcDoneHead with the

address of this TD. This is set to logic 0 whenever the Host Controller

writes the content of this register to HCCA.

3 to 0 - reserved

Product data sheet Rev. 02 — 5 March 2007 50 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.14 HcFmInterval register (address: content of the base address register + 34h)

The HcFmInterval register contains a 14-bit value that indicates the bit time interval in a

frame, that is, between two consecutive SOFs, and a 15-bit value indicating the full-speed

maximum packet size that the Host Controller may transmit or receive, without causing a

scheduling overrun. The HCD may carry out minor adjustment on the FI (Frame Interval)

by writing a new value over the present at each SOF. This provides the possibility for the

Host Controller to synchronize with an external clocking resource and to adjust any

unknown local clock offset. The bit allocation of the register is given in Table 69.

Table 69. HcFmInterval register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol FIT FSMPS[14:8]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 23 22 21 20 19 18 17 16

Symbol FSMPS[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol reserved FI[13:8]

Reset 00101110

Access - - R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol FI[7:0]

Reset 11011111

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 70. HcFmInterval register: bit description

Bit Symbol Description

31 FIT Frame Interval Toggle: The HCD toggles this bit whenever it loads

a new value to Frame Interval.

30 to 16 FSMPS[14:0] FS Largest Data Packet: This ﬁeld speciﬁes a value that is loaded

into the largest data packet counter at the beginning of each frame.

The counter value represents the largest amount of data in bits that

can be sent or received by the Host Controller in a single

transaction at any given time, without causing a scheduling

overrun. The ﬁeld value is calculated by the HCD.

15 to 14 - reserved

13 to 0 FI[13:0] Frame Interval: This speciﬁes the interval between two

consecutive SOFs in bit times. The nominal value is set to 11,999.

The HCD must store the current value of this ﬁeld before resetting

the Host Controller because this causes the ﬁeld to be reset the

nominal value. The HCD can then restore the stored value on

completing the reset sequence.

Product data sheet Rev. 02 — 5 March 2007 51 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.15 HcFmRemaining register (address: content of the base address register +

38h)

The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in

the current frame. Table 71 contains the bit allocation of this four-byte register.

11.1.16 HcFmNumber register (address: content of the base address register + 3Ch)

This register is a 16-bit counter, and the bit allocation is given in Table 73. It provides a

timing reference among events happening in the Host Controller and the HCD. The HCD

may use the 16-bit value speciﬁed in this register and generate a 32-bit frame number

without requiring frequent access to the register.

Table 71. HcFmRemaining register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol FRT reserved

Reset 00000000

Access R/W-------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved FR[13:8]

Reset 00000000

Access - - R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol FR[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 72. HcFmRemaining register: bit description

Bit Symbol Description

31 FRT Frame Remaining Toggle: This bit is loaded from the FIT (Frame Interval

Toggle) ﬁeld of HcFmInterval whenever FR (Frame Remaining) reaches 0.

This bit is used by the HCD for the synchronization between FI (Frame

Interval) and FR.

30 to 14 - reserved

13 to 0 FR[13:0] Frame Remaining: This counter is decremented at each bit time. When it

reaches 0, it is reset by loading the FI value speciﬁed in HcFmInterval at

the next bit time boundary. When entering the USBOPERATIONAL state,

the Host Controller reloads the content with the FI of HcFmInterval and

uses the updated value from the next SOF.

Table 73. HcFmNumber register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Product data sheet Rev. 02 — 5 March 2007 52 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.17 HcPeriodicStart register (address: content of the base address register +

40h)

The HcPeriodicStart register has a 14-bit programmable value that determines when is

the earliest time for the Host Controller to start processing the periodic list. The bit

allocation is given in Table 75.

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved FN[13:8]

Reset 00000000

Access - - R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol FN[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 74. HcFmNumber register: bit description

Bit Symbol Description

31 to 14 - reserved

13 to 0 FN[13:0] Frame Number: Incremented when HcFmRemaining is re-loaded. It

must be rolled over to 0h after FFFFh. Automatically incremented when

entering the USBOPERATIONAL state. The content is written to HCCA

after the Host Controller has incremented Frame Number at each frame

boundary and sent a SOF but before the Host Controller reads the ﬁrst

ED in that frame. After writing to HCCA, the Host Controller sets the SF

(Start-of-Frame) in HcInterruptStatus.

Table 75. HcPeriodicStart register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved P_S[13:8]

Reset 00000000

Access - - R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 02 — 5 March 2007 53 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.18 HcLSThreshold register (address: content of the base address register +

44h)

This register contains an 11-bit value used by the Host Controller to determine whether to

commit to the transfer of a maximum of 8-byte low-speed packet before EOF. Neither the

Host Controller nor the HCD can change this value. The bit allocation of the

HcLSThreshold register is given in Table 77.

Bit 76543210

Symbol P_S[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 76. HcPeriodicStart register: bit description

Bit Symbol Description

31 to 14 - reserved

13 to 0 P_S[13:0] Periodic Start: After a hardware reset, this ﬁeld is cleared. It is then set

by the HCD during the Host Controller initialization. The value is

calculated roughly as 10 % of the HcFmInterval. A typical value is 3E67h.

When HcFmRemaining reaches the value speciﬁed, processing of the

periodic lists have priority over control or bulk processing. The Host

Controller, therefore, starts processing the interrupt list after completing

the current control or bulk transaction that is in progress.

Table 77. HcLSThreshold register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved LST[11:8]

Reset 00000110

Access ----R/WR/WR/WR/W

Bit 76543210

Symbol LST[7:0]

Reset 00101000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 02 — 5 March 2007 54 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.19 HcRhDescriptorA register (address: content of the base address register +

48h)

The HcRhDescriptorA register is the ﬁrst of two registers describing the characteristics of

the root hub. Reset values are implementation-speciﬁc.

Table 79 contains the bit allocation of the HcRhDescriptorA register.

[1] X is 1 for OHCI1 (2P) and OHCI2 (2P); X is 0 for OHCI1 (1P) and OHCI2 (1P).

[2] X is 0 for OHCI1 (2P) and OHCI2 (2P); X is 1 for OHCI1 (1P) and OHCI2 (1P).

Table 78. HcLSThreshold register: bit description

Bit Symbol Description

31 to 12 - reserved

11 to 0 LST[11:0] LS Threshold: This ﬁeld contains a value that is compared to the FR

(Frame Remaining) ﬁeld prior to initiating a low-speed transaction.

The transaction is started only if FR ≥ this ﬁeld. The value is

calculated by the HCD, considering the transmission and set-up

overhead.

Table 79. HcRhDescriptorA register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol POTPGT[7:0]

Reset 11111111

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved NOCP OCPM DT NPS PSM

Reset 00001001

Access - - - R/W R/W R R/W R/W

Bit 76543210

Symbol NDP[7:0]

Reset 000000X

[1] X[2]

Access RRRRRRRR

Product data sheet Rev. 02 — 5 March 2007 55 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.20 HcRhDescriptorB register (address: content of the base address register +

4Ch)

The HcRhDescriptorB register is the second of two registers describing the characteristics

of the root hub. The bit allocation is given in Table 81. These ﬁelds are written during

initialization to correspond with the system implementation. Reset values are

implementation-speciﬁc.

Table 80. HcRhDescriptorA register: bit description

Bit Symbol Description

31 to 24 POTPGT[7:0] Power On To Power Good Time: This byte speciﬁes the duration the

HCD must wait before accessing a powered-on port of the root hub. It is

implementation-speciﬁc. The unit of time is 2 ms. The duration is

calculated as POTPGT × 2ms.

23 to 13 - reserved

12 NOCP No Overcurrent Protection: This bit describes how the overcurrent

status for root hub ports are reported. When this bit is cleared, the

OCPM (Overcurrent Protection Mode) ﬁeld speciﬁes global or per-port

reporting.

0 — Overcurrent status is reported collectively for all downstream ports

1 — No overcurrent protection supported

11 OCPM Overcurrent Protection Mode: This bit describes how the overcurrent

status for root hub ports are reported. At reset, this ﬁelds reﬂects the

same mode as Power Switching Mode. This ﬁeld is valid only if the

NOCP ﬁeld is cleared.

0 — Overcurrent status is collectively reported for all downstream ports

1 — Overcurrent status is reported on a per-port basis

10 DT Device Type: This bit speciﬁes that the root hub is not a compound

device. The root hub is not permitted to be a compound device. This

ﬁeld must always read 0.

9 NPS No Power Switching: This bit is used to specify whether power

switching is supported or ports are always powered. It is

implementation-speciﬁc. When this bit is cleared, the PSM (Power

Switching Mode) ﬁeld speciﬁes global or per-port switching.

0 — Ports are power switched

1 — Ports are always powered on when the Host Controller is powered

8 PSM Power Switching Mode: This bit is used to specify how the power

switching of root hub ports is controlled. It is implementation-speciﬁc.

This ﬁeld is only valid if the NPS ﬁeld is cleared.

0 — All ports are powered at the same time.

1 — Each port is powered individually. This mode allows port power to

be controlled by either the global switch or per-port switching. If the

PPCM (Port Power Control Mask) bit is set, the port responds only to

port power commands (Set/Clear Port Power). If the port mask is

cleared, then the port is controlled only by the global power switch

(Set/Clear Global Power).

7 to 0 NDP[7:0] Number Downstream Ports: These bits specify the number of

downstream ports supported by the root hub. It is

implementation-speciﬁc. The minimum number of ports is 1. The

maximum number of ports supported by OHCI is 15.

Product data sheet Rev. 02 — 5 March 2007 56 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.21 HcRhStatus register (address: content of the base address register + 50h)

The HcRhStatus register is divided into two parts. The lower word of a DWORD

represents the Hub Status ﬁeld and the upper word represents the Hub Status Change

ﬁeld. Reserved bits must always be written as logic 0. Table 83 contains the bit allocation

of the register.

Table 81. HcRhDescriptorB register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol PPCM[15:8]

Reset 00000000

Access R/W R/W R/W R/W R R/W R/W R/W

Bit 23 22 21 20 19 18 17 16

Symbol PPCM[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol DR[15:8]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol DR[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 82. HcRhDescriptorB register: bit description

Bit Symbol Description

31 to 16 PPCM[15:0] Port Power Control Mask: Each bit indicates whether a port is

affected by a global power control command when Power Switching

Mode is set. When set, the power state of the port is only affected

by per-port power control (Set/Clear Port Power).When cleared, the

port is controlled by the global power switch (Set/Clear Global

Power). If the device is conﬁgured to global switching mode (Power

Switching Mode = 0), this ﬁeld is not valid.

Bit 0 — reserved

Bit 1 — Ganged-power mask on port #1

Bit 2 — Ganged-power mask on port #2

15 to 0 DR[15:0] Device Removable: Each bit is dedicated to a port of the root hub.

When cleared, the attached device is removable. When set, the

attached device is not removable.

Bit 0 — reserved

Bit 1 — Device attached to port #1

Bit 2 — Device attached to port #2

Product data sheet Rev. 02 — 5 March 2007 57 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

Table 83. HcRhStatus register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol CRWE reserved

Reset 00000000

Access R/W-------

Bit 23 22 21 20 19 18 17 16

Symbol reserved CCIC LPSC

Reset 00000000

Access ------R/WR/W

Bit 15 14 13 12 11 10 9 8

Symbol DRWE reserved

Reset 00000000

Access R/W-------

Bit 76543210

Symbol reserved OCI LPS

Reset 00000000

Access ------RRW

Table 84. HcRhStatus register: bit description

Bit Symbol Description

31 CRWE On write Clear Remote Wake-up Enable: Writing logic 1 clears DRWE

(Device Remote Wake-up Enable). Writing logic 0 has no effect.

30 to 18 - reserved

17 CCIC Overcurrent Indicator Change: This bit is set by hardware when a change

has occurred to the OCI (Overcurrent Indicator) ﬁeld of this register. The HCD

clears this bit by writing logic 1. Writing logic 0 has no effect.

16 LPSC On read Local Power Status Change: The root hub does not support the

local power status feature. Therefore, this bit is always logic 0.

On write Set Global Power: In global power mode (Power Switching Mode =

0), logic 1 is written to this bit to turn on power to all ports (clear Port Power

Status). In per-port power mode, it sets Port Power Status only on ports

whose Port Power Control Mask bit is not set. Writing logic 0 has no effect.

15 DRWE On read Device Remote Wake-up Enable: This bit enables the Connect

Status Change bit as a resume event, causing a state transition

USBSUSPEND to USBRESUME and setting the Resume Detected interrupt.

0 — Connect Status Change is not a remote wake-up event

1 — Connect Status Change is a remote wake-up event

On write Set Remote Wake-up Enable: Writing logic 1 sets DRWE (Device

Remote Wake-up Enable). Writing logic 0 has no effect.

Product data sheet Rev. 02 — 5 March 2007 58 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.1.22 HcRhPortStatus[1:4] register (address: content of the base address

The HcRhPortStatus[1:4] register is used to control and report port events on a per-port

basis. NumberofDownstreamPort represents the number of HcRhPortStatus registers that

are implemented in hardware. The lower word reﬂects the port status. The upper word

reﬂects status change bits. Some status bits are implemented with special write behavior.

If a transaction, token through handshake, is in progress when a write to change port

status occurs, the resulting port status change is postponed until the transaction

completes. Always write logic 0 to the reserved bits. The bit allocation of the register is

given in Table 85.

14 to 2 - reserved

1 OCI Overcurrent Indicator: This bit reports overcurrent conditions when global

reporting is implemented. When set, an overcurrent condition exists. When

cleared, all power operations are normal. If the per-port overcurrent protection

is implemented, this bit is always logic 0.

0 LPS On read Local Power Status: The root hub does not support the local power

status feature. Therefore, this bit is always read as logic 0.

On write Clear Global Power: In global power mode (Power Switching

Mode = 0), logic 1 is written to this bit to turn off power to all ports (clear Port

Power Status). In per-port power mode, it clears Port Power Status only on

ports whose Port Power Control Mask bit is not set. Writing logic 0 has no

effect.

Table 84. HcRhStatus register: bit description

…continued

Bit Symbol Description

Table 85. HcRhPortStatus[1:4] register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved PRSC OCIC PSSC PESC CSC

Reset 00000000

Access - - - R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol reserved LSDA PPS

Reset 00000000

Access ------R/WR/W

Bit 76543210

Symbol reserved PRS POCI PSS PES CCS

Reset 00000000

Access - - - R/W R/W R/W R/W R/W

Product data sheet Rev. 02 — 5 March 2007 59 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

Table 86. HCRhPortStatus[1:4] register: bit description

Bit Symbol Description

31 to 21 - reserved

20 PRSC Port Reset Status Change: This bit is set at the end of the 10 ms port reset

signal. The HCD can write logic 1 to clear this bit. Writing logic 0 has no

effect.

0 — Port reset is not complete

1 — Port reset is complete

19 OCIC Port Overcurrent Indicator Change: This bit is valid only if overcurrent

conditions are reported on a per-port basis. This bit is set when the root hub

changes the POCI (Port Overcurrent Indicator) bit. The HCD can write logic 1

to clear this bit. Writing logic 0 has no effect.

0 — No change in Port Overcurrent Indicator

1 — POCI has changed

18 PSSC Port Suspend Status Change: This bit is set when the full resume

sequence is completed. This sequence includes the 20 ms resume pulse, LS

EOP and 3 ms re-synchronization delay. The HCD can write logic 1 to clear

this bit. Writing logic 0 has no effect. This bit is also cleared when Reset

Status Change is set.

0 — Resume is not completed

1 — Resume is completed

17 PESC Port Enable Status Change: This bit is set when hardware events cause the

PES (Port Enable Status) bit to be cleared. Changes from the HCD writes do

not set this bit. The HCD can write logic 1 to clear this bit. Writing logic 0 has

no effect.

0 — No change in PES

1 — Change in PES

16 CSC Connect Status Change: This bit is set whenever a connect or disconnect

event occurs. The HCD can write logic 1 to clear this bit. Writing logic 0 has

no effect. If CCS (Current Connect Status) is cleared when a Set Port Reset,

Set Port Enable or Set Port Suspend write occurs, this bit is set to force the

driver to re-evaluate the connection status because these writes must not

occur if the port is disconnected.

0 — No change in CCS

1 — Change in CCS

Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a

root hub reset to inform the system that the device is attached.

15 to 10 - reserved

9 LSDA On read Low-speed Device Attached: This bit indicates the speed of the

device attached to this port. When set, a low-speed device is attached to this

port. When cleared, a full-speed device is attached to this port. This ﬁeld is

valid only when the CCS is set.

0 — Port is not suspended

1 — Port is suspended

On write Clear Port Power: The HCD can clear the PPS (Port Power Status)

bit by writing logic 1 to this bit. Writing logic 0 has no effect.

Product data sheet Rev. 02 — 5 March 2007 60 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

8 PPS On read Port Power Status: This bit reﬂects the port power status,

regardless of the type of power switching implemented. This bit is cleared if

an overcurrent condition is detected. The HCD can set this bit by writing Set

Port Power or Set Global Power. The HCD can clear this bit by writing Clear

Port Power or Clear Global Power. Power Switching Mode and

PortPowerControlMask[NDP] determine which power control switches are

enabled. In Global Switching mode (Power Switching Mode = 0), only

Set/Clear Global Power controls this bit. In the per-port power switching

(Power Switching Mode = 1), if the PortPowerControlMask[NDP] bit for the

port is set, only Set/Clear Port Power commands are enabled. If the mask is

not set, only Set/Clear Global Power commands are enabled.

When port power is disabled, CCS (Current Connect Status), PES (Port

Enable Status), PSS (Port Suspend Status) and PRS (Port Reset Status)

must be reset.

0 — Port power is off

1 — Port power is on

On write Set Port Power: The HCD can write logic 1 to set the PPS (Port

Power Status) bit. Writing logic 0 has no effect.

Remark: This bit always reads logic1 if power switching is not supported.

7 to 5 - reserved

4 PRS On read Port Reset Status: When this bit is set by a write to Set Port Reset,

port reset signaling is asserted. When reset is completed and PRSC (Port

Reset Status Change) is set, this bit is cleared.

0 — Port reset signal is not active

1 — Port reset signal is active

On write Set Port Reset: The HCD can set the port reset signaling by writing

logic 1 to this bit. Writing logic 0 has no effect. If CCS is cleared, this write

does not set PRS (Port Reset Status) but instead sets CCS. This informs the

driver that it attempted to reset a disconnected port.

3 POCI On read Port Overcurrent Indicator: This bit is valid only when the root hub

is conﬁgured to show overcurrent conditions are reported on a per-port basis.

If the per-port overcurrent reporting is not supported, this bit is set to logic 0.

If cleared, all power operations are normal for this port. If set, an overcurrent

condition exists on this port.

0 — No overcurrent condition

1 — Overcurrent condition detected

On write Clear Suspend Status: The HCD can write logic 1 to initiate a

resume. Writing logic 0 has no effect. A resume is initiated only if PSS (Port

Suspend Status) is set.

Table 86. HCRhPortStatus[1:4] register: bit description

…continued

Bit Symbol Description

Product data sheet Rev. 02 — 5 March 2007 61 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.2 USB legacy support registers

The ISP1561 supports legacy keyboard and mouse. Four operational registers are used

to provide the legacy support. Each of these registers is located on a 32-bit boundary. The

offset of these registers is relative to the base address of the Host Controller operational

registers with HceControl located at offset 100h.

2 PSS On read Port Suspend Status: This bit indicates whether the port is

suspended or is in the resume sequence. It is set by a Set Suspend State

write and cleared when PSSC (Port Suspend Status Change) is set at the

end of the resume interval. This bit is not set if CCS (Current Connect Status)

is cleared. This bit is also cleared when PRSC (Port Reset Status Change) is

set at the end of the port reset or when the Host Controller is placed in the

USBRESUME state. If an upstream resume is in progress, it will propagate to

the Host Controller.

0 — Port is not suspended

1 — Port is suspended

On write Set Port Suspend: The HCD can set the PSS (Port Suspend

Status) bit by writing logic 1 to this bit. Writing logic 0 has no effect. If CCS is

cleared, this write does not set PSS; instead it sets CSS. This informs the

driver that it attempted to suspend a disconnected port.

1 PES On read Port Enable Status: This bit indicates whether the port is enabled

or disabled. The root hub may clear this bit when an overcurrent condition,

disconnect event, switched-off power or operational bus error is detected.

This change also causes Port Enabled Status Change to be set. The HCD

can set this bit by writing Set Port Enable and clear it by writing Clear Port

Enable. This bit cannot be set when CCS (Current Connect Status) is

cleared. This bit is also set on completing a port reset when Reset Status

Change is set or on completing a port suspend when Suspend Status

Change is set.

0 — Port is disabled

1 — Port is enabled

On write Set Port Enable: The HCD can set PES (Port Enable Status) by

writing logic 1. Writing logic 0 has no effect. If CCS is cleared, this write does

not set PES, but instead sets CSC (Connect Status Change). This informs

the driver that it attempted to enable a disconnected port.

0 CCS On read Current Connect Status: This bit reﬂects the current state of the

downstream port.

0 — No device connected

1 — Device connected

On write Clear Port Enable: The HCD can write logic 1 to this bit to clear the

PES (Port Enable Status) bit. Writing logic 0 has no effect. The CCS (Current

Connect Status) bit, on read, is not affected by any write to Clear Port

Enable.

Remark: This bit always reads logic 1 when the attached device is

nonremovable (DeviceRemoveable[NDP]).

Table 86. HCRhPortStatus[1:4] register: bit description

…continued

Bit Symbol Description

Product data sheet Rev. 02 — 5 March 2007 62 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.2.1 HceControl register (address: content of the base address register + 100h)

Table 89 shows the bit allocation of the register.

Table 87. Legacy support registers

Offset Register Description

100h HceControl used to enable and control the emulation hardware and report various

status information

104h HceInput emulation of the legacy Input Buffer register

108h HceOutput emulation of the legacy Output Buffer register in which the software

writes keyboard and mouse data

10Ch HceStatus emulation of the legacy Status register

Table 88. Emulated registers

I/O

address Cycle

type Register Contents

accessed or modiﬁed Side effects

60h IN HceOutput IN from port 60h sets OUT_FULL (bit 0) in HceStatus

to logic 0

60h OUT HceInput OUT to port 60h sets IN_FULL (bit 1) to logic 1 and

CMD_DATA (bit 3) to logic 0 in HceStatus

64h IN HceStatus IN from port 64h returns current value of HceStatus

with no other side effect

64h OUT HceInput OUT to port 64h sets IN_FULL to logic 0 and

CMD_DATA to logic 1 in HceStatus

Table 89. HceControl register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved A20S

Reset 00000000

Access -------R/W

Bit 76543210

Symbol IRQ12A IRQ1A GA20S EIRQEN IRQEN C_P EI EE

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R R/W

Product data sheet Rev. 02 — 5 March 2007 63 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.2.2 HceInput register (address: content of the base address register + 104h)

The HceInput register is a 4-byte register, and the bit allocation is given in Table 91. The

I/O data that is written to ports 60h and 64h is captured in this register, when emulation is

enabled. This register may directly be read or written by accessing it in the Host

Controller’s operational register space. When directly accessed in a memory cycle, reads

and writes of this register have no side effects.

Table 90. HceControl register: bit description

Bit Symbol Description

31 to 9 - reserved

8 A20S A20 State: This bit indicates the current state of gate A20 on the keyboard

controller. It is used to compare against value written to 60h when GA20S

(Gate A20 Sequence) is active.

7 IRQ12A IRQ12 Active: This bit indicates that a positive transition on IRQ12 from

the keyboard controller has occurred. Writing logic 1 sets IRQ12 to logic 0

(inactive). Writing logic 0 to this bit has no effect.

6 IRQ1A IRQ1 Active: This bit indicates that a positive transition on IRQ1 from the

keyboard controller has occurred. Writing logic 1 sets IRQ1 to logic 0

(inactive). Writing logic 0 to this bit has no effect.

5 GA20S Gate A20 Sequence: This bit is set by the Host Controller when a data

value of D1h is written to I/O port 64h and cleared, on a write to I/O port

64h of any value other than D1h.

4 EIRQEN External IRQ Enable: When this bit is set to logic 1, IRQ1 and IRQ12 from

the keyboard controller cause an emulation interrupt. This bit is

independent of the setting of the EE (Emulation Enable) bit in this register.

3 IRQEN IRQ Enable: When this bit is set, the Host Controller generates IRQ1 or

IRQ12 as long as the OUT_FULL (Output Full) bit in HceStatus is set to

logic 1. If the AUX_OUT_FULL (Auxiliary Output Full) bit of HceStatus is

logic 0, then IRQ1 is generated; if it is logic 1, then an IRQ12 is generated.

2 C_P Character Pending: When this bit is set, an emulation interrupt is

generated when the OUT_FULL (Output Full) bit of the HceStatus register

is set to logic 0.

1EI Emulation Interrupt: This bit shows the emulation interrupt condition.

0 — Legacy emulation enabled

1 — Legacy emulation disabled

0EE Emulation Enable: When this bit is set to logic 1, the Host Controller is

enabled for legacy emulation. The Host Controller decodes accesses to

I/O registers 60h and 64h, and enables interrupts on IRQ1 or IRQ12, or

both. The Host Controller also generates an emulation interrupt at

appropriate times to invoke the emulation software.

Table 91. HceInput register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Product data sheet Rev. 02 — 5 March 2007 64 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.2.3 HceOutput register (address: content of the base address register + 108h)

Data placed in this register by the emulation software is returned when I/O port 60h is

read and emulation is enabled. On a read of this location, the OUT_FULL (Output Full) bit

in HceStatus is set to logic 0. The bit allocation is given in Table 93.

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset 00000000

Access --------

Bit 76543210

Symbol IN_DATA[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 92. HceInput register: bit description

Bit Symbol Description

31 to 8 - reserved

7 to 0 IN_DATA[7:0] Input Data: This register holds data that is written to I/O ports 60h or 64h.

Table 93. HceOutput register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset 00000000

Access --------

Bit 76543210

Symbol OUT_DATA[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 02 — 5 March 2007 65 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.2.4 HceStatus register (address: content of the base address register + 10Ch)

The contents of the HceStatus register are returned on an I/O read of port 64h when

emulation is enabled. Reads and writes of port 60h, and writes to port 64h can cause

changes in this register. Emulation software can directly access this register through its

memory address in the Host Controller’s operational register space. Accessing this

allocation.

Table 94. HceOutput register: bit description

Bit Symbol Description

31 to 8 - reserved

7 to 0 OUT_DATA[7:0] Output Data: This register holds the data that is returned when an I/O

read of port 60h is requested by application software.

Table 95. HceStatus register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset 00000000

Access --------

Bit 76543210

Symbol PARITY TIMEOUT AUX_OUT

_FULL INH_SW CMD_DATA FLAG IN_FULL OUT_FULL

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 96. HceStatus register: bit description

Bit Symbol Description

31 to 8 - reserved

7 PARITY Parity: This bit indicates parity error on keyboard and mouse data.

6 TIMEOUT Time-out: This bit indicates a time-out.

5 AUX_OUT_

FULL Auxiliary Output Full: IRQ12 is asserted whenever this bit is set to

logic 1, OUT_FULL (Output Full) is set to logic 1, and the IRQEN bit is set.

4 INH_SW Inhibit Switch: This bit reﬂects the state of the keyboard inhibit switch. If

set, the keyboard is active.

3 CMD_DATA Cmd Data: The Host Controller sets this bit to logic 0 on an I/O write to

port 60h and to logic 1 on an I/O write to port 64h.

Product data sheet Rev. 02 — 5 March 2007 66 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.3 EHCI controller capability registers

Other than the OHCI Host Controller, there are some registers in EHCI that deﬁne the

capability of EHCI. The address range of these registers is located before the operational

registers.

11.3.1 CAPLENGTH/HCIVERSION register (address: content of the base address

The bit allocation of this 4-byte register is given in Table 97.

2 FLAG Flag: Nominally used as a system ﬂag by software to indicate a warm or

cold boot.

1 IN_FULL Input Full: Except for the case of a gate A20 sequence, this bit is set to

logic 1 on an I/O write to address 60h or 64h. While this bit is set to logic 1

and emulation is enabled, an emulation interrupt condition exists.

0 OUT_FULL Output Full: The Host Controller sets this bit to logic 0 on a read of I/O

port 60h. If IRQEN is set, AUX_OUT_FULL (Auxiliary Output Full)

determines which IRQ is activated. While this bit is logic 0 and C_P

(Character Pending) in HceControl is set to logic 1, an emulation interrupt

condition exists.

Table 96. HceStatus register: bit description

…continued

Bit Symbol Description

Table 97. CAPLENGTH/HCIVERSION register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol HCIVERSION[15:8]

Reset 10010101

Access RRRRRRRR

Bit 15 14 13 12 11 10 9 8

Symbol HCIVERSION[7:0]

Reset 00000000

Access RRRRRRRR

Bit 76543210

Symbol CAPLENGTH[7:0]

Reset 00001100

Access RRRRRRRR

Product data sheet Rev. 02 — 5 March 2007 67 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.3.2 HCSPARAMS register (address: content of the base address register + 04h)

The Host Controller Structural Parameters (HCSPARAMS) register is a set of ﬁelds that

are structural parameters. The bit allocation is given in Table 99.

Table 98. CAPLENGTH/HCIVERSION register: bit description

Bit Symbol Description

31 to 24 - reserved

23 to 8 HCIVERSION

[15:0] Host Controller Interface Version Number: It contains a BCD

encoded version number of the interface to which the Host Controller

interface conforms.

7 to 0 CAPLENGTH

[7:0] Capability Register Length: This is used as an offset. It is added to the

Table 99. HCSPARAMS register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol DPN[3:0] reserved P_INDI

CATOR

Reset 00000000

Access RRRR- - -R

Bit 15 14 13 12 11 10 9 8

Symbol N_CC[3:0] N_PCC[3:0]

Reset 00100010

Access RRRRRRRR

Bit 76543210

Symbol PRR reserved PPC N_PORTS[3:0]

Reset 00010100

Access R- -RRRRR

Table 100. HCSPARAMS register: bit description

Bit Symbol Description

31 to 24 - reserved

23 to 20 DPN[3:0] Debug Port Number: This ﬁeld identiﬁes which of the Host Controller

ports is the debug port. A nonzero value in this ﬁeld indicates the

presence of a debug port. The value in this register must not be greater

than N_PORTS.

19 to 17 reserved

16 P_

INDICATOR Port Indicators: This bit indicates whether the ports support port

indicator control. When this bit is logic 1, the port status and control

registers include a read/writable ﬁeld to control the state of the port

indicator.

Product data sheet Rev. 02 — 5 March 2007 68 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.3.3 HCCPARAMS register (address: content of the base address register + 08h)

The Host Controller Capability Parameters (HCCPARAMS) register is a 4-byte register,

and the bit allocation is given in Table 101.

15 to 12 N_CC

[3:0] Number of Companion Controller: This ﬁeld indicates the number of

companion controllers associated with this Hi-Speed USB Host

Controller. A value of zero in this ﬁeld indicates there are no companion

Host Controllers. Port-ownership hand-off is not supported. Only

high-speed devices are supported on the Host Controller root ports. A

value larger than zero in this ﬁeld indicates there are companion Original

USB Host Controller(s). Port-ownership hand-offs are supported.

11 to 8 N_PCC

[3:0] Number of Ports per Companion Controller: This ﬁeld indicates the

number of ports supported per companion Host Controller. It is used to

indicate the port routing conﬁguration to system software. For example, if

N_PORTS has a value of 6 and N_CC has a value of 2, then N_PCC can

have a value of 3. The convention is that the ﬁrst N_PCC ports are

assumed to be routed to companion controller 1, the next N_PCC ports

to companion controller 2, and so on. In the previous example, N_PCC

could have been 4, in which case the ﬁrst four are routed to companion

controller 1 and the last two are routed to companion controller 2.

The number in this ﬁeld must be consistent with N_PORTS and N_CC.

7 PRR Port Routing Rules: This ﬁeld indicates the method used to map ports

to companion controllers.

0 — The ﬁrst N_PCC ports are routed to the lowest numbered function

companion Host Controller, the next N_PCC ports are routed to the next

lowest function companion controller, and so on.

1 — The port routing is explicitly enumerated by the ﬁrst N_PORTS

elements of the HCSP-PORTROUTE array.

6 to 5 - reserved

4 PPC Port Power Control: This ﬁeld indicates whether the Host Controller

implementation includes port power control. Logic 1 indicates the port

has port power switches. Logic 0 indicates the port does not have port

power switches. The value of this ﬁeld affects the functionality of the Port

Power ﬁeld in each port status and control register.

3 to 0 N_PORTS

[3:0] N_Ports: This ﬁeld speciﬁes the number of physical downstream ports

implemented on this Host Controller. The value of this ﬁeld determines

how many port registers are addressable in the operational register

space. Valid values are in the range of 1h to Fh. Logic 0 in this ﬁeld is

undeﬁned.

Table 100. HCSPARAMS register: bit description

…continued

Bit Symbol Description

Table 101. HCCPARAMS register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Product data sheet Rev. 02 — 5 March 2007 69 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.4 Operational registers of enhanced USB Host Controller

11.4.1 USBCMD register (address: content of the base address register + 0Ch)

The USB Command (USBCMD) register indicates the command to be executed by the

serial Host Controller. Writing to this register causes a command to be executed.

Table 103 shows the USBCMD register bit allocation.

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset 00000000

Access --------

Bit 76543210

Symbol IST[3:0] reserved PFLF 64AC

Reset 00010010

Access RRRR- -RR

Table 102. HCCPARAMS register: bit description

Bit Symbol Description

31 to 8 - reserved

7 to 4 IST[3:0] Isochronous Scheduling Threshold: Default = implementation

dependent. This ﬁeld indicates, relative to the current position of the

executing Host Controller, where software can reliably update the

isochronous schedule. When IST[3] is logic 0, the value of the least

signiﬁcant three bits indicates the number of micro frames a Host

Controller can hold a set of isochronous data structures, one or more,

before ﬂushing the state. When IST[3] is logic 1, then host software

assumes the Host Controller may cache an isochronous data structure

for an entire frame.

3 to 2 - reserved

1 PFLF Programmable Frame List Flag: Default = implementation

dependent. If this bit is cleared, the system software must use a frame

list length of 1024 elements with this Host Controller. The USBCMD

cleared. If PFLF is set, the system software can specify and use a

smaller frame list and conﬁgure the host through the USBCMD register

FLS ﬁeld. The frame list must always be aligned on a 4 kB page

boundary to ensure that the frame list is always physically contiguous.

0 64AC 64-bit Addressing Capability: This ﬁeld documents the addressing

range capability.

0 — Data structures using 32-bit address memory pointers

1 — Data structures using 64-bit address memory pointers

Table 103. USBCMD register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Product data sheet Rev. 02 — 5 March 2007 70 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

Bit 23 22 21 20 19 18 17 16

Symbol ITC[7:0]

Reset 00001000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset 00000000

Access --------

Bit 76543210

Symbol LHCR IAAD ASE PSE FLS[1:0] HC

RESET RS

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 104. USBCMD register: bit description

Bit Symbol Description

31 to

24 - reserved

23 to

16 ITC[7:0] Interrupt Threshold Control: Default 08h. This ﬁeld is used by system

software to select the maximum rate at which the Host Controller will issue

interrupts. If software writes an invalid value to this register, the results are

undeﬁned. Valid values are:

00h — reserved

01h — 1 micro frame

02h — 2 micro frames

04h — 4 micro frames

08h — 8 micro frames (equals 1 ms)

10h — 16 micro frames (equals 2 ms)

20h — 32 micro frames (equals 4 ms)

40h — 64 micro frames (equals 8 ms)

Software modiﬁcations to this ﬁeld while HCH (HC Halted) bit is zero results in

undeﬁned behavior.

15 to 8 - reserved

7 LHCR Light Host Controller Reset: This control bit is not required. It allows the

driver software to reset the EHCI controller, without affecting the state of the

ports or the relationship to the companion Host Controllers. If not

implemented, a read of this ﬁeld will always return zero. If implemented, on

read:

Logic 0 — Indicates the Light Host Controller Reset has completed and it is

ready for the host software to re-initialize the Host Controller

Logic 1 — Indicates the Light Host Controller Reset has not yet completed

Product data sheet Rev. 02 — 5 March 2007 71 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

6 IAAD Interrupt on Asynchronous Advance Doorbell: This bit is used as a

doorbell by software to notify the Host Controller to issue an interrupt the next

time it advances the asynchronous schedule. Software must write logic 1 to

this bit to ring the doorbell. When the Host Controller has evicted all

appropriate cached schedule states, it sets the IAA (Interrupt on

Asynchronous Advance) status bit in the USBSTS register. If the IAAE

(Interrupt on Asynchronous Advance Enable) bit in the USBINTR register is

logic 1, then the Host Controller will assert an interrupt at the next interrupt

threshold. The Host Controller sets this bit to logic 0 after it sets IAA (Interrupt

on Asynchronous Advance) status bit in the USBSTS register. Software must

not set this bit when the asynchronous schedule is inactive because this

results in an undeﬁned value.

5 ASE Asynchronous Schedule Enable: Default = 0. This bit controls whether the

Host Controller skips processing the asynchronous schedule.

0 — Do not process the asynchronous schedule

1 — Use the ASYNCLISTADDR register to access the asynchronous

schedule

4 PSE Periodic Schedule Enable: Default = 0. This bit controls whether the Host

Controller skips processing the periodic schedule.

0 — Do not process the periodic schedule

1 — Use the PERIODICLISTBASE register to access the periodic schedule

3 to 2 FLS[1:0] Frame List Size: Default = 00b. This ﬁeld is read and write only if PFLF (bit 1)

in the HCCPARAMS register is set to logic 1. This ﬁeld speciﬁes the size of the

frame list. The size the frame list controls which bits in the Frame Index

00b — 1024 elements (4096 bytes)

01b — 512 elements (2048 bytes)

10b — 256 elements (1024 bytes) for small environments

11b — reserved

1HC

RESET Host Controller Reset: This control bit is used by the software to reset the

Host Controller. The effects of this on Root Hub registers are similar to a chip

hardware reset. Setting this bit causes the Host Controller to reset its internal

pipelines, timers, counters, state machines, and so on, to their initial values.

Any transaction currently in progress on USB is immediately terminated. A

USB reset is not driven on downstream ports. This reset does not affect PCI

Conﬁguration registers. All operational registers, including port registers and

port state machines, are set to their initial values. Port ownership reverts to the

companion Host Controller(s). The software must re-initialize the Host

Controller to return it to an operational state. This bit is cleared by the Host

Controller when the reset process is complete. Software cannot terminate the

reset process early by writing logic 0 to this register. Software must check the

HCH (HC Halted) bit in the USBSTS register is logic 0 before setting this bit.

Attempting to reset an actively running Host Controller results in undeﬁned

behavior.

0RSRun/Stop: 1 = Run. 0 = Stop. When set, the Host Controller executes the

schedule. The Host Controller continues execution as long as this bit is set.

When this bit is cleared, the Host Controller completes the current and active

transactions in the USB pipeline, and then halts. The HCH (HC Halted) bit in

the USBSTS register indicates when the Host Controller has ﬁnished the

transaction and has entered the stopped state. Software must check HCH (HC

Halted) in the USBSTS register is logic 1, before setting this bit.

Table 104. USBCMD register: bit description

…continued

Bit Symbol Description

Product data sheet Rev. 02 — 5 March 2007 72 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.4.2 USBSTS register (address: content of the base address register + 10h)

The USB Status (USBSTS) register indicates pending interrupts and various states of the

Host Controller. The status resulting from a transaction on the serial bus is not indicated in

this register. Software clears the register bits by writing ones to them. The bit allocation is

given in Table 105.

Table 105. USBSTS register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol ASS PSSTAT RECL HCH reserved

Reset 00010000

Access RRRR----

Bit 76543210

Symbol reserved IAA HSE FLR PCD USB

ERRINT USBINT

Reset 00000000

Access - - R R/W R/W R/W R/W R/W

Table 106. USBSTS register: bit description

Bit Symbol Description

31 to 16 - reserved

15 ASS Asynchronous Schedule Status: 0 = Default. The bit reports the

current real status of the asynchronous schedule. If this bit is logic 0,

the status of the asynchronous schedule is disabled. If this bit is

logic 1, the status of the asynchronous schedule is enabled. The

Host Controller is not required to immediately disable or enable the

asynchronous schedule when software changes the ASE

(Asynchronous Schedule Enable) bit in the USBCMD register. When

this bit and the ASE (Asynchronous Schedule Enable) bit have the

same value, the asynchronous schedule is either enabled (1) or

disabled (0).

14 PSSTAT Periodic Schedule Status: 0 = Default. This bit reports the current

status of the periodic schedule. If this bit is logic 0, the status of the

periodic schedule is disabled. If this bit is logic 1, the status of the

periodic schedule is enabled. The Host Controller is not required to

immediately disable or enable the periodic schedule when software

changes the PSE (Periodic Schedule Enable) bit in the USBCMD

periodic schedule is either enabled (1) or disabled (0).

13 RECL Reclamation: 0 = Default. This is a read-only status bit that is used

to detect an empty asynchronous schedule.

Product data sheet Rev. 02 — 5 March 2007 73 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

12 HCH HC Halted: 1 = Default. This bit is logic 0 when the Run/Stop bit of

the USBCMD register is logic 1. The Host Controller sets this bit to

logic 1 after it has stopped executing because the Run/Stop bit is set

to logic 0, either by software or by the Host Controller hardware. For

example, on an internal error.

11 to 6 - reserved

5 IAA Interrupt on Asynchronous Advance: Default = 0. The system

software can force the Host Controller to issue an interrupt the next

time the Host Controller advances the asynchronous schedule by

writing logic 1 to the IAAD (Interrupt on Asynchronous Advance

Doorbell) bit in the USBCMD register. This status bit indicates the

assertion of that interrupt source.

4 HSE Host System Error: The Host Controller sets this bit when a serious

error occurs during a host system access, involving the Host

Controller module. In a PCI system, conditions that set this bit

include PCI parity error, PCI master abort and PCI target abort.

When this error occurs, the Host Controller clears the RS (Run/Stop)

bit in the USBCMD register to prevent further execution of the

scheduled TDs.

3 FLR Frame List Rollover: The Host Controller sets this bit to logic 1

when the frame list index rolls over from its maximum value to zero.

The exact value at which the rollover occurs depends on the frame

list size. For example, if the frame list size (as programmed in the

FLS (Frame List Size) ﬁeld of the USBCMD register) is 1024

elements (see Table 111), the Frame Index register rolls over every

time bit 13 of the FRINDEX register toggles. Similarly, if the size is

512 elements, the Host Controller sets this bit to logic 1 every time

bit 12 of the FRINDEX register toggles.

2 PCD Port Change Detect: The Host Controller sets this bit to logic 1

when any port, where the PO (Port Owner) bit is cleared, changes to

logic 1, or a Force Port Resume bit changes to logic 1 as a result of

a J-K transition detected on a suspended port. This bit is allowed to

be maintained in the auxiliary power well. Alternatively, it is also

acceptable that, on a D3-to-D0 transition of the EHCI Host Controller

device, this bit is loaded with the logical OR of all of the PORTSC

change bits, including force port resume, overcurrent change,

enable or disable change, and connect status change.

1 USBERRINT USB Error Interrupt: The Host Controller sets this bit when an error

condition occurs because of completing a USB transaction. For

example, error counter underﬂow. If the Transfer Descriptor (TD) on

which the error interrupt occurred also had its IOC bit set, both this

bit and USBINT bit are set.

0 USBINT USB Interrupt: The Host Controller sets this bit on completing a

USB transaction, which results in the retirement of a TD that had its

IOC bit set. The Host Controller also sets this bit when a short

packet is detected, that is, the actual number of bytes received was

less than the expected number of bytes.

Table 106. USBSTS register: bit description

…continued

Bit Symbol Description

Product data sheet Rev. 02 — 5 March 2007 74 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.4.3 USBINTR register (address: content of the base address register + 14h)

The USB Interrupt Enable (USBINTR) register enables and disables reporting of the

corresponding interrupt to the software. When a bit is set and the corresponding interrupt

is active, an interrupt is generated to the host. Interrupt sources that are disabled in this

Table 107. USBINTR register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset 00000000

Access --------

Bit 76543210

Symbol reserved IAAE HSEE FLRE PCIE USBERR

INTE USBINTE

Reset 00000000

Access - - R/W R/W R/W R/W R/W R/W

Table 108. USBINTR register: bit description

Bit Symbol Description

31 to 6 - reserved

5 IAAE Interrupt on Asynchronous Advance Enable: When this bit and the

IAA (Interrupt on Asynchronous Advance) bit in the USBSTS register

are set, the Host Controller issues an interrupt at the next interrupt

threshold. The interrupt is acknowledged by software clearing bit IAA.

4 HSEE Host System Error Enable: When this bit and the Host System Error

Status bit in the USBSTS register are set, the Host Controller issues

an interrupt. The interrupt is acknowledged by software clearing the

HSE (Host System Error) bit.

3 FLRE Frame List Rollover Enable: When this bit and the FLR (Frame List

Rollover) bit in the USBSTS register are set, the Host Controller

issues an interrupt. The interrupt is acknowledged by software

clearing the FLR (Frame List Rollover) bit.

Product data sheet Rev. 02 — 5 March 2007 75 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.4.4 FRINDEX register (address: content of the base address register + 18h)

The Frame Index (FRINDEX) register is used by the Host Controller to index into the

periodic frame list. The register updates every 125 µs, once each microframe. Bits N to 3

are used to select a particular entry in the periodic frame list during periodic schedule

execution. The number of bits used for the index depends on the size of the frame list as

set by system software in the FLS (Frame List Size) ﬁeld in the USBCMD register. This

the HCH (HC Halted) bit. A write to this register while the RS (Run/Stop) bit is set

produces undeﬁned results. Writes to this register also affect the SOF value. The bit

allocation is given in Table 109.

2 PCIE Port Change Interrupt Enable: When this bit and the PCD (Port

Change Detect) bit in the USBSTS register are set, the Host Controller

issues an interrupt. The interrupt is acknowledged by software

clearing the PCD (Port Change Detect) bit.

1 USB

ERRINTE USB Error Interrupt Enable: When this bit and the USBERRINT bit in

the USBSTS register are set, the Host Controller issues an interrupt at

the next interrupt threshold. The interrupt is acknowledged by software

clearing the USBERRINT bit.

0 USBINTE USB Interrupt Enable: When this bit and the USBINT bit in the

USBSTS register are set, the Host Controller issues an interrupt at the

next interrupt threshold. The interrupt is acknowledged by software

clearing the USBINT bit.

Table 108. USBINTR register: bit description

…continued

Bit Symbol Description

Table 109. FRINDEX register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved FRINDEX[13:8]

Reset 00000000

Access - - R/W R/W R/W R/W R/W R/W

Bit 76543210

Symbol FRINDEX[7:0]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 02 — 5 March 2007 76 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.4.5 CTRLDSSEGMENT register (address: content of the base address register +

1Ch)

The Control Data Structure Segment (CTRLDSSEGMENT) register corresponds to the

most signiﬁcant address bits (bits 63 to 32) for all EHCI data structures. If the 64AC (64-bit

Addressing Capability) ﬁeld in HCCPARAMS is cleared, then this register is not used and

software cannot write to it (reading from this register returns zero).

If the 64AC (64-bit Addressing Capability) ﬁeld in HCCPARAMS is set, this register is used

with link pointers to construct 64-bit addresses to EHCI control data structures. This

ASYNCLISTADDR, or any control data structure link ﬁeld to construct a 64-bit address.

This register allows the host software to locate all control data structures within the same

4 GB memory segment.

11.4.6 PERIODICLISTBASE register (address: content of the base address

The Periodic Frame List Base Address (PERIODICLISTBASE) register contains the

beginning address of the periodic frame list in the system memory. If the Host Controller is

in 64-bit mode, as indicated by logic 1 in the 64AC (64-bit Addressing Capability) ﬁeld in

the HCCPARAMS register, the most signiﬁcant 32 bits of every control data structure

address comes from the CTRLDSSEGMENT register. The system software loads this

structure referenced by this physical memory pointer is assumed as 4 kB aligned. The

contents of this register are combined with the FRINDEX register to enable the Host

Controller to step through the periodic frame list in sequence. The bit allocation is given in

Table 112.

Table 110. FRINDEX register: bit description

Bit Symbol Description

31 to 14 - reserved

13 to 0 FRINDEX [13:0] Frame Index: Bits in this register are used for the frame number in

the SOF packet and as the index into the frame list. The value in this

micro frame. The bits used for the frame number in the SOF token

are taken from bits 13 to 3 of this register. Bits N to 3 are used for the

frame list current index. This means that each location of the frame

list is accessed eight times, frames or micro frames, before moving

to the next index. Table 111 illustrates N based on the value of the

FLS (Frame List Size) ﬁeld in the USBCMD register.

Table 111. N based value of FLS[1:0]

FLS[1:0] Number elements N

00b 1024 12

01b 512 11

10b 256 10

11b reserved -

Product data sheet Rev. 02 — 5 March 2007 77 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.4.7 ASYNCLISTADDR register (address: content of the base address register +

24h)

This 32-bit register (bit allocation: Table 114) contains the address of the next

asynchronous queue head to be executed. If the Host Controller is in 64-bit mode, as

indicated by logic 1 in 64AC (64-bit Addressing Capability) ﬁeld in the HCCPARAMS

the CTRLDSSEGMENT register. Bits 4 to 0 of thisregister always return zeros when read.

The memory structure referenced by the physical memory pointer is assumed to be

32 bytes (cache aligned).

Table 112. PERIODICLISTBASE register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol BA[19:12]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 23 22 21 20 19 18 17 16

Symbol BA[11:4]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol BA[3:0] reserved

Reset 00000000

Access R/WR/WR/WR/W----

Bit 76543210

Symbol reserved

Reset 00000000

Access --------

Table 113. PERIODICLISTBASE register: bit description

Bit Symbol Description

31 to 12 BA[19:0] Base Address: These bits correspond to memory address signals 31 to 12,

respectively.

11 to 0 - reserved

Table 114. ASYNCLISTADDR register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol LPL[26:19]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit 23 22 21 20 19 18 17 16

Symbol LPL[18:11]

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Product data sheet Rev. 02 — 5 March 2007 78 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.4.8 CONFIGFLAG register (address: content of the base address register + 4Ch)

The bit allocation of the Conﬁgure Flag (CONFIGFLAG) register is given in Table 116.

Bit 15 14 13 12 11 10 9 8

Symbol LPL[10:3]

Reset 00000000

Access R/WR/WR/WR/W----

Bit 76543210

Symbol LPL[2:0] reserved

Reset 00000000

Access --------

Table 115. ASYNCLISTADDR register: bit description

Bit Symbol Description

31 to 5 LPL[26:0] Link Pointer List: These bits correspond to memory address signals 31 to

5, respectively. This ﬁeld may only reference a Queue Head (QH).

4 to 0 - reserved

Table 116. CONFIGFLAG register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved

Reset 00000000

Access --------

Bit 15 14 13 12 11 10 9 8

Symbol reserved

Reset 00000000

Access --------

Bit 76543210

Symbol reserved CF

Reset 00000000

Access -------R/W

Table 117. CONFIGFLAG register: bit description

Bit Symbol Description

31 to 1 - reserved

0CFConﬁgure Flag: The host software sets this bit as the last action in its

process of conﬁguring the Host Controller. This bit controls the default

port-routing control logic.

0 — Port routing control logic default-routes each port to an implementation

dependent classic Host Controller

1 — Port routing control logic default-routes all ports to this Host Controller

Product data sheet Rev. 02 — 5 March 2007 79 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

11.4.9 PORTSC registers 1, 2, 3, 4 (address: content of the base address register +

50h + (4 times Port Number − 1)) where Port Number is 1, 2, 3,...N_Ports

The Port Status and Control (PORTSC) register (bit allocation: Table 118) is in the

auxiliary power well. It is only reset by hardware when the auxiliary power is initially

applied or in response to a Host Controller reset. The initial conditions of a port are:

•No device connected

•Port disabled

If the port has power control, software cannot change the state of the port until it sets port

power bits. Software must not attempt to change the state of the port until power is stable

on the port; maximum delay is 20 ms from the transition.

Table 118. PORTSC 1, 2, 3, 4 register: bit allocation

Bit 31 30 29 28 27 26 25 24

Symbol reserved

Reset 00000000

Access --------

Bit 23 22 21 20 19 18 17 16

Symbol reserved WKOC_E WKDS

CNNT_E WKCNNT_

EPTC[3:0]

Reset 00000000

Access - R/W R/W R/W R/W R/W R/W R/W

Bit 15 14 13 12 11 10 9 8

Symbol PIC[1:0] PO PP LS[1:0] reserved PR

Reset 00100000

Access R R R/W R/W R/W R/W - R

Bit 76543210

Symbol SUSP FPR OCC OCA PEDC PED ECSC ECCS

Reset 00000000

Access R/W R/W R R R/W R/W R/W R

Table 119. PORTSC 1, 2, 3, 4 register: bit description

Bit Symbol Description

31 to 23 - reserved

22 WKOC_E Wake on Overcurrent Enable: Default = 0. Setting this bit enables the port

to be sensitive to overcurrent conditions as wake-up events.[1]

21 WKDS

CNNT_E Wake on Disconnect Enable: Default = 0. Setting this bit enables the port

to be sensitive to device disconnects as wake-up events.[1]

20 WKCNNT

_E Wake on Connect Enable: Default = 0. Setting this bit enables the port to

be sensitive to device connects as wake-up events.[1]

Product data sheet Rev. 02 — 5 March 2007 80 of 103

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HS USB PCI Host Controller

19 to 16 PTC[3:0] Port Test Control: Default = 0000b. When this ﬁeld is logic 0, the port is not

operating in test mode. A nonzero value indicates that it is operating in test

mode and test mode is indicated by the value. The encoding of test mode

bits are:

0000b — test mode disabled

0001b — test J_STATE

0010b — test K_STATE

0011b — test SE0_NAK

0100b — test packet

0101b — test FORCE_ENABLE

0110b to 1111b — reserved

15 to 14 PIC[1:0] Port Indicator Control: Default = 0. Writing to this ﬁeld has no effect if the

P_INDICATOR bit in the HCSPARAMS register is logic 0. If P_INDICATOR

bit is logic 1, then the bit encoding is:

00b — Port indicators are off

01b — amber

10b — green

11b — undeﬁned

For a description on how these bits are implemented, refer to Ref. 8

“Universal Serial Bus Speciﬁcation”.[1]

13 PO Port Owner: Default = 1. This bit unconditionally goes to logic 0 when the

Conﬁgured bit in the CONFIGFLAG register makes logic 0 to logic 1

transition. This bit unconditionally goes to logic 1 whenever the Conﬁgured

bit is logic 0. The system software uses this ﬁeld to release ownership of the

port to a selected Host Controller, if the attached device is not a high-speed

device. Software writes logic 1 to this bit when the attached device is not a

high-speed device. Logic 1 in this bit means that a companion Host

Controller owns and controls the port.

12 PP Port Power: The function of this bit depends on the value of the Port Power

Control (PPC) ﬁeld in the HCSPARAMS register.

If PPC = 0 and PP = 1 — The Host Controller does not have port power

control switches. Each port is hardwired to power.

If PPC = 1 and PP = 1 or 0 — The Host Controller has port power control

switches. This bit represents the current setting of the switch: logic 0 = off,

logic 1 = on. When PP is logic 0, the port is nonfunctional and will not report

any status

When an overcurrent condition is detected on a powered port and PPC is

logic 1, the PP bit in each affected port may be changed by the Host

Controller from logic 1 to logic 0, removing power from the port.

11 to 10 LS[1:0] Line Status: This ﬁeld reﬂect the current logical levels of the DP (bit 11) and

DM (bit 10) signal lines. These bits are used to detect low-speed USB

devices before the port reset and enable sequence. This ﬁeld is valid only

when the Port Enable bit is logic 0, and the current connect status bit is set

to logic 1.

00b — SE0: Not a low-speed device, perform EHCI reset

01b — K-state: Low-speed device, release ownership of port

10b — J-state: Not a low-speed device, perform EHCI reset

11b — undeﬁned: Not a low-speed device, perform EHCI reset.

If Port Power (PP) is logic 0, this ﬁeld is undeﬁned.

Table 119. PORTSC 1, 2, 3, 4 register: bit description

…continued

Bit Symbol Description

Product data sheet Rev. 02 — 5 March 2007 81 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

9 - reserved

8PR Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not

in reset. Default = 0. When software sets this bit from logic 0, the bus reset

sequence as deﬁned in Ref. 8 “Universal Serial Bus Speciﬁcation” is started.

Software clears this bit to terminate the bus reset sequence. Software must

hold this bit at logic 1 until the reset sequence, as speciﬁed in Ref. 8

“Universal Serial Bus Speciﬁcation”, is completed.

Remark: When software sets this bit, it must also clear the Port Enable bit.

Remark: When software clears this bit, there may be a delay before the bit

status changes to logic 0 because it will not read logic 0 until the reset is

completed. If the port is in high-speed mode after reset is completed, the

Host Controller will automatically enable this port; it can set the Port Enable

bit. A Host Controller must terminate the reset and stabilize the state of the

port within 2 ms of software changing this bit from logic 1 to logic 0. For

example, if the port detects that the attached device is high-speed during a

reset, then the Host Controller must enable the port within 2 ms of software

clearing this bit.

The HCH (HC Halted) bit in the USBSTS register must be logic 0 before

software attempts to use this bit. The Host Controller may hold Port Reset

asserted when the HCH (HC Halted) bit is set.[1]

7 SUSP Suspend: Default = 0. A logic 1 means the port is in the suspend state. A

logic 0 means the Port is not suspended. The Port Enabled bit and the

Suspend bit of this register deﬁne the port states as follows:

PED = 0 and SUSP = x — Port is disabled

PED = 1 and SUSP = 0 — Port is enabled

PED = 1 and SUSP = 1 — Port is suspended

When in the suspend state, downstream propagation of data is blocked on

this port, except for the port reset. If a transaction was in progress when this

bit was set, blocking occurs at the end of the current transaction. In the

suspend state, the port is sensitive to resume detection. The bit status does

not change until the port is suspended and there may be a delay in

suspending a port, if there is a transaction currently in progress on USB.

Attempts to clear this bit are ignored by the Host Controller. The Host

Controller will unconditionally set this bit to logic 0 when:

•Software changes the FPR (Force Port Resume) bit to logic 0.

•Software changes the PR (Port Reset) bit to logic 1.

If the host software sets this bit when the Port Enabled bit is logic 0, the

results are undeﬁned.[1]

Table 119. PORTSC 1, 2, 3, 4 register: bit description

…continued

Bit Symbol Description

Product data sheet Rev. 02 — 5 March 2007 82 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

[1] These ﬁelds read logic 0, if the Port Power (PP) (bit 12 in register PORTSC 1,2,3,4) is logic 0.

6 FPR Force Port Resume: Logic 1 means resume detected or driven on the port.

Logic 0 means no resume (K-state) detected or driven on the port. Default =

0. Software sets this bit to drive the resume signaling. The Host Controller

sets this bit if a J-to-K transition is detected while the port is in the suspend

state. When this bit changes to logic 1 because a J-to-K transition is

detected, the PCD (Port Change Detect) bit in the USBSTS register is also

set to logic 1. If software sets this bit to logic 1, the Host Controller must not

set the PCD (Port Change Detect) bit. When the EHCI controller owns the

port, the resume sequence follows the sequence speciﬁed in Ref. 8

“Universal Serial Bus Speciﬁcation”. The resume signaling (full-speed ‘K’) is

driven on the port as long as this bit remains set. Software must time the

resume and clear this bit after the correct amount of time has elapsed.

Clearing this bit causes the port to return to high-speed mode, forcing the

bus below the port into a high-speed idle. This bit will remain at logic 1, until

the port has switched to the high-speed idle. The Host Controller must

complete this transition within 2 ms of software clearing this bit.[1]

5 OCC Overcurrent Change: Default = 0. This bit is set to logic 1 when there is a

change in overcurrent active. Software clears this bit by setting this bit to

logic 1.

4 OCA Overcurrent Active: Default = 0. If set to logic 1, this port has an

overcurrent condition. If set to logic 0, this port does not have an overcurrent

condition. This bit will automatically change from logic 1 to logic 0 when the

overcurrent condition is removed.

3 PEDC Port Enable/Disable Change: Logic 1 means the port enabled/disabled

status has changed. Logic 0 means no change. Default = 0. For the root

hub, this bit gets set only when a port is disabled because of appropriate

conditions existing at the EOF2 point. For deﬁnition of port error, refer to

Chapter 11 of Ref. 8 “Universal Serial Bus Speciﬁcation”. Software clears

this bit by setting it.[1]

2 PED Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable.

Default = 0. Ports can only be enabled by the Host Controller as a part of the

reset and enable sequence. Software cannot enable a port by writing logic 1

to this ﬁeld. The Host Controller will only set this bit when the reset

sequence determines that the attached device is a high-speed device. Ports

can be disabled by either a fault condition or by host software. The bit status

does not change until the port state has actually changed. There may be a

delay in disabling or enabling a port because of other Host Controller and

bus events. When the port is disabled, downstream propagation of data is

blocked on this port, except for reset.[1]

1 ECSC Connect Status Change: Logic 1 means change in ECCS (Current

Connect Status). Logic 0 means no change. Default = 0. This bit indicates a

change has occurred in the port’s ECCS (Current Connect Status). The

Host Controller sets this bit for all changes to the port device connect status,

even if system software has not cleared an existing connect status change.

For example, the insertion status changes twice before system software has

cleared the changed condition, hub hardware will be “setting” an already-set

bit, that is, the bit will remain set. Software clears this bit setting it.[1]

0 ECCS Current Connect Status: Logic 1 indicates a device is present on port.

Logic 0 indicates no device is present. Default = 0. This value reﬂects the

current state of the port and may not correspond directly to the event that

caused the ECSC (Connect Status Change) bit to be set.[1]

Table 119. PORTSC 1, 2, 3, 4 register: bit description

…continued

Bit Symbol Description

Product data sheet Rev. 02 — 5 March 2007 83 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

12. Current consumption

Table 120 shows the current consumption when two ports are active, that is, the

SEL2PORTS pin is connected to VDD.

[1] When one or two full-speed or low-speed power devices are connected, the current consumption is comparable with the current

consumption when no high-speed devices are connected. There is a difference of approximately 1 mA.

Table 121 shows the current consumption when four ports are active, that is, the

SEL2PORTS pin is connected to ground.

Table 120. Current consumption when SEL2PORTS is HIGH

Cumulative current Conditions Typ Unit

Total current on pins VAUX plus AVAUX

plus AVAUX_PLL plus VDD

no devices connected to the ISP1561[1] 151 mA

one high-speed device connected to the ISP1561 181 mA

two high-speed devices connected to the ISP1561 209 mA

Auxiliary current on pins VAUX plus

AVAUX plus AVAUX_PLL

no devices connected to the ISP1561[1] 98 mA

one high-speed device connected to the ISP1561 124 mA

two high-speed devices connected to the ISP1561 153 mA

On pin VDD no devices connected to the ISP1561[1] 53 mA

one high-speed device connected to the ISP1561 56 mA

two high-speed devices connected to the ISP1561 56 mA

Table 121. Current consumption when SEL2PORTS is LOW

Cumulative current Conditions Typ Unit

Total current on pins VAUX plus

AVAUX plus AVAUX_PLL plus VDD

no devices connected to the ISP1561[1] 207 mA

one high-speed device connected to the ISP1561 236 mA

two high-speed devices connected to the ISP1561 261 mA

three high-speed devices connected to the ISP1561 288 mA

four high-speed devices connected to the ISP1561 314 mA

Auxiliary current on pins VAUX plus

AVAUX plus AVAUX_PLL

no devices connected to the ISP1561[1] 151 mA

one high-speed device connected to the ISP1561 178 mA

two high-speed devices connected to the ISP1561 206 mA

three high-speed devices connected to the ISP1561 232 mA

four high-speed devices connected to the ISP1561 259 mA

On pin AVAUX no devices connected to the ISP1561[1] 7mA

one high-speed device connected to the ISP1561 33 mA

two high-speed devices connected to the ISP1561 58 mA

three high-speed devices connected to the ISP1561 84 mA

four high-speed devices connected to the ISP1561 108 mA

On pin AVAUX_PLL no devices connected to the ISP1561 3 mA

one high-speed device connected to the ISP1561 3 mA

two high-speed devices connected to the ISP1561 3 mA

three high-speed devices connected to the ISP1561 3 mA

four high-speed devices connected to the ISP1561 3 mA

Product data sheet Rev. 02 — 5 March 2007 84 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

[1] When one to four full-speed or low-speed power devices are connected, the current consumption is comparable with the current

consumption when no high-speed devices are connected. There is a difference of only about 3 mA.

[1] S1 represents the system state that will determine the B1 and D1 states. For details, refer to Ref. 5 “PCI

Bus Power Management Interface Speciﬁcation”.

[2] S3 represents the system state that will determine the B3 and D3 states. For details, refer to Ref. 5 “PCI

Bus Power Management Interface Speciﬁcation”.

[3] When I2C-bus and legacy support are present.

[4] When I2C-bus and legacy support are not present.

On pin VDD no devices connected to the ISP1561 56 mA

one high-speed device connected to the ISP1561 57 mA

two high-speed devices connected to the ISP1561 57 mA

three high-speed devices connected to the ISP1561 57 mA

four high-speed devices connected to the ISP1561 57 mA

Table 121. Current consumption when SEL2PORTS is LOW

…continued

Cumulative current Conditions Typ Unit

Table 122. Current consumption: S1 and S3

Current consumption Typ Unit

S1[1] 130 mA

S3[2] 1.5[3] mA

0.52[4] mA

Product data sheet Rev. 02 — 5 March 2007 85 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

13. Limiting values

[1] Valid only when the supply voltage is present.

[2] Test method available on request.

14. Recommended operating conditions

[1] Valid only when the supply voltage is present.

Table 123. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +4.6 V

VAUX auxiliary voltage −0.5 +4.6 V

AVAUX analog auxiliary voltage (3.3 V);

supply voltage −0.5 +4.6 V

AVAUX_PLL analog auxiliary voltage (3.3 V);

supply voltage for PLL −0.5 +4.6 V

VI(5V) input voltage on 5 V buffers 3.0 V < VDD < 3.6 V [1] −0.5 +6.0 V

VI(3.3V) input voltage on 3.3 V buffers 3.0 V < VDD < 3.6 V −0.5 +4.6 V

Ilu latch-up current VI< 0 V or VI> VCC - 100 mA

Vesd electrostatic discharge voltage all pins (ILI < 1 µA) −1000 +1000 V

on pins DM1 to DM4, DP1

to DP4, and all GND pins

(ILI < 1 µA)

[2] −4000 +4000 V

Tstg storage temperature −40 +125 °C

Table 124. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3.0 3.3 3.6 V

VAUX auxiliary voltage 3.0 3.3 3.6 V

AVAUX analog auxiliary voltage (3.3 V);

supply voltage 3.0 3.3 3.6 V

AVAUX_PLL analog auxiliary voltage (3.3 V);

supply voltage for PLL 3.0 3.3 3.6 V

VI(5V) input voltage on 5 V buffers [1] 0 - 5.5 V

VI(3.3V) input voltage on 3.3 V buffers 0 - VDD V

Tamb ambient temperature −40 - +85 °C

Tjjunction temperature −40 - +125 °C

Product data sheet Rev. 02 — 5 March 2007 86 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

15. Static characteristics

[1] All pins are 5 V tolerant.

Table 125. Static characteristics: I2C-bus interface (SDA and SCL)

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input voltage 2.1 - - V

VIL LOW-level input voltage - - 0.9 V

Vhys hysteresis voltage 0.15 - - V

VOL LOW-level output voltage IOL = 3 mA - - 0.4 V

Table 126. Static characteristics: digital pins

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

[1]

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input voltage 2.0 - - V

VIL LOW-level input voltage - - 0.8 V

Vhys hysteresis voltage 0.4 - 0.7 V

VOL LOW-level output voltage IOL = 3 mA - - 0.4 V

VOH HIGH-level output voltage 2.4 - - V

Table 127. Static characteristics: PCI interface block

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

[1]

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input voltage 2.0 - 5.5 V

VIL LOW-level input voltage 0 - 0.9 V

VIPU input pull-up voltage 2.1 - - V

ILI input leakage current 0 V < VIN < VDD −10 - +10 µA

VOH HIGH-level output voltage IOUT = 500 µA 2.7 - - V

VOL LOW-level output voltage IOUT = 1500 µA - - 0.3 V

CIN input pin capacitance - - 10 pF

CCLK CLK pin capacitance 5 - 12 pF

CIDSEL IDSEL pin capacitance - - 8 pF

Table 128. Static characteristics: USB interface block (pins DM1 to DM4 and DP1 to DP4)

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Input levels for high-speed

VHSSQ high-speed squelch detection

threshold voltage (differential signal

amplitude)

squelch detected - - 100 mV

no squelch

detected 150 - - mV

Product data sheet Rev. 02 — 5 March 2007 87 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

[1] HS termination resistor disabled, pull-up resistor connected. Only during reset, when both hub and device are capable of high-speed

operation.

VHSDSC high-speed disconnect detection

threshold voltage (differential signal

amplitude)

disconnect

detected 625 - - mV

disconnect not

detected - - 525 mV

VHSCM high-speed data signaling common

mode voltage range (guideline for

receiver)

−50 - +500 mV

Output levels for high-speed

VHSOI high-speed idle level voltage −10 - +10 mV

VHSOH high-speed data signaling

HIGH-level voltage 360 - 440 mV

VHSOL high-speeddatasignalingLOW-level

voltage −10 - +10 mV

VCHIRPJ chirp J level (differential voltage) 700[1] - 1100 mV

VCHIRPK chirp K level (differential voltage) −900[1] -−500 mV

Input levels for full-speed and low-speed

VIH HIGH-level input voltage drive 2.0 - - V

VIHZ HIGH-level input voltage (ﬂoating) 2.7 - 3.6 V

VIL LOW-level input voltage - - 0.8 V

VDI differential input sensitivity |VDP − VDM|0.2 - - V

VCM differential common mode voltage

range 0.8 - 2.5 V

Output levels for full-speed and low-speed

VOH HIGH-level output voltage 2.8 - 3.6 V

VOL LOW-level output voltage 0 - 0.3 V

VOSE1 SE1 output voltage 0.8 - - V

VCRS output signal crossover voltage 1.3 - 2.0 V

Table 128. Static characteristics: USB interface block (pins DM1 to DM4 and DP1 to DP4)

…continued

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 02 — 5 March 2007 88 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

16. Dynamic characteristics

[1] Suggested values for external capacitors when using a crystal are 22 pF to 27 pF.

[2] Recommended accuracy of the clock frequency is 50 ppm for the crystal and oscillator. The oscillator should have 3.3 V power supply.

[1] All pins are 5 V tolerant.

[2] The bus capacitance (CB) is speciﬁed in pF. To meet the speciﬁcation for VOL and the maximum rise time (300 ns), use an external

pull-up resistor with Rmax = 850 / CBkΩ and Rmin = (VDD − 0.4) / 3 kΩ.

[3] Output fall time VIH to VIL.

[1] All pins are 5 V tolerant.

[2] Standard load is 10 pF together with a pull-up and pull-down resistor of 10 kΩ.

[3] Output slew rate (rise, fall).

Table 129. Dynamic characteristics: system clock timing

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Crystal oscillator

fclk clock frequency crystal[1] [2] - 12 - MHz

oscillator - 48 - MHz

External clock input

δclock duty cycle - 50 - %

External clock input

J external clock jitter - - 50 ppm

tCR rise time - - 3 ns

tCF fall time - - 3 ns

δclk clock duty factor - 50 - %

tsstart-up time - 5 10 ms

Table 130. Dynamic characteristics: I2C-bus interface (SDA and SCL)

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

[1]

Symbol Parameter Conditions Min Typ Max Unit

tffall time 10 pF < CB< 400 pF[2] [3] - 0 250 ns

Table 131. Dynamic characteristics: PCI interface block

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

[1]

Symbol Parameter Conditions Min Typ Max Unit

SR slew rate standard load[2] [3] 1 - 4 V/ns

Table 132. Dynamic characteristics: high-speed source electrical characteristics

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Driver characteristics

tHSR rise time (10 % to 90 %) 500 - - ps

tHSF fall time (10 % to 90 %) 500 - - ps

Product data sheet Rev. 02 — 5 March 2007 89 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

ZHSDRV driver output impedance

(which also serves as

high-speed termination)

includes the RS

resistor 40.5 45 49.5 Ω

Clock timing

tHSDRAT high-speed data rate 479.76 - 480.24 Mb/s

tHSFRAM microframe interval 124.9375 - 125.0625 µs

tHSRFI consecutive microframe

interval difference 1 - four

high-speed

bit times

Table 132. Dynamic characteristics: high-speed source electrical characteristics

…continued

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Table 133. Dynamic characteristics: full-speed source electrical characteristics

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Driver characteristics

tFR rise time CL= 50 pF; 10 % to

90 % of |VOH − VOL|4 - 20 ns

tFF fall time CL= 50 pF; 90 % to

10 % of |VOH − VOL|4 - 20 ns

tFRFM differential rise and fall time

matching 90 - 111.1 %

ZDRV driver output impedance for

driver which is not high-speed

capable

28 - 44 Ω

Data timing: see Figure 8

tFDEOP source jitter for differential

transition to SE0 transition full-speed timing −2- 5 ns

tFEOPT source SE0 interval of EOP 160 - 175 ns

tFEOPR receiver SE0 interval of EOP 82 - - ns

tLDEOP upstream facing port source

jitter for differential transition to

SE0 transition

low-speed timing −40 - 100 ns

tLEOPT source SE0 interval of EOP 1.25 - 1.5 µs

tLEOPR receiver SE0 interval of EOP 670 - - ns

tFST width of SE0 interval during

differential transition --14ns

Table 134. Dynamic characteristics: low-speed source electrical characteristics

= 3.0 V to 3.6 V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Driver characteristics

tLR transition time: rise time 75 - 300 ns

tLF transition time: fall time 75 - 300 ns

tLRFM rise and fall time matching 90 - 125 %

Product data sheet Rev. 02 — 5 March 2007 90 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

16.1 Timing

[1] REQ# and GNT# are point-to-point signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All others are bus signals.

Table 135. PCI clock and IO timing

Symbol Parameter Conditions Min Typ Max Unit

PCI clock timing; see Figure 5

Tcyc CLK cycle time 30 - 32 ns

thigh CLK HIGH time 11 - - ns

tlow CLK LOW time 11 - - ns

SRCLK CLK slew rate 1 - 4 V/ns

SRRST# RST# slew rate 50 - - mV/ns

PCI input timing; see Figure 6

tsu input set-up time to CLK - bused signals 7 - - ns

tsu(ptp) input set-up time to CLK - point-to-point [1] 10--ns

thinput hold time from CLK 0 - - ns

PCI output timing; see Figure 7

tval CLK to signal valid delay time - bused signals 2 - 11 ns

tval(ptp) CLK to signal valid delay time - point-to-point [1] 2 - 12 ns

ton ﬂoat to active delay time 2 - - ns

toff active to ﬂoat delay time - - 28 ns

PCI reset timing

trst-clk reset active time after CLK stable 100 - - µs

trst reset active time after power stable 1 - - ms

Fig 5. PCI clock

minimum value

0.4VDD

Tcyc

mbl341

tHIGH tLOW

0.6VDD

0.5VDD

0.4VDD

0.3VDD

0.2VDD

Product data sheet Rev. 02 — 5 March 2007 91 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

Fig 6. PCI input timing

Fig 7. PCI output timing

mbl344

0.6VDD

0.2VDD

0.6VDD

0.2VDD

tsu; tsu(ptp) th

0.4VDD

inputs valid

CLK

input

delay

mbl345

0.6VDD

0.2VDD

0.4VDD

0.615VDD (falling edge)

0.285VDD (rising edge)

output

delay

CLK

toff

ton

tval; tval(ptp)

TPERIOD is the bit duration corresponding with the USB data rate.

Full-speed timing symbols have a subscript preﬁx ‘F’, low-speed timings a preﬁx ‘L’.

Fig 8. USB source differential data-to-EOP transition skew and EOP width

mgr776

TPERIOD

differential

data lines

crossover point

differential data to

SE0/EOP skew

N × TPERIOD + tDEOP

source EOP width: tEOPT

receiver EOP width: tEOPR

crossover point

extended

+3.3 V

0 V

Product data sheet Rev. 02 — 5 March 2007 92 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

17. Package outline

Fig 9. Package outline SOT420-1 (LQFP128)

UNIT A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 1.45

1.35 0.25 0.23

0.13 0.20

0.09 14.1

13.9 0.4 16.15

15.85 0.95

0.65 7

0.070.2 0.081

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT420-1 MS-026 99-11-03

03-02-20

D(1) (1)(1)

14.1

13.9

16.15

15.85

0.95

0.65

0 5 10 mm

scale

EA1

detail X

(A )

HA2

HvMB

vMA

max.

1.6

LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 14 x 1.4 mm SOT420-1

pin 1 index

128

Product data sheet Rev. 02 — 5 March 2007 93 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

18. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus PbSn soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

Product data sheet Rev. 02 — 5 March 2007 94 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

18.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 10) than a PbSn process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 136 and 137

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 10.

Table 136. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 137. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 02 — 5 March 2007 95 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

19. Abbreviations

20. References

[1] Designing a Hi-Speed USB Host PCI Adapter Using the ISP1561 — AN10006

[2] Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus —

Rev. 095

MSL: Moisture Sensitivity Level

Fig 10. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 138. Abbreviations

Acronym Description

DID Device ID

EHCI Enhanced Host Controller Interface

EMI ElectroMagnetic interference

EOF End-Of-Frame

HC Host Controller

HCCA Host Controller Communication Area

HCD Host Controller Driver

HCI Host Controller Interface

OHCI Open Host Controller Interface

PMC Power Management Capabilities

PME Power Management Event

PMCSR Power Management Control/Status

USB Universal Serial Bus

VID Vendor ID

Product data sheet Rev. 02 — 5 March 2007 96 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

[3] ISP1561 Evaluation Board User’s Guide — UM10005

[4] Open Host Controller Interface Speciﬁcation for USB — Rev. 1.0a

[5] PCI Bus Power Management Interface Speciﬁcation — Rev. 1.1

[6] PCI Local Bus Speciﬁcation — Rev. 2.2

[7] The I2C-bus Speciﬁcation — Version 2.1

[8] Universal Serial Bus Speciﬁcation — Rev. 2.0

Product data sheet Rev. 02 — 5 March 2007 97 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

21. Revision history

Table 139. Revision history

Document ID Release date Data sheet status Change notice Supersedes

ISP1561_2 20070305 Product data sheet - ISP1561-01

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Symbols and descriptions have been updated, wherever applicable, to comply with the new

identity guidelines of NXP Semiconductors.

•Updated Figure 1 “Block diagram”.

•Table 2 “Pin description”: updated description for XTAL1, XTAL2, GLn, PWEn, AMBn and GRNn.

Updated I/O detail of pin SERR#.

•Section 8.2.1.20 “TRDY Timeout register (R/W: 40h)” and Section 8.2.1.21 “Retry Timeout

•Table 23 “MIN_GNT register: bit description” and Table 24 “MAX_LAT register: but description”:

updated the access type from R/W to R.

•Section 11.4.8 “CONFIGFLAG register (address: content of the base address register + 4Ch)”:

corrected the address in the title from 5Ch to 4Ch.

•Table 119 “PORTSC 1, 2, 3, 4 register: bit description”: updated description for ﬁeld LS[1:0].

•Section 12 “Current consumption”: updated.

•Table 114 “ASYNCLISTADDR register: bit allocation” and Table 115 “ASYNCLISTADDR register:

bit description”: changed LPL[19:0] to LPL[26:0].

•Table 124 “Recommended operating conditions”: added Tj.

•Table 125 “Static characteristics: I2C-bus interface (SDA and SCL)” and Table 130 “Dynamic

characteristics: I2C-bus interface (SDA and SCL)”: updated table title.

•Table 129 “Dynamic characteristics: system clock timing”: updated.

•Table 135 “PCI clock and IO timing”: updated th and added the max value for Tcyc.

ISP1561-01

(9397 750 10015) 20030206 Product data sheet - -

Product data sheet Rev. 02 — 5 March 2007 98 of 103

NXP Semiconductors ISP1561

HS USB PCI Host Controller

22. Legal information

22.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

22.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

22.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

GoodLink — is a trademark of NXP B.V.

I2C-bus — logo is a trademark of NXP B.V.

23. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

Product data sheet Rev. 02 — 5 March 2007 99 of 103

continued >>

NXP Semiconductors ISP1561

HS USB PCI Host Controller

24. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3. PCI conﬁguration space registers of OHCI1,

OHCI2 and EHCI . . . . . . . . . . . . . . . . . . . . . . .13

Table 4. Vendor ID register: bit description . . . . . . . . . .14

Table 5. Device ID register: bit description . . . . . . . . . .14

Table 6. Command register: bit allocation . . . . . . . . . . .15

Table 7. Command register: bit description . . . . . . . . . .15

Table 8. Status register: bit allocation . . . . . . . . . . . . . .16

Table 9. Status register: bit description . . . . . . . . . . . . .17

Table 10. Revision ID register: bit description . . . . . . . . .18

Table 11. Class Code register: bit allocation . . . . . . . . . .18

Table 12. Class Code register: bit description . . . . . . . . .18

Table 13. CacheLine Size register: bit description . . . . .19

Table 14. Latency Timer register: bit description . . . . . . .19

Table 15. Header Type register: bit allocation . . . . . . . . .19

Table 16. Header Type register: bit description . . . . . . . .19

Table 17. BAR0 register: bit description . . . . . . . . . . . . .20

Table 18. Subsystem Vendor ID register: bit description .20

Table 19. Subsystem ID register: bit description . . . . . . .21

Table 20. Capabilities Pointer register: bit description . . .21

Table 21. Interrupt Line register: bit description . . . . . . .21

Table 22. Interrupt Pin register: bit description . . . . . . . .22

Table 23. MIN_GNT register: bit description . . . . . . . . . .22

Table 24. MAX_LAT register: but description . . . . . . . . .22

Table 25. EHCI-speciﬁc PCI registers . . . . . . . . . . . . . . .23

Table 26. SBRN register: bit description . . . . . . . . . . . . .23

Table 27. FLADJ register: bit allocation . . . . . . . . . . . . . .23

Table 28. FLADJ register: bit description . . . . . . . . . . . .23

Table 29. FLADJ value as a function of SOF cycle time .23

Table 30. PORTWAKECAP register: bit description . . . .24

Table 31. Power management registers . . . . . . . . . . . . .24

Table 32. CAP_ID register: bit description . . . . . . . . . . .24

Table 33. NEXT_ITEM_PTR register: bit description . . .25

Table 34. PMC register: bit allocation . . . . . . . . . . . . . . .25

Table 35. PMC register: bit description . . . . . . . . . . . . . .25

Table 36. PMCSR register: bit allocation . . . . . . . . . . . . .27

Table 37. PMCSR register: bit description . . . . . . . . . . .27

Table 38. PMCSR_BSE register: bit allocation . . . . . . . .28

Table 39. PMCSR_BSE register: bit description . . . . . . .28

Table 40. PCI bus power and clock control . . . . . . . . . . .29

Table 41. Data register: bit description . . . . . . . . . . . . . .29

Table 42. USB Host Controller registers . . . . . . . . . . . . .33

Table 43. HcRevision register: bit allocation . . . . . . . . . .35

Table 44. HcRevision register: bit description . . . . . . . . .36

Table 45. HcControl register: bit allocation . . . . . . . . . . .36

Table 46. HcControl register: bit description . . . . . . . . . .37

Table 47. HcCommandStatus register: bit allocation . . .39

Table 48. HcCommandStatus register: bit description . .39

Table 49. HcInterruptStatus register: bit allocation . . . . .40

Table 50. HcInterruptStatus register: bit description . . . .41

Table 51. HcInterruptEnable register: bit allocation . . . .42

Table 52. HcInterruptEnable register: bit description . . .42

Table 53. HcInterruptDisable register: bit allocation . . . .43

Table 54. HcInterruptDisable register: bit description . . .44

Table 55. HcHCCA register: bit allocation . . . . . . . . . . . .45

Table 56. HcHCCA register: bit description . . . . . . . . . .45

Table 57. HcPeriodCurrentED register: bit allocation . . .45

Table 58. HcPeriodCurrentED register: bit description . .46

Table 59. HcControlHeadED register: bit allocation . . . .46

Table 60. HcControlHeadED register: bit description . . .46

Table 61. HcControlCurrentED register: bit allocation . .47

Table 62. HcControlCurrentED register: bit description .47

Table 63. HcBulkHeadED register: bit allocation . . . . . .47

Table 64. HcBulkHeadED register: bit description . . . . .48

Table 65. HcBulkCurrentED register: bit allocation . . . . .48

Table 66. HcBulkCurrentED register: bit description . . .49

Table 67. HcDoneHead register: bit allocation . . . . . . . .49

Table 68. HcDoneHead register: bit description . . . . . . .49

Table 69. HcFmInterval register: bit allocation . . . . . . . .50

Table 70. HcFmInterval register: bit description . . . . . . .50

Table 71. HcFmRemaining register: bit allocation . . . . .51

Table 72. HcFmRemaining register: bit description . . . .51

Table 73. HcFmNumber register: bit allocation . . . . . . . .51

Table 74. HcFmNumber register: bit description . . . . . .52

Table 75. HcPeriodicStart register: bit allocation . . . . . .52

Table 76. HcPeriodicStart register: bit description . . . . .53

Table 77. HcLSThreshold register: bit allocation . . . . . .53

Table 78. HcLSThreshold register: bit description . . . . .54

Table 79. HcRhDescriptorA register: bit allocation . . . . .54

Table 80. HcRhDescriptorA register: bit description . . . .55

Table 81. HcRhDescriptorB register: bit allocation . . . . .56

Table 82. HcRhDescriptorB register: bit description . . . .56

Table 83. HcRhStatus register: bit allocation . . . . . . . . .57

Table 84. HcRhStatus register: bit description . . . . . . . .57

Table 85. HcRhPortStatus[1:4] register: bit allocation . .58

Table 86. HCRhPortStatus[1:4] register: bit description .59

Table 87. Legacy support registers . . . . . . . . . . . . . . . . .62

Table 88. Emulated registers . . . . . . . . . . . . . . . . . . . . .62

Table 89. HceControl register: bit allocation . . . . . . . . . .62

Table 90. HceControl register: bit description . . . . . . . . .63

Table 91. HceInput register: bit allocation . . . . . . . . . . . .63

Table 92. HceInput register: bit description . . . . . . . . . .64

Table 93. HceOutput register: bit allocation . . . . . . . . . .64

Table 94. HceOutput register: bit description . . . . . . . . .65

Table 95. HceStatus register: bit allocation . . . . . . . . . . .65

Product data sheet Rev. 02 — 5 March 2007 100 of 103

continued >>

NXP Semiconductors ISP1561

HS USB PCI Host Controller

Table 96. HceStatus register: bit description . . . . . . . . . .65

Table 97. CAPLENGTH/HCIVERSION register: bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 98. CAPLENGTH/HCIVERSION register: bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 99. HCSPARAMS register: bit allocation . . . . . . . .67

Table 100.HCSPARAMS register: bit description . . . . . . .67

Table 101.HCCPARAMS register: bit allocation . . . . . . . .68

Table 102.HCCPARAMS register: bit description . . . . . . .69

Table 103.USBCMD register: bit allocation . . . . . . . . . . .69

Table 104.USBCMD register: bit description . . . . . . . . . .70

Table 105.USBSTS register: bit allocation . . . . . . . . . . . .72

Table 106.USBSTS register: bit description . . . . . . . . . . .72

Table 107.USBINTR register: bit allocation . . . . . . . . . . .74

Table 108.USBINTR register: bit description . . . . . . . . . .74

Table 109.FRINDEX register: bit allocation . . . . . . . . . . .75

Table 110.FRINDEX register: bit description . . . . . . . . . .76

Table 111.N based value of FLS[1:0] . . . . . . . . . . . . . . . .76

Table 112.PERIODICLISTBASE register: bit allocation . .77

Table 113.PERIODICLISTBASE register: bit description .77

Table 114.ASYNCLISTADDR register: bit allocation . . . .77

Table 115.ASYNCLISTADDR register: bit description . . .78

Table 116.CONFIGFLAG register: bit allocation . . . . . . .78

Table 117.CONFIGFLAG register: bit description . . . . . .78

Table 118.PORTSC 1, 2, 3, 4 register: bit allocation . . . .79

Table 119.PORTSC 1, 2, 3, 4 register: bit description . . .79

Table 120.Current consumption when SEL2PORTS is

HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 121.Current consumption when SEL2PORTS is

LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 122.Current consumption: S1 and S3 . . . . . . . . . . .84

Table 123.Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 124.Recommended operating conditions . . . . . . . .85

Table 125.Static characteristics: I2C-bus interface (SDA

and SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 126.Static characteristics: digital pins . . . . . . . . . . .86

Table 127.Static characteristics: PCI interface block . . . .86

Table 128.Static characteristics: USB interface block

(pins DM1 to DM4 and DP1 to DP4) . . . . . . . .86

Table 129.Dynamic characteristics: system clock timing .88

Table 130.Dynamic characteristics: I2C-bus interface

(SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . .88

Table 131.Dynamic characteristics: PCI interface block . .88

Table 132.Dynamic characteristics: high-speed source

electrical characteristics . . . . . . . . . . . . . . . . .88

Table 133.Dynamic characteristics: full-speed source

electrical characteristics . . . . . . . . . . . . . . . . .89

Table 134.Dynamic characteristics: low-speed source

electrical characteristics . . . . . . . . . . . . . . . . .89

Table 135.PCI clock and IO timing . . . . . . . . . . . . . . . . . .90

Table 136.SnPb eutectic process (from J-STD-020C) . . .94

Table 137.Lead-free process (from J-STD-020C) . . . . . .94

Table 138.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .95

Table 139.Revision history . . . . . . . . . . . . . . . . . . . . . . . .97

Product data sheet Rev. 02 — 5 March 2007 101 of 103

continued >>

NXP Semiconductors ISP1561

HS USB PCI Host Controller

25. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2. Pin conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . .5

Fig 3. EEPROM connection diagram. . . . . . . . . . . . . . .30

Fig 4. Information loading from EEPROM . . . . . . . . . . .31

Fig 5. PCI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Fig 6. PCI input timing . . . . . . . . . . . . . . . . . . . . . . . . . .91

Fig 7. PCI output timing . . . . . . . . . . . . . . . . . . . . . . . . .91

Fig 8. USB source differential data-to-EOP transition

skew and EOP width . . . . . . . . . . . . . . . . . . . . . .91

Fig 9. Package outline SOT420-1 (LQFP128) . . . . . . . .92

Fig 10. Temperature proﬁles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Product data sheet Rev. 02 — 5 March 2007 102 of 103

continued >>

NXP Semiconductors ISP1561

HS USB PCI Host Controller

26. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Functional description . . . . . . . . . . . . . . . . . . 11

7.1 OHCI Host Controller . . . . . . . . . . . . . . . . . . . 11

7.2 EHCI Host Controller . . . . . . . . . . . . . . . . . . . 11

7.3 Dynamic port-routing logic . . . . . . . . . . . . . . . 11

7.4 Hi-Speed USB analog transceivers . . . . . . . . 11

7.5 LED indicators for downstream ports . . . . . . . 11

7.6 Power management . . . . . . . . . . . . . . . . . . . . 12

7.7 Legacy support. . . . . . . . . . . . . . . . . . . . . . . . 12

7.8 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . 12

8 PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8.1 PCI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 12

8.1.1 PCI conﬁguration space . . . . . . . . . . . . . . . . . 12

8.1.2 PCI initiator and target . . . . . . . . . . . . . . . . . . 13

8.2 PCI conﬁguration registers . . . . . . . . . . . . . . . 13

8.2.1 PCI conﬁguration header registers. . . . . . . . . 14

8.2.1.1 Vendor ID register (address: 00h). . . . . . . . . . 14

8.2.1.2 Device ID register (address: 02h). . . . . . . . . . 14

8.2.1.3 Command register (address: 04h) . . . . . . . . . 15

8.2.1.4 Status register (address: 06h) . . . . . . . . . . . . 16

8.2.1.5 Revision ID register (address: 08h) . . . . . . . . 18

8.2.1.6 Class Code register (address: 09h) . . . . . . . . 18

8.2.1.7 CacheLine Size register (address: 0Ch). . . . . 19

8.2.1.8 Latency Timer register (address: 0Dh). . . . . . 19

8.2.1.9 Header Type register (address: 0Eh) . . . . . . . 19

8.2.1.10 BIST register (address: 0Fh) . . . . . . . . . . . . . 20

8.2.1.11 Base Address registers. . . . . . . . . . . . . . . . . . 20

8.2.1.12 CardBus CIS Pointer register (address: 28h) . 20

8.2.1.13 Subsystem Vendor ID register (address: 2Ch) 20

8.2.1.14 Subsystem ID register (address: 2Eh) . . . . . . 21

8.2.1.15 Expansion ROM Base Address register

(address: 30h). . . . . . . . . . . . . . . . . . . . . . . . . 21

8.2.1.16 Capabilities Pointer register (address: 34h) . . 21

8.2.1.17 Interrupt Line register (address: 3Ch). . . . . . . 21

8.2.1.18 Interrupt Pin register (address: 3Dh) . . . . . . . 22

8.2.1.19 MIN_GNT and MAX_LAT registers (address:

3Eh and 3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.2.1.20 TRDY Timeout register (R/W: 40h). . . . . . . . . 22

8.2.1.21 Retry Timeout register (R/W: 41h) . . . . . . . . . 22

8.2.2 Enhanced Host Controller-speciﬁc PCI

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.2.2.1 SBRN register (address: 60h) . . . . . . . . . . . . 23

8.2.2.2 FLADJ register (address: 61h). . . . . . . . . . . . 23

8.2.2.3 PORTWAKECAP register (address: 62h) . . . 24

8.2.3 Power management registers. . . . . . . . . . . . . 24

8.2.3.1 CAP_ID register (address: value read from

address 34h + 0h) . . . . . . . . . . . . . . . . . . . . . 24

8.2.3.2 NEXT_ITEM_PTR register (address: value

read from address 34h + 1h) . . . . . . . . . . . . . 25

8.2.3.3 PMC register (address: value read from

address 34h + 2h) . . . . . . . . . . . . . . . . . . . . . 25

8.2.3.4 PMCSR register (address: value read from

address 34h + 4h) . . . . . . . . . . . . . . . . . . . . . 26

8.2.3.5 PMCSR_BSE register (address: value read

from address 34h + 6h) . . . . . . . . . . . . . . . . . 28

8.2.3.6 Data register (address: value read from

address 34h + 7h) . . . . . . . . . . . . . . . . . . . . . 29

2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 30

9.1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9.2 Hardware connections . . . . . . . . . . . . . . . . . . 30

9.3 Information loading from EEPROM . . . . . . . . 31

10 Power management. . . . . . . . . . . . . . . . . . . . . 31

10.1 PCI bus power states. . . . . . . . . . . . . . . . . . . 31

10.2 USB bus states . . . . . . . . . . . . . . . . . . . . . . . 32

11 USB Host Controller registers . . . . . . . . . . . . 32

11.1 OHCI USB Host Controller operational

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

11.1.1 HcRevision register (address: content of the

base address register + 00h) . . . . . . . . . . . . . 35

11.1.2 HcControl register (address: content of the

base address register + 04h) . . . . . . . . . . . . . 36

11.1.3 HcCommandStatus register (address: content

of the base address register + 08h) . . . . . . . . 38

11.1.4 HcInterruptStatus register (address: content

of the base address register + 0Ch). . . . . . . . 40

11.1.5 HcInterruptEnable register (address: content

of the base address register + 10h) . . . . . . . . 41

11.1.6 HcInterruptDisable register (address: content

of the base address register + 14h) . . . . . . . . 43

11.1.7 HcHCCA register (address: content of the

base address register + 18h) . . . . . . . . . . . . . 44

11.1.8 HcPeriodCurrentED register (address: content

of the base address register + 1Ch). . . . . . . . 45

11.1.9 HcControlHeadED register (address: content

of the base address register + 20h) . . . . . . . . 46

NXP Semiconductors ISP1561

HS USB PCI Host Controller

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 5 March 2007

Document identifier: ISP1561_2

Please be aware that important notices concerning this document and the product(s)