6.07
JANUARY 2009
DSC-3016/10
1
©2009 Integrated Device Technology, Inc.
Random
Access
Port
Controls
Sequential
Access
Port
Controls
8KX16
Memory
Array
Data
L
Data
R
Addr
L
Addr
R
I/O
0-15
SI/O
0-15
Pointer/
Counter
13
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
EOB
1
EOB
2
13
13
13
16
13
13
RST
COMPARATOR
LB
UB
A
0-12
13
CE
OE
R/W
LSB
MSB
CMD
16
RST
SCLK
CNTEN
SOE
SSTRT
2
SCE
SR/W
SLD
SSTRT
1
16
13
3016 drw 01
Reg.
,
HIGH SPEED 128K (8K X 16 BIT)
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM™)
Functional Block Diagram
IDT70825S/L
Features
◆◆
◆◆
◆High-speed access
– Commercial: 20/25/35/45ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT70825S
Active: 775mW (typ.)
Standby: 5mW (typ.)
– IDT70825L
Active: 775mW (typ.)
Standby: 1mW (typ.)
◆◆
◆◆
◆8K x 16 Sequential Access Random Access Memory
(SARAM™)
– Sequential Access from one port and standard Random
Access from the other port
– Separate upper-byte and lower-byte control of the
Random Access Port
◆◆
◆◆
◆High speed operation
– 20ns tAA for random access port
– 20ns tCD for sequential port
– 25ns clock cycle time
◆◆
◆◆
◆Architecture based on Dual-Port RAM cells
◆◆
◆◆
◆Compatible with Intel BMIC and 82430 PCI Set
◆◆
◆◆
◆Width and Depth Expandable
◆◆
◆◆
◆Sequential side
– Address based flags for buffer control
– Pointer logic supports up to two internal buffers
◆◆
◆◆
◆Battery backup operation - 2V data retention
◆◆
◆◆
◆TTL-compatible, single 5V (+10%) power supply
◆◆
◆◆
◆Available in 80-pin TQFP and 84-pin PGA
◆◆
◆◆
◆Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Description
The IDT70825 is a high-speed 8K x 16-Bit Sequential Access
Random Access Memory (SARAM). The SARAM offers a single-chip
solution to buffer data sequentially on one port, and be accessed
randomly (asynchronously) through the other port. The device has a
Dual-Port RAM based architecture with a standard SRAM interface for the
random (asynchronous) access port, and a clocked interface with counter
2
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PN-80-1 package body is approximately 14mm x 14mm x 1.4mm.
G84-3 package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
sequencing for the sequential (synchronous) access port.
Fabricated using CMOS high-performance technology, this memory
device typically operates on less than 775mW of power at maximum
high-speed clock-to-data and Random Access. An automatic power
down feature, controlled by CE, permits the on-chip circuitry of each port
to enter a very low standby power mode.
The IDT70825 is packaged in a 80-pin Thin Quad Flatpack (TQFP)
or 84-pin Pin Grid Array (PGA).
3016 drw 02
4
5
6
7
8
9
10
INDEX
11
12
13
14
180 79 78 77 76 75 74 73 72 71
23 24 25 26 27 28 29 30 31 32 33 34 35
3
2
15
16
17
18
19
20
21 22 36 37 38 39 4041
42
43
62 61
60
59
58
57
56
55
54
53
52
6364
51
50
49
48
47
46
45
44
70 69 68 67 66 65
IDT70825PF
PN80-1
(4)
80-PinTQFP
Top View
(5)
GND
GND
V
CC
GND
V
CC
V
CC
GND
V
CC
N/C
A
12
GND
V
CC
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
1
A
2
CMD
CE
LB
UB
R/W
OE
A
11
V
CC
A
0
SSTRT
1
SCLK
SI/O
9
SI/O
7
SI/O
10
SI/O
15
SI/O
14
SI/O
8
SI/O
11
SI/O
12
SI/O
4
SI/O
2
SI/O
13
SI/O
6
GND
SI/O
0
N/C
I/O
0
CNTEN
SLD
SCE
SR/W
RST
SSTRT
2
SI/O
1
GND
GND
GND
EOB
2
V
CC
SOE
EOB
1
I/O
1
I/O
15
I/O
14
I/O
13
I/O
12
I/O
2
I/O
3
I/O
4
I/O
5
I/O
7
I/O
6
I/O
9
I/O
10
I/O
11
I/O
8
SI/O
5
SI/O
3
,
3016 drw 03
63 61 60 58 55 54 51 48 46 45
66
67
69
72
75
76
79
81
82
83
125
7
8
11
10
12
14 17 20
23
26
28 29
32 31
33 35
38
41
43
IDT70825G
G84-3
(4)
84-Pin PGA
Top View
(5)
ABCDEFGHJKL
42
59 56 49 50 40
25
27
30
36
34
37
39
84346915131618
22 24
19 21
68
71
70
77
80
11
10
09
08
07
06
05
04
03
02
01
64
65
62
57 53 52
47 44
73
74
78
A
3
NC R/WUB A
1
CE A
5
A
6
A
8
A
9
A
11
I/O
14
NC V
CC
CMD A
2
NC SI/O
15
I/O
12
I/O
13
SI/O
14
SI/O
13
I/O
9
I/O
5
I/O
8
SI/O
9
SI/O
10
SI/O
6
I/O
4
SI/O
4
SI/O
5
I/O
3
GND
SSTRT1
SCLK GND SI/O
2
V
CC
I/O
7
I/O
6
GND SI/O
8
SI/O
7
GND
NC I/O
0
EOB
2
SOE RST SLD SI/O
1
SI/O
3
SCE SI/O
0
I/O
1
GND
CNTEN
GND
SSTRT2
SR/WGND NC
NCV
CC
I/O
15
GND OE A
0
LB V
CC
A
10
A
12
GND
A
4
A
7
I/O
10
V
CC
V
CC
SI/O
11
I/O
11
SI/O
12
I/O
2
V
CC
INDEX
EOB
1
,
Pin Configura tions(1,2,3)
6.42
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
3
Pin Descriptions: Random Access Port(1)
Pin Descriptions: Sequential Access Port(1)
NOTE:
1. "I/O" is bidirectional input and output. "I" is input and "O" is output.
SYMBOL NAME I/O DESCRIPTIONS
A
0-
A
12
Address Line s I Ad dress inputs to acc ess the 8192-word (16-Bit) memory array.
I/O
0
-I/O
15
Inp uts/Outp uts I Rand o m ac ce ss d ata inp uts / o utp uts fo r 16-B it wid e d a ta.
CE Chip Enable I When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled
into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during CE =
V
IH
, unless it is altered by the sequential port. CE and CMD m ay not be L O W at the sam e ti me .
CMD Co ntro l Reg is te r
Enable I When CMD is LOW, add res s lines A
0
-A
2
, R/ W, and i n p uts / out p uts I/O
0
-I/O
12
, are use d to ac ce ss the control
register, the flag register, and the start and end of buffer registers. CMD and CE may not be LOW at the same
time.
R/WRead/ Wri te E na b l e I If CE is LOW and CMD is HIGH, d ata i s written i n to the array whe n R/ W is LOW and read o ut of the array when
R/W is HIGH. If CE i s HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and
CMD may not be LOW at the same time.
OE Outp ut Enable I When OE is LOW and R/ W is HIGH, I/O
0
-I/O
15
outp uts are enab le d . When OE is HIGH, th e I/ O o utputs are in
the High-impedance state.
LB, UB Lo we r By te , Up p e r
Byte Enables I W hen LB is LOW, I/O
0
-I/O
7
are ac ce ss ib le fo r read and write o pe ratio ns. Whe n LB is HIGH I/O
0
-I/O
7
are tri-
stated and blocked during read and write operations. UB c ontro ls acc ess fo r I/O
8
-I/O
15
in the same manne r and
is asynchronous from LB.
V
CC
Power Supply I Seven +5V powe r supply pins. All V
CC
pins must be co nnecte d to the same +5V V
CC
supply.
GND Gro und I Ten gro und p ins. All ground pins must be connecte d to the same ground sup ply.
3 016 tb l 01
SYMBOL NAME I/O DESCRIPTIONS
SI/O
0-15
Inp uts/Outp uts I S e q ue ntial d ata inp uts /o utp uts fo r 16-b it wid e d ata.
SCLK Clock I SI/O
0
-SI/O
15
, SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential
ac ces s p ort a d d re ss p oi nte r i nc re m e n ts b y 1 o n e a ch L OW -to -HIG H tr an s i ti o n o f S CLK wh e n CNTEN is LOW.
SCE Chip Enable I When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of SCLK. When SCE
is HIGH, the sequential access port is disabled into powere d-down mode on the LOW-to-HIGH transition of
SCLK, and the SI/O outputs are in the High-impedance state. All data is retained, unless altered by the random
access port.
CNTEN Control Enable I When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is
independent of CE.
SR/WRe ad /Wri te E nab l e I Whe n S R/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/ W is
HIGH, a nd SCE and SOE are LOW, a read c ycle is initiated o n the LOW-to-HIGH transitio n of SCLK. Termi nation
of a write cycle is d one on the LOW-to-HIGH trans ition of SCLK if SR/ W or SCE is HIGH.
SLD Address Pointer
Load Control IWhen SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. When
SLD is LOW, data on the inputs SI/O
0
-SI/O
12
is lo ad e d into a da ta-i n r eg is ter o n the LOW-to -HIGH transitio n o f
SCLK. On the cycle following SLD, the address pointer changes to the address location contained in the data-
in register. SSTRT
1
and SSTRT
2
may not be LOW while SLD is LOW or during the cycle following SLD.
SSTRT
1
,
SSTRT
2
Load S tart of
Address Register IWhen SSTRT
1
or SSTRT
2
is LOW, the start of address register #1 or #2 is loaded into the address pointer on
the LOW-to-HIGH transition of SCLK. The start address are stored in internal registers. SSTRT
1
and SSTRT
2
may no t b e LOW whil e SLD is LOW or during the cycle following SLD.
EOB
1
,
EOB
2
End of Buffer Flag I EOB
1
or EOB
2
is output LOW when the address pointer is incremented to match the addre ss stored in the end
of the buffer registers. The flags can be cleared by either asserting RST LOW or by writing zero into Bit 0
and/or Bit 1 of the control register at address 101. EOB
1
and EOB
2
are dependent on separate internal
registers, and therefore separate match addresses.
SOE Output Enable I SOE controls the data outputs and is independent of SCLK. When SOE is LOW, o utput b uffe rs and the
sequentially addressed data is output. When SOE is HIGH, the SI/O output bus is in the High-impedance state.
SOE is asynchronous to SCLK.
RST Reset I When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the
EOB
1
and EOB
2
flag s are se t HIG H. Rs t is as ync hr ono us to SCLK .
3016 tbl 02
4
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Capacitance
(TA = +25°C, f = 1.0mhz, TQFP only)
Recommended DC Oper ating
Conditions
Recommended Operating
Temperature and Supply Voltage(1,2)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM >
Vcc + 10%.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2.Industrial temperature: for specific speeds, packages and powers contact your
sales office.
NOTES:
1. VIL > –1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization, but is not production
tested.
2.3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Symbol Rating Commercial
& Industrial Unit
V
TERM
(2)
Terminal Voltage
with Re sp e ct
to GND
-0.5 to +7.0 V
T
BIAS
Temperature
Under Bias -55 to + 125
o
C
T
STG
Storage
Temperature -65 to + 150
o
C
I
OUT
DC O utp u t
Current 50 mA
3016 tb l 03a
Grade Ambient
Temperature GND Vcc
Commercial 0
O
C to + 70
O
C0V5.0V
+
10%
Industrial -40
O
C to +8 5
O
C0V5.0V
+
10%
3016 tb l 04a
Symbol Parameter Min. Typ. Max. Unit
V
CC
Sup p ly Vol tag e 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.2
____
6.0
(2)
V
V
IL
Input Lo w Voltage -0.5
(1)
____
0.8 V
3016 tbl 05
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Inp ut Cap ac itance V
IN
= 3dV 9 pF
C
OUT
Output Cap acitanc e V
OUT
= 3dV 10 pF
3016 tbl 06
Symbol Parameter Test Conditions
70825S 70825L
UnitMin. Max. Min. Max.
|I
LI
| Inp ut Le akag e Curre nt V
CC
= 5.5V, V
IN
= 0V to V
CC
___
5
___
1µA
|I
LO
| Outp ut Le ak age Curre nt V
OUT
= 0V to V
CC
___
5
___
1µA
V
OL
Output Low Vo ltage I
OL
= +4mA
___
0.4
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
3016 tbl 07
6.42
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,2,8) (VCC = 5.0V ± 10%)
Data Retention Characteristics Over All Temperature Ranges
(L Ver sion Only) (VLC < 0.2V, VHC > VCC - 0.2V)
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. VCC = 5V, TA = +25°C; guaranteed by device characterization but not production tested.
3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. SCE may transition, but is LOW (SCE=VIL) when clocked in by SCLK.
6. SCE may be - 0.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown.
7. If one port is enabled (either CE or SCE = LOW) then the other port is disabled (SCE or CE = HIGH, respectively). CMOS HIGH > Vcc - 0.2V and LOW < 0.2V, and
TTL HIGH = VIH and LOW = VIL.
8. Industrial temperature: for other speeds, packages and powers contact your sales office.
NOTES :
1. TA = +25°C, VCC = 2V; guaranteed by device characterization but not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention, SCE = VIH must be clocked in.
70825X20
Com'l Only 70825X25
Com'l Only 70825X35
Co m ' l O nl y 70825X45
Com 'l On ly
Symbol Parameter Test Condition Versi on Typ. Max. Typ. Max. Typ. Max. Typ. Max. Uni t
I
CC
Dy nami c Op e rating
Current
(Both Ports Active)
CE = V
IL
,
Outputs Disabled
SCE = V
IL
(5)
f = f
MAX
(3)
COM'L S
L180
180 380
330 170
170 360
310 160
160 340
290 155
155 340
290 mA
I
SB1
S tand b y Curre nt
(B o th Ports - TTL
Le v e l Inp uts )
SCE and CE > V
IH
(7)
CMD = V
IH
f = f
MAX
(3)
COM'L S
L25
25 70
50 25
25 70
50 20
20 70
50 16
16 70
50 mA
I
SB2
S tand b y Curre nt
(One P o rt - TTL
Le v e l Inp uts )
CE or SCE
= V
IH
Active Port Outputs Disabled,
f=f
MAX
(3)
COM'L S
L115
115 260
230 105
105 250
220 95
95 240
210 90
90 240
210 mA
I
SB3
Full Standby Current
(Both Po rts -
CM O S Lev el In pu ts)
Both Po rts CE and
SCE > V
CC
- 0. 2V
(6,7)
V
IN
> V
CC
- 0. 2V o r
V
IN
< 0. 2V, f = 0
(4)
COM'L S
L1.0
0.2 15
51.0
0.2 15
51.0
0.2 15
51.0
0.2 15
5mA
I
SB4
Full Standby Current
(One Po rt -
CM O S Lev el In pu ts)
One Po rt CE or
SCE > V
CC
- 0. 2V
(6)
Outputs Disabled (Active Port)
V
IN
> V
CC
- 0. 2V o r V
IN
< 0. 2V
f = f
MAX
(3)
COM'L S
L110
110 240
200 100
100 230
190 90
90 220
180 85
85 220
180 mA
3016 tbl 08a
Symbol Parameter Test Condition Min. Typ.
(1)
Max. Unit
V
DR
V
CC
fo r Data Re te ntio n V
CC
= 2V 2. 0
___ ___
V
I
CCDR
Data Re te nti o n Curre nt CE > V
HC
V
IN
= V
HC
or = V
LC
IND.
___
100 4000 µA
COM'L.
___
100 1500
t
CDR
(3)
Chip Dese lec t to Data Re te ntio n Time SCE = V
HC
(4)
whe n SCLK = ↑
CMD = V
HC
___ ___ ___
V
t
R
(3)
Op e ratio n Re c ov ery Time t
RC
(2)
___ ___
V
3016 tb l 09a
6
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
DATA RETENTION MODE
V
CC
CE
3016 drw 04
4.5V
t
CDR
t
R
V
DR
V
IH
4.5V
V
DR
2V
≥
S
CLK
SCE
V
IH
I
CC
I
SB
t
PD
I
SB
t
PU
NOTES:
1. SCE is synchronized to the sequential clock input.
2. CMD > VCC - 0.2V.
Data Retention and Power Down/Up Waveform
(Random and Sequential Por t)
(1,2)
Figure 3. Lumped Capacitance Load Typical Derating Curve
Figure 1. AC Output Test Load
AC TEST CONDITIONS
Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, t CHZ,
tBHZ, tOHZ, tWHZ, tCKHZ, and tCKLZ)
*Including scope and jig.
3016 drw 06
893Ω
30pF
347Ω
5V
DATA
OUT
893Ω
5pF*
347Ω
5V
DATA
OUT
3016 drw 05
,
Inp ut Pul se Le ve ls
Inp ut Ris e/Fall Time s
Inp ut Timi ng Re fere nce Le ve ls
Outp ut Refe renc e Le ve ls
Outp ut Lo ad
GND to 3.0V
3ns Max.
1.5V
1.5V
Fi gu re s 1, 2 and 3
3016 t b l 10
1
2
3
4
5
6
7
8
20 40 60 80 100 120 140 160180 200
CAPACITANCE (pF)
10pF is the I/O
capacitance of
this device, and
30pF is the AC
Test Load
capacitance.
3016 drw 07
tAA/tCD/tEB
(Typical, ns)
-1
-2
-3
,
6.42
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
7
Truth Table II: Sequential Read(1,2,3,6,8)
Truth Table I: Random Access R ead and Write(1,2)
Truth Ta ble III: Sequential Write(1,2,3,4,5,6,7,8)
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT2, SCLK, SI/O0-SI/O15, EOB1, EOB2, and SOE are unrelated to the random access port control and operation.
3. If OE = VIL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using UB and LB separately are also allowed.
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance. LOW = VOL.
2. RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations.
3. CE, OE, R/W, CMD, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the sequential
port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge of the clock
during the cycle in which SR/W = VIL.
5. SI/OIN refers to SI/O0-SI/O15 inputs.
6. "LAST" refers to the previous value still being output, no change.
7. Termination of a write is done on the LOW-to-HIGH transition of SCLK if SR/W or SCE is HIGH.
8. When CLKEN=LOW, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter Enable Cycle after
Reset, Read (and write) Cycle".
Inputs/Outputs
Mode
CE CMD R/WOE LB UB I/O
0
-I/O
7
I/O
8-
I/O
15
LHHLLLDATA
OUT
DATA
OUT
Re ad b oth By te s.
LHHLLHDATA
OUT
Hig h-Z Re ad l o wer Byte o nly.
LHHLHLHigh-ZDATA
OUT
Read upp e r By te o nly.
LHL H
(3)
LLDATA
IN
DATA
IN
Wri te to both B y tes .
LHL H
(3)
LHDATA
IN
Hig h-Z Write to lo we r B y te o nly.
LHL H
(3)
H L High-Z DATA
IN
Write to upper Byte only.
H H X X X X High-Z High-Z Both Bytes deselected and powered down.
L H H H X X High-Z High-Z Outputs disabled but not powered down.
L H X X H H High-Z High-Z Both Bytes deselected but not powered down.
HLL H
(3)
L
(4)
L
(4)
DATA
IN
DATA
IN
Wri te I/ O
0
-I/O
11
to the B u ffe r C o m man d Re gi s ter.
HLHL
L
(4)
L
(4)
DATA
OUT
DATA
OUT
Read c onte nts o f the Buffer Command Reg ister
via I/O
0
-I/O
12
.
3016 tbl 11
Inputs/Outputs
MODESCLK SCE CNTEN SR/WEOB
1
EOB
2
SOE SI/O
↑LLHLOWLASTL[EOB
1
] Co unte r A dv anc e d Se quenti al Re ad wi th EOB
1
reac hed.
↑L H H LAST LAST L [EOB
1 - 1
] Non-Counter Advanced Sequential Read, without EOB
1
re ache d
↑LLHLASTLOWL[EOB
2
] Co unte r A dv anc e d Se quenti al Re ad wi th EOB
2
re c he d .
↑L H H LAST LAST L [EOB
2 - 1
] Non-Counter Advanced Sequential Read without EOB
2
reac hed .
↑L L H L OW LOW H Hi gh-Z Co unt er A d v ance d Se que ntial No n-Read wit h EOB
1
and EOB
2
re ached .
3016 tbl 12
Inputs/Outputs
MODESCLK SCE CNTEN SR/WEOB
1
EOB
2
SOE SI/O
↑L H L LAST LAST H SI/O
IN
Non-Counter Advanced Sequential Write, without EOB
1
or EOB
2
re ache d .
↑LL LLOWLOWHSI/O
IN
Coounte r Advanced Sequential Write with EOB
1
and EOB
2
re ached .
↑H H X LAST LAST X High-Z No Write or Read due to Sequential port Deselect. No counter advance.
↑H L X NEXT NEXT X High-Z No Write or Read due to Sequential port Deselect. Counter does advance.
3016 tbl 13
8
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
Truth Table IV: Sequential Ad dress Pointer Operations(1,2,3,4,5)
Address Pointer Load Control (SLD)
In SLD mode, there is an internal delay of one cycle before the
address pointer changes in the cycle following SLD. When SLD is
LOW, data on the inputs SI/O0-SI/O12 is loaded into a data-in register
on the LOW-to-HIGH transition of SCLK. On the cycle following SLD,
the address pointer changes to the address location contained in the
data-in register. SSTRT1, SSTRT2 may not be low while SLD is LOW,
or during the cycle following SLD. The SSTRT1 and SSTRT2 require
only one clock cycle, since these addresses are pre-loaded in the
registers already.
NOTE:
1. At SCLK edge (A), SI/O0-SI/O12 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e. address
pointer changes). At SCLK edge (A), SSTRT1 and SSTRT2 must be HIGH to ensure for proper sequential address pointer loading. At SCLK edge (B), SLD and
SSTRT1,2 must be HIGH to ensure for proper sequential address pointer loading. For SSTRT1 or SSTRT2, the data to be read will be ready for edge (B), while data will
not be ready at edge (B) when SLD is used, but will be ready at edge (C).
Sequential Load of Address into Pointer/Counter(1)
SLD MODE(1)
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST is continuously HIGH. The conditions of SCE, CNTEN, and SR/W are unrelated to the sequential address pointer operations.
3. CE, OE, R/W, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with the sequential port
operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address is not incremented
during the two cycles.
6. SOE may be LOW with SCE deselect or in the write mode using SR/W.
Inputs/Outputs
MODESCLK SLD SSTRT
1
SSTRT
2
SOE
↑H L H X Start address for Buffer #1 loaded into Address Pointer.
↑H H L X Start address for Buffer #2 loaded into Address Pointer.
↑LH H H
(6) Data o n SI/O
0
-SI/O
12
lo ad ed into Ad dre ss Pointer.
3016 tbl 14
SLD
SCLK
S
I/O0-12
SSTRT(1 or 2)
AB
ADDRIN
3016 drw 08
C
DATAOUT
(1)
15
M
SB LSB SI/O BITS
3016 drw 09
HHH
12 ------------------------------------------------------------------------------------------------------------
Address Loaded into Pointer 0
14 13
NOTE:
1. "H" = VIH for the SI/O intput state.
6.42
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
9
Case 5: Buffer Flow Modes
Within the SARAM, the user can designate one of four buffer flow
modes for each buffer. Each buffer flow mode defines a unique set of
actions for the sequential port address pointer and EOB flags. In
BUFFER CHAINING mode, after the address pointer reaches the end
of the buffer, it sets the corresponding EOB flag and continues from the
start address of the other buffer. In STOP mode, the address pointer
stops incrementing after it reaches the end of the buffer. In LINEAR
mode, the address pointer ignores the end of buffer address and
increments past it, but sets the EOB flag. MASK mode is the same as
LINEAR mode except EOB flags are not set.
Cases 1 through 4: Start and End of Buffer Register Description(1,2)
Command Mode also allows reading and clearing the status of the
EOB flags. Seven different CMD cases are available depending on the
conditions of A0-A2 and R/W. Address bits A3-A12 and data I/O bits
I/O13-I/O15 are not used during this operation.
Random Access Port CMD Mode(1)
Reset (RST)
Setting RST LOW resets the control state of the SARAM. RST
functions asynchronously of SCLK, (i.e. not registered). The default
states after a reset operation are as follows:
BUFFER COMMAND MODE (CMD)
Buffer Command Mode (CMD) allows the random access port to
control the state of the two buffers. Address pins A0-A2 and I/O pins I/
O0-I/O12 are used to access the start of buffer and the end of buffer
addresses and to set the flow control mode of each buffer. The Buffer
NOTES:
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
2. A write into the buffer occurs when R/W = VIL and a read when R/W = VIH. EOB1/SOB1 and EOB2/SOB2 are chosen through address A0-A2 while CMD = VIL and CE = VIH.
NOTES:
1. R/W input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
Register Contents
Address Pointer 0
EOB Flags Cle are d to Hig h State
Buffer Flo w Mo de BUFFER CHAINING
Start Address Buffer #1 0 (1)
End Address Buffer #1 4095 (4K)
Start Address Buffer #2 4096 (4K+1)
End Add re ss Buffe r # 2 8191 (8K)
Registered State SCE = V
IH
, SR/W = V
IL
3016 tbl 15
Case # A
2
-A
0
R/W DESCRIPTIONS
1 000 0 (1) Write (read) the start address of Buffer #1 through I/O
0
-I/O
12
.
2 001 0 (1) Write (read ) the e nd a dd res s o f B uffer # 1 thro ugh I/ O
0
-I/O
12
.
3 010 0 (1) Write (read) the start address of Buffer #2 through I/O
0
-I/O
12
.
4 011 0 (1) Write (re ad) the e nd a dd res s o f B uffer # 2 thro ugh I/ O
0
-I/O
12
.
5 100 0 (1) Write (re ad) fl ow co ntrol reg ister.
6 1 01 0 Write only - cle ar EOB
1
and / or EOB
2
flag .
7 101 1 Read only - flag status register.
8 110/111 (X) (Reserved)
3016 tbl 16
15
M
SB LSB I/O BITS
3016 drw 10
HH
12 ------------------------------------------------------------------------------------------------------------
Address Loaded into Buffer 0
14 13
H
10
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
EndofbufferflagforBuffer#
1
EndofbufferflagforBuffer#2
15
0
M
SBHHH HHH HH HHHH H 1 0LSBI/OBITSH
3016 drw 12
Buffer #1 flow control
Buffer #2 flow control
Counter Release
(STOP Mode Only)
15
SB LSB I/O BITS
HHHH HHH432 1 0HHHH
3016 drw 11
NOTE:
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
Flow Control Re gister Description(1,2)
Cases 6 and 7: Flag Status Register Bit Description(1)
Flow Control Bits
Cases 6: Flag Status Register
Write Conditions(1) Case 7: Flag Status Register Read
Conditions
NOTES:
1. "H" = VOH for I/O in the output state and "Don't Cares"' for I/O in the input state.
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously
of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled by CNTEN. The pointer is also released
by RST, SLD, SSTRT1 and SSTRT2 operations.
Cases 8 and 9: (Reserved)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
NOTES:
1. EOB1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
2. CMD flow control bits are unchanged, the count does not continue advancement.
3. If EOB1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1.
4. If counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK otherwise the flow control will
remain in the STOP mode.
NOTES:
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be
cleared while the second is left alone or cleared.
2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
Fl ow Control
Bit 1 & Bit 0
(Bit 3 & B it 2) Mode Functional Description
00 BUFFER
CHAINING EOB
1
(EOB
2
) is asserted (active LOW outp ut) when the pointer matches the end address of Buffe r #1 (Buffer #2). The
pointer value is changed to the start address of Buffer #2 (Buffer #1)
(1,3)
01 STOP EOB
1
(EOB
2
) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
The address pointer will stop incrementing when it reaches the next address (EOB address + 1), if CNTEN is LOW on the
next clock's rising edge. Otherwise, the address pointer will stop incrementing on EOB. Sequential write operations are
inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow control register.
(1,2,4)
10 LINEAR EOB
1
(EOB
2
) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2). The pointer keeps
incrementing for further operations.
(1)
11 MASK EOB
1
(EOB
2
) is not asserted when the pointe r reaches the end address of Buffer #1 (Buffer #2), although the flag status
bits will be set. The pointe r keep s incrementing for furthe r operatio ns.
3016 tbl 17
Flag Status Bit 0, (Bit 1) Functional Description
0 Cl e ars Buffe r Flag EOB
1
, (EOB
2
).
1No change to the Buffer Flag .
(2)
3016 tbl 18
Fl ag S tatus Bi t 0, (Bit 1) Functi onal Descri pti on
0EOB
1
(EOB
2
) flag has not been set, the
pointer has not reached the end of the
buffer.
1EOB
1
(EOB
2
) flag has been set, the
pointer has reached the end of the
buffer.
3016 tbl 19
6.42
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
11
Random Access Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(2,4,5)
Random Access port: AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(2,4,5)
NOTES:
1 . Transition measured at 0mV from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not production
tested.
2. 'X' in part number indicates power rating (S or L).
3. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to turn off and
on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse
is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degradation to tCW timing.
4. CMD access follows standard timing listed for both read and write accesses, (CE = VIH when CMD = VIL) or (CMD = VIH when CE = VIL).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
70825X20
Com'l Only 70825X25
Com'l Only 70825X35
Com'l Only 70825X45
Com 'l Onl y
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.
READ CYCL E
t
RC
Re ad Cyc le Time 20
____
25
____
35
____
45
____
ns
t
AA
Address Access Time
____
20
____
25
____
35
____
45 ns
t
ACE
Chip E nab le A c ce s s Ti me
____
20
____
25
____
35
____
45 ns
t
BE
By te Enab le Ac ce ss Time
____
20
____
25
____
35
____
55 ns
t
OE
Outp ut Enab le Acce ss Time
____
10
____
10
____
15
____
20 ns
t
OH
Output Ho l d fro m A d dre s s Ch ang e 3
____
3
____
3
____
3
____
ns
t
CLZ
Chip S e le c t Lo w-Z Ti me
(1)
3
____
3
____
3
____
3
____
ns
t
BLZ
By te Enab le Lo w-Z Time
(1)
3
____
3
____
3
____
3
____
ns
t
OLZ
Output E nabl e Lo w-Z Tim e
(1)
2
____
2
____
2
____
2
____
ns
t
CHZ
Chip S e le c t Hig h-Z Ti me
(1)
____
10
____
12
____
15
____
15 ns
t
BHZ
By te Enab le Hig h-Z Time
(1)
____
10
____
12
____
15
____
15 ns
t
OHZ
Output E nabl e High-Z Tim e
(1)
____
9
____
11
____
15
____
15 ns
t
PU
Ch ip S e lec t P ower Up Ti m e 0
____
0
____
0
____
0
____
ns
t
PD
Ch ip S e lec t P ower Do w n Ti me
____
20
____
25
____
35
____
45 ns
3016 tb l 20a
Symbol Parameter
70825X20
Com'l Only 70825X25
Co m 'l O nl y 70825X35
Co m 'l On l y 70825X45
Com'l Only
UnitMin. Max. Min. Max. Min. Max. Min. Max.
WRI T E CYC LE
t
WC
Write Cyc le Time 20
____
25
____
35
____
45
____
ns
t
CW
Chip Enab le to End-of-Wri te 15
____
20
____
25
____
30
____
ns
t
AW
Address Valid to End-of-Write
(3)
15
____
20
____
25
____
30
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
(3)
13
____
20
____
25
____
30
____
ns
t
BP
By te Enab le Puls e Width
(3)
15
____
20
____
25
____
30
____
ns
t
WR
Write Rec ove ry Time 0
____
0
____
0
____
0
____
ns
t
WHZ
Write Enable Output in Hig h-Z Time
(1)
____
10
____
12
____
15
____
15 ns
t
DW
Da ta Set- u p Ti m e 1 3
____
15
____
20
____
25
____
ns
t
DH
Da ta Ho l d Tim e 0
____
0
____
0
____
0
____
ns
t
OW
Output Active from End-of-Write 3
____
3
____
3
____
3
____
ns
3016 tb l 21a
12
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
Waveform of Read Cycles: Random Access Port(1,2)
NOTES:
1. R/W is HIGH for read cycle.
2. Address valid prior to or coincident with CE transition LOW; otherwise tAA is the limiting parameter.
Waveform of Read Cycles: Buffer Command Mode
NOTE:
1. CE = VIH when CMD = VIL.
ADDR
OE
t
RC
t
AA
t
OH
ValidDataOut
t
CHZ
t
OHZ
t
BE
t
BLZ
t
OE
t
OLZ
CE
LB,UB
t
ACS
t
CLZ
t
BHZ
I/O
OUT
3016 drw 13
(2)
ADDR
OE
t
RC
t
AA
t
OH
Valid Data Out
t
CHZ
t
OHZ
t
BE
t
BLZ
t
OE
t
OLZ
CMD
LB,UB
t
ACS
t
CLZ
t
BHZ
I/O
OUT
3016 drw 14
(1)
6.42
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
13
Waveform of Write Cycle No.1 (R/W Controlled Timing)
Random Access Port(1,6)
Waveform of Write Cycle No.2 (CE, LB, and/or UB Controlled Timing)
Random Access Port(1,6,7)
NOTES:
1. R/W, CE, or LB and UB must be inactive during all address transitions.
2. A write occurs during the overlap of R/W = VIL, CE = VIL and LB = VIL and/or UB = VIL.
3. tWR is measured from the earlier of CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and the input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to turn off and
on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum write pulse
is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degregation to tCW timing.
7. I/OOUT is never enabled, therefore the output is in HIGH-Z state during the entire write cycle.
8. CMD access follows the standard CE access described above. If CMD = VIL, then CE must = VIH or, when CE = VIL, CMD must = VIH.
CE,LB,UB
ADDR
t
AW
t
WR
t
DW
I/O
IN
t
WC
t
WP
t
DH
R/W
t
AS
I/O
OUT
t
WHZ
t
BE
t
ACS
OE t
OHZ
t
OW
3016 drw 15
(5)
(2) (3)
Data Out
Data Out
(4) (4)
Valid Data In
(8)
t
WR
CE,LB,UB
t
AW
t
DW
I/O
IN
ADDR
t
WC
R/W
t
DH
t
AS
3016 drw 16
Valid Data
(5)
t
BP
(2)
t
CW
(2) (3)
(8)
14
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
Sequential Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(1,3)
Sequential Port: AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,3)
NOTES:
1. 'X' in part number indicates power rating (S or L).
2 . Transition measured at 0mV from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not production
tested.
3. Industrial temperature: for specific speeds, packages and powers contact your sales office.
70825X20
Com'l Only 70825X25
Com'l Only 70825X35
Com'l Only 70825X45
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.
RE AD CYCLE
t
CYC
Sequential Clock Cycle Time 25
____
30
____
40
____
50
____
ns
t
CH
Clock Pulse HIGH 10
____
12
____
15
____
18
____
ns
t
CL
Clock Pulse LOW 10
____
12
____
15
____
18
____
ns
t
ES
Co unt E nab le and A d d re s s P o inte r Set-up Time 5
____
5
____
6
____
6
____
ns
t
EH
Co unt E nab le and Ad dre s s P o i nte r Ho ld Tim e 2
____
2
____
2
____
2
____
ns
t
SOE
Ou tp ut E na b l e to D ata Val i d
____
8
____
10
____
15
____
20 ns
t
OLZ
Output E nab l e Lo w-Z Tim e
(2)
2
____
2
____
2
____
2
____
ns
t
OHZ
Output E nab l e Hig h-Z Tim e
(2)
____
9
____
11
____
15
____
15 ns
t
CD
Clo ck to Valid Data
____
20
____
25
____
35
____
45 ns
t
CKHZ
Clo ck Hig h-Z Time
(2)
____
12
____
14
____
17
____
20 ns
t
CKLZ
Clo ck Lo w-Z Tim e
(2)
3
____
3
____
3
____
3
____
ns
t
EB
Clo ck to EOB
____
13
____
15
____
18
____
23 ns
3016 tbl 22a
Symbol Parameter
70825X20
Com 'l Only 70825X25
Com'l Only 70825X35
Com'l Only 70825X45
Com'l Only
UnitMin. Max. Min. Max. Min. Max. Min. Max.
WRI T E CYCL E
t
CYC
Sequential Clock Cycle Time 25
____
30
____
40
____
50
____
ns
t
FS
Flo w Re start Time 13
____
15
____
20
____
20
____
ns
t
WS
Chip Sele ct and Re ad/Write Se t-up Time 5
____
5
____
6
____
6
____
ns
t
WH
Chip Se le c t and Read /Write Ho ld Time 2
____
2
____
2
____
2
____
ns
t
DS
Inp ut Data S e t-up Time 5
____
5
____
6
____
6
____
ns
t
DH
Inp ut Data Ho ld Ti me 2
____
2
____
2
____
2
____
ns
3016 tb l 23a
6.42
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
15
Sequential Port: Write, Pointer Load Non-Incrementing Read
Sequential Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(1,2)
NOTE:
1. 'X' in part number indicates power rating (S or L).
2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
Symbol Parameter
70825X20
Com'l Only 70825X25
Com'l Only 70825X35
Com'l Only 70825X45
Com'l Only
UnitMin. Max. Min. Max. Min. Max. Min. Max.
RESET CYCLE
t
RSPW
Reset Pulse Width 13
____
15
____
20
____
20
____
ns
t
WERS
Write Enab le HIGH to Re se t HIGH 10
____
10
____
10
____
10
____
ns
t
RSRC
Re s e t HIGH to Write E nab le LOW 10
____
10
____
10
____
10
____
ns
t
RSFV
Res et HIG H to F l ag Val i d 15
____
20
____
25
____
25
____
ns
30 16 tb l 2 4a
SLD
CNTEN
D0
SR/W
SCE
SOE
SCLK
t
CYC
t
CH
t
CL
t
DS
t
DH
t
OHZ
t
EH
t
ES
t
EH
t
ES
(1)
(3)
A0Dx
D0 D0
HIGH IMPEDANCE
t
WS
t
WH
t
CD
t
SOE
t
OLZ
t
CKLZ
t
WS
t
WH
t
WS
t
WH
t
WS
t
WH
t
CSZ
SI/O
IN
SI/O
OUT
3016 drw 17
(2)
t
CKHZ
16
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
Sequential Port: Write, Pointer Load, Burst Read
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
Read STRT/EOB Flag Timing - Sequential Port(1)
t
CYC
D1D0
t
CH
t
CL
t
DS
t
DH
t
OHZ
t
EH
t
ES
t
EH
t
ES
(1)
(3)
A0Dx HIGH IMPEDANCE
t
WS
t
WH
t
WH
t
OLZ
t
CKLZ
t
WS
t
WH
t
WH
(2)
D2
t
DS
t
DH
(2)
SLD
CNTEN
SR/W
SCE
SOE
SCLK
SI/O
IN
SI/O
OUT
3016 drw 18
t
WS
t
WS
t
CD
t
SOE
CNTEN
(2)
t
OLZ
t
OHZ
D1 D2
SSTRT1/2
SR/W
SCE
SOE
SCLK
t
CYC
t
CH
t
CL
t
EH
t
ES
t
EH
t
ES
(4)
(1)
Dx HIGH IMPEDANCE
t
WS
t
WH
t
WS
t
WH
t
CD
t
SOE
t
WS
t
WH
t
WS
t
WH
(2)
D3
t
DS
t
DH
D0
t
CKLZ
(3)
(5)
EOB
1/2
t
EB
SI/O
IN
SI/O
OUT
3016 drw19
NOTES: (Also used in the Figure "Read STRT/EOB Flag Timing")
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that cycle. If SCE
= VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus contention and permit a write
on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.42
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
17
Waveform of Write Cy cles: Sequential Port
NOTES :
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incrementing on cycle immediately following SLD even if CNTEN is LOW.
4. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
5. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
Waveform of Burst Write Cycles: Sequential Port
SLD
CNTEN
t
CYC
SR/W
SCE
SOE
SCLK t
CH
t
CL
t
DS
t
DH
t
OHZ
t
EH
t
ES
(3)
(1)
t
EH
t
ES
Dx A0
D0
HIGH IMPEDANCE
t
WS
t
WH
t
WS
t
WH
t
CD
t
CKLZ
t
WS
t
WH
t
WS
t
WH
t
CKHZ
D0
t
DS
t
DH
(4)
(5)
t
EH
t
ES
D1
t
DS
t
DH
HIGH IMPEDANCE
SI/O
IN
SI/O
OUT
3016 drw 20
(4)
SLD
CNTEN
D
2
SR/W
SCLK
t
CYC
t
CH
t
CL
t
DS
t
DH
t
EH
t
ES
t
EH
t
ES
(1)
(3)
A0Dx
HIGH IMPEDANCE
t
WS
t
WH
t
WS
t
WH
t
CKLZ
t
WS
t
WH
t
WS
t
WH
D1D0 D2
t
DS
t
DH
t
CD
SCE
SOE
(2)
SI/O
IN
SI/O
OUT
3016 drw 21
(5)
(5)
18
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
Waveform of Write Cycles: Sequential Port (STRT/EOB Flag Timing)
NOTES: (Also used in the Figure "Read STRT/EOB Flag Timing")
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that cycle. If
SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus contention and
permit a write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
SSTRT
1/2
CNTEN
D3
SR/W
SCE
SOE
SCLK
t
CH
t
CL
t
EH
t
ES
t
EH
t
ES
(4)
(1)
(3)
Dx
HIGH IMPEDANCE
t
WS
t
WH
t
WS
t
WH
t
CKLZ
t
WS
t
WH
t
WS
t
WH
(2)
D2
D1 D3
t
DS
t
DH
t
CD
(6)
HIGH IMPEDANCE
D0
EOB
1/2
t
EB
SI/O
IN
SI/O
OUT
3016 drw 22
(5)
6.42
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
19
Sequential Counter Enable Cycle After Reset, Write Cycle(1,4,6)
Sequential Counter Enable Cycle After Reset, Read Cycle(1,4)
NOTES:
1. 'D0' represents data input for Address=0, 'D1' represents data input for Address=1, etc.
1. If CNTEN=VIL then 'D1' would be written into 'A1' at this point.
3. Data output is available at a t CD after the SR/W=VIH is clocked. The RST sets SR/W=LOW internally and therefore disables the output until the next clock.
4. SCE=VIL throughout all cycles.
5. If CNTEN=VIL then 'D1' would be clocked out (read) at this point.
6. SR/W=VIL.
RST
CNTEN
SCLK
(2)
D0
SI/O
IN
3016 drw 23
D1 D2 D3 D4
RST
CNTEN
SCLK
(5)
SI/O
OUT
3016 drw 24
D0 D2
D1 D3
SR/W
(3)
(5)
20
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
Random Access Port - Reset Timing
Random Access Port Restart Timing of Sequential Port(1)
NOTES:
1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5).
2. "0" is written to Bit 4 from the random port at address [A2 - A0] = 100, when CMD = VIL and CE = VIH. The device is in the Buffer Command Mode
(see Case 5).
3. CLR is an internal signal only and is shown for reference only.
4. Sequential port must also prohibit SR/W or SCE from being LOW for tWERS and tRSRC periods, or SCLK must not toggle from LOW-to-HIGH until after tRSRC.
t
RSPW
RST
R
/W,SR/WCMD
or (UB +LB)
t
RSRC
t
WERS
EOB
(1 or 2)
Flag Valid
t
RSFV
3016 drw 25
(4)
t
FS
SCLK
R/W
(Internal Signal)
2-5ns
6-7ns
0.5 x t
CYC
3016 drw 26
CLR
Block
(3)
(2)
6.42
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
21
Ordering Information
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
3016 drw 27
X
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
Blank
I
(1)
B
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
Military (–55°C to +125°C)
Compliant to MIL-PRF-38535 QML
G
PF 84-pin PGA (G84-3)
80-pin TQFP (PN80-1)
20
25
35
45
S
LStandard Power
Low Power
70825
Device
Type
128K (8K x 16) Sequential Access Random
Access Memory
70825
Speed in nanoseconds
Commercial Only
Commercial Only
Commercial & Military
Commercial & Military
,
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
1/27/99: Initiated datasheet document history
Converted to new format
6/4/99: Changed drawing format
11/10/99: Replaced IDT logo
4/18/00: Page 3 Changed "Clock" to "Inputs/Outputs" in Random pin description table
Added "Outputs" in Sequential pin description table
Changed ±200mV to 0mV in notes
5/23/00: Page 4 Increased storage temperature parameter
Clarified TA parameter
Page 5 DC Electrical parameters–changed wording from "open" to "disabled"
01/29/09: Page 21 Removed "IDT" from orderable part number