1 ppm, 20-Bit,
±1 LSB INL, Voltage Output DAC
Enhanced Product
AD5791-EP
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
1 ppm resolution
1 ppm INL
7.5 nV/√Hz noise spectral density
0.19 LSB long-term linearity stability
<0.05 ppm/°C temperature drift
1 µs settling time
1.4 nV-sec glitch impulse
20-lead TSSOP package
Wide power supply range up to ±16.5 V
35 MHz Schmitt triggered digital interface
1.8 V compatible digital interface
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC
standard)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Product change notification
Qualification data available on request
APPLICATIONS
Medical instrumentation
Test and measurement
Industrial control
High end scientific and aerospace instrumentation
FUNCTIONAL BLOCK DIAGRAM
A1 6.8kΩ
6kΩ
6.8kΩ
R1 R
FB
20-BIT
DAC
DAC
REG 2020
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
POWER-ON RESET
AND CLEAR LO GI C
AD5791-EP
IOV
CC
SDIN
V
CC
V
DD
V
REFPF
V
REFPS
V
REFNF
AGNDV
SS
DGND V
REFNS
SCLK
SYNC
SDO
LDAC
CLR
RESET
R
FB
INV
V
OUT
10455-001
Figure 1.
COMPANION PRODUCTS
Ultra precision op amps: AD8675, AD8676
High voltage op amp: ADA4898-1
Additional companion products on the AD5791 product page
Table 1. Related Device
Part No. Description
AD5781 18-bit, 0.5 LSB INL, voltage output DAC
GENERAL DESCRIPTION
The AD5791-EP1 is a single 20-bit, unbuffered voltage-output
digital-to-analog converter (DAC) that operates from a bipolar
supply of up to 33 V. The AD5791 accepts a positive reference
input in the range 5 V to VDD − 2.5 V and a negative reference
input in the range VSS + 2.5 V to 0 V. T h e AD5791-EP offers a
relative accuracy specification of ±1 LSB max, and operation is
guaranteed monotonic with a ±1 LSB differential nonlinearity
(DNL) maximum specification.
The part uses a versatile 3-wire serial interface that operates at
clock rates up to 35 MHz and that is compatible with standard
serial peripheral interface (SPI), QSPI™, MICROWIRE™, and
DSP interface standards. The part incorporates a power-on
reset circuit that ensures the DAC output powers up to 0 V in a
known output impedance state and remains in this state until a
valid write to the device takes place. The part provides an
output clamp feature that places the output in a defined load
state.
The AD5791-EP is available in a compact, 20-lead TSSOP
package and operates at the extended automotive temperature
range of −55°C to +125°C. Additional application and technical
information can be found in the AD5791 data sheet.
PRODUCT HIGHLIGHTS
1. 1 ppm Accuracy.
2. Wide Power Supply Range up to ±16.5 V.
3. Operating Temperature Range: −55°C to +125°C.
4. Low 7.5 nV/√Hz Noise Spectral Density.
5. Low 0.05 ppm/°C Temperature Drift.
1 Protected by U.S. Patents No. 7,884,747 and 8,089,380. Other patents pending.
AD5791-EP Enhanced Product
Rev. B | Page 2 of 17
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Companion Products ....................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications .....................................................................................3
Timing Characteristics .................................................................5
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions ..............................8
Typical Performance Characteristics ..............................................9
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
3/2018—Rev. A to Rev. B
Changes to Features Section and Enhanced Product Features
Section ................................................................................................ 1
Changes to Ordering Guide .......................................................... 17
7/2013—Re v. 0 to Rev. A
Changes to t1 Test Conditions/Comments and Endnote 2 ......... 5
Deleted Figure 4 ................................................................................ 7
2/2012—Revision 0: Initial Version
Enhanced Product AD5791-EP
Rev. B | Page 3 of 17
SPECIFICATIONS
VDD = 12.5 V to 16.5 V, VSS = −16.5 V to −12.5 V, VREFP = 10 V, VREFN = −10 V, VCC = 2.7 V to +5.5 V, IOVCC = 1.71 V to 5.5 V,
RL = unloaded, CL = unloaded, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1 Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE2
Resolution 20 Bits
Integral Nonlinearity Error (Relative Accuracy) −1 ±0.25 +1 LSB VREFP = +10 V, VREFN = −10 V,
TA = 0°C to 105°C
−1.5 ±0.25 +1.5 LSB VREFP = +10 V, VREFN = −10 V
−1.5 ±0.5 +1.5 LSB VREFP = 10 V, VREFN = 0 V3
−3 ±1 +3 LSB VREFP = 5 V, VREFN = 0 V3
Differential Nonlinearity Error −1 ±0.5 +1 LSB VREFP = +10 V, VREFN = −10 V
−1.5 ±0.75 +1.5 LSB VREFP = 10 V, VREFN = 0 V
−2.5 ±1 +2.5 LSB VREFP = 5 V, VREFN = 0 V
Linearity Error Long-Term Stability4 0.16 LSB After 500 hours at TA = 125°C
0.19 LSB After 1000 hours at TA = 125°C
0.11 LSB After 1000 hours at TA = 100°C
Full-Scale Error
−7
±0.1
LSB
VREFP = +10 V, VREFN = −10 V
3
−11 ±0.25 +11 LSB VREFP = 10 V, VREFN = 0 V3
−21 ±0.8 +21 LSB VREFP = 5 V, VREFN = 0 V3
−4 ±0.1 +4 LSB VREFP = +10 V, VREFN = −10 V3, TA = 0°C to 105°C
−4 ±0.25 +4 LSB VREFP = 10 V, VREFN = 0 V3, TA = 0°C to 105°C
−6 ±0.8 +6 LSB VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
Full-Scale Error Temperature Coefficient ±0.02 ppm FSR/°C
Zero-Scale Error −7 ±0.1 +7 LSB VREFP = +10 V, VREFN = −10 V3
−10 ±0.15 +10 LSB VREFP = 10 V, VREFN = 0 V3
−21 ±0.75 +21 LSB VREFP = 5 V, VREFN = 0 V3
−4 ±0.1 +4 LSB VREFP = +10 V, VREFN = −10 V3, TA = 0°C to 105°C
−4 ±0.15 +4 LSB VREFP = 10 V, VREFN = 0 V3, TA = 0°C to 105°C
−6 ±0.75 +6 LSB VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
Zero-Scale Error Temperature Coefficient3 ±0.04 ppm FSR/°C
Gain Error −6 ±0.3 +6 ppm FSR VREFP = +10 V, VREFN = −10 V3
−10 ±0.4 +10 ppm FSR VREFP = 10 V, VREFN = 0 V3
−20 ±0.4 +20 ppm FSR VREFP = 5 V, VREFN = 0 V3
−6 ±0.3 +6 ppm FSR VREFP = +10 V, VREFN = −10 V3, TA = 0°C to 105°C
−6 ±0.4 +6 ppm FSR VREFP = 10 V, VREFN = 0 V3, TA = 0°C to 105°C
−7 ±0.4 +7 ppm FSR VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
Gain Error Temperature Coefficient
3
±0.04
ppm FSR/°C
R1, RFB Matching 0.01 %
OUTPUT CHARACTERISTICS3
Output Voltage Range VREFN VREFP V
Output Slew Rate 50 V/µs
Output Voltage Settling Time 1 µs 10 V step to 0.02%, using the AD845 buffer
in unity-gain mode
1 µs 500 code step to ±1 LSB5
Output Noise Spectral Density 7.5 nV/√Hz at 1 kHz, DAC code = midscale
7.5 nV/√Hz at 10 kHz, DAC code = midscale
7.5 nV/√Hz At 100 kHz, DAC code = midscale
Output Voltage Noise 1.1 µV p-p DAC code = midscale, 0.1 Hz to 10 Hz
bandwidth6
AD5791-EP Enhanced Product
Rev. B | Page 4 of 17
Parameter1 Min Typ Max Unit Test Conditions/Comments
Midscale Glitch Impulse7 3.1 nV-sec VREFP = +10 V, VREFN = −10 V
1.7 nV-sec VREFP = 10 V, VREFN = 0 V
1.4 nV-sec VREFP = 5 V, VREFN = 0 V
MSB Segment Glitch Impulse7 9.1 nV-sec VREFP = +10 V, VREFN = −10 V, see Figure 42
3.6 nV-sec VREFP = 10 V, VREFN = 0 V, see Figure 43
1.9 nV-sec VREFP = 5 V, VREFN = 0 V, see Figure 44
Output Enabled Glitch Impulse 45 nV-sec On removal of output ground clamp
Digital Feedthrough 0.4 nV-sec
DC Output Impedance (Normal Mode) 3.4 kΩ
DC Output Impedance (Output Clamped
to Ground)
6 kΩ
Spurious Free Dynamic Range 100 dB 1 kHz tone, 10 kHz sample rate
Total Harmonic Distortion 97 dB 1 kHz tone, 10 kHz sample rate
REFERENCE INPUTS3
VREFP Input Range 5 VDD − 2.5 V V
VREFN Input Range VSS + 2.5 V 0
DC Input Impedance 5 6.6 kΩ VREFP, VREFN, code dependent,
typical at midscale code
Input Capacitance 15 pF VREFP, VREFN
LOGIC INPUTS3
Input Current8 −1 +1 µA
Input Low Voltage, VIL 0.3 × IOVCC V IOVCC = 1.71 V to 5.5 V
Input High Voltage, V
IH
0.7 × IOV
CC
V
IOV
CC
= 1.71 V to 5.5 V
Pin Capacitance 5 pF
LOGIC OUTPUT (SDO)3
Output Low Voltage, VOL 0.4 V IOVCC = 1.71 V to 5.5 V, sinking 1 mA
Output High Voltage, VOH IOVCC − 0.5 V V IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
High Impedance Leakage Current ±1 µA
High Impedance Output Capacitance 3 pF
POWER REQUIREMENTS All digital inputs at DGND or IOVCC
VDD 7.5 VSS + 33 V
VSS VDD − 33 −2.5 V
VCC 2.7 5.5 V
IOVCC 1.71 5.5 V IOVCC ≤ VCC
IDD 4.2 5.2 mA
ISS 4 4.9 mA
ICC 600 900 µA
IOICC 52 140 µA SDO disabled
DC Power Supply Rejection Ratio3, 9 ±0.6 µV/V VDD ± 10%, VSS = 15 V
±0.6 µV/V VSS ± 10%, VDD = 15 V
AC Power Supply Rejection Ratio3 95 dB VDD ± 200 mV, 50 Hz/60 Hz, VSS = −15 V
95 dB ∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V
1 Temperature range: −55°C to +125°C, typical at +25°C and VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.
2 Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer.
3 Guaranteed by design and characterization; not production tested.
4 Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified.
5 AD5791-EP configured in ×2 gain mode, 25 pF compensation capacitor on AD797.
6 Includes noise contribution from AD8676BRZ voltage reference buffers.
7 The AD5791-EP is configured in bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer,
lead capacitance, and so forth).
8 Current flowing in an individual logic pin.
9 Includes PSRR of AD8676BRZ voltage reference buffers.
Enhanced Product AD5791-EP
Rev. B | Page 5 of 17
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit1
Unit Test Conditions/Comments
IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.5 V
t12 40 28 ns min SCLK cycle time
92 60 ns min SCLK cycle time (readback mode)
t2 15 10 ns min SCLK high time
t
3
9
5
ns min
SCLK low time
t4 5 5 ns min SYNC to SCLK falling edge setup time
t5 2 2 ns min SCLK falling edge to SYNC rising edge hold time
t6 48 40 ns min Minimum SYNC high time
t7 8 6 ns min SYNC rising edge to next SCLK falling edge ignore
t8 9 7 ns min Data setup time
t
9
12
7
ns min
Data hold time
t10 13 10 ns min LDAC falling edge to SYNC falling edge
t11 20 16 ns min SYNC rising edge to LDAC falling edge
t12 14 11 ns min LDAC pulse width low
t13 130 130 ns typ LDAC falling edge to output response time
t14 130 130 ns typ SYNC rising edge to output response time (LDAC tied low)
t15 50 50 ns min CLR pulse width low
t16 140 140 ns typ CLR pulse activation time
t17 0 0 ns min SYNC falling edge to first SCLK rising edge
t18 65 60 ns max SYNC rising edge to SDO tristate (CL = 50 pF)
t19 62 45 ns max SCLK rising edge to SDO valid (CL = 50 pF)
t
20
0
0
ns min
SYNC rising edge to SCLK rising edge ignore
t21 35 35 ns typ RESET pulse width low
t22 150 150 ns typ RESET pulse activation time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback mode.
AD5791-EP Enhanced Product
Rev. B | Page 6 of 17
t
7
2421
DB23 DB0
t
10
t
8
t
4
t
6
t
5
t
3
t
1
t
2
t
9
t
11
t
12
t
13
t
14
t
15
t
16
t
21
t
22
V
OUT
V
OUT
V
OUT
V
OUT
RESET
CLR
LDAC
SDIN
SYNC
SCLK
10455-002
Figure 2. Write Mode Timing Diagram
DB23 DB0
NOP CONDITION
REGISTER CONTENTS CLOCKED OUT
t1
t17
t2
t5t17 t5
t19
t18
t20
t3
t4
t8
t9
t6
t7
24221 24 1
DB23 DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
SDIN
SYNC
SCLK
10455-003
Figure 3. Readback Mode Timing Diagram
Enhanced Product AD5791-EP
Rev. B | Page 7 of 17
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 4.
Parameter Rating
V
DD
to AGND
−0.3 V to +34 V
VSS to AGND −34 V to +0.3 V
VDD to VSS −0.3 V to +34 V
VCC to DGND −0.3 V to +7 V
IOVCC to DGND −0.3 V to VCC + 0.3 V or +7 V
(whichever is less)
Digital Inputs to DGND −0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
VOUT to AGND −0.3 V to VDD + 0.3 V
VREFPF to AGND −0.3 V to VDD + 0.3 V
VREFPS to AGND −0.3 V to VDD + 0.3 V
V
REFNF
to AGND
V
SS
− 0.3 V to + 0.3 V
VREFNS to AGND VSS − 0.3 V to + 0.3 V
DGND to AGND −0.3 V to +0.3 V
Operating Temperature Range, TA
Industrial −55°C to + 125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature,
TJ max
150°C
Power Dissipation (TJ max − TA)/θJA
TSSOP Package
θJA Thermal Impedance 143°C/W
θJC Thermal Impedance 45°C/W
Lead Temperature JEDEC industry standard
Soldering J-STD-020
ESD (Human Body Model) 1.5 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
This device is a high performance integrated circuit with an
ESD rating of 1.5 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
AD5791-EP Enhanced Product
Rev. B | Page 8 of 17
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
V
OUT
V
REFPS
V
REFPF
CLR
RESET
V
DD
INV
IOV
CC
V
CC
LDAC
20
19
18
17
16
15
14
13
12
11
AGND
V
SS
V
REFNS
SYNC
DGND
V
REFNF
SDO
SDIN
SCLK
R
FB
AD5791-EP
TOP VIEW
(Not to Scale)
10455-005
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 INV Connection to Inverting Input of External Amplifier.
2 VOUT Analog Output Voltage.
3 VREFPS Positive Reference Sense Voltage Input. A voltage range of 5 V to VDD − 2.5 V can be connected. A unity gain
amplifier must be connected at this pin in conjunction with the VREFPF pin.
4 VREFPF Positive Reference Force Voltage Input. A voltage range of 5 V to VDD − 2.5 V can be connected. A unity gain
amplifier must be connected at this pin in conjunction with the VREFPS pin.
5 VDD Positive Analog Supply Connection. A voltage range of 7.5 V to 16.5 V can be connected; VDD should be decoupled
to AGND.
6 RESET Active Low Reset Logic Input Pin. Asserting this pin returns the AD5791-EP to its power-on status.
7 CLR Active Low Clear Logic Input Pin. Asserting this pin sets the DAC register to a user defined value and updates the
DAC output. The output value depends on the DAC register coding that is being used, either binary or twos
complement.
8 LDAC Active Low Load DAC Logic Input Pin. This is used to update the DAC register and, consequently, the analog
output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during
the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The
LDAC pin should not be left unconnected.
9 VCC Digital Supply Connection. A voltage range of 2.7 V to 5.5 V can be connected. VCC should be decoupled to DGND.
10 IOVCC Digital Interface Supply Pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage in
the range of 1.71 V to 5.5 V can be connected. IOVCC should not be allowed to exceed VCC.
11 SDO Serial Data Output Pin. Data is clocked out on the rising edge of the serial clock input.
12 SDIN Serial Data Input Pin. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input.
13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at clock rates of up to 35 MHz.
14 SYNC Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data.
When SYNC is low, it enables the input shift register, and data is then transferred in on the falling edges of the
following clocks. The input shift register is updated on the rising edge of SYNC.
15 DGND Ground Reference Pin for Digital Circuitry.
16 VREFNF Negative Reference Force Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain
amplifier must be connected at this pin in conjunction with the VREFNS pin.
17 VREFNS Negative Reference Sense Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain
amplifier must be connected at this pin in conjunction with the VREFNF pin.
18 VSS Negative Analog Supply Connection. A voltage range of −16.5 V to −2.5 V can be connected. VSS should be
decoupled to AGND.
19 AGND Ground Reference Pin for Analog Circuitry.
20 RFB Feedback Connection for External Amplifier.
Enhanced Product AD5791-EP
Rev. B | Page 9 of 17
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.00200000 400000 600000 800000 1000000
DAC CODE
INL ERRO R ( LSB)
TA = +125°C
TA = +25°C
TA = –40° C
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
VREFP = + 10V
VREFN = –10V
VDD = + 15V
VSS = –15V
10455-006
Figure 5. Integral Nonlinearity Error vs. DAC Code, ±10 V Span
1.5
1.0
0.5
0
–0.5
–1.0
–1.50200000 400000 600000 800000 1000000
DAC CODE
INL ERRO R ( LSB)
TA = +125°C
TA = +25°C
TA = –40° C
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
VREFP = + 10V
VREFN = 0V
VDD = + 15V
VSS = –15V
10455-007
Figure 6. Integral Nonlinearity Error vs. DAC Code, +10 V Span
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.50200000 400000 600000 800000 1000000
DAC CODE
INL ERRO R ( LSB)
T
A
= +125°C
T
A
= +25°C
T
A
= –40° C
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
V
REFP
= +5V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
10455-008
Figure 7. Integral Nonlinearity Error vs. DAC Code, +5 V Span
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.80200000 400000 600000 800000 1000000
DAC CODE
INL ERRO R ( LSB)
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
TA = –40° C
TA = +125°C
TA = +25°C
VREFP = + 10V
VREFN = 0V
VDD = + 15V
VSS = –15V
10455-009
Figure 8. Integral Nonlinearity Error vs. DAC Code, ±10 V Span, ×2 Gain Mode
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.00200000 400000 600000 800000 1000000
DAC CODE
DNL ERROR (LSB)
T
A
= +125°C
T
A
= +25°C
T
A
= –40° C
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R V
REFP
= +10V
V
REFN
= –10V
V
DD
= +15V
V
SS
= –15V
10455-010
Figure 9. Differential Nonlinearity Error vs. DAC Code, ±10 V Span
1.5
1.0
0.5
0
–0.5
–1.0
–1.50200000 400000 600000 800000 1000000
DAC CODE
DNL ERROR (LSB)
T
A
= +125°C
T
A
= +25°C
T
A
= –40° C
V
REFP
= +10V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
10455-011
Figure 10. Differential Nonlinearity Error vs. DAC Code, +10 V Span
AD5791-EP Enhanced Product
Rev. B | Page 10 of 17
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.00200000 400000 600000 800000 1000000
DAC CODE
DNL ERROR (LSB)
V
REFP
= +5V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
T
A
= +125°C
T
A
= +25°C
T
A
= –40° C
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
10455-012
Figure 11. Differential Nonlinearity Error vs. DAC Code, +5 V Span
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.00200000 400000 600000 800000 1000000
DAC CODE
DNL ERROR (LSB)
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
V
REFP
= +10V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
T
A
= +25°C
T
A
= –40° C
T
A
= +125°C
10455-013
Figure 12. Differential Nonlinearity Error vs. DAC Code, ±10 V Span,
×2 Gain Mode
1.0
1.5
2.0
0.5
0
–0.5
–1.0
–1.5
–55 –35 –15 525 45 65 85 105 125
TEMPERATURE (°C)
INL ERROR (LS B)
±10V SPAN MAX I N L
+5V S PAN MAX I N L
+10V SPAN MIN INL
+10V SPAN MAX I N L
±10V SPAN MIN INL
+5V S PAN MIN INL
AD8676 REF E RE NCE BUFF E RS
AD8675 OUTPUT BUF FE R
VDD = + 15V
VSS = –15V
10455-014
Figure 13. Integral Nonlinearity Error vs. Temperature
1.0
0.5
0
–0.5
–1.0
–1.5
–55 –35 –15 525 45 65 85 105 125
TEMPERATURE (°C)
DNL ERROR (LSB)
±10V SPAN MAX DN L
+5V S PAN MAX DNL
+10V SPAN MIN DN L
+10V SPAN MAX DN L
±10V SPAN MIN DN L
+5V S PAN MIN DNL
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
V
DD
= +15V
V
SS
= –15V
10455-015
Figure 14. Differential Nonlinearity Error vs. Temperature
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.2
–0.1
–0.3
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
VDD/|VSS| (V)
INL ERRO R ( LSB)
TA = 25° C
VREFP = + 10V
VREFN = –10V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
INL MAX
INL MIN
10455-016
Figure 15. Integral Nonlinearity Error vs. Supply Voltage, ±10 V Span
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
V
DD
(V)
INL ERRO R ( LSB)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
V
SS
(V)
T
A
= 25° C
V
REFP
= +5V
V
REFN
= 0V
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
INL MAX
INL MIN
10455-017
Figure 16. Integral Nonlinearity Error vs. Supply Voltage, +5 V Span
Enhanced Product AD5791-EP
Rev. B | Page 11 of 17
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
VDD/|VSS| (V)
DNL ERROR (LSB)
TA = 25° C
VREFP = + 10V
VREFN = –10V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
DNL M AX
DNL M IN
10455-018
Figure 17. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span
0.4
0.2
0
–0.6
–0.4
–0.2
–0.8
–1.0
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
VDD (V)
DNL ERROR (LSB)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
VSS (V)
TA = 25° C
VREFP = +5V
VREFN = 0V
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
DNL M AX
DNL M IN
10455-019
Figure 18. Differential Nonlinearity Error vs. Supply Voltage, +5 V Span
0.6
0.5
0.4
0.3
0.2
0.1
0
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
V
DD
/|V
SS
| (V)
ZE RO -SCAL E E RROR (LSB)
T
A
= 25° C
V
REFP
= +10V
V
REFN
= –10V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
10455-020
Figure 19. Zero-Scale Error vs. Supply Voltage, ±10 V Span
0.6
0.5
0.4
0.1
0.2
0.3
0
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
VDD (V)
ZE RO -SCAL E E RROR (LSB)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
VSS (V)
TA = 25° C
VREFP = +5V
VREFN = 0V
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
10455-021
Figure 20. Zero-Scale Error vs. Supply Voltage, +5 V Span
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
V
DD
/|V
SS
| (V)
MI DS CALE E RROR (LSB)
T
A
= 25° C
V
REFP
= +10V
V
REFN
= –10V
AD8676 REF E RE NCE BUFF E RS
AD8675 OUTPUT BUF FER
10455-022
Figure 21. Midscale Error vs. Supply Voltage, ±10 V Span
0.2
0.1
0
–0.5
–0.6
–0.3
–0.4
–0.1
–0.2
–0.7
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
V
DD
(V)
MI DS CALE ERROR (LSB)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
V
SS
(V)
T
A
= 25° C
V
REFP
= +5V
V
REFN
= 0V
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
10455-023
Figure 22. Midscale Error vs. Supply Voltage, +5 V Span
AD5791-EP Enhanced Product
Rev. B | Page 12 of 17
–0.015
–0.035
–0.055
–0.075
–0.095
–0.115
–0.135
–0.155
–0.175
–0.195
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
V
DD
/|V
SS
| (V)
FULL - S CALE E RROR (LSB)
T
A
= 25° C
V
REFP
= +10V
V
REFN
= –10V
AD8676 REF E RE NCE BUFF E RS
AD8675 OUTPUT BUF FER
10455-024
Figure 23. Full-Scale Error vs. Supply Voltage, ±10 V Span
0.25
0.20
0.15
0.10
0.05
0
–0.05
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
V
DD
(V)
FULL - S CALE ERROR (LSB)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
V
SS
(V)
T
A
= 25° C
V
REFP
= +5V
V
REFN
= 0V
AD8676 REF ERE NCE BUFF E RS
AD8675 OUT P UT BUF FER
10455-025
Figure 24. Full-Scale Error vs. Supply Voltage, +5 V Span
–0.30
–0.35
–0.40
–0.45
–0.50
–0.55
–0.60
–0.65
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
V
DD
/|V
SS
| (V)
GAI N E RROR (pp m FSR)
T
A
= 25° C
V
REFP
= +10V
V
REFN
= –10V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
10455-026
Figure 25. Gain Error vs. Supply Voltage, ±10 V Span
0.10
0.05
0
–0.35
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
–0.40
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
V
DD
(V)
GAI N E RROR (pp m FSR)
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
V
SS
(V)
T
A
= 25° C
V
REFP
= +5V
V
REFN
= 0V
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
10455-027
Figure 26. Gain Error vs. Supply Voltage, +5 V Span
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
VREFP/|VREFN| (V)
INL ERRO R ( LSB)
TA = 25° C
VDD = + 15V
VSS = –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
INL MAX
INL MIN
10455-028
Figure 27. Integral Nonlinearity Error vs. Reference Voltage
0.4
0.2
0.3
0.1
0
–0.1
–0.2
–0.3
–0.5
–0.4
–0.6
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
VREFP/|VREFN| (V)
DNL ERROR (LSB)
DNL M AX
DNL M IN
TA = 25° C
VDD = + 15V
VSS = –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
10455-029
Figure 28. Differential Nonlinearity Error vs. Reference Voltage
Enhanced Product AD5791-EP
Rev. B | Page 13 of 17
0.60
0.55
0.50
0.45
0.40
0.35
0.30
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
VREFP/|VREFN| (V)
ZE RO -SCAL E E RROR (LSB)
TA = 25° C
VDD = + 15V
VSS = –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
10455-030
Figure 29. Zero-Scale Error vs. Reference Voltage
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
V
REFP
/|V
REFN
| (V)
MI DSCALE E RROR (LSB)
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
10455-031
Figure 30. Midscale Error vs. Reference Voltage
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
V
REFP
/|V
REFN
| (V)
FULL - S CALE ERROR (LSB)
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
10455-032
Figure 31. Full-Scale Error vs. Reference Voltage
–0.30
–0.35
–0.40
–0.45
–0.50
–0.55
–0.60
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
V
REFP
/|V
REFN
| (V)
GAI N E RROR (pp m FSR)
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
AD8676 REFE RE NCE BUFF E RS
AD8675 OUT P UT BUF FER
10455-033
Figure 32. Gain Error vs. Reference Voltage
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–55 –35 –15 525 45 65 85 105 125
TEMPERATURE (°C)
FULL - S CALE ERROR (LSBs)
±10V SPAN
+10V SPAN
+5V S PAN
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
V
DD
= +15V
V
SS
= –15V
10455-034
Figure 33. Full-Scale Error vs. Temperature
2.0
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
–55 –35 –15 525 45 65 85 105 125
TEMPERATURE (°C)
MI DS CALE ERROR (LSBs)
±10V SP AN
+10V SP AN
+5V SPAN
AD8676 REF ERE NCE BUFF E RS
AD8675 OUTPUT BUFF E R
V
DD
= +15V
V
SS
= –15V
10455-035
Figure 34. Midscale Error vs. Temperature
AD5791-EP Enhanced Product
Rev. B | Page 14 of 17
5
4
3
2
1
0
–1
–2
–3
–4
–5
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
ZERO-SCALE ERROR (LSBs)
±10V SPAN
+10V SPAN
+5V SPAN
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
V
DD
= +15V
V
SS
= –15V
10455-036
Figure 35. Zero-Scale Error vs. Temperature
4
3
2
1
0
–1
–2
–3
–4
–5
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
GAIN ERROR (ppm FSR)
±10V SPAN
+10V SPAN
+5V SPAN
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
VDD = +15V
VSS = –15V
10455-037
Figure 36. Gain Error vs. Temperature
900
800
700
600
500
400
300
200
100
001
T
A
= 25°C
23456
LOGIC INPUT VOLTAGE (V)
IOI
CC
(µA)
IOV
CC
= 5V, LOGIC VOLTAGE
INCREASING
IOV
CC
= 5V, LOGIC VOLTAGE
DECREASING
IOV
CC
= 3V, LOGIC VOLTAGE
INCREASING
IOV
CC
= 3V, LOGIC VOLTAGE
DECREASING
10455-038
Figure 37. IOICC vs. Logic Input Voltage
5
4
3
2
1
0
–1
–2
–3
–4
–5
–20 –15 –10 –5 0 5 10 15 20
V
DD
/V
SS
(V)
I
DD
, I
SS
(mA)
T
A
= 25°C
I
DD
I
SS
10455-039
Figure 38. Power Supply Currents vs. Power Supply Voltages
CH3 5V CH4 5V 200ns
3
4
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
AD8676 REFERENCE BUFFERS
OUTPUT UNBUFFERED
LOAD = 10MΩ||20pF
10455-040
Figure 39. Rising Full-Scale Voltage Step
CH3 5V CH4 5V 200ns
3
4
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
AD8676 REFERENCE BUFFERS
OUTPUT UNBUFFERED
LOAD = 10MΩ||20pF
10455-041
Figure 40. Falling Full-Scale Voltage Step
Enhanced Product AD5791-EP
Rev. B | Page 15 of 17
10.8
10.6
10.4
10.2
10.0
9.8
9.6
9.4 0 1 5432
VOUT (mV)
TIME (µs)
±10V VREF
OUTPUT GAIN OF 1
BIAS COMP E NSATION MODE
20pF COMPENS ATION CAPACITOR
RC LO W-PASS FILTER
10455-042
Figure 41. 500 Code Step Settling Time
10
0
1
2
3
4
5
6
7
8
9
16384
65536
OUTPUT GL IT CH ( nV–sec)
CODE
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
851968
901120
950272
999424
POSITIVE CODE
CHANGE
NEGATI V E CODE
CHANGE
5V V
OUTPUT GAIN OF 1
BIAS COMP E NSATION MODE
20pF COMPENS ATION CAPACITOR
RC LO W-PASS FILTER
REF
10455-043
Figure 42. 6 MSB Segment Glitch Energy for ±10 V VREF
4.0
0
2.0
1.5
1.0
0.5
2.5
3.0
3.5
16384
65536
OUTPUT GL IT CH ( nV–sec)
CODE
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
851968
901120
950272
999424
POSITIVE CODE
CHANGE
NEGATI V E CODE
CHANGE
10V VREF
OUTPUT GAIN OF 1
BIAS COMP E NSATION MODE
20pF COMPENS ATION CAPACITOR
RC LO W-PASS FILTER
10455-044
Figure 43. 6 MSB Segment Glitch Energy for +10 V VREF
3.0
–0.2
2.2
1.0
1.4
1.8
0.6
0.2
2.6
16384
65536
OUTPUT GL IT CH ( nV–sec)
CODE
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
851968
901120
950272
999424
NEGATI V E CODE
CHANGE
5V VREF
OUTPUT GAIN OF 1
BIAS COMP E NSATION MODE
20pF COMPENS ATION CAPACITOR
RC LO W-PASS FILTER
POSITIVE CODE
CHANGE
10455-045
Figure 44. 6 MSB Segment Glitch Energy for +5 V VREF
40
–20
–10
0
10
20
30
–1.0 –0.5 2.01.51.00.50
V
OUT
(mV)
TIME (µs)
±10V V
REF
OUTPUT GAIN OF 1
BIAS COMP E NSATION MODE
20pF CO M P E NS ATION CAPACITOR
RC LOW -PASS FILTER
C
X
= 143p F + 0pF
C
X
= 143p F + 220pF
C
X
= 143p F + 470pF
C
X
= 143p F + 1,000p F
10455-046
Figure 45. Midscale Peak-to-Peak Glitch for ±10 V
800
600
400
200
0
–200
–400
–6000 1 2 3 4 5 6 7 8 9 10
TIME (Seconds)
OUTPUT VOLTAGE (nV)
MI DS CALE CO DE LO ADE D
OUTPUT UNBUFF E RE D
AD8676 REF ERE NCE BUFF E RS
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
10455-047
Figure 46. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth
AD5791-EP Enhanced Product
Rev. B | Page 16 of 17
100
1
0.1 100k
NSD (nV/Hz)
FRE Q UE NCY ( Hz )
110 100 1k 10k
10
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
CODE = M IDSCALE
10455-048
Figure 47. Noise Spectral Density vs. Frequency
350
300
250
200
150
100
50
0
–50 0 1–1 2 3 4 5 6
TIME (µs)
OUTPUT VOLTAGE (mV)
TA = 25° C
VDD = + 15V
VSS = –15V
VREFP = + 10V
VREFN = –10V
AD8675 OUTPUT BUFF E R
10455-049
Figure 48. Glitch Impulse on Removal of Output Clamp
Enhanced Product AD5791-EP
Rev. B | Page 17 of 17
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AC
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC 1.20 MAX 0.20
0.09 0.75
0.60
0.45
8°
0°
COPLANARITY
0.10
Figure 49. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range INL Package Description Package Option
AD5791SRU-EP −55°C to +125°C ±1.5 LSB 20-Lead TSSOP RU-20
AD5791SRUZ-EP −55°C to +125°C ±1.5 LSB 20-Lead TSSOP RU-20
1 Z = RoHS Compliant Part
©2012–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10455-0-4/18(B)