PRELIMINARY Integrated Circuit Systems, Inc. ICS840014I FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS840014I is a 4 output LVCMOS/LVTTL Synthesizer optimized to generate Fibre Channel HiPerClockSTM reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. This device uses a 26.5625MHz, 18pF parallel resonant crystal to synthesize 106.25MHz. Using FemtoClock'sTM ultra-low phase noise VCO technology, the ICS840014I can achieve 1ps or lower typical random rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS840014I is packaged in a small 20-pin TSSOP package. * Four LVCMOS/LVTTL outputs, 15 typical output impedance ICS * Selectable crystal oscillator interface or LVCMOS single-ended input * Output frequency: 106.25MHz or 53.125MHz * RMS phase jitter @ 106.25MHz (637KHz - 5MHz): 0.72ps (typical) * Output supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * -40C to 85C ambient operating temperature FREQUENCY SELECT FUNCTION TABLE Input Frequency 26.5625 Inputs M Divider N Divider F_SEL1 Value Value 0 24 6 26.5625 1 24 M/N Ratio Value 4 12 2 Output Frequency Range 106.25 53.125 BLOCK DIAGRAM PIN ASSIGNMENT OE Pullup F_SEL Pullup nPLL_SEL Pulldown nXTAL_SEL Pulldown XTAL_IN 26.5625MHz OSC 0 F_SEL 0 /6 1 /12 1 XTAL_OUT TEST_CLK Pulldown 1 Phase Detector VCO Q0 Q1 0 F_SEL nc nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA nc VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT ICS840014I 20-Lead TSSOP Q2 M = /24 (fixed) Q3 6.5mm x 4.4mm x 0.92mm package body G Package Top View MR Pulldown The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 840014AGI www.icst.com/products/hiperclocks.html 1 REV. A DECEMBER 23, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS840014I FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 F_SEL Input 2, 9, 20 nc Unused 3 nXTAL_SEL Input Pulldown 4 TEST_CLK Input Pulldown 5 OE Input Pullup 6 MR Input Pulldown 7 nPLL_SEL Input Pulldown 8 VDDA Power 10 11, 12 13, 19 14, 15 17, 18 VDD XTAL_OUT, XTAL_IN GND Q3, Q2, Q1, Q0 Power 16 VDDO Pullup Input Power Output Power Frequency select pin. LVCMOS/LVTTL interface levels. No connect. Selects between the cr ystal or TEST_CLK inputs as the PLL reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL inpus. LVCMOS/LVTTL interface levels. Single-ended LVCMOS/LVTTL clock input. Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the otuputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, the PLL is bypassed and the output frequency = reference clock frequency/N output divider. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Cr ystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. Power supply ground. Single-ended clock outputs. LVCMOS/LVTTL interface levels. 15 typical output impedence. Output supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions VDD, VDDA, VDDO = 3.465V CPD Power Dissipation Capacitance Minimum Typical Maximum Units 4 pF TBD pF VDD, VDDA = 3.465V, VDDO = 2.625V TBD pF VDD, VDDA, VDDO = 2.625V TBD pF RPULLUP Input Pullup Resistor 51 K RPULLDOWN Input Pulldown Resistor 51 K ROUT Output Impedance 15 840014AGI www.icst.com/products/hiperclocks.html 2 REV. A DECEMBER 23, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS840014I FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol VDD Parameter Core Supply Voltage VDDA Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 Units V Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 3.465 VDDO Output Supply Voltage IDD Power Supply Current 75 mA IDDA IDDO Analog Supply Current Output Supply Current 6 5 mA mA V TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C Symbol VDD Parameter Core Supply Voltage Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 Units V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 75 mA IDDA IDDO Analog Supply Current Output Supply Current 6 4 mA mA TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C Symbol VDD Parameter Core Supply Voltage Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 Units V V VDDA Analog Supply Voltage 2.375 2.5 2.625 VDDO Output Supply Voltage 2.375 2.5 2.625 IDD Power Supply Current 70 mA IDDA IDDO Analog Supply Current Output Supply Current 6 4 mA mA 840014AGI www.icst.com/products/hiperclocks.html 3 V REV. A DECEMBER 23, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS840014I FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 3D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = -40C TO 85C Symbol Parameter VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions nPLL_SEL, nXTAL_SEL, F_SEL, OE, MR TEST_CLK nPLL_SEL, nXTAL_SEL, F_SEL, OE, MR TEST_CLK F_SEL, OE nPLL_SEL, MR, nXTAL_SEL, TEST_CLK F_SEL, OE nPLL_SEL, MR, nXTAL_SEL, TEST_CLK VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V Minimum Typical Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V 5 A 150 A -150 A VDD = 3.465V or 2.625V, VIN = 0V -5 A VDDO = 3.3V 5% 2.6 V VDDO = 2.5V 5% 1.8 V VDDO = 3.3V or 2.5V 5% 0.5 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Mode of Oscillation Minimum Typical Maximum Units Fundamental Frequency 26.5625 MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF NOTE: Characterized using an 18pf parallel resonant crystal. 840014AGI www.icst.com/products/hiperclocks.html 4 REV. A DECEMBER 23, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS840014I FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter fOUT Output Frequency tsk(o) Output Skew; NOTE 1, 3 tjit(O) RMS Phase Jitter (Random); NOTE 2 tL PLL Lock Time tR / tF Output Rise/Fall Time Test Conditions Minimum Typical Maximum Units 106.25 MHz 53.125 MHz TBD ps 106.25MHz (637KHz - 5MHz) 0.75 ps 53.125MHz (637KHz - 5MHz) 0.63 ps 1 20% to 80% 550 ms ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter fOUT Output Frequency tsk(o) Output Skew; NOTE 1, 3 tjit(O) RMS Phase Jitter (Random); NOTE 2 tL PLL Lock Time tR / tF Output Rise/Fall Time Test Conditions Minimum Typical Maximum Units 106.25 MHz 53.125 MHz TBD ps 106.25MHz (637KHz - 5MHz) 0.72 ps 53.125MHz (637KHz - 5MHz) 0.63 ps 1 20% to 80% 500 ms ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter fOUT Output Frequency tsk(o) Output Skew; NOTE 1, 3 tjit(O) RMS Phase Jitter (Random); NOTE 2 tL PLL Lock Time tR / tF Output Rise/Fall Time Test Conditions Minimum Typical Units 106.25 MHz 53.125 MHz TBD ps 106.25MHz (637KHz - 5MHz) 0.72 ps 53.125MHz (637KHz - 5MHz) 0.67 ps 1 20% to 80% 500 odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 840014AGI Maximum www.icst.com/products/hiperclocks.html 5 ms ps % REV. A DECEMBER 23, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS840014I FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 53.125MHZ (3.3V) 0 -10 -20 Fibre ChannelFilter Filter -40 53.125MHz -50 RMS Phase Jitter (Random) 637KHz to 5MHz = 0.63ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 -120 NOISE POWER dBc Hz -30 -130 -140 -150 -160 -170 Phase Noise Result by adding Fibre Channel Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 106.25MHZ (3.3V) 0 -10 -20 Fibre ChannelFilter -40 106.25MHz -50 RMS Phase Jitter (Random) 637KHz to 5MHz = 0.75ps (typical) -60 -70 -80 -90 -100 Raw Phase Noise Data -110 NOISE POWER dBc Hz -30 -120 -130 -140 -150 -160 -170 Phase Noise Result by adding Fibre Channel Filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 840014AGI www.icst.com/products/hiperclocks.html 6 REV. A DECEMBER 23, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS840014I FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2.05V5% 1.25V5% 1.65V5% SCOPE VDD, VDDA, VDDO Qx LVCMOS SCOPE VDD, VDDA VDDO Qx LVCMOS GND GND -1.25V5% -1.65V5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.25V5% Noise Power Phase Noise Plot SCOPE VDD, VDDA, VDDO Qx LVCMOS Phase Noise Mask GND Offset Frequency f1 RMS Jitter = Area Under the Masked Phase Noise Plot -1.25V5% RMS PHASE JITTER 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT V DDO Qx 80% 80% tR tF 2 Clock Outputs V DDO Qy f2 20% 20% 2 t sk(o) OUTPUT SKEW OUTPUT RISE/FALL TIME V DDO 2 Q0:Q3 Pulse Width t odc = PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 840014AGI www.icst.com/products/hiperclocks.html 7 REV. A DECEMBER 23, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS840014I FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840014I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA. 3.3V VDD .01F 10 VDDA .01F 10F FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS840014I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 ICS840014I Figure 2. CRYSTAL INPUt INTERFACE 840014AGI www.icst.com/products/hiperclocks.html 8 REV. A DECEMBER 23, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS840014I FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE C1=22pF and C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 1K pullup or pulldown resistors can be used for the logic control input pins. Figure 3 shows a schematic example of the ICS840014I. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant 26.5625MHz crystal is used. The Logic Control Input Examples Set Logic Input to '1' 3.3V Set Logic Input to '0' 3.3V RU1 1K R3 36 RU2 Not Install To Logic Input pins To Logic Input pins U1 LVCMOS RD2 1K RD1 Not Install 3.3V VDDA R2 10 C3 10uF 3.3V C4 0.01u Zo = 50 Ohm 1 2 3 4 5 6 7 8 9 10 F_SEL nc nXTAL_SEL TEST_CLK OE MR nPLL_SEL VDDA nc VDD nc GND Q0 Q1 VDDO Q2 Q3 GND XTAL_IN XTAL_OUT 20 19 18 17 16 15 14 13 12 11 3.3V R4 36 Zo = 50 Ohm C5 C6 0.1u LVCMOS 0.1u ICS840014 ICS80014I XTAL_OUT C2 22pF X1 XTAL_IN C1 22pF FIGURE 3. ICS840014I SCHEMATIC EXAMPLE RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5C/W 73.2C/W 98.0C/W 66.6C/W 88.0C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS840014I is: 3085 840014AGI www.icst.com/products/hiperclocks.html 9 REV. A DECEMBER 23, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS840014I FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER 20 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 840014AGI www.icst.com/products/hiperclocks.html 10 REV. A DECEMBER 23, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS840014I FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count ICS840014AGI ICS840014AGIT Temperature TBD 20 Lead TSSOP 72 per tube -40C to 85C TBD 20 Lead TSSOP on Tape and Reel 2500 -40C to 85C The aforementioned trademarks, HiPerClockSTM and FEMTOCLOCKSTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840014AGI www.icst.com/products/hiperclocks.html 11 REV. A DECEMBER 23, 2004