NJU3610
-1-
Ver.2009.12.4
1bit Delta-Sigma Stereo ADC
General Description
The NJU3610 is the stereo Analog to Digital Convector (ADC) that covers from 8
to 192 kHz sampling frequency. The NJU3610 provides 1bit Delta-Sigma
technology with high accuracy and low power consumption. The analog inputs are
differential signal and stereo 4-1 selectors are provided. The NJU3610 provides two
power-supply 1.8V / 3.3V(typical) or single power-supply 3.3V(typical) application.
Features
1bit Delta-Sigma stereo ADC
64fs over sampling (MCK=256fs, 384fs)
32fs over sampling (MCK=128fs)
Digital Fi lter
High-pass filter
Stereo 4-1 selectors
Sampling Rate : 8 to 192kHz
Dynamic Range : 100dB(typ@3.3V, 96kHz)
S/N : 100dB(typ@3.3V, 96kHz)
S/(N+D) : 90dB(typ@3.3V, 48kHz, -1.0dBFS)
Master Clock : 128fs(8 to 192kHz), 256fs / 384fs(8 to 96kHz)
Power Supply : Single power supply 3.0 to 3.6V(3.3Vtyp) Built-in regulator using together
: Two po wer supply 3.0 to 3.6V(Analog, I/O:3.3Vtyp)
1.65 to 2.0V(Digital:1.8Vtyp)
Digital Audio Format : 24/16bit Left-justified, I2S Master/Sla ve
Operating Temperature : -40 to +85°C
Package : LQFP48-R3 (Pb-Free)
Package
NJU3610FR3
NJU3610
- 2 - Ver. 2009.12.4
Function Block Diagram
AINLP1
AINLN1
AINLP2
AINLN2
AINLP3
AINLN3
AINLP4
AINLN4
AINRP1
AINRN1
AINRP2
AINRN2
AINRP3
AINRN3
AINRP4
AINRN4
Decimation
Digital
Filter
with
High-Pass
Filter
Serial
Audio
Interface
SEL0
SEL1
VCOM
4-1
Selector
Lch
5th Order
Delta-Sigma
Modulator
Lch
1bit
PDM
4-1
Selector
Rch 5th Order
Delta-Sigma
Modulator
Rch 1bit
PDM
24bit
PCM
24bit
PCM
VREGI
VREGO Voltage
Regulator
each Analog
Blocks
Power Control
Clock and Timing Control
MCK
BCK
LRCK
SDO
FMT0
MODE0
MODE1
HPF
RESETb
PDNb
AVDD
AVSS
VDD18
VDD33
VSS
FMT1
AVDD/AVSS : Analog Power Supply (typ:3.3V)
VDD18 : Digital Logic (typ:1.8V)
VDD33 : Digital I/O (typ:3.3V)
VSS : Digital GND and Regulator GND
Feedback
1bit DAC Rch
Feedback
1bit DAC Lch
Clock(64 or 32Fs)
/ Control Signal
Power
Power
Reference
REFLP
REFLN
REFRP
REFRN
Reference
Fig. 1 NJU3610 Block Diagram
NJU3610
-3-
Ver.2009.12.4
Pin Conf iguratio n
Fig.2 NJU3610 Pin Co nf iguration
24
23
22
21
20
19
18
17
16
15
14
37
38
39
40
41
42
43
44
45
46
47
36
35
34
33
32
31
30
29
28
27
26
25
13 48
1
2
3
4
5
6
7
8
9
10
11
12
NJU3610FR3
SDO
LRCK
BCK
HPF
VSS
VDD18
VDD33
MCK
FMT0
FMT1
SEL0
SEL1
AINLN4
AINLP4
REFLP
REFLN
TEST
AVSS
AVDD
VCOM
REFRN
REFRP
AINRP4
AINRN4
AINRP3
AINRN3
AINRP2
AINRN2
AINRP1
AINRN1
AIVSS
AVDD
MODE1
MODE0
RESETb
PDNb
AINLP3
AINLN3
AINLP2
AINLN2
AINLP1
AINLN1
AVSS
AVDD
VDD33
VSS
VREGI
VREGO
NJU3610
- 4 - Ver. 2009.12.4
Pin Descripti on
Table.1 P in De scri ptio n
Pin No. Symbol I/O Descripti on
1 AINLP3 AI Lch Analog Positive Input 3 Pin
2 AINLN3 AI Lch Analog Negative Input 3 Pin
3 AINLP2 AI Lch Analog Positive Input 2 Pin
4 AINLN2 AI Lch Analog Negative Input 2 Pin
5 AINLP1 AI Lch Analog Positive Input 1 Pin
6 AINLN1 AI Lch Analog Negative Input 1 Pin
7 AVSS AG Analog Ground Pin
8 AVDD AP Analog P ower Supply Pin, 3.3V
9 VDD33 DP Digital Power Supply Pin, 3.3V
10 VSS DG Digital Ground Pin
11 VREGI RI Built-in Regulator Input Pin, 3.3V
12 VREGO RO Built-in Regulator Output Pin, 1.8V (typ)
13 SDO DO Aud i o Seri al Dat a Out pu t Pin
14 LRCK DIO LR Clock
15 BCK DIO Bit Clock
16 HP F DI HP F for Of f-s et C an c el (“H”: ON, “ L”: OFF)
17 VSS DG Digital Ground Pin
18 VDD18 DL Digital Power Supply Pin, 1.8V
19 VDD33 DP Digital Power Supply Pin, 3.3V
20 MCK DI Master Clock Input Pin
21 FMT0 DI Control Serial Data Format 0 Pin
22 FMT1 DI Control Serial Data Format 1 Pin
23 SEL0 DI Control Input Selector 0 Pin
24 SEL1 DI Control Input Selector 1 Pin
25 PDNb DI Power Down Mode Pin (”H”: Power up, “L”: Power down)
26 RESETb DI Reset Pin (“H”: Reset OFF, “L”: Reset ON)
27 MODE0 DI Control Mode 0 Pin
28 MODE1 DI Control Mode 1 Pin
29 AVDD AP Anal og Po wer Supply Pin, 3.3V
30 AVSS AG Analog Ground Pin
31 AINRN1 AI Rch Analog Negative Input 1 Pin
32 AINRP1 AI Rch Analog Positive Input 1 Pin
33 AINRN2 AI Rch Analog Negative Input 2 Pin
34 AINRP2 AI Rch Analog Positive Input 2 Pin
35 AINRN3 AI Rch Analog Negative Input 3 Pin
36 AINRP3 AI Rch Analog Positive Input 3 Pin
37 AINRN4 AI Rch Analog Negative Input 4 Pin
38 AINRP4 AI Rch Analog Positive Input 4 Pin
39 REFRP AI Rch Voltage Reference Input Pin, AVDD
40 REFRN AI Rch Voltage Reference Input Pin, GND
41 VC OM AO C ommon Volta ge Ou tp u t Pin, AVDD/2
Connected to AVSS with a 10uF electrolytic capacitor.
42 AVDD AP Anal og Po wer Supply Pin, 3.3V
43 AVSS AG Analog Ground Pin
44 TEST AI Test Pin (Connected to AVSS)
45 REFLN AI Lch Voltage Reference Input Pin, GND
46 REFLP AI Lch Voltage Reference Input Pin, AVDD
47 AINLP4 AI Lch Analog Positive Input 4 Pin
48 AINLN4 AI Lch Analog Negative Input 4 Pin
* AP : Analog power supply, 3.3V AG : Analog ground AI : Analog input
AO : Analo g outp ut DP : Digital power supply, 3.3V
DL : Digi tal po wer suppl y, 1.8 V DG : Digital gro und and b uilt -in re gulator gro und
RI : buil t-i n regu lator i nput RO : built -in re g ulator o utp ut
DI : Digital i np ut DO : Digital o utp ut
DIO : Bi-direct io nal o f Digi ta l
NJU3610
-5-
Ver.2009.12.4
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings (VSS=AVSS=0V=GND, Ta=25°C)
Parameter Symbol Rating Units
Analog AVDD
VDD33 -0.3 to +4.2
Digital VDD18 -0.3 to +2.3
Built-in Regulator
Input VREGI -0.3 to +4.2
Po wer supp lie s
Built-in Regulator
Output VREGO -0.3 to +2.3
Digital I nput Vx(IN) -0.3 to +5.5 (VDD33≥3.0V)
-0.3 to +4.2 (VDD33<3.0V)
Digital O utp ut Vx(OUT) -0.3 to VDD33 + 0.3
Analog Inp ut Vx(AIN)
Pin Voltage
VCOM Output Vx(VCOM) -0.3 to AVDD + 0.3
Po wer Dissip atio n PD 800
Mount ed on t wo- l ayer boa r d of based on the J E DE C . mW
Operating Temperature TOPR -40 to +85 °C
Storage Temperature TSTR -40 to +125 °C
* AVDD : 8, 29, 42pin
* VDD33 : 9pin
* VDD18 : 18pin
* VR EGI : 11pin
* VR EGO : 12pin
* VX( IN) : 16, 20-28pin, and 14-15pin (set in the state of the input.)
* VX(O UT) : 13pin, and 14-15pin (set in the state of the output.)
* VX( AIN) : 1-6, 31-40, 44-48pin
* VX(V COM) : 41pin
Note 1) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using
LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the
electrical characteristic s conditions will cause malfunctio n and poor reliability.
Note 2) Please do not open the digital input terminal. Moreover, please do not open the digital I/O terminal set
in the state o f the input.
Recommended operating conditions
Table 3. Recommended operating conditions
Parameter Symbol
Recommended operating
condition s Units
Analog AVDD
*1
VDD33 *1 3.0 to 3.6
AVDD33≥VDD3 3
Digital VDD18 *2 1.65 to 2.0
(Or, a built-in regulator supplies
the voltage.)
Power
Supplies
Built-i n Re gul ator I np ut VREGI *3 3.0 to VDD33
V
*1 VDD33 is recommended to be turned on from AVDD and simultaneous or AVDD back.
*2 The power up sequence VDD18 is not critical.
*3 When a built-in regulator is used, VREGI is connected with VDD33. When a built-in regulator is not used,
VREGI and VREGO are connected with VSS.
V
NJU3610
- 6 - Ver. 2009.12.4
Electric Characteristics
Table 4. Analog Characteristics
Parameter Condition Min. Typ. Max. Units
AI N * * * Pi n
(Differe nt ial one side ) AVDD x 0.7
Full-scale voltage level *1 AIN*** Pin
(Between differential motions) AVDD x 1.4 Vpp
S/(N+D)
(-1. 0dBFS )
fs=48kHz
fs=96kHz
fs=192kHz
85
-
-
90
90
90
-
-
- dB
Dynamic Range
(-60dBFS, A-weighted)
fs=48kHz
fs=96kHz
fs=192kHz
93
-
-
99
100
100
-
-
- dB
S/N
(A-weighted)
fs=48kHz
fs=96kHz
fs=192kHz
93
-
-
99
100
100
-
-
- dB
Cross Talk
(During t he select ion and non-se lect ion) fs=48kHz, 1kHz BPF - 110 - dB
Channel Sep ara tio n
(Between L and R) fs=48kHz, 1kHz BPF 97 110 - dB
Equivalent input impedance
(Selec tion inp ut terminal)
fs=48kHz
fs=96kHz
fs=192kHz
-
-
-
100
50
50
-
-
- kOhm
Input impedance *2
(Non-Se lect ion input termina l)
fs=48kHz
fs=96kHz
fs=192kHz
40
40
40
58
58
58
-
-
- KOhm
Gain Mismatch fs=48kHz -0.1 - 0.1 dB
(Ta=25°C, AVDD=VDD33=3.3V, VDD18=VREGO, HPF=ON, Input signal=1kHz(AINL*4/AINR*4), BCK=64fs,
MCK=256fs(48/96kHz), 128fs(192kHz), Measurement frequency=20Hz-20kHz at fs=48kHz, 20Hz-40kHz at
fs=96kHz, 20Hz-40kHz at fs=192kHz)
*1 The full-scale voltage level indicates full-scale value (0dBFS) of the analog input voltage. A full-scale voltage is
proportional to the AVDD voltage. The meaning between differential motions is an operation result of the
differential input s ignal. T he input volta ge o f the ter minal is up to AVDD volta ge.
*2 The analog input ter minal of non-selectio n does the bias to VCOM by the resista nce of this value.
Table 5. P ow er Supply Cur rent （Ta=25°C, AVDD=VDD33=3.3V, VDD18=1.8V）
Parameter Condition Min. Typ. Max. units
3.3V, Power Supply Current: IDD + IDD A
(Not contain a built-in regulator)
fs=48kHz
fs=96kHz
fs=192kHz
-
-
-
7.0
8.0
8.0
-
-
12 mA
1.8V, Power Supply Current: IDDL
(Not contain a built-in regulator)
fs=48kHz
fs=96kHz
fs=192kHz
-
-
-
2.0
4.0
8.0
-
-
10 mA
Power down mode: IDDQ+IDDLQ
(Not contain a built-in regulator) Clock stop
PDNb=Low - - 100
µA
Built-i n regulato r Curr e nt: IRIN VREGI=3.3V
IOUT=0mA - 50 70
µA
NJU3610
-7-
Ver.2009.12.4
Table 6. Digital DC Characteristics (Ta=25°C, VDD33=3.3V, VDD18=1.8V)
Parameter Symbol Condition Min. Typ. Max. Units
High-Leve l Inp ut Vo lta ge VIH 2.2 - VDD33 *1 V
Low-Level Inp ut Volta ge VIL 0 - 0.8 V
High-Leve l O utput Vol tage VOH I
OH=-1mA VDD33 x 0.8 - VDD33 V
Low-Level O utput Voltage VOL I
OL=1mA 0 - VDD33 x 0.2 V
Input Leakage Current IIN V
IN=VSS, VDD -10 - 10 µA
*1 The digital i nput ter minal and t he inp ut d igital I /O t er minal are 5V tolera nt o nly at VDD33 ra tin gs.
Table 7. Reset AC Characteristics (Ta=25°C, VDD33=3.3V, VDD18=1.8V)
Parameter Symbol Condition Min. Typ. Max. Units
Reset Time tRESETb RESETb 100 - - ns
Table 8. Digital Filter Characteristics (Ta=25°C, VDD33=3.3V, VDD18L=1.8V)
Parameter Condition Min. Typ. Max. Units
Cut-off frequency
(HPF=High) -3.0dB - fs/44100 - Hz
LPF P a s s b and 0 - 0.454 fs
LPF Pass band ripple - -
±0.005 dB
LPF Stop band 0.546 - - fs
LPF Stop band attenuation -80 - - dB
Group Delay - 27 - 1/fs
NJU3610
- 8 - Ver. 2009.12.4
Table 9. Clock Timi ng (Ta=25°C, VDD33=3.3V, VDD18=1.8V)
Parameter Symbol Condition Min. Typ. Max. Units
MCK Frequency *1 fMCK 128fs
256fs
384fs
1.024
2.048
3.072
-
-
-
24.576
24.576
36.864 MHz
BCK Fr eque nc y *2 fSCK Slave 0.256 - 12.288 MHz
LRCK Fre q ue ncy *2 fLRCK Slave 8.0 - 192 kHz
MCK Pulse Width Low
MCK Pulse Width High tMIL
tMIH 0.475/fMCK
0.475/fMCK 0.5/fMCK
0.5/fMCK 0.525/fMCK
0.525/fMCK ns
BCK Pulse Width Low
BCK Pulse Width High tSIL
tSIH Slave
Slave 35
35 0.5/fMCK
0.5/fMCK -
- ns
BCK to LRCK *3 tSLI Slave 20 - - ns
LRCK to BCK *3 tLSI Slave 20 - - ns
*1 For fs=8 to 192kHz at 128fs mode. For fs=8 to 96kHz at 256fs/384fs mode.
*2 MCK s hould synchr o n iz ed wit h B CK a nd LRC K. ( No t ne c es sa r y to p h ase i t. )
*3 BCKI rising edge must not occur at t he same time as LRCK ed ge
Fig.3 MCK Timing diagram
Fig.4 BCK, LRCK Timing Diagram
Table 10. Serial Audio Output Timing (Ta=25°C VDD33=3.3V, VDD18=1.8V)
Parameter symbol Condition Min. Typ. Max. Units
BCK to LRCK Ti me *1 tSLO CL=25pF -20 - 20 ns
Data Output Delay tDOD CL=25pF - - 20 ns
*1 I t is r eg ulatio n i n Master mode.
Fig.5 Serial Audio Output Timing Diagram
MC
K
tMIL
tMIH
LRCK
BCK
tSIH tLSI
tSIL tSLI
SDO
t
DO
D
LRCK
BCK
t
S
L
NJU3610
-9-
Ver.2009.12.4
1. Power-supply, RE SET , Power Down
1.1 Power-supply
The power-supply should be used under the recommended condition. The power-on level procedure should
increase monotonously. During the operation, the power-supply should not become out of the recommended
condition.
The large size decoupling capacitor should be implemented near the NJU3610. The analog/digital power line
should be taken from this large capacitor. Also the power-supply terminals should have enough decoupling
capacitors to the terminals.
The REFLP, REFLN, RE FRP, RE FRN are the re ference voltage ter minals o f the 1bit -feedback-DAC. The REFLP
and REFRP should be connected to AVDD power line. The REFLPN and REFRN should be connected to AVSS line.
These terminals affect the an alog performance, so the de co upling capacitor is ver y important.
The VCOM output is the half of the AVDD voltage level with the voltage-follower buffer. The VCOM voltage
level is t he inter nal reference. T he non-selected input term inals are p ull-upped to the i nternal reference via 58 k-oh m
resistors. The 10uF capacitor is recommended to improve noise and channel separation performance. This terminal
output is available for the a nalog reference le vel o f the input circuit.
The NJU3610 provides the internal voltage regulator for internal digital circuit. The VREGI terminal is the input
to the internal regulator. The input to VREGI should be the same voltage as VDD33 input. The output of the
internal voltage regulator is VREGO. If the VREGO output is connected to VDD18, no other 1.8V power-supply is
necessary.
If the internal voltage regulator is used, put the capacitor (around 4.7 to 10uF) between VREGO and VSS.
If the internal volta ge re gula to r is no t used, co nnect bo t h VREGI and VREGO to VSS.
The internal volta ge re gula tor is p rovided for the NJU3 61 0 circuit, d o not use it for the other circ u it.
If the VDD33 and AVDD are different power-supply, follow the next power-on procedure.
First power on analog power-supply (AVDD). Next power on digital power-supply (VDD33).
Also it is possible to power on analog and digital power-supply simultaneously.
Power-on Timing Condition: AVDD (before)
≥ VDD33 (same or after)
There is no constraining on VDD18 power-on procedure. Also there is no constraining on power-down procedure
for all po wer-supplie s.
NJU3610
- 10 - Ver. 2009.12.4
1.2 Digital Input Terminal
All digital input terminals are 5V tolerant under the recommended VDD33 power-on condition. Also BCK and
LRCK that ar e assi gned a s in put mode ar e 5V tolera nt und er the re co mmended VDD33 po wer-on condition.
Input/output setting of BCK and LRCK are defined by FMT1 terminal. These terminals are input mode in case of
FMT1 = “Low” and o utput mode in case o f FMT1 = “Hi gh”.
During RESET b ter minal = ” Low”, B CK and LRCK are i nput mode reg ardles s of FM T 1 conditio n.
1.3 RESET and Power Down
During RESET b ter mi nal = ”Low”, di gital filter a nd a nalo g integra tor ar e init ialized and SDO o utp ut is lo w level.
The internal reference voltage generator is operating during RESETb terminal = ”Low”.
If the terminal setting or clock is changed under ADC operation, RESETb should be initialized again.
In case of PDNb = ”Low”, all analog circuit become power-down mode. The digital filter is operating under PDNb
= ”Low”, but the clock to analog circuit is stopped. If power-down mode is not used, PDNb should be “high”.
After power-on, the next reset procedure should be done at least one time to initialize the NJU3610. RESETb
should be “Low” level and become “High” level again. Changing PDNb from “Low “level to “High” level makes
VCOM reference level generated. The setup time of VCOM-reference-le vel depends o n the attac hed capacitor.
The proced ure to c hange RE SET b level (“ Low” to “Hig h”) should b e do ne, a fter VCOM le vel beco me s stab le.
The procedure of SDO audio data output is as following: First RESET is released from “Low” to “High” level.
After RESET r elease, wait 136±8fs period and SDO generates audio data. But to get the accurate output data, VCOM
reference le vel should b eco me hal f of AVDD level.
If the High Pass Filter is used to cancel offset (HPF=”High”), some more time (max. 8192fs) after generating audio
data is necessary to get accurate output data.
In order to power down the NJU3610 completely, PDNb should be “Low” and, also clocks to MCK, BCK and
LRCK should be stopped.
Notice:
The internal regulator does not provide power-down mode. As far as power is supplied to VREG1, it generates
output vo ltage wit h c o ns u min g p o wer.
NJU3610
-11-
Ver.2009.12.4
2. ADC Function
2.1 Clock and Digital Audio Interface
The NJU3610 requires MCK, BCK and LRCK audio clock. BCK and LRCK can be generated by MCK i n Master
mode. MCK, BCK and LRCK are synchronized in Master mode.
In Slave mode, BCK and LRCK are inputted from the outside. In Slave mode, MCK, BCK and LRCK should be
synchronized. But it is not necessar y that the phase of thes e three cloc ks are synchronized.
MCK frequency should be one of 128fs, 256fs or 384fs. If fs>96KHz, MCK should be 128fs. The ADC operates
wit h the ne xt freq uenc y. T he operat e freq uency i s 64 fs in cas e of fs ≦96KHz. The operate frequency is 32fs in case
of fs>96KHz.
Mode0 and mode1 terminals select the MCK frequency and ADC operating frequency.
In case that ADC operating frequency is 32fs, the effective bandwidth is 1/4fs. Between 1/4fs and 1/2fs, ADC
shaping noise exists.
The NJU3610 digital audio format provides Left-justified and I2S 24bit(BCK=64clocks/fs) in Master mode. The
NJU3610 digital audio format provides Left-justified, I2S 16bit (BCK=32clocks/fs) and I2S 24bit(BCK=64clocks/fs)
in Slave mode.
FMT0 and FMT1 terminals select the above digital audio format. When FMT0, FMT1, MODE0 and MODE1 are
cha nge d , R E SET sho ul d b e d o ne agai n.
MCK, BCK and LRCK frequency is shown in table11. Digital Audio Format and operation mode is shown in table12.
In Master mode, BCK and LRCK terminals generate clocks. BCK output clock is fixed at 64fs in Master mode. In
Slave mode, BCK and LRCK ter minals are assigned input.
Table 11.
MCK, BCK, LRCK (1)
LRCK(kHz)
Mast er: Gene rat ion fro m MCK
Slave: From outside MCK (MHz) BCK(MHz)
128fs 256fs 384fs
32fs
Slave only: from outside
64fs
Mast er: Gene rat ion fro m MCK
Slave: From outside
8 -*2 2.048 3.072 0.256 0.512
16 -*2 4.096 6.144 0.512 1.024
22.05 -*2 5.6448 8.4672 0.7056 1.4112
32 -*2 8.192 12.288 1.024 2.048
44.1 -*2 11.2896 16.9344 1.4112 2.8224
48 -*2 12.288 18.432 1.536 3.072
64 -*2 16.384 24.576 2.048 4.096
88.2 -*2 22.5792 33.8688 2.8224 5.6448
96 -*2 24.576 36.864 3.072 6.144
176.4
*1 22.5792 - - 5.6448 11.2896
192
*1 24.576 - - 6.144 12.288
*1 It i s o n l y a settin g o f “C K M OD E[ 1 :0 ] =1 0 ,11”. At thi s t i me, fr eque ncy b a ndwid t h i s up to 1 /4fs.
The shaping noise o f the ADC is included in the ba nd from 1/4fs to 1/2fs.
*2 Because an e ffective band widt h is li mited, it is not pr acticab le.
NJU3610
- 12 - Ver. 2009.12.4
Table 12. MCK,BCK,LRCK (2)
CMKODE FMT
1 0 1 0 Master /
Slave A/D
mode MCK
(fs) For mat
0 0 0 0 I2S (32 or 64fs)
0 0 0 1 Slave Left-justified(32 or 64fs)
0 0 1 0 I2S (64fs)
0 0 1 1 Master 64fs 256fs
(≦96kHz) Left-justified(64fs)
0 1 0 0 I2S (32 or 64fs)
0 1 0 1 Slave Left-justified(32 or 64fs)
0 1 1 0 I2S (64fs)
0 1 1 1 Master 64fs 384fs
(≦96kHz) Left-justified(64fs)
1 0 0 0 I2S (32 or 64fs)
1 0 0 1 Slave Left-justified(32 or 64fs)
1 0 1 0 I2S (64fs)
1 0 1 1 Master 32fs 256fs
(>96kHz) Left-justified(64fs)
1 1 0 0 I2S (32 or 64fs)
1 1 0 1 Slave Left-justified(32 or 64fs)
1 1 1 0 I2S (64fs)
1 1 1 1 Master 32fs 128fs
(>96kHz) Left-justified(64fs)
Fig.6 Left-justified Data Format 64fs, 24bit Data
Fig.7 I 2S Da ta For mat 6 4fs, 2 4b it Data
Fig.8 Left-justified Data Format 32fs, 16bit Data
Fig.9 I 2S Da ta For mat 3 2fs, 1 6b it Data
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23
Left Ch anne l Right Cha nne l
MSB MSB LSB LSB
32 Clock s 32 Clock s
LRCK
BCK
SDO
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Left Chann el Right Channel
MSB MSB LSB LSB
32 C locks 32 C lock s
LRCK
BCK
SDO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Left Channe l Right Cha nnel
MSB MSB LSB LSB
16 Clock s 16 Clocks
LRCK
BCK
SDO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Left Channe l Right Cha nnel
MSB MSB LSB LSB
16 Clock s 16 Clocks
LRCK
BCK
SDO
NJU3610
-13-
Ver.2009.12.4
2.2 High Pass Filter for offset-cancel
The NJU3610 provides High Pass Filter (digital filter) to cancel offset. Normally HPF terminal is set “High”. In
case of HFP=”High”, High Pass Filter is active. The frequency characteristics are shown in table 8. The cutoff
frequency is set at low frequency. But sampling rate changes the cutoff frequency. HFP terminal setting can be
changed during NJU3610 operating. But changing HPF setup makes pop noise that is caused by offset change.
2.3 Analog Input and 4-1 Selector
The NJU3610 provides four differential-stereo-inputs. SEL0 and SEL1 terminals select one of four stereo-input.
After this selector, input signal goes to ADC input. SEL0 and SEL1 combination is shown in table13.
Table 13 . S EL1 , SE L0 combinat io n
Lch Rch
SEL1 SEL0 Non-reversing
input
Reversing
input
Non-reversing
input
Reversing
input
0 0 AINLP1 AINLN1 AINRP1 AINRN1
0 1 AINLP2 AINLN2 AINRP2 AINRN2
1 0 AINLP3 AINLN3 AINRP3 AINRN3
1 1 AINLP4 AINLN4 AINRP4 AINRN4
Each differential-signal input should be biased with VCOM reference level. The half of AVDD le vel is available
instead of VCOM reference level. Input full-scale level (0dBFS) is “AVDDx0.7Vpp”. In differential signal, Input
full-scale le vel i s “AVD D x1.4Vpp ”. Maxi mum a vailable inpu t ran ge is fro m GND to AVDD with disto rtio n. B ut in
this case, the distortion occurs. When AMP with high voltage power-supply is used before the ADC, the input level
should not exceed the ADC input range.
SEL0 and SEL1 settings are taken in at MCK rising edge. In case of RESETb=”Low”, AINLP1, AINLN1,
AINRP1 and AINRN1 are selected regardless of SEL0/SEL1 settings. In case that PDNb level is changed from
“high” to “Lo w”, the lates t c onditio n is maintai ned.
The terminals that are not selected by SEL0/SEL1 are pull-upped by VCOM bias via 58ohm resisters. The analog
input terminals that are not used should be left open or adds the capacitors between terminals and GND. If these
terminals connect directly to po wer-supply or GND, VCOM fluctuates and the NJU3610 does not operate properly.
The NJU3610 operates with 32fs over sampling at Mode1=”High”. The NJU3610 operates with 64fs over
sampling at Mode1=”Low”. If noise exists around over sampling frequency, the noise folds back. To avoid this
folding bac k noise, p a ssi ve RC filter is r equir ed.
The example of input buffer circuit is shown in figure10. VCOM output is used for bias level. The J1 selects RCA
or XLR input. The RC-passive-filter is consist of Ra/Rb(220ohm), Ca/Cb(100pF) and Cc(200pF). The cutoff
frequency of RC-passive-filter is 1447KHz.
This input buffer circuit should be implemented to analog input terminals as far as short distance. The layout
pattern should be symmetric.
AIN*N*
AIN*P*
R1
C1
R2
Ra=220
Rb=220
Ca=100p
Cb=100p
Cc=200p
VCOM_OUT
BIAS(VDDAx0.5)
10μ
R1
C1
R2
47μ
47μ
BIAS
BIAS
1
2
3
NJU3610
RCA
XLR
J1
Fig.10 Input buffer example
NJU3610
- 14 - Ver. 2009.12.4
Package dimension
LQFP48-R3 (Pb-Free)
Plating: Sn-Bi
0.076
モールド底面
0.1±0.05 1.4±0.05
1.5±0.1
0.17TYP
0〜10°
0.6±0.1
1
12
48
37
36
13
24
25
9±0.1
7±0.1
7±0.1
9±0.1
0.5 0.22±0.1
[CAUTION]
The specifications on this data book are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this data book are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Mold
