HIGH SPEED IDT7130SA/LA 1K X 8 DUAL-PORT IDT7140SA/LA STATIC SRAM Features * High-speed access * On-chip port arbitration logic (1DT7130 Only) ~ Military: 25/35/55/100ns (max.) * BUSY output flag on IDT7130; BUSY input on IDT7140 - Industrial: 55/100ns (max.) * INT flag for port-to-port communication - Commercial: 20/25/35/55/100ns (max.) * Fully asynchronous operation from either port * Low-power operation * Battery backup operation-2V data retention (LA only) ~ IDT7130/DT7140SA * TTL-compatible, single SV +10% power supply Active: 550mW (typ.) * Military product compliant to MIL-PRF-38535 QML Standby: 5mW (typ.) * Industrial temperature range (-40 T to +85 C) is available IDT7130/IDT7140LA for selected speeds Active: 550mW (typ.) * Available in 48-pin DIP and LCC, 52-pin PLCC, and 64-pin Standby: 1mW (typ.) STQFP and TQFP * MASTER IDT7130 easily expands data bus width to 16-or- more-bits using SLAVE IDT7140 Functional Block Diagram OEL OER CEL CER RAL R/AWR VOoL- VO7L V/Oor-1/O7R VO VO Control Control Busyd'?) Ast MEMORY ARRAY nor ARBITRATION and INTERRUPT LOGIC INTA? 2689 drw 01 int? NOTES: 1. (017130 (MASTER): BUSY is open drain output and requires putlup resistor. 1DT7140 (SLAVE): BUSY is input. 2. Open drain output: requires putlup resistor. pen cain ouput: requres pum MARCH 1999 DSC-2689/8IDT7130SA/LA and IDT714NSAILA High-Speed 1K x & Duai-Port Static SHAN Scie eriireLsE-TiNtcl Me cits Me marsha Lslc Tea ELM Raab S20: 10s Teas Cel a0e (oS) Description The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or- more-bit memory system applications results in full-speed, error- free operation without the need for additional discrete logic. Both devices provide two independent ports with separate con- trol, address, and 1/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry Pin Configurations 2) of each port to enter a very low standby power made. Fabricated using IDT's CMOS high-performance tech-nology, these devices typically operate on only 550mW of power. Low- power (LA) versions offer battery backup data retention capability, with each Dual-Port typically consuming 200pW from a 2V battery. The 1DT7130/DT7140 devices are packaged in 48-pin sidebraze or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP and STQFP. Military grade products are manufactured in compli- ance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. ae ce. G1 48. Vec _ RAW Le 47.) CEr BUSY: L/3 46] B/We INTL 4 45] BUSYR OE: C15 44] INTR Ao. C16 43L] OER AiLl]7 42C] Aor A2aL 8 iptzis940 41 Air As.Elg Forg, 40L] Aor AaClio P41 39C] par Ast (]11 cas-24) 38} Aan Ast 412 pin Of 5R A713. Bie 36L. Asa Asi L]14Top View) 350] A7R Ao. C15 34L] Asa VOo. F416 33/5 ASR S| cit Yoncig SD Ie HEB op 963868 2L R INDEX z |O |< Oo >10 m |Z |O va. F119 30F} vOsh oN. = /O4R VO. 120 on vO 65 4 3 2 48 47 46 45 44 43 VOs_ Lj21 28 3R 1 VOe. L122 27,1 VO2R Aifl7 Aor vor. E23 264 /O1R Aa [18 41 C1 Air GND C 24 25] VOor ASL 19 401 Aor 2689 drw 02 Aa F 10 IDT7130/40L.48 or F 394 Asr Asif] 11 4g 118) 387] Aar As. F112 F48-1(4) 37] Asr A7_L-113 36] Aer Aa 114 1B vis Figtback 351 Arr Agi tJ 15 34 (J Asr NOTES: Oo. [J 16 33(C] Aor 1. AllVec pins must be connected to power supply. VO) 17 32] vO7r 2. All GND pins must be connected to ground supply. ; VOet ] 18 31 Cl V/Oer * Celi lapedeemee) ecsemice NC 192021 2823 24 2526 27 2829 607 48-1 package body is approximately 57 in x7 in x 68 i, HoOoOoOODoDoOoOoOoOoG F48-1 package body is approximately .75 in x .75 in x .11 in. axe ezegr7PQ ETE or co 2689 drw 03 4. This package code is used to reference the package diagram. Ooo0o00ag0 42 8 OoOoO0a000 5. This text does not indicate orientation of the actual part-marking. =Ss SES SS 035 252535 2555IDT7130SA/LA and IDT7140S 4/14 High-Speed 1K x 8 Duai-F ems l ent IEEE Le UML LC TERT ALS OTSA eS TEE ane RcLaaT s)-1e- tet oe = eeT NTs] 19 Pin Configurations 23) (con't.) ee ie GSP Eo INDEX. gBSEB SASMIERBES 76 5 4 3 2 52 51 50 49 48 47 Ait f-18 1 46(J O&R Aa --19 45 Aor As. [1 10 4407 air Aa F111 43] Aor ns 2 rong of Ae. P13 . 41L] aan An 14 "Top Views) 40(] Asa Ase 7] 15 39] A6R Ast. 1 16 387 A7R VOo. [4 17 377] Asr vOi. F118 36(7] Aor V/Oat 119 35CJ NIC /Os_ FJ 20 347] vozr 21 22 23 24 25 26 27 28 29 3031 3233 \ goon. os > > 10 = 4 oo o,f epee SSHERESSS INDEX", OEL OER Aot. AOR Ait AIR Aat. A2R A3L A3R At IDT7130/40TF or PF A4r ASL PP64-1 & PN64-1(4) ASR on 64-Pin STQFP AsR N/C 64-Pin TOFP N/C AZL Top View(5) A7R A8L A&R ASL AOR N/C N/C Oot NIC VO8L VO7R VO2t' \/O6R 2689 drw 05 NOTES: 1. All Vcc pins must be connected to power supply. 2. AN GND pins must be connected to ground supply. 3. J52-1 package body is approximately .75 in x .75 in x .17 in. PP64-1 package body is approximately 10 mm x 10 mm x 1.4mm. PN64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.IDT7130SA4/1.A and IDT7140S 4/1. High-Speed 1K x 8 Dual-Port Sian: SRAM SUSE anecdote erie ieee ete Te (2 Absolute Maximum Ratings Recommended DC Operating Symbol Rating Commercial Military Unit Conditions & Industrial . : Symbol Parameter Min. | Typ. | Max. | Unit VierM? | Terminal Voltage 0.5 to +7.0 0.5 to +7.0 v with Respect Vcc | Supply Voltage 4.5 5.0 5.5 Vv to GND GND | Ground 0 en Oe TRIAS Temperature -55 to +125 65 to +135 C : 3 Under Bias Vit | Input High Voltage 2.2 ~~ | 600] Vv mM fo Ts1G Storage 55 to +125 65 to +150 C Vit Input Low Voltage 0.5 0.8 V Temperature 2689 tbl 02 NOTES: lout DC Output 50 50 mA 1. Vit (min.) > -1.5V for pulse width less than 10ns. Current 2. VTERM must not exceed Vcc + 10%. NOTES: 2689 tbi 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in Recommended Operating Temperature and Supply Voltagd'?) the operational sections of the specification is not implied. Exposure to absolute , maximum rating conditions for extended periods may affect reliability. Grade Ambient GND Vec 2. VTeRM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns Temperature maximum, and is limited to < 20mA for the period of Vrerm > Vcc + 10%. Military BPC to +125C OV 5.0V + 10% Commercial 0C to +70C ov 5.0V + 10% Capacitance (Ta = +25C, f = 1.0MHz) industrial 40C to +85C | OV 5.0V + 10% STQFP and TQFP Packages Only 2689 ti 03 NOTES: Symbol Parameter!) Conditions | Max | Unit | 1. Thisis the parameter Ta. CN input Capacitance VN = 3dV 9 pF 2. insta temperature for specific speeds, packages and powers contact your Cour | Output Capacitance Vout = 3dV 10 pF 2689 toi 05 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the inpul and output signals switch from OV to 3V or from 3V to OV. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage RangeiVcc = 5.0V + 10%) 7130SA 7130LA 7140SA 7140LA Symbol Parameter Test Conditions Min. Max. Min. Max Unit jul Input Leakage Current Vcc = 5.5V, Vin = OV to Vec ~ 10 5 uA {ko Output Leakage Current Vee - 5.5V, ~ 40 5 pA CE = Vix, Vout = OV to Vcc VoL Output Low Voltage (/O0-/O7} lo. = 4mA ~ 0.4 -- 0.4 Vor. Open Drain Output. lo. = 16mA ~ 0.5 _ 0.5 Low Voltage (BUSY, INT} Vox Output High Voltage lou = 4mA 24 24 - Vv 2689 bl 04 NOTE: 1. At Vec < 2.0V leakages are undefined.DC Electrical Characteristics Over the Operating IDT7130SA/LA and IDT7140S AL. & High-Speed 1K x Dual-Pori sta) ingust rot ere are Temperature and Supply Voltage Rang'*) (vcc = 5.0V + 10%) ort eta LMR Ate or) 7430X 20) 7130X25 7130X35 7140X202 7440X25 7140X35 Com't Only Com & Com'l & Military Military Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. | Unit Icc Dynamic Operating CEL and CEr = Vi. COML SA 110 250 110 220 110 165 mA Current Outputs Open LA] 110 200 110 170 110 120 (Both Ports Active) f= fMax MIL & SA 410 280 410 230 IND LA 110 220 440 170 Isai | Standby Curent CE: and CEr = Vin COM'L SA | 30 65 30 65 25 65 | mA (Both Ports - TTL f= fMax?) LA 3 45 30 45 2 45 Level inputs) MIL & SA 30 80 25 80 IND LA 30 60 2 60 Isp2__| Standby Current CEA = Vu and CE = Viv COM'L SA| 65 165 65 150 50 125 | mA (One Port - TTL Active Port Outputs Open, LA 65 125 65 15 50 90 Level inputs) iva MIL & SA 65 160 50 160 IND LA 65 125 50 15 Isa Full Standby Current CE. and COM'L SA 1.0 15 4.0 15 4.0 16 mA (Both Ports - CER 2 Vec - 0.2V, LA 0.2 5 02 4 0.2 4 CMOS Level inputs) Vin > Vee - 0.2V or Vin < 0.2V, f= 08 MIL & SA 1.0 30 1.0 30 IND LA 0.2 10 0.2 10 Ispa Full Standby Current CEs < < 0.2V and COM'L SA 60 155 60 146 45 410 mA {One Por - CEs = Veo - 0.2V% LA 60 15 60 105 45 85 CMOS Level Inputs) Vin 2 Vee - 0.2V or Vin < O.2V Active Fort Outputs Open, MIL & SA 60 155 45 145 f= Mae IND LA 60 115 45 105 2689 tbl 06a 7430X55 7130X100 7140X55 7140X100 Com't, ind Com'l, Ind & Military & Military Symbo} Parameter Test Condition Version Typ. Max Typ. Max. | Unit Icc | Dynamic Operating CEL and CEr = Vi, COM'L SA | 110 155 110 155 | mA Current Outputs i Open LA | 110 140 140 110 (Both Ports Active) f= Max? MIL & SA 110 190 410 190 IND LA 110 140 110 140 Isat | Standby Current CE. and CER = ViH COM'L SA 20 65 20 55 mA (Both Ports - TTL eaten tA 20 36 20 35 Level inputs) MIL & SA 20 65 20 65 IND LA 20 45 20 45 \saz Standby Current C&ra" = Va and CEs = Viv COM'L SA 40 110 40 10 mA (One Port - TTL Active Port Outputs Open, LA 40 75 40 75 Level Inputs) fivax) MIL & SA 40 125 40 125 IND LA 40 90 40 90 {sea Full Standby Current CEL and COM'L SA 10 18 10 45 mA (Both Ports - CER 2 Vcc - 0.2V, LA 0.2 4 0.2 4 CMOS Level Inputs) Vin 2 Voc - 0.2V or Vin < 0.2, f= of MIL & SA 1.0 30 1.0 30 IND LA 0.2 10 0.2 10 isa -| Full Standby Current CE*a < 0.2V and COM'L SA} 40 100 40 95 mA (One Port - CE*a > Vcc - 0.2v) LA 40 70 40 70 CMOS Level Inputs) Vin > Vec - 0.2V or Vin < 0.2V Active Port Outputs Open, MiL & SA 40 110 40 110 f= fMax) IND LA 40 85 40 80 wore: 2689 1 060 X in part numbers indicates power rating (SA or LA). 2 PLCC and TOFP packages only. 3. Atf= fax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tcyc, and using AC TEST CONDITIONS" of input levels of GND to 3V. 4. f= 0means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Vec = 5V, Ta=+25 C for Typ and is not production tested. Vec DC = 100 mA (Typ) 6. Port "A" may be either left or right port. Port "B" is opposite from port A. Industrial temperature: for other speeds, packages and powers contact your sales office. 7.IDT7130SA/LA and IDT7140S AL A High-Speed IK x 8 Dual-Port Static SRAM Jibtary, ingustet Data Retention Characteristics(LA Version Only) Teles Rie MR OL*LiSios(oL outs MMEsIORTOL=2 8c LGCESME SET aTe (oS) T130LAI7140LA Symbol Parameter Test Condition Min. Typ. Max. | Unit VbR Vcc for Data Retention 2.0 ~ Vv Iccor Data Retention Current MIL. & IND. 400 4000 pA Vee = 2.0V, CE > Voc -0.2V COM'L. - 100 4500 teor) Chip Deselect to Data Retention Time Vin > Vcc -0.2V or Vin < 0.2V 0 ~ ~ nis R) Operation Recovery Time tro@ - ns 2689 tbi 7 NOTES: 1. Vec= 2V, Ta = +25 C, and is not production tested. 2. trc = Read Cycle Time 3. This parameter is quaranteed but not production tested. Data Retention Waveform DATA RETENTION MODE Voc VDR2>2.0V 4.5V {CDR *tR _ VDR CE VIH VIH 2692 drw 06IDT7130SA/LA and IDT7140S ALA High-Speed 1K x 8 Dual-Port Static SRAM AC Test Conditions Miltary iidustiai and Commercial Temperature Ranges Input Pulse Levels GND to 3.0V Input Rise/Fall Times Sns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1,2 and 3 2689 tl 08 BV. a 5V 12500 12502 DATAouT DATAouT 77530 == 30pF* 7752 = Spr *100pF for 55 and 100ns versions Figure 1. Output Test Load Figure 2. Output Test Load {for tuz, tLz, twz, and tow) * including scope and jig BV. A 270Q BUSY or INT 30pF* *100pF for 55 and 100ns versions Figure 3. BUSY and INT AC Output Test Load 2689 drw 07IDT7 130SA4/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Wiltary, industial and Commercial lemperature Rages AC Electrical Characteristics Over the Operating Temperature Supply Voltage Rang*) 7130X202) 7130X25 7130X35 7140X207 7140X25 7140X35 Com'l Only Com'l & Com'! & Military Military Symbol Parameter Min. | Max. Min. | Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 o 25 ad 35 os ns taA Address Access Time 20 f[ - 25 _ 35 ns tace Chip Enable Access Time oa 20 a 25 -- 35 ns taoe Output Enable Access Time _ 1 a 12 20 ns tOH Output Hold from Address Change 3 ~ 3 3 : ns uz Output Low-Z Time!!*! 0 ~- 0 - Q a ns thz Output High-Z Time") 10 ~ 10 - 15 ns {Pu Chip Enable to Power Up Time! 0 ~ 0 - 0 o ns PD Chip Disable to Power Down Time" a 20 _ 25 ~ 35 ns 2689 thi 09a 7130X55 7130X100 7140X55 7140X100 Com'l, Ind Com'l, ind & Military & Military Symbol Parameter Min. | Max. Min. Max. Unit READ CYCLE IRC Read Cycle Time 55 400 ns faa Address Access Time 56 _ 100 ns tACE Chip Enable Access Time ~ 55 100 ns {AOE Output Enable Access Time oo 25 - 40 ns tOH Output Hold from Address Change 3 10 - ns wz Output LowZ Time" 5 ~- 5 ~ ns HZ Output High-Z Time'4) a 25 o- 40 ns Pu Chip Enable to Power Up Time! 0 -- 0 ~- ns iPp Chip Disable to Power Down Time") _ 50 50 ns 2689 tht 090 NOTES: 1. Transition is measured +500mV from Low or High-impedance voltage Output Test Load (Figure 2). 2. PLCC, TQFP and STQFP packages only. 3. X in part numbers indicates power rating (SA or LA). 4. This parameter is guaranteed by device characterization, but is not production tested. 5. Industrial temperature: for other speeds, packages and powers contact your sales office.IDT7130SA/LA and IDT714A0SAILA High-Speed 1K & Dual-Pert Static SHAN Miuotary. iadustrai ang Coinmerciai Temperature Ranges Timing Waveform of Read Cycle No. 1, Either Sid@) on tAC ADDRESS v i tAA tOH _ toH DATAouT PREVIOUS DATA VALID DATA VALID BUSYouT WAAAY L teoon 2 2689 drw 08 NOTES: 1. RW = Vin, CE = Vil, and is OE = Vic. Address is valid prior to the coincidental with CE transition LOW. 2. tepp delay is required only in the case where the opposite port is compieting a write operation ta the same the address location. For simultaneous read operations, BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tack, tace, taa, and teDD. Timing Waveform of Read Cycle No. 2, Either Sid@) tACE DATAouT VALID DATA wz tipo!) icc {PU CURRENT f 50% 50% Iss 2689 drw 09 NOTES: __ 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. RAW = Vinand GE = VIL, and the address is valid prior to or coincidental with CE transition LOW 4. Start of valid data depends on which timing becomes effective last tack, tace, taa, and tBDD.IDT7130SA4/LA and IDT7140SA/LA High-Speed 1K x 8 Duai-Port Static SRAM Miltary, Industial ang Carmmercial temperative Ranges AC Electrical Characteristics Over the Operating Temperature Supply Voltage Rang@) 7130X20) 7130X25 7130X35 7140X20!) 7140X25 7140X35 Com'l Only Com'l & Com'l & Military Military Symbol Parameter Min. | Max. Min. | Max. Min. Max. Unit WRITE CYCLE we Write Cycle Time 20 oo 25 35 - ns tew Chip Enable to End-of-Write HB of oo 20 + ~ ns taw Address Valid to End-of Wiite 15 _ 20 _ 3% - ns fas Address Set-up Time 0 ae ] 0 a ns twe Write Pulse Width 15 15 [| 25 - ns tw Write Recovery Time ) 0 _ 0 _ ns tow Data Valid to End-of Write 140 a 12 a 18 ns tz Output High-Z Time" a 10 10 --- 15 ns {DH Data Hold Time 0 om 0 0 vee ns wz Write Enable to Output in High-Z 10 _ 10 _ 15 ns tow Output Active from End-of- Write 0 - oO | 0 a ns 2689 tb 10a 7130X55 7130X100 7140X55 7140X100 Com'l, tnd Com'l, Ind & Military & Military Symbol Parameter Min. | Max Min. Max. Unit WRITE CYCLE twe Write Cycle Time 55 100 _ ns tew Chip Enable to End-of-Write 40 -- 90 ns. taw Address Valid to End-ofWrite 40 90 -- ns tas Address Set-up Time 0 ~~ 0 ns we Write Pulse Width 30 - 55 os ns twR Write Recovery Time 0 _ 0 - ns tw Data Valid to End-of-Write 20 40 ~ ns Hz Output High-Z Time a 25 40 ns {DH Data Hold Time 0 -- 0 ns rd Write Enable to Output in High-Z vo 25 ~ 40 ns tow Output Active from End-of- Write 0 - 0 ns NOTES: 2689 tb! 106 1. Transition is measured +500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is quaranteed by device characterization but is not production tested. 2. PLCC, TQFP and STQFP packages only. For MASTER/SLAVE combination, twe = teaa + twe, since R/W = Vii must occur after (BAA. 4. tf OE is LOW during a RAW controlled write cycle, the write pulse width must be the larger of twp or (tz + tow) to alfow the /O drivers to turn off data to be placed on the bus for the required tow. if OE is HIGH during a RAV controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp. "X in part numbers indicates power rating (SA of LA). 6. Industrial temperature: for other speeds, packages and powers contact your sales office. w wmIDT7130SA/LA and IDT7140S AL & High-Speed 1K x 8 Dual-Port & te PALALELS POR LASTER LO LALO Oa? REEL LetACR LMR abAN (cL Oe Gee St Lae [21 Timing Waveform of Write Cycle No. 1, (RW Controlled Timing)"**) twe ADDRESS x tz) OE J \/ 4 on taw > CE N \ KY [ H+ tas < twp?) ere twr?) tHz"7) e RW N H bt tyyz'7) tow -_>| DATAOuUT ~< ia) _ tow >_- tb ] DATAIN N\ 2689 drw 10 Timing Waveform of Write Cycle No. 2, CE Controlled Timing)" . twe - ADDRESS *K x tae > cE fo A he 1456 he tew?) =| tw R/W \ LS $$ {DW + {DH >} DATAIN 2689 dw 11 NOTES: RIW or CE must be HIGH during ail address transitions. A write occurs during the overlap (tew or twe) of CE = Vic and RW = Vit. twr is measured from the earlier of CE or RAW going HIGH to the end of the write cycle. During this period, the VO pins are in the output state and input signals must nat be applied. If the CE LOW transition occurs simultaneously with or after the RAW LOW transition, the outputs remain in the HIGH impedance state. Timing depends on which enable signal (CE or R/W) is asserted last. This parameter is determined be device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of twp or {twz + tow) to allow the 1/0 drivers to turn off data to be placed on the bus for the required tow. if OE is HIGH during a RAW controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twe. MOO wr osIDT7130SA/LA and IDT71490SA/LA High-Speed 1K x & Dual-Port Static SRA! Miidary. dusted ang Lommercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Rang@*) 7130x20!" 7130X25 7130X35 7140X20" 7140X25 7140X35 Com't Only Com'l & Com't & Military Military Symbol Parameter Min. | Max. Min. | Max. Min. Max. Unit BUSY TIMING (For MASTER IDT 7130) IBAA BUSY Access Time from Address 20 20 20 ns tBDA BUSY Disable Time from Address 20 20 20 ns tBAC BUSY Access Time from Chip Enable 20 20 20 ns teoc BUSY Disable Time from Chip Enable 20 20 20 ns twH Write Hold After BUSY 12 15 20 ns two Write Pulse to Data Delay 40 50 60 ns tooo Write Data Valid t Read Data Delay x 35 35 ns taps Arbitration Priority Setup Time 5 5 5 ns tap0 BUSY Disable to Valid Data 25 35 35 ns BUSY INPUT TIMING (For SLAVE IDT 7140) we Write to BUSY Input Q 0 0 ns tw Write Hold After BUSY 12 15 20 ns twoo Write Pulse to Data Delay) 40 50 60 ns tooo Write Data Valid to Read Data Delay) 30 35 5 ns 2689 tol a TA3OX55 7130X 100 7140X55 7140X100 Com't, ind Com't, Ind & Mititary & Military Symbol Parameter Min. Max. Min. Max. Unit BUSY TIMING (For MASTER IDT 7130) BAA BUSY Access Time from Address 30 50 ns 1BDA BUSY Disable Time from Address 30 50 ns tBAC BUSY Access Time from Chip Enable 30 50 ns tpoc BUSY Disable Time from Chip Enable 30 50 ns tH Write Hold After BUSY 20 20 ns twoo Write Pulse to Data Delay! 80 120 ns bop Write Data Valid to Read Data Delay 55 : 100 ns taps Arbitration Priority Setup Time! 5 5 ns tBoo BUSY Disable to Valid Data 55 65 ns BUSY INPUT TIMING (For SLAVE IDT 7140} twe Write to BUSY Input 0 i) ns twH Write Hold After BUSY") 20 20 ns two Write Pulse to Data Delay . 80 120 ns p00 Write Data Valid to Read Data Delay 55 100 ns 2689 tbi 1b NOTES: 1. PLCC, TOFP and STOQFP packages oniy. 2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to Timing Waveform of Write with Port -to-Port Read and BUSY. 3. To ensure that the earlier of the two ports wins. 4. teop is a calculated parameter and is the greater of 0, two - fwr (actual) of DD tow (actual). 5. To ensure that a write cycle is inhibited on port B during contention on port A. 6. To ensure that a write cycle is completed on port 'B' after contention on port A. 7. "Xin part numbers indicates power rating (S or L). 8. industrial temperature: for other speeds, packages and powers contact your sales office.IDT7130S4/LA and IDT7140SA/LA High-Speed 1K x 8 Qual-Port Slatic SHAM Timing Waveform of Write with Port-to-Port Read andBUSY*4) Miitaly. industial and Cominercial jemperature Ranges + twec > ADDR x MATCH xK ~t twP mal RW'a" x Sr _ tow ~* tDH DATAN'A a < VALID ee taps! ADDR'S ~ MATCH } IBAA tBDA> tBop > sm ee, twDD = + topp > 2689 drw 12 NOTES: 1. To ensure that the earlier of the two ports wins. ts00 is ignored for slave (1DT7140). 2. Ct=CER= Vi 3. GE = Vit for the reading port. 4. All timing is the same for the left and right ports. Port A may be either the left or right port. Port B" is opposite from port "A", Timing Waveform of Write withBUSY) twp _ <i ~il RWa: \ X K twB BUSY's" x >| twa?) R/W'8" \ \ \ \ 2) NOTES: 1. two must be met for both BUSY Input (IDT7148, slave} or Output (IDT7130 master). 2. BUSY is asserted on port "B blocking RV's, until BUSYs" goes HIGH. 3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B is oppsite from port A. 2689 drw 13IDT?130SA/LA and IDT7140SA/L A High-Speed 1K x 8 Dual-Port Sta ites Cie eee taio (SES cero Tee Te me One ai iatAeear- TEE Aaer ticle] (S1T Me Ta Ts 3) Timing Waveform of BUSY Arbitration Controlled byCE Timing ADDR ADDRESSES MATCH \ AND 'B' X SM xX CEB ~ /| taps | CEx y BUSY's { L 2689 drw 14 Timing Waveform byBUSY Arbitration Controlled by Address Match Timing tac OR two ADDRw ADDRESSES MATCH K _ADDRESSESDONOTMATCH OX 2 taps ADDR xX tBAA i tBDA BUSY's' 2689 drw 15 NOTES: 1, All timing is the same for left and right ports. Port A may be either left or right port. Port B is the opposite from port A. 2. if taps is not satisified, the BUSY will be asserted on one side or the other, but there is no quarantee on which side BUSY will be asserted (7130 only). AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Rang@*) 7430X20 7430X25 7130X35 7440X20") 7140X25 7140X35 Com't Only Com'l & Com't & Military Military Symbol Parameter Min. | Max. Min. [ Max Min. Max. Unit INTERRUPT TIMING tas Address Setup Time 0 _ 0 = 0 ~ ns twR White Recovery Time 0 - 0 0 - ns ONS Interrupt Set Time 20 _ 25 25 ns twR Interrupt Reset Time ~ 20 - 25 ~ 25 ns 2689 tbl 12a NOTES: 1. PLCC, TQFP and STOFP package only. 2. 'X in part numbers indicates power rating (SA or LA). 3. Industrial temperature: for other speeds, packages and powers contact your sales office.IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SHAW IRIS Lm MURR LURES AE LS ORS EATER CLARE: LEER Oa Leda aa ean (23 AC Electrical characteristics Over the Operating Temperature and Supply Voltage Rang@?) 7130X55 7130X100 7140X55 7140X100 Com'l, Ind Com'l, Ind & Military & Military Symbol Parameter Min. | Max. Min. Max. Unit INTERRUPT TIMING fas Address Setup Time 0 0 vo ns twR Write Recovery Time 0 0 oo ns tNS Interrupt Set Time -- 45 a 60 ns {INR Interrupt Reset Time _ 45 = 60 ns 2689 tb! 12b NOTES: 1. 'X in part numbers indicates power rating (SA or LA). 2. Industrial temperature: for other speeds, packages and powers contact your sales office. Timing Waveform of Interrupt Modd" INT Set: t* two ADDR INTERRUPT ADDRESS XK X tas) twa ee tins?) INT Clear: 2689 drw 16 tRC ~ appre XX XX OOOOOOOFK p| Oe K\AANRAAADDDRNAAS NOTES:. INTERRUPT CLEAR ADDRESS - tas (3) N / tiINR oo 2689 diw 17 1. All timing is the same for left and right ports. Port A may be either left or right port. Port "B is the opposite from port A. 2. See Interrupt Truth Table Il. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-assented first.PRAT ieee ORME abot ess High-Speed 1K x & Ouai-Port Stati Wibaary, industiai ana Commercial leniperature Ranges Truth Tables Truth Table | Non-Contention Read/Write Controf) Inputs RW CE OE Do? Function X H X Z Port Disabled and in Power-Down Mode, Isa or IsB4 X H X z CER = CEL = Vin, Power-Down Mode, Isat or Ise3 L L X DATAin _| Data on Port Written into Memory) H L L DATAour | Data in Memory Output on Port H L H Z High Impedance Outputs NOTES: meets 1. AOL A10L + AOR - A10R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see twoo and topo timing. 4. 'H = Vin, L' = Vit, 'X' = DONT CARE, 'Z = HIGH IMPEDANCE Truth Table Il Interrupt Flag'*) Left Port Right Port RW CE OEL AgL-Aot INTL RiWe CEr OER Agr-Aor INTR Function L L x OFF x x x x X L@ | Set Right INTr Flag x x x x x x L L 3FF HO Reset Right INTR Flag Xx x x Xx LS L L x 3FE xX Set Left INTL Flag x L L 3FE H?) x x x xX X Reset Left INTL Flag NOTES: agers 1. Assumes BUSYt = BUSYR = Vin 2, if BUSYL = Vi, then No Change. 3. IBUSYR = Vit, then No Change. 4. 'H'= HIGH, L' = LOW,' X' = DON'T CARE Truth Table lll AddressBUSY Arbitration Inputs Outputs Aot-Ast CE. | CEr Aor-AgR BUSY. | BUSYa" Function x X NO MATCH H H Normal H x MATCH H H Normai X H MATCH H H Normal L L MATCH (2) (2) Write inhibit?) NOTES: ee 1. Pins BUSY: and BUSY are both outputs for 1DT7130 (master). Both are inputs for 1DT7140 (slave). BUSYx outputs on the 1DT7130 are open drain, not push-pull outputs. On slaves the BUSY input internally inhibits writes. 2. L'ifthe inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H if the inputs to the opposite port became stable after the address and enable inputs of this port. if taps is not met, either BUSY or BUSYR = LOW will result. BUSY: and BUSYr outputs can not be LOW simuitaneously. 3, Writes to the left port are internally ignored when BUSY outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual fogic level on the pin.IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x & Dual-Port Static SRAN Functional Description The IDT7130/1DT7140 provides two ports with separate control, address and (/O pins that permit independent access for reads or writes to any location in memory. The IDT7130/IDT7140 has an automatic power down feature controlled by CE. The CE controls on- chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = Vin). When a port is enabled, access to the entire memory array is permitted. Interrupts ifthe user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 3FE (HEX), where a write is defined as the CER = R/WR = ViL per Truth Table II. The left port clears the interrupt by access address location 3FE access when CEL = OEL = Vi, RWW is a "don't care. Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 3FF. The message (8 bits) at 3FE or 3FF is user-defined, since it is an addressable SRAM location. Ifthe interrupt function is not used, address locations 3FE and 3FF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table Il for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAMis Busy. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applica- tions. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flagthe event of an illegal or illogical operation. In slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT7130 RAM (Master) are open drain type outputs and require open drain resistors to operate. If these Miltary. industrial ana Commercial Temperature Ranges RAMs ate being expanded in depth, then the BUSY indication for the resulting array does not require the use of an external AND gate. Width Expansion with Busy Logic Master/Slave Arrays When expanding an RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT7130/1DT7140 RAMs the BUSY pin is an output if the part is Master (IDT7130), and the BUSY pin is an input if the part is a Slave (IDT7140) as shown in Figure 3. { ti SY |masteR = CE SLAVE cE Bl ey Dual Port Dual Port 9 2700 Bosv. _susva| [Bue susva| | L2 2700 tf . { T MASTER CE SLAVE CE Dual Port Dual Port BUSY. BUSYR US. BUSYR _ (___F 1 1 __ susva BUSYL-4+ te 2689 cirw 1& Figure 3. Busy and chip enable routing for both width and depth expansion with 1DT7130 (Master) and 1DT7140 (Slave)RAMs. If two or more master parts were used when expanding in width, asplit decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, ona Master, is based onthe chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid jong enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.IDT7130SA/LA and IDT7140SA/L A High-Speed 1K x 8 Dual-Port Static SRA: Mitvary, industrial and Commercial Temperature Ranges Ordering Information IDT XXXX A 999 AU LA Device Type Power Speed Package Process/ Temperature | Range BLANK pommercial (OC to +70C) Industrial (-40C to +85C) B Military (-55C to +125C Compliant to MIL-PRF-38535 QML 48-pin Plastic DIP (rel), 48-pin Sidebraze DIP (C48-2) 52-pin PLCC (J52-1) L48 48-pin LCC (L48-1) COU F 48-pin Ceramic Flatpack (F48-1) PF 64-pin TQFP Nee) TF 64-pin STQFP (PP64-1) 20 Commercial PLCC, TQFP and STQFP Only 25 Commercial & Military . 35 Commercial & Military Speed in nanoseconds 55 Commercial, industrial & Military 100 Commercial, industrial & Military i LA Low Power i SA Standard Power | 7130 8K {} Kx SB MASTER Dual-Port RAM 17140 8K (1K x 8-Bit) SLAVE Dual-Port RAM 2689 drw 19 NOTES. 1. Industrial temperature range is available on selected PLCC packages in standard temperature. For other speeds, packages and powers contact your sales office. Datasheet Document History 3/15/99: initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations CORPORATE HEADQUARTERS for SALES: for Tech Support: a> iDT 2975 Stender Way 800-345-7015 or 408-727-5166 | 831-754-4613 - Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com Www. idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. mod