Automotive Power
Data Sheet
Rev. 1.1, 2015-09-25
TLE75004-ELD
SPI Driver for Enhanced Relay Control
SPIDER+ 12V
Data Sheet 2 Rev. 1.1, 2015-09-25
TLE75004-ELD
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Block Diagram and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.1 PCB set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.2 Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 Input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 IDLE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 Electrical Characteristics Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.3 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.4 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.5 Limp Home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.6 Definition of Power Supply modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.1 Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.2 Low Operating Power on VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3 Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1 Output ON-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.1 Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.2 Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.3 Maximum Load Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 Switching Channels in parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3 Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3 Over Temperature and Over Load Protection in Limp Home mode . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.4 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.5 Over Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.6 Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9 Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1 Over Load and Over Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2 Output Status Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table of Contents
TLE75004-ELD
Table of Contents
Data Sheet 3 Rev. 1.1, 2015-09-25
9.3 Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.5 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.6 SPI Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.6.1 Standard Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.6.2 Register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.6.3 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.6.4 SPI command quick list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.1 Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TLE75004-ELD
List of Figures
Data Sheet 4 Rev. 1.1, 2015-09-25
Figure 1 Block Diagram of TLE75004-ELD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2 Voltage and Current definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3 Pin Configuration TLE75004-ELD in PG-SSOP-14-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4 2s2p PCB Cross Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5 PC Board for Thermal Simulation with 600 mm² Cooling Area . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6 PC Board for Thermal Simulation with 2s2p Cooling Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7 Typical Thermal Impedance. PCB setup according Chapter 4.3.1 . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8 Typical Thermal Resistance. PCB setup 1s0p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9 Input Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10 TLE75004-ELD Internal Power Supply concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11 “Cranking Operative Range” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12 Operation Mode state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13 Transition Time diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14 VS Undervoltage Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15 Switching a Resistive Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16 Output Clamp concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17 Over Load current thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 18 Latch OFF at Over Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19 Restart timer in Limp Home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 20 Output Status Monitor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21 Output Status Monitor - concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 22 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23 Combinatorial Logic for TER bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 24 Daisy Chain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 25 Data Transfer in Daisy Chain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 26 Timing Diagram SPI Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 27 Relationship between SI and SO during SPI communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 28 Register content sent back to µC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 29 TLE75004-ELD response after a error in transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 30 TLE75004-ELD response after coming out of Power-On reset at VDD . . . . . . . . . . . . . . . . . . . . . . 52
Figure 31 TLE75004-ELD response after a command syntax error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 32 TLE75004-ELD Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 33 PG-SSOP-14-5 Package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 34 TLE75004-ELD Package pads and stencil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
List of Figures
TLE75004-ELD
List of Tables
Data Sheet 5 Rev. 1.1, 2015-09-25
Table 1 Product Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3 Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5 Electrical Characteristics: Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6 Device capability as function of VS and VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7 Device function in relation to operation modes, VS and VDD voltages . . . . . . . . . . . . . . . . . . . . . . 25
Table 8 Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9 Electrical Characteristics: Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10 Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 11 Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 12 Electrical Characteristics Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 13 SPI Command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 14 Standard Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 15 Register structure - all registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 16 Register addressing space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 17 Addressable registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 18 SPI command quick list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 19 Suggested Component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
List of Tables
PG-SSOP-14-5
Package Marking
PG-SSOP-14-5 TLE75004ELD
Data Sheet 6 Rev. 1.1, 2015-09-25
SPI Driver for Enhanced Relay Control TLE75004-ELD
1Overview
Features
• 16-bit serial peripheral interface for control and diagnosis
• Daisy Chain capability SPI also compatible with 8-bit SPI devices
• 2 CMOS compatible parallel input pins with Input Mapping
functionality
• Cranking capability down to VS = 3.0 V (supports LV124)
• Digital supply voltage range compatible with 3.3 V and 5 V
microcontrollers
• Very low quiescent current (with usage of IDLE pin)
• Limp Home mode (with usage of IDLE and IN pins)
• Green Product (RoHS compliant)
• AEC Qualified
Description
The TLE75004-ELD is a four channel low-side power switch in PG-SSOP-14-5 package providing embedded
protective functions. It is specially designed to control relays and LEDs in automotive and industrial applications.
A serial peripheral interface (SPI) is utilized for control and diagnosis of the loads as well as of the device. For
direct control and PWM there are two input pins available connected to two outputs by default. Additional or
different outputs can be controlled by the same input pins (programmable via SPI).
Table 1 Product Summary
Parameter Symbol Values
Analog supply voltage VS3.0 V … 28 V
Digital supply voltage VDD 3.0 V … 5.5 V
Minimum overvoltage protection VS(AZ) 42 V (see Chapter 8.5 for details)
Maximum on-state resistance at TJ = 150 °C RDS(ON) 2.2
Nominal load current (TA = 85 °C, all channels) IL(NOM) 470 mA
Maximum Energy dissipation - repetitive EAR 10 mJ @ IL(EAR) = 220 mA
Minimum Drain to Source clamping voltage VDS(CL) 42 V
Maximum overload switch OFF threshold IL(OVL0) 2.3 A
Maximum total quiescent current at TJ 85 °C ISLEEP 5µA
Maximum SPI clock frequency fSCLK 5MHz
TLE75004-ELD
Overview
Data Sheet 7 Rev. 1.1, 2015-09-25
Applications
• Low-side switches for 12 V in automotive or industrial applications such as lighting, heating, motor driving,
energy and power distribution
• Especially designed for driving relays, LEDs and motors.
Protective Functions
• Reverse battery protection on VS without external components
• Short circuit to ground and battery protection
• Stable behavior at under voltage conditions (“Lower Supply Voltage Range for Extended Operation”)
• Over Current latch OFF
• Thermal shutdown latch OFF
• Overvoltage protection
• Loss of ground protection
• Loss of battery protection
• Electrostatic discharge (ESD) protection
Diagnostic Features
• Latched diagnostic information via SPI register
• Over Load detection at ON state
• Open Load detection at OFF state using Output Status Monitor function
• Output Status Monitor
• Input Status Monitor
Application Specific Functions
• Fail-safe activation via Input pins in Limp-Home Mode
• SPI with Daisy Chain capability
• Safe operation at low battery voltage (cranking)
Detailed Description
The TLE75004-ELD is a four channel low-side switch providing embedded protective functions. The output stages
incorporate four low-side switches (typical RDS(ON) at TJ = 25°C is 1 ).
The 16-bit serial peripheral interface (SPI) is utilized to control and diagnose the device and the loads. The SPI
interface provides daisy chain capability in order to assemble multiple devices (also devices with 8 bit SPI) in one
SPI chain by using the same number of microcontroller pins.
This device is designed for low supply voltage operation, therefore being able to keep its state at low battery
voltage (VS 3.0 V). The SPI functionality, including the possibility to program the device, is available only when
the digital power supply is present (see Chapter 6 for more details).
The TLE75004-ELD is equipped with two input pins that are connected to two outputs, making them controllable
even when the digital supply voltage is not available. With the Input Mapping functionality it is possible to connect
the input pins to different outputs, or assign more outputs to the same input pin. In this case more channels can
be controlled with one signal applied to one input pin.
TLE75004-ELD
Overview
Data Sheet 8 Rev. 1.1, 2015-09-25
In Limp Home mode (Fail-Safe mode) the input pins are directly routed to channels 2 and 3. When IDLE pin is
“low”, it is possible to activate the two channels using the input pins independently from the presence of the digital
supply voltage.
The device provides diagnosis of the load via Open Load at OFF state (with DIAG_OSM.OUTn bits) and short
circuit detection. For Open Load at OFF state detection, a internal current source IOL can be activated via SPI.
Each output stage is protected against short circuit. In case of Overload, the affected channel switches OFF when
the Overload Detection Current IL(OVLn) is reached and can be reactivated via SPI. In Limp Home mode operation,
the channels connected to an input pin set to “high” restart automatically after Output Restart time tRETRY(LH) is
elapsed. Temperature sensors are available for each channel to protect the device against Over Temperature.
The power transistors are built by N-channel power MOSFET . The inputs are ground referenced TTL compatible.
The device is monolithically integrated in Smart Power Technology.
TLE75004-ELD
Block Diagram and Terms
Data Sheet 9 Rev. 1.1, 2015-09-25
2 Block Diagram and Terms
2.1 Block Diagram
Figure 1 Block Diagram of TLE75004-ELD
BlockDiagram _4LS.emf
control,
diagnostic
and
protective
functions
Limp Home
IN1
IDLE
IN0
power supply
OUT1_LS
OUT2_LS
CSN
SI
SCLK
SO
diagnosis
register
input register
SPI
Power mode
control
OUT0_LS
OUT3_LS
GND
Output Status
Monitor
temperature
sensor
Over Load
detection
low-side
gate control
VS
VDD
TLE75004-ELD
Block Diagram and Terms
Data Sheet 10 Rev. 1.1, 2015-09-25
2.2 Terms
Figure 2 shows all terms used in this data sheet, with associated convention for positive values.
Figure 2 Voltage and Current definition
In all tables of electrical characteristics the channel related symbols without channel numbers are valid for each
channel separately (e.g. VDS specification is valid for VDS0 ... VDS3).
Furthermore, parameters relative to output current can be indicated without specifying whether the current is going
into the Drain pin or going out of the Source pin, unless otherwise specified. For instance, nominal output current
can be indicated in the following ways: IL(NOM) IL_LS(NOM) IL_D(NOM)
All SPI registers bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.RST) with the exception of the bits in
the Diagnosis frames which are marked only with PARAMETER (e.g. UVRVS).
Terms_4LS.emf
V
IN 1
V
S
V
SO
I
VD D
I
SI
I
CSN
I
VS
VDD
IDLE
SI
CSN
VS
I
IN 1
IN1
I
SC L K
SCLK
I
IN 0
IN0
OUT0_LS
OUT2_LS
I
ID L E
OUT1_LS
I
L_D1
I
L_D0
SO
I
SO
I
L_D2
GND
I
GND
OUT3_LS
I
L_D3
V
DS0
V
SC L K
V
CSN
V
IN 0
V
ID L E
V
DD
V
SI
V
DS3
V
DS2
V
DS1
TLE75004-ELD
Pin Configuration
Data Sheet 11 Rev. 1.1, 2015-09-25
3 Pin Configuration
3.1 Pin Assignment
Figure 3 Pin Configuration TLE75004-ELD in PG-SSOP-14-5
PinOut_4LS.emf
(top view)
CSN VDD
SCLK
SI
SO
GND
OUT0_LS
OUT2_LS
IN0
IN1
IDLE
VS
OUT1_LS
OUT3_LS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
15
SUB
exposed pad (bottom)
TLE75004-ELD
Pin Configuration
Data Sheet 12 Rev. 1.1, 2015-09-25
3.2 Pin Definitions and Functions
Pin Symbol I/O Function
Power Supply Pins
10 VS – Analog supply VS
Positive supply voltage for power switches gate control (incl. protections)
14 VDD – Digital supply VDD
Supply voltage for SPI with support function to VS
5GND–Ground
Ground connection
SPI Pins
1CSNIChip Select
“low” active, integrated pull-up to VDD
2SCLKISerial Clock
“high” active, integrated pull-down to ground
3SIISerial Input
“high” active, integrated pull-down to ground
4SOOSerial Output
“Z” (tri-state) when CSN is “high”
Input and Stand-by Pins
11 IDLE I Idle mode
power mode control, “high” active, integrated pull-down to ground
13 IN0 I Input pin 0
connected to channel 2 by default and in Limp Home mode, “high” active,
integrated pull-down to ground
12 IN1 I Input pin 1
connected to channel 3 by default and Limp Home mode, “high” active,
integrated pull-down to ground
Power Ouput Pins
6 OUT0_LS O Drain of low-side power transistor (channel 0)
7 OUT2_LS O Drain of low-side power transistor (channel 2)
8 OUT3_LS O Drain of low-side power transistor (channel 3)
9 OUT1_LS O Drain of low-side power transistor (channel 1)
Cooling Tab
15 GND – Exposed pad
It is recommended to connect it to PCB ground for cooling and EMC - not
usable as electrical GND pin. Electrical ground must be provided by pin 5.
TLE75004-ELD
General Product Characteristics
Data Sheet 13 Rev. 1.1, 2015-09-25
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings 1)
TJ = -40 °C to +150 °C
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
Supply Voltages
Analog Supply voltage VS-0.3 – 28 V – P_4.1.1
Digital Supply voltage VDD -0.3 – 5.5 V – P_4.1.2
Supply voltage for load dump
protection
VS(LD) ––42V
2) P_4.1.3
Supply voltage for short circuit
protection (single pulse)
VS(SC) 0–28V– P_4.1.4
Reverse polarity voltage -VS(REV) ––16V
3)
TJ(0) = 25 °C
t 2 min
See Chapter 11 for
general setup.
RL=70 on all
channels
P_4.1.5
Current through VS pin IVS -10 – 10 mA t 2 min P_4.1.7
Current through VDD pin IVDD -50 – 10 mA t 2 min P_4.1.8
Power Stages
Load current |IL|––IL(OVL0) A single channel P_4.1.9
Voltage at power transistor VDS -0.3 – 42 V – P_4.1.10
Maximum energy dissipation
single pulse
EAS ––50mJ
4)
TJ(0) = 25 °C
IL(0) = 2*IL(EAR)
P_4.1.13
Maximum energy dissipation
single pulse
EAS ––25mJ
4)
TJ(0) = 150 °C
IL(0) = 400 mA
P_4.1.14
Maximum energy dissipation
repetitive pulses - IL(EAR)
EAR ––10mJ
4)
TJ(0) = 85 °C
IL(0) = IL(EAR)
2*106 cycles
P_4.1.16
IDLE pin
Voltage at IDLE pin VIDLE -0.3 5.5 V – P_4.1.23
Current through IDLE pin IIDLE -0.75 0.75 mA – P_4.1.25
Current through IDLE pin IIDLE -10.0 2.0 mA t 2min. P_4.1.26
TLE75004-ELD
General Product Characteristics
Data Sheet 14 Rev. 1.1, 2015-09-25
Input Pins
Voltage at input pins VIN -0.3 5.5 V – P_4.1.28
Current through input pins IIN -0.75 0.75 mA – P_4.1.30
Current through input pins IIN -10.0 2.0 mA t 2min. P_4.1.31
SPI Pins
Voltage at chip select pin VCSN -0.3 5.5 V – P_4.1.33
Current through chip select pin ICSN -0.75 0.75 mA – P_4.1.34
Current through chip select pin ICSN -10.0 2.0 mA t 2min. P_4.1.35
Voltage at serial clock pin VSCLK -0.3 5.5 V P_4.1.37
Current through serial clock pin ISCLK -0.75 0.75 mA – P_4.1.38
Current through serial clock pin ISCLK -10.0 2.0 mA t 2min. P_4.1.39
Voltage at serial input pin VSI -0.3 5.5 V P_4.1.41
Current through serial input pin ISI -0.75 0.75 mA – P_4.1.42
Current through serial input pin ISI -10.0 2.0 mA t 2min. P_4.1.43
Voltage at serial output pin SO VSO -0.3 VDD+0.3 V P_4.1.58
Current through serial output pin
SO
ISO -0.75 0.75 mA P_4.1.45
Current through serial output pin
SO
ISO -2.0 10.0 mA t 2min. P_4.1.46
Temperatures
Junction Temperature TJ-40 – 150 °C – P_4.1.48
Storage Temperature Tstg -55 – 150 °C – P_4.1.49
ESD Susceptibility
ESD Susceptibility HBM
OUT pins vs. VS or GND
VESD -4 – 4 kV 5)
HBM
P_4.1.50
ESD Susceptibility HBM
other pins
VESD -2 – 2 kV 5)
HBM
P_4.1.51
ESD Susceptibility CDM
Pin 1, 7, 8, 14 (corner pins)
VESD -750 – 750 V 6)
CDM
P_4.1.53
ESD Susceptibility CDM VESD -500 – 500 V 6)
CDM
P_4.1.54
1) Not subject to production test, specified by design.
2) For a duration of ton = 400 ms; ton/toff = 10%; limited to 100 pulses
3) Device is mounted on a FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; the Product
(Chip+Package) was simulated on a 76.2 *114.3 *1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4) Pulse shape represents inductive switch off: IL(t) = IL(0) x (1 - t / tpulse); 0 < t < tpulse
5) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5k , 100 pF)
6) ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1
Table 2 Absolute Maximum Ratings (cont’d)1)
TJ = -40 °C to +150 °C
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
TLE75004-ELD
General Product Characteristics
Data Sheet 15 Rev. 1.1, 2015-09-25
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
4.2 Functional Range
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
Table 3 Functional range
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
Supply Voltage Range for
Normal Operation
VS(NOR) 7–18V– P_4.2.1
Upper Supply Voltage Range
for Extended Operation
VS(EXT,UP) 18 – 28 V Parameter deviation
possible
P_4.2.2
Lower Supply Voltage Range
for Extended Operation
VS(EXT,LOW) 3 – 7 V Parameter deviation
possible
P_4.2.3
Junction Temperature TJ-40 – 150 °C – P_4.2.4
Logic supply voltage VDD 3–5.5V– P_4.2.5
TLE75004-ELD
General Product Characteristics
Data Sheet 16 Rev. 1.1, 2015-09-25
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
4.3.1 PCB set up
Figure 4 2s2p PCB Cross Section
Table 4 Thermal Resistance
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Junction to Soldering Point RthJSP –57K/W
1)
measured to exposed
pad (pin 15)
1) not subject to production test, specified by design
P_4.3.2
Junction to Ambient RthJA –32–K/W
2)
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product
(Chip+Package) was simulated on a 76.2 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
P_4.3.6
1.5mm
70µm
35µm
0.3mm Zth_PCB_2s2p.emf
TLE75004-ELD
General Product Characteristics
Data Sheet 17 Rev. 1.1, 2015-09-25
Figure 5 PC Board for Thermal Simulation with 600 mm² Cooling Area
Figure 6 PC Board for Thermal Simulation with 2s2p Cooling Area
TLE75004-ELD
General Product Characteristics
Data Sheet 18 Rev. 1.1, 2015-09-25
4.3.2 Thermal Impedance
Figure 7 Typical Thermal Impedance. PCB setup according Chapter 4.3.1
Figure 8 Typical Thermal Resistance. PCB setup 1s0p
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 100 1000
ZthJA (K/W)
Tambient = 105°C
Time (s)
4 Channels Low Side
2s2p
1s0p - 600 mm²
1s0p - 300 mm²
1s0p - footprint
50
60
70
80
90
100
110
0 100 200 300 400 500 600
RthJA (K/W)
Area (mm²)
4 Channels Low Side
1s0p - Tambient = 105°C
TLE75004-ELD
Control Pins
Data Sheet 19 Rev. 1.1, 2015-09-25
5 Control Pins
The device has three pins (IN0, IN1 and IDLE) to control directly the device without using SPI.
5.1 Input pins
TLE75004-ELD has two input pins available. Each input pin is connected by default to one channel (IN0 to channel
2, IN1 to channel 3). Input Mapping Registers MAPIN0 and MAPIN1 can be programmed to connect additional or
different channels to each input pin, as shown in Figure 9. The signals driving the channels are an OR
combination between OUT register status, IN0 and IN1 (according to Input Mapping registers status).
Figure 9 Input Mapping
The logic level of the input pins can be monitored via the Input Status Monitor Register (INST). The Input Status
Monitor is operative also when TLE75004-ELD is in Limp Home mode. If one of the Input pins is set to “high” and
the IDLE pin is set to “low”, the device switches into Limp Home mode and activates the channel mapped by
default to the input pins. See Chapter 6.1.5 for further details.
5.2 IDLE pin
The IDLE pin is used to bring the device into Sleep mode operation when is set to “low” and all input pins are set
to “low”.When IDLE pin is set to “low” while one of the input pins is set to “high” the device enters Limp Home mode.
To ensure a proper mode transition, IDLE pin must be set for at least tIDLE2SLEEP (P_6.3.54, transition from “high”
to “low”) or tSLEEP2IDLE (P_6.3.53, transition from “low” to “high”).
Setting the IDLE pin to “low” has the following consequences:
• All registers in the SPI are reset to default values
•VDD and VS Undervoltage detection circuits are disabled to decrease current consumption (if both inputs are
set to “low”)
• No SPI communication is allowed (SO pin remains in high impedance state also when CSN pin is set to “low”)
if both input pins are set to “low”
InputMapping_4ch.emf
Channel 3
Channel 2
Channel 1
Channel 0
OR
&
IN1
I
IN 1
IN0
I
IN 0
&
OR
4
4
4
4
4
4
4
MAPIN1
MAPIN0
OUT
Limp Home mode
(default )
Limp Home mode
(default )
TLE75004-ELD
Control Pins
Data Sheet 20 Rev. 1.1, 2015-09-25
5.3 Electrical Characteristics Control Pins
Table 5 Electrical Characteristics: Control Pins
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
IDLE pin
L-input level VIDLE(L) 00.8V– P_5.3.1
H-input level VIDLE(H) 2.0 5.5 V – P_5.3.2
L-input current IIDLE(L) 51220AVIDLE = 0.8 V P_5.3.3
H-input current IIDLE(H) 14 28 45 AVIDLE = 2.0 V P_5.3.4
Input Pins
L-input level VIN(L) 00.8V– P_5.3.5
H-input level VIN(H) 2.0 5.5 V – P_5.3.6
L-input current IIN(L) 51220AVIN = 0.8 V P_5.3.7
H-input current IIN(H) 14 28 45 AVIN = 2.0 V P_5.3.8
TLE75004-ELD
Power Supply
Data Sheet 21 Rev. 1.1, 2015-09-25
6 Power Supply
The TLE75004-ELD is supplied by two supply voltages:
•VS (analog supply voltage used also for the logic)
•VDD (digital supply voltage)
The VS supply line is connected to a battery feed and used, in combination with VDD supply, for the driving circuitry
of the power stages. In situations where VS voltage drops below VDD voltage (for instance during cranking events
down to 3.0 V), an increased current consumption may be observed at VDD pin.
VS and VDD supply voltages have an undervoltage detection circuit, which prevents the activation of the associated
function in case the measured voltage is below the undervoltage threshold. More in detail:
• An undervoltage on both VS and VDD supply voltages prevents the activation of the power stages and any SPI
communication (the SPI registers are reset)
• An undervoltage on VDD supply prevents any SPI communication. SPI read/write registers are reset to default
values.
• An undervoltage on VS supply forces the TLE75004-ELD to drain all needed current for the low-side switches
and for the logic from VDD supply.
Figure 10 shows a basic concept drawing of the interaction between supply pins VS and VDD, the output stage
drivers and SO supply line.
Figure 10 TLE75004-ELD Internal Power Supply concept
When 3.0 V VS VDD - VSDIFF TLE75004-ELD operates in “Cranking Operative Range” (COR). In this condition
the current consumption from VDD pin increases while it decreases from VS pin where the total current
consumption remains within the specified limits. Figure 11 shows the voltage levels at VS pin where the device
goes in and out of COR. During the transition to and from COR operative region, IVS and IVDD change between
values defined for normal operation and for COR operation. The sum of both current remains within limits specified
in “Overall current consumption” section (see Table 8).
VS
VDD
IVS
IVDD
VREG
SPI
SO
UVR
VDD
UVR
VS
GD
GND
LS
SupplyConcept_xLS.emf
TLE75004-ELD
Power Supply
Data Sheet 22 Rev. 1.1, 2015-09-25
Figure 11 “Cranking Operative Range”
Furthermore, when VS(UV) ≤ VS VS(OP) it may be not possible to switch ON a channel that was previously OFF.
All channels that are already ON keep their state unless they are switched OFF via SPI or via INn pins. An
overview of channel behavior according to different VS and VDD supply voltages is shown in Table 6 (the table is
valid after a successful power-up, see Chapter 6.1.1 for more details).
Supply transitionSupply transition
SupplyConcept_COR.emf
t
VS
VDD + VSD IFF
VDD -V
SD IFF
3.0 V
(no )COR yes (no)
t
IVS
VDD
IVDD
t
TLE75004-ELD
Power Supply
Data Sheet 23 Rev. 1.1, 2015-09-25
Table 6 Device capability as function of VS and VDD
VDD VDD(UV)
(VDD(UV) = P_6.3.25)
VDD = VDD(LOP)
(VDD(LOP) = P_6.3.24)
VDD > VDD(LOP)
VS 3.0 V
3.0 V = VS(UV),max
(P_6.3.1)
channels cannot be
controlled
channels can be switched
ON and OFF (SPI control)
(RDS(ON) deviations possible)
channels can be switched
ON and OFF (SPI control)
(RDS(ON) deviations possible)
SPI registers reset SPI registers available SPI registers available
SPI communication not
available (fSCLK = 0 MHz)
SPI communication possible
(fSCLK = 1 MHz) (P_10.4.34)
SPI communication possible
(fSCLK = 5 MHz) (P_10.4.22)
Limp Home mode not
available
Limp Home mode available
(RDS(ON) deviations possible)
Limp Home mode available
(RDS(ON) deviations possible)
3.0 V < VS VS(OP)
(VS(OP) = P_6.3.2)
channels cannot be
controlled by SPI
channels can be switched
ON and OFF (SPI control)1)
(RDS(ON) deviations possible)
channels can be switched
ON and OFF (SPI control)1)
(RDS(ON) deviations possible)
SPI registers reset SPI registers available SPI registers available
SPI communication not
available (fSCLK = 0 MHz)
SPI communication possible
(fSCLK = 1 MHz) (P_10.4.34)
SPI communication possible
(fSCLK = 5 MHz) (P_10.4.22)
Limp Home mode available1)
(RDS(ON) deviations possible)
1) undervoltage condition on VS must be considered - see Chapter 6.2.1 for more details
Limp Home mode available1)
(RDS(ON) deviations possible)
Limp Home mode available
(RDS(ON) deviations possible)
VS > VS(OP) channels cannot be
controlled by SPI
channels can be switched
ON and OFF
(small RDS(ON) dev. possible
when VS = VS(EXT,LOW))
channels can be switched
ON and OFF
(small RDS(ON) dev. possible
when VS = VS(EXT,LOW))
SPI registers reset SPI registers available SPI registers available
SPI communication not
available (fSCLK = 0 MHz)
SPI communication possible
(fSCLK = 5 MHz) (P_10.4.22)
SPI communication possible
(fSCLK = 5 MHz) (P_10.4.22)
Limp Home mode available
(RDS(ON) dev. possible when
VS = VS(EXT,LOW))
Limp Home mode available
(RDS(ON) dev. possible when
VS = VS(EXT,LOW))
Limp Home mode available
(RDS(ON) dev. possible when
VS = VS(EXT,LOW))
TLE75004-ELD
Power Supply
Data Sheet 24 Rev. 1.1, 2015-09-25
6.1 Operation Modes
TLE75004-ELD has the following operation modes:
• Sleep mode
• Idle mode
• Active mode
• Limp Home mode
The transition between operation modes is determined according to following levels and states:
• logic level at IDLE pin
• logic level at INn pins
•OUT.OUTn bits state
•HWCR.ACT bit state
The state diagram including the possible transitions is shown in Figure 12. The behaviour of TLE75004-ELD as
well as some parameters may change in dependence from the operation mode of the device. Furthermore, due
to the undervoltage detection circuitry which monitors VS and VDD supply voltages, some changes within the same
operation mode can be seen accordingly.
The operation mode of the TLE75004-ELD can be observed by:
• status of output channels
• status of SPI registers
• current consumption at VDD pin (IVDD)
• current consumption at VS pin (IVS)
The default operation mode to switch ON the loads is Active mode. If the device is not in Active mode and a request
to switch ON one or more outputs comes (via SPI or via Input pins), it will switch into Active or Limp Home mode,
according to IDLE pin status. Due to the time needed for such transitions, output turn-on time tON will be extended
due to the mode transition latency.
Figure 12 Operation Mode state diagram
OpModes.emf
Sleep
Idle
IDLE = „high“
IDLE = „low“
Active
INn = „high“
& IDLE = „low“
IDLE = „high“
Limp Home
HWCR.ACT = 1
or OUT.OUTn = 1
or INn = „high“
HWCR.ACT = 0
& OUT.OUTn = 0
& INn = „low“
IDLE = „low“
& INn = „high“
INn = „low“
init
IDLE = „low“
& INn = „low“
INn = „low“
& V
DD
< V
DD(UV)
TLE75004-ELD
Power Supply
Data Sheet 25 Rev. 1.1, 2015-09-25
Table 7 shows the correlation between device operation modes, VS and VDD supply voltages, and state of the most
important functions (channels operativity, SPI communication and SPI registers).
6.1.1 Power-up
The Power-up condition is satisfied when one of the supply voltages (VS or VDD) is applied to the device and the
INn or IDLE pins are set to “high”. If VS is above the threshold VS(OP) or if VDD is above the threshold VDD(LOP) the
internal power-on signal is set.
6.1.2 Sleep mode
When TLE75004-ELD is in Sleep mode, all outputs are OFF and the SPI registers are reset, independently from
the supply voltages. The current consumption is minimum. See parameters IVDD(SLEEP) and IVS(SLEEP), or parameter
ISLEEP for the whole device.
6.1.3 Idle mode
In Idle mode, the current consumption of the device can reach the limits given by parameters IVDD(IDLE) and IVS(IDLE),
or by parameter IIDLE for the whole device. The internal voltage regulator is working. Diagnosis functions are not
available. The output channels are switched OFF, independently from the supply voltages. When VDD is available,
the SPI registers are working and SPI communication is possible. In Idle mode the ERRn bits are not cleared for
functional safety reasons.
6.1.4 Active mode
Active mode is the normal operation mode of TLE75004-ELD when no Limp Home condition is set and it is
necessary to drive some or all loads. Voltage levels of VDD and VS influence the behavior as described at the
beginning of Chapter 6. Device current consumption is specified with IVDD(ACTIVE) and IVS(ACTIVE) (IACTIVE for the
Table 7 Device function in relation to operation modes, VS and VDD voltages
Operation
Mode
Function Undervoltage
condition on VS1)
VDD ≤ VDD(UV)
1) see Chapter 6.2.1 for more details
Undervoltage
condition on VS
VDD > VDD(UV)
VS not in
undervoltage
VDD ≤ VDD(UV)
VS not in
undervoltage
VDD >VDD(UV)
Sleep Channels not available not available not available not available
SPI comm. not available not available not available not available
SPI registers reset reset reset reset
Idle Channels not available not available not available not available
SPI comm. not available ✔not available ✔
SPI registers reset ✔reset ✔
Active Channels not available ✔✔ (IN pins only) ✔
SPI comm. not available ✔not available ✔
SPI registers reset ✔reset ✔
Limp Home Channels not available ✔ (IN pins only) ✔ (IN pins only) ✔ (IN pins only)
SPI comm. not available ✔ (read-only) not available ✔ (read-only)
SPI registers reset ✔ (read-only)2)
2) see Chapter 6.1.5 for a detailed overview
reset ✔ (read-only)2)
TLE75004-ELD
Power Supply
Data Sheet 26 Rev. 1.1, 2015-09-25
whole device). The device enters Active mode when IDLE pin is set to “high” and one of the input pins is set to
“high” or one OUT.OUTn bit is set to “1”. If HWCR.ACT is set to “0”, the device returns to Idle mode as soon as all
inputs pins are set to “low” and OUT.OUTn bits are set to “0”. If HWCR.ACT is set to “1”, the device remains in Active
mode independenly of the status of input pins and OUT.OUTn bits. An undervoltage condition on VDD supply brings
the device into Idle mode, if all input pins are set to “low”. Even if the registers MAPIN0 and MAPIN1 are both set
to “00H” but one of the input pins INn is set to “high”, the device goes into Active mode.
6.1.5 Limp Home mode
TLE75004-ELD enters Limp Home mode when IDLE pin is “low” and one of the input pins is set to “high”, switching
ON the channel connected to it. SPI communication is possible but only in read-only mode (SPI registers can be
read but cannot be written). More in detail:
•UVRVS and LOPVDD are set to “1”
•MODE bits are set to “01B” (Limp Home mode)
•TER bit is set to “1” on the first SPI command after entering Limp Home mode. Afterwards it works normally
•OLOFF bits is set to “0”
•ERRn bits work normally
•DIAG_OSM.OUTn bits can be read and work normally
• All other registers are set to their default value and cannot be programmed as long as the device is in Limp
Home mode
See Table 6 for a detailed overview of supply voltage conditions required to switch ON channels 2 and 3 during
Limp Home. All other channels are OFF.
A transmission of SPI commands during transition from Active to Limp Home mode or Limp Home to Active mode
may result in undefined SPI responses.
6.1.6 Definition of Power Supply modes transition times
The channel turn-ON time is as defined by parameter tON when TLE75004-ELD is in Active mode or in Limp Home
mode. In all other cases, it is necessary to add the transition time required to reach one of the two aforementioned
Power Supply modes (as shown in Figure 13).
TLE75004-ELD
Power Supply
Data Sheet 27 Rev. 1.1, 2015-09-25
Figure 13 Transition Time diagram
6.2 Reset condition
One of the following 3 conditions resets the SPI registers to the default value:
•VDD is not present or below the undervoltage threshold VDD(UV)
• IDLE pin is set to “low”
• a reset command (HWCR.RST set to “1”) is executed
–ERRn bits are not cleared by a reset command (for functional safety)
–UVRVS and LOPVDD bits are cleared by a reset command
In particular, all channels are switched OFF (if there are no input pin set to “high”) and the Input Mapping
configuration is reset.
6.2.1 Undervoltage on VS
Between VS(UV) and VS(OP) the undervoltage mechanism is triggered. If the device is operative and the supply
voltage drops below the undervoltage threshold VS(UV), the logic set the bit UVRVS to “1”. As soon as the supply
voltage VS is above the minimum voltage operative threshold VS(OP), the bit UVRVS is set to “0” after the first
Standard Diagnosis readout. Undervoltage condition on VS influences the status of the channels, as described in
Table 6. Figure 14 sketches the undervoltage behavior.
OpModesTimings.emf
Sleep
Idle
t
SLEEP2IDLE
Active
Limp Home
init
t
IDLE2SLEEP
t
ACTIVE2IDLE
t
IDLE2ACTIVE
t
ON
t
ACTIVE2LH
t
LH2ACTIVE
t
LH2SLEEP
t
SLEEP2LH
t
ON
Channel ON
t
ACTIVE2SLEEP
TLE75004-ELD
Power Supply
Data Sheet 28 Rev. 1.1, 2015-09-25
Figure 14 VS Undervoltage Behavior
6.2.2 Low Operating Power on VDD
When VDD supply voltage is in the range indicated by VDD(LOP), the bit LOPVDD is set to “1”. As soon as VDD >
VDD(LOP) the bit LOPVDD is set to “0” after the first Standard Diagnosis readout.
If VDD supply voltage is not present, a voltage applied to pins CSN or SO can supply the internal logic (not
recommended in normal operation due to internal design limitations).
Supply_UVRVS_LS.emf
V
S(OP)
V
S(UV)
1UVRVS 0 1
t
V
S(HYS)
t
V
S
TLE75004-ELD
Power Supply
Data Sheet 29 Rev. 1.1, 2015-09-25
6.3 Electrical Characteristics Power Supply
Table 8 Electrical Characteristics Power Supply
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 2 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
VS pin
Analog supply undervoltage
shutdown
VS(UV) 1.5 – 3.0 V OUTn = ON
from VDS 1V
to UVRVS = 1B
RL = 50
P_6.3.1
Analog supply minimum
operative voltage
VS(OP) ––4.0VOUT.OUTn = 1B
from UVRVS = 1B
to VDS 1V
RL = 50
P_6.3.2
Undervoltage shutdown
hysteresis
VS(HYS) –1–V
1) P_6.3.3
Analog supply current
consumption in Sleep mode
with loads
IVS(SLEEP) –0.13µA
1)
VIDLE floating
VINn floating
VCSN = VDD
TJ 85 °C
P_6.3.4
Analog supply current
consumption in Sleep mode
with loads
IVS(SLEEP) –0.1–µA
1)
VIDLE floating
VINn floating
VCSN = VDD
TJ 85 °C
VS = 13.5 V
P_6.3.63
Analog supply current
consumption in Sleep mode
with loads
IVS(SLEEP) –0.120µAVIDLE floating
VINn floating
VCSN = VDD
TJ = 150 °C
P_6.3.5
Analog supply current
consumption in Idle mode
with loads
IVS(IDLE) – – 2.2 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 0B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
P_6.3.6
TLE75004-ELD
Power Supply
Data Sheet 30 Rev. 1.1, 2015-09-25
Analog supply current
consumption in Idle mode
with loads (COR)
IVS(IDLE) – – 0.3 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 0B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
VS VDD - 1 V
P_6.3.7
Analog supply current
consumption in Active mode
with loads - channels OFF
IVS(ACTIVE) – – 3.2 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
P_6.3.11
Analog supply current
consumption in Active mode
with loads - channels OFF
(COR)
IVS(ACTIVE) – 0.1 0.3 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
VS VDD - 1 V
P_6.3.12
Analog supply current
consumption in Active mode
with loads - channels ON
IVS(ACTIVE) – – 3.2 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 1B
DIAG_IOL.OUTn =
0B
VCSN = VDD
P_6.3.19
Analog supply current
consumption in Active mode
with loads - channels ON
(COR)
IVS(ACTIVE) – 0.1 0.3 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 1B
DIAG_IOL.OUTn =
0B
VCSN = VDD
VS VDD - 1 V
P_6.3.20
Table 8 Electrical Characteristics Power Supply (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 2 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
TLE75004-ELD
Power Supply
Data Sheet 31 Rev. 1.1, 2015-09-25
VDD pin
Logic Supply Operating
voltage
VDD(OP) 3.0 – 5.5 V fSCLK = 5 MHz P_6.3.23
Logic Supply Lower
Operating Voltage
VDD(LOP) 3.0 – 4.5 V – P_6.3.24
Undervoltage shutdown VDD(UV) 1–3.0VVSI = 0 V
VSCLK = 0 V
VCSN = 0 V
SO from “low” to
high impedance
P_6.3.25
Logic supply current in Sleep
mode
IVDD(SLEEP) –0.12.5µA
1)
VIDLE floating
VINn floating
VCSN = VDD
TJ 85 °C
P_6.3.26
Logic supply current in Sleep
mode
IVDD(SLEEP) ––10µAVIDLE floating
VINn floating
VCSN = VDD
TJ = 150 °C
P_6.3.27
Logic supply current in Idle
mode
IVDD(IDLE) – – 0.3 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 0B
OUT.OUTn = 0B
VCSN = VDD
P_6.3.28
Logic supply current in Idle
mode (COR)
IVDD(IDLE) – – 2.2 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 0B
OUT.OUTn = 0B
VCSN = VDD
VS VDD - 1 V
P_6.3.29
Logic supply current in Active
mode - channels OFF
IVDD(ACTIVE) – – 0.3 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 0B
VCSN = VDD
P_6.3.30
Table 8 Electrical Characteristics Power Supply (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 2 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
TLE75004-ELD
Power Supply
Data Sheet 32 Rev. 1.1, 2015-09-25
Logic supply current in Active
mode - channels OFF (COR)
IVDD(ACTIVE) – – 3.2 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 0B
VCSN = VDD
VS VDD - 1 V
P_6.3.34
Logic supply current in Active
mode - channels ON
IVDD(ACTIVE) – – 0.3 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 1
VCSN = VDD
P_6.3.35
Logic supply current in Active
mode - channels ON (COR)
IVDD(ACTIVE) – – 3.2 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 1B
VCSN = VDD
VS = VDD - 1 V
P_6.3.38
Overall current consumption
Overall current consumption
in Sleep mode
IVS(SLEEP) + IVDD(SLEEP)
ISLEEP ––5µA
1)
VIDLE floating
VINn floating
VCSN = VDD
TJ 85 °C
P_6.3.40
Overall current consumption
in Sleep mode
IVS(SLEEP) + IVDD(SLEEP)
ISLEEP ––5µA
1)
VIDLE floating
VINn floating
VCSN = VDD
TJ 85 °C
VS = 13.5 V
P_6.3.64
Overall current consumption
in Sleep mode
IVS(SLEEP) + IVDD(SLEEP)
ISLEEP ––30µAVIDLE floating
VINn floating
VCSN = VDD
TJ = 150 °C
P_6.3.41
Table 8 Electrical Characteristics Power Supply (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 2 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
TLE75004-ELD
Power Supply
Data Sheet 33 Rev. 1.1, 2015-09-25
Overall current consumption
in Idle mode
IVS(IDLE) + IVDD(IDLE)
IIDLE – – 2.5 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 0B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
P_6.3.42
Overall current consumption
in Active mode - channels
OFF
IVS(ACTIVE) + IVDD(ACTIVE)
IACTIVE – – 3.5 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 0B
DIAG_IOL.OUTn =
0B
VCSN = VDD
P_6.3.46
Overall current consumption
in Active mode - channels ON
IVS(ACTIVE) + IVDD(ACTIVE)
IACTIVE – – 3.5 mA IDLE = “high”
VINn floating
fSCLK = 0 MHz
HWCR.ACT = 1B
OUT.OUTn = 1B
DIAG_IOL.OUTn =
0B
VCSN = VDD
P_6.3.51
Voltage difference between
VS and VDD supply lines
VSDIFF –200–mV
1) P_6.3.52
Timings
Sleep to Idle delay tSLEEP2IDLE – 200 400 µs 1)
from IDLE pin to
TER + INST register
= 8680H (see
Chapter 10.6.1 for
details)
P_6.3.53
Idle to Sleep delay tIDLE2SLEEP – 100 200 µs 1)
from IDLE pin to
Standard Diagnosis
= 0000H (see
Chapter 10.5 for
details)
external pull-down
SO to GND
required
P_6.3.54
Table 8 Electrical Characteristics Power Supply (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 2 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
TLE75004-ELD
Power Supply
Data Sheet 34 Rev. 1.1, 2015-09-25
Idle to Active delay tIDLE2ACTIVE – 100 200 µs 1)
from INn or CSN
pins to MODE = 10B
P_6.3.55
Active to Idle delay tACTIVE2IDLE – 100 200 µs 1)
from INn or CSN
pins to MODE = 11B
P_6.3.56
Sleep to Limp Home delay tSLEEP2LH –300
+tON
600
+tON
µs 1)
from INn pins
to VDS = 10% VS
P_6.3.57
Limp Home to Sleep delay tLH2SLEEP –200
+tOFF
400
+tOFF
µs 1)
from INn pins to
Standard Diagnosis
= 0000H (see
Chapter 10.6.1 for
details). External
pull-down SO to
GND required
P_6.3.58
Limp Home to Active delay tLH2ACTIVE –50100µs
1)
from IDLE pin to
MODE = 10B
P_6.3.59
Active to Limp Home delay tACTIVE2LH –50100µs
1)
from IDLE pin to
TER + INST register
= 8683H (IN0 = IN1
= “high”) or
8682H(IN1 = “high”,
IN0 = “low”) or
8681H (IN1 = “low”,
IN0 = “high”) (see
Chapter 10.5 for
details)
P_6.3.60
Active to Sleep delay tACTIVE2SLEEP –50100µs
1)
from IDLE pin to
Standard Diagnosis
= 0000H (see
Chapter 10.6.1 for
details). External
pull-down SO to
GND required.
P_6.3.61
1) Not subject to production test - specified by design
Table 8 Electrical Characteristics Power Supply (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C, all voltages with respect to ground, positive currents
flowing as described in Figure 2 (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
TLE75004-ELD
Power Stages
Data Sheet 35 Rev. 1.1, 2015-09-25
7 Power Stages
The TLE75004-ELD is an four channels low-side relay switch. The power stages are built by N-channel lateral
power MOSFET transistors.
7.1 Output ON-state resistance
The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature TJ.
7.1.1 Switching Resistive Loads
When switching resistive loads the following switching times and slew rates can be considered.
Figure 15 Switching a Resistive Load
7.1.2 Inductive Output Clamp
When switching off inductive loads, the voltage across the power switch rises to VDS(CL) potential, because the
inductance intends to continue driving the current. The voltage clamping is necessary to prevent device
destruction.
Figure 16 shows a concept drawing of the implementation. Nevertheless, the maximum allowed load inductance
is limited. The clamping structure protects the device in all operative modes (Sleep, Idle, Active, Limp Home).
V
DS
t
SwitchON .emf
t
ON
t
OFF
t
90% of V
S
dV/
dt
ON
70%
dV/
dt
OFF
30%
t
DELAY(ON)
t
DELAY(OFF)
INn /
OUT.OUTn
70% of V
S
30% of V
S
10% of V
S
TLE75004-ELD
Power Stages
Data Sheet 36 Rev. 1.1, 2015-09-25
Figure 16 Output Clamp concept
7.1.3 Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the TLE75004-ELD. Equation (7.1)
shows how to calculate the energy for low-side switches:
(7.1)
The maximum energy, which is converted into heat, is limited by the thermal design of the component. The EAR
value provided in Table 2 assumes that all channels can dissipate the same energy when the inductances
connected to the outputs are demagnetized at the same time.
7.2 Switching Channels in parallel
In case of appearance of a short circuit with channels in parallel, it may happen that the two channels switch OFF
asynchronously, therefore bringing an additional thermal stress to the channel that switches OFF last. In order to
avoid this condition, it is possible to parametrize in the SPI registers the parallel operation of two neighbour
channels (bits HWCR.PAR). When operating in this mode, the fastest channel to react to an Over Load or Over
Temperature condition will deactivate also the other. The inductive energy that two channels can handle once set
in parallel is lower than twice the single channel energy (see P_7.6.11). It is possible to synchronize the following
couples of channels:
• channel 0 and channel 2 HWCR.PAR (0) set to “1”
• channel 1 and channel 3 HWCR.PAR (1) set to “1”
The synchronization bits influence only how the channels react to Over Load or Over Temperature conditions.
Synchronized channels have to be switched ON and OFF individually by the micro-controller.
PowerStage_LS.emf
V
S
Low -side
Channel L,
R
L
I
L_ D
OUT
V
DS
V
DS(CL)
GND
I
L
EV
DS CL()
VSVDS CL()
–
RL
--------------------------------- 1RLI⋅L
VSVDS CL()
–
---------------------------------–
⎝⎠
⎛⎞
IL
+ln⋅L
RL
------
⋅⋅=
TLE75004-ELD
Power Stages
Data Sheet 37 Rev. 1.1, 2015-09-25
7.3 Electrical Characteristics Power Stages
Table 9 Electrical Characteristics: Power Stage
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
Output Characteristics
On-State Resistance RDS(ON) –1.0–1)
TJ = 25 °C
P_7.6.1
On-State Resistance RDS(ON) –1.82.2TJ = 150 °C
IL = IL(EAR) =
220 mA
P_7.6.2
Nominal load current
(all channels active)
IL(NOM) – 470 5002)3) mA 1)
TA = 85 °C
TJ 150 °C
P_7.6.6
Nominal load current
(all channels active)
IL(NOM) – 370 5002)3) mA 1)
TA = 105 °C
TJ 150 °C
P_7.6.7
Load current for maximum
energy dissipation - repetitive
(all channels active)
IL(EAR) –220–mA
1)
TA = 85 °C
TJ 150 °C
P_7.6.8
Maximum energy dissipation
repetitive pulses - 2*IL(EAR)
(two channels in parallel)
EAR ––15mJ
1)
TJ(0) = 85 °C
IL(0) = 2*IL(EAR)
2*106 cycles
HWCR.PAR = “1” for
affected channels
P_7.6.11
Power stage voltage drop at
low battery
VDS(OP) ––1VRL = 50 supplied
by VS = 4 V
VS = VS(OP),max or
VDD = 4.5 V, VS pin
open
refer to Figure 16
P_7.6.12
Drain to Source Output
clamping voltage
VDS(CL) 42 46 55 V IL = 20 mA P_7.6.16
Output leakage current
(each channel)
TJ 85 °C
IL(OFF) –0.010.5µA
1)
VIN = 0 V or floating
VDS = 28 V
OUT.OUTn = 0
TJ 85 °C
P_7.6.19
Output leakage current
(each channel)
TJ = 150 °C
(Low-Side channels)
IL(OFF) –0.15µA
1)
VIN = 0 V or floating
VDS = 28 V
OUT.OUTn = 0
TJ = 150 °C
P_7.6.20
TLE75004-ELD
Power Stages
Data Sheet 38 Rev. 1.1, 2015-09-25
Timings
Turn-ON delay
(from INn pin or bit to VOUT =
90% VS)
tDELAY(ON) 148µsRL = 50
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.21
Turn-OFF delay
(from INn pin or bit to VOUT =
10% VS)
tDELAY(OFF) 1612µsRL = 50
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.22
Turn-ON time
(from INn pin or bit to VOUT =
10% VS)
tON 61535µsRL = 50
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.23
Turn-OFF time
(from INn pin or bit to VOUT =
90% VS)
tOFF 61535µsRL = 50
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.24
Turn-ON/OFF matching tON - tOFF -10 0 10 µs RL = 50
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.25
Turn-ON slew rate
VDS = 70% to 30% VS
dV/dtON 0.7 1.3 1.9 V/µs RL = 50
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.26
Turn-OFF slew rate
VDS = 30% to 70% VS
-dV/dtOFF 0.7 1.3 1.9 V/µs RL = 50
VS = 13.5 V
Active mode or
Limp Home mode
P_7.6.27
Internal reference frequency
synchronization time
tSYNC –510µs
1) P_7.6.45
1) Not subject to production test - specified by design
2) If one channel has IL(NOM),max applied, the remaining channels must be underloaded accordingly so that TJ < 150°C
3) IL(NOM),max can reach IL(OVL1),min
Table 9 Electrical Characteristics: Power Stage (cont’d)
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
TLE75004-ELD
Protection Functions
Data Sheet 39 Rev. 1.1, 2015-09-25
8 Protection Functions
8.1 Over Load Protection
The TLE75004-ELD is protected in case of over load or short circuit of the load. There are two over load current
thresholds (see Figure 17):
•IL(OVL0) between channel switch ON and tOVLIN
•IL(OVL1) after tOVLIN
Every time the channel is switched OFF for a time longer than 2 * tSYNC the over load current threshold is set back
to IL(OVL0).
Figure 17 Over Load current thresholds
In case the load current is higher than IL(OVL0) or IL(OVL1), after time tOFF(OVL) the over loaded channel is switched
OFF and the according diagnosis bit ERRn is set. The channel can be switched ON after clearing the protection
latch by setting the corresponding HWCR_OCL.OUTn bit to “1”. This bit is set back to “0” internally after de-latching
the channel. Please refer to Figure 18 for details.
Figure 18 Latch OFF at Over Load
8.2 Over Temperature Protection
A temperature sensor is integrated for each channel, causing an overheated channel to switch OFF to prevent
destruction. The according diagnosis bit ERRn is set (combined with Over Load protection). The channel can be
INn
I
L(OVL)
t
t
OverLoadStep.emf
t
OVLIN
OUT.OUTn
I
L(OVL0)
I
L(OVL 1)
INn
I
Ln
t
t
OverLoad.emf
t
OFF(OVL)
I
L(OVLn)
OUT.OUTn
SPI command to set
HWCR_OCL.OUTn = 1
b
t
t
ERRn 1 00
t
1 00
HWCR_OCL.OUTn
TLE75004-ELD
Protection Functions
Data Sheet 40 Rev. 1.1, 2015-09-25
switched ON after clearing the protection latch by setting the corresponding HWCR_OCL.OUTn bit to “1”. This bit is
set back to “0” internally after de-latching the channel.
8.3 Over Temperature and Over Load Protection in Limp Home mode
When TLE75004-ELD is in Limp Home mode, channels 2 and 3 can be switched ON using the input pins. In case
of Over Load, Short Circuit or Over Temperature the channels switch OFF. If the input pins remain “high”, the
channels restart with the following timings:
• 10 ms (first 8 retries)
• 20 ms (following 8 retries)
• 40 ms (following 8 retries)
• 80 ms (as long as the input pin remains “high” and the error is still present)
If at any time the input pin is set to “low” for longer than 2*tSYNC, the restart timer is reset. At the next channel
activation while in Limp Home mode the timer starts from 10 ms again. See Figure 19 for details. Over Load
current thresholds behave as described in Chapter 8.1.
Figure 19 Restart timer in Limp Home mode
8.4 Reverse Polarity Protection
In Reverse Polarity (also known as Reverse Battery) condition, power dissipation is caused by the intrinsic body
diode of each DMOS channel. Each ESD diode of the logic and supply pins contributes to total power dissipation.
The reverse current through the channels has to be limited by the connected loads. The current through digital
power supply VDD and input pins has to be limited as well (please refer to the Absolute Maximum Ratings listed
on Chapter 4.1).
Note: No protection mechanism like temperature protection or current limitation is active during reverse polarity.
8.5 Over Voltage Protection
In the case of supply voltages between VS(SC) and VS(LD) the output transistors are still operational and follow the
input pins or the OUT register.
In addition to the output clamp for inductive loads as described in Chapter 7.1.2, there is a clamp mechanism
available for over voltage protection for the logic and all channels, monitoring the voltage between VS and GND
pins (VS(AZ)).
IN0
IN1
I
L2
I
L3
t
t
LHrestart.emf
t
RETRY0(LH)
10 ms
018
t
RETRY1(LH)
20 ms
1 8
t
RETRY2(LH)
40 ms
1 8
t
RETRY3(LH)
80 ms
t
RETRY0(LH)
10 ms
01
TLE75004-ELD
Protection Functions
Data Sheet 41 Rev. 1.1, 2015-09-25
8.6 Electrical Characteristics Protection
Table 10 Electrical Characteristics Protection
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
Over Load
Over Load detection current IL(OVL0) 1.3 1.7 2.3 A TJ = -40 °CP_8.8.19
Over Load detection current IL(OVL0) 1.25 1.55 2.3 A 1)
TJ = 25 °C
P_8.8.20
Over Load detection current IL(OVL0) 11.452ATJ = 150 °CP_8.8.21
Over Load detection current IL(OVL1) 0.7 0.95 1.3 A TJ = -40 °CP_8.8.22
Over Load detection current IL(OVL1) 0.65 0.85 1.3 A 1)
TJ = 25 °C
P_8.8.23
Over Load detection current IL(OVL1) 0.5 0.8 1.25 A TJ = 150 °CP_8.8.24
Over Load threshold switch
delay time
tOVLIN 110 170 260 µs 1) P_8.8.5
Over Load shut-down delay
time
tOFF(OVL) 4711µs
1) P_8.8.26
Over Temperature and Over Voltage
Thermal shut-down
temperature
TJ(SC) 150 1751)
1) Not subject to production test - specified by design
2201) °C P_8.8.7
Over voltage protection VS(AZ) 42 50 60 V IVS = 10 mA
Sleep mode
P_8.8.8
Reverse Polarity
Drain Source diode during
reverse polarity
VDS(REV) –800–mV
1)
IL = -10 mA
TJ = 25 °C
Sleep mode
P_8.8.9
Drain Source diode during
reverse polarity
VDS(REV) –650–mVIL = -10 mA
TJ = 150 °C
Sleep mode
P_8.8.10
Timings
Restart time in Limp Home
mode
tRETRY0(LH) 71013ms
1) P_8.8.13
Restart time in Limp Home
mode
tRETRY1(LH) 14 20 26 ms 1) P_8.8.14
Restart time in Limp Home
mode
tRETRY2(LH) 28 40 52 ms 1) P_8.8.15
Restart time in Limp Home
mode
tRETRY3(LH) 56 80 104 ms 1) P_8.8.16
TLE75004-ELD
Diagnosis
Data Sheet 42 Rev. 1.1, 2015-09-25
9 Diagnosis
The SPI of TLE75004-ELD provides diagnosis information about the device and the load status. Each channel
diagnosis information is independent from other channels. An error condition on one channel has no influence on
the diagnostic of other channels in the device (unless configured to work in parallel, see Chapter 7.2 for more
details).
9.1 Over Load and Over Temperature
When either an Over Load or an Over Temperature occurs on one channel, the diagnosis bit ERRn is set
accordingly. As described in Chapter 8.1 and Chapter 8.2, the channel latches OFF and must be reactivated
setting corresponding HWCR_OCL.OUTn bit to “1”.
9.2 Output Status Monitor
The device compares each channel VDS with VDS(OL) and sets the corresponding DIAG_OSM.OUTn bits
accordingly. The bits are updated every time DIAG_OSM register is read.
•VDS < VDS(OL) DIAG_OSM.OUTn = “1”
A diagnosis current IOL in parallel to the power switch can be enabled by programming the DIAG_IOL.OUTn bit,
which can be used for Open Load at OFF detection. Each channel has its dedicated diagnosis current source. If
the diagnosis current IOL is enabled or if the channel changes state (ON OFF or OFF ON) it is necessary to
wait a time tOSM for a reliable diagnosis. Enabling IOL current sources increases the current consumption of the
device. Even if an Open Load is detected, the channel is not latched OFF.
See Figure 20 for a timing overview (the values of DIAG_IOL.OUTn refer to a channel in normal operation
properly connected to the load).
Figure 20 Output Status Monitor timing
Output Status Monitor diagnostic is available when VS=VS(NOR) and VDD VDD(UV).
Due to the fact that Output Status Monitor checks the voltage level at the outputs in real time, for Open Load in
OFF diagnostic it is necessary to sychronize the reading of DIAG_OSM register with the OFF state of the
channels.
Figure 21 shows how Output Status Monitor is implemented at concept level.
INn
t
OutStatMon_timings.emf
OUT.OUTn
1
t
t
ON
+ t
OSM
DIAG_OSM.OUTn
0
t
x
t
SPI readout of
DIAG_OSM.OUTn
1 00
Output volt age
comparator
t
OFF
+ t
OSM
x 0
x x
TLE75004-ELD
Diagnosis
Data Sheet 43 Rev. 1.1, 2015-09-25
Figure 21 Output Status Monitor - concept
In Standard Diagnosis the bit OLOFF represents the OR combination of all DIAG_OSM.OUTn bits for all channels
in OFF state which have the corresponding current source IOL activated.
OutStatMon_LS.emf
V
S
Low-side
Channel R
OL
OUT
V
DS
GND
I
OL
I
OL
V
DS(OL)
DIAG_OSM.OUTn
V
DS
< V
DS(OL)
ÆDIAG_OSM.OUTn = „1"
TLE75004-ELD
Diagnosis
Data Sheet 44 Rev. 1.1, 2015-09-25
9.3 Electrical Characteristics Diagnosis
Table 11 Electrical Characteristics Diagnosis
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
Output Status Monitor
Output Status Monitor
comparator settling time
tOSM ––20µs
1)
1) Not subject to production test - specified by design
P_9.5.1
Output Status Monitor
threshold voltage
VDS(OL) 33.33.6V P_9.5.2
Output diagnosis current IOL 70 85 100 µA VDS = 3.3 V
P_9.5.5
Open Load equivalent
resistance
ROL 30 – 300 k1) P_9.5.6
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 45 Rev. 1.1, 2015-09-25
10 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO,
SI, SCLK and CSN. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CSN
indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on
line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo 8/16
counter ensures that data is taken only when a multiple of 8 bit has been transferred after the first 16 bits.
Otherwise a TER bit is asserted. In this way the interface provides daisy chain capability with 16 bit as well as with
8 bit SPI devices.
Figure 22 Serial Peripheral Interface
10.1 SPI Signal Description
CSN - Chip Select
The system microcontroller selects the TLE75004-ELD by means of the CSN pin. Whenever the pin is in “low”
state, data transfer can take place. When CSN is in "high" state, any signals at the SCLK and SI pins are ignored
and SO is forced into a high impedance state.
CSN “high” to “low” Transition
• The requested information is transferred into the shift register.
• SO changes from high impedance state to "high" or “low” state depending on the logic OR combination
between the transmittion error flag (TER) and the signal level at pin SI. This allows to detect a faulty
transmission even in daisy chain configuration.
• If the device is in Sleep mode, SO pin remains in high impedance state and no SPI transmission occurs.
Figure 23 Combinatorial Logic for TER bit
14 13 12 11
14 13 12 11MSB
MSB
SPI_16bit.emf
LSB6 5 4 3 2 1
LSB6 5 4 3 2 1
10 9 8
10 9 8
7
7
SO
SI
CSN
SCLK
time
SPI _TER.emf
SI
SPI
OR
TER
0
1
SO
CSN
SCLK
S
SO
S
SI
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 46 Rev. 1.1, 2015-09-25
CSN “low” to "high" Transition
• Command decoding is only done, when after the falling edge of CSN exactly a multiple (1, 2, 3, …) of eight
SCLK signals have been detected after the first 16 SCLK pulses. In case of faulty transmission, the
transmission error bit (TER) is set and the command is ignored.
• Data from shift register is transferred into the addressed register.
SCLK - Serial Clock
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in “low” state whenever chip select CSN makes any transition, otherwise the
command may be not accepted.
SI - Serial Input
Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Chapter 10.5 for
further information.
SO Serial Output
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CSN pin
goes to “low” state. New data appears at the SO pin following the rising edge of SCLK.
Please refer to Chapter 10.5 for further information.
10.2 Daisy Chain Capability
The SPI of TLE75004-ELD provides daisy chain capability. In this configuration several devices are activated by
the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see
Figure 24), in order to build a chain. The end of the chain is connected to the output and input of the master device,
MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line
of each device in the chain.
Figure 24 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where each bit from SI line is shifted in each SCLK. The
bit shifted out occurs at the SO pin. After sixteen SCLK cycles, the data transfer for one device is finished. In single
chip configuration, the CSN line must turn “high” to make the device acknowledge the transferred data. In daisy
SI
device 1
SPI
SCLK
SO
CSN
SI
device 2
SPI
SCLK
SO
CSN
SI
device 3
SPI
SCLK
SO
CSN
MO
MI
MCSN
MCLK SPI_DaisyChain_1.emf
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 47 Rev. 1.1, 2015-09-25
chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in
daisy chain, several multiples of 8 bits have to be shifted through the devices (depending on how many devices
with 8 bit SPI and how many with 16 bit SPI). After that, the MCSN line must turn “high” (see Figure 25).
Figure 25 Data Transfer in Daisy Chain Configuration
10.3 Timing Diagrams
Figure 26 Timing Diagram SPI Access
MI
MO
MCSN
MCLK
SI device 3 SI device 2 SI device 1
SO device 3 SO device 2 SO device 1
SPI_DaisyChain_2.emf
CSN
SCLK
SI
t
CSN(lead)
t
CSN(td)
t
CSN(lag)
t
SC L K (H )
t
SCLK ( L)
t
SC L K(P )
t
SI ( s u)
t
SI (h)
SO
t
SO( v )
t
SO(en)
t
SO (dis )
V
CSN(H)
SPI _Timings.e m f
V
CSN(L)
V
SC L K( H )
V
SC L K( L)
V
SI (H)
V
SI (L)
V
SO( H )
V
SO( L )
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 48 Rev. 1.1, 2015-09-25
10.4 Electrical Characteristics
VDD = 3 V to 5.5 V, VS = 7 V to 18 V, TJ = -40 °C to +150 °C (unless otherwise specified)
Typical values: VDD = 5 V, VS = 13.5 V, TJ = 25 °C
Table 12 Electrical Characteristics Serial Peripheral Interface (SPI)
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
Input Characteristics (CSN, SCLK, SI) - “low” level of pin
CSN VCSN(L) 0–0.8V– P_10.4.1
SCLK VSCLK(L) 0–0.8V– P_10.4.2
SI VSI(L) 0–0.8V– P_10.4.3
Input Characteristics (CSN, SCLK, SI) - “high” level of pin
CSN VCSN(H) 2–VDD V–P_10.4.4
SCLK VSCLK(H) 2–VDD V–P_10.4.5
SI VSI(H) 2–VDD V–P_10.4.6
Input Pull-Up Current at Pin CSN
L-input pull-up current at CSN pin -ICSN(L) 30 60 90 AVDD = 5 V
VCSN = 0.8 V
P_10.4.7
H-input pull-up current at CSN pin -ICSN(H) 20 40 65 AVDD = 5 V
VCSN = 2 V
P_10.4.8
L-Input Pull-Down Current at Pin
SCLK ISCLK(L) 51220AVSCLK = 0.8 V P_10.4.9
SI ISI(L) 51220AVSI = 0.8 V P_10.4.10
H-Input Pull-Down Current at Pin
SCLK ISCLK(H) 14 28 45 AVSCLK = 2 V P_10.4.11
SI ISI(H) 14 28 45 AVSI = 2 V P_10.4.12
Output Characteristics (SO)
L level output voltage VSO(L) 0–0.4VISO = -1.5 mA P_10.4.13
H level output voltage VSO(H) VDD -
0.4
–VDD VISO = 1.5 mA P_10.4.14
Output tristate leakage current ISO(OFF) -1 – 1 AVCSN =VDD
VSO = 0 V
P_10.4.15
Output tristate leakage current ISO(OFF) -1 – 1 AVCSN =VDD
VSO = VDD
P_10.4.16
Timings
Enable lead time (falling CSN to
rising SCLK)
tCSN(lead) 200 – – ns 1)
VDD = 4.5 V or
VS > 7 V
P_10.4.17
Enable lag time (falling SCLK to
rising CSN)
tCSN(lag) 200 – – ns 1)
VDD = 4.5 V or
VS > 7 V
P_10.4.18
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 49 Rev. 1.1, 2015-09-25
Transfer delay time (rising CSN to
falling CSN)
tCSN(td) 250 – – ns 1)
VDD = 4.5 V or
VS > 7 V
P_10.4.19
Output enable time (falling CSN to
SO valid)
tSO(en) ––200ns
1)
VDD = 4.5 V or
VS > 7 V
CL = 20 pF at SO
pin
P_10.4.20
Output disable time (rising CSN to
SO tristate)
tSO(dis) ––200ns
1)
VDD = 4.5 V or
VS > 7 V
CL = 20 pF at SO
pin
P_10.4.21
Serial clock frequency fSCLK ––5 MHz
1)
VDD = 4.5 V or
VS > 7 V
P_10.4.22
Serial clock period tSCLK(P) 200 – – ns 1)
VDD = 4.5 V or
VS > 7 V
P_10.4.23
Serial clock “high” time tSCLK(H) 75 – – ns 1)
VDD = 4.5 V or
VS > 7 V
P_10.4.24
Serial clock “low” time tSCLK(L) 75 – – ns 1)
VDD = 4.5 V or
VS > 7 V
P_10.4.25
Data setup time (required time SI to
falling SCLK)
tSI(su) 20 – – ns 1)
VDD = 4.5 V or
VS > 7 V
P_10.4.26
Data hold time (falling SCLK to SI) tSI(h) 20 – – ns 1)
VDD = 4.5 V or
VS > 7 V
P_10.4.27
Output data valid time with
capacitive load
tSO(v) ––100ns
1)
VDD = 4.5 V or
VS > 7 V
CL = 20 pF at SO
pin
P_10.4.28
Enable lead time (falling CSN to
rising SCLK)
tCSN(lead) 1–– s1)
VDD = VS = 3.0 V
P_10.4.29
Enable lag time (falling SCLK to
rising CSN)
tCSN(lag) 1–– s1)
VDD = VS = 3.0 V
P_10.4.30
Transfer delay time (rising CSN to
falling CSN)
tCSN(td) 1.25 – – s1)
VDD = VS = 3.0 V
P_10.4.31
Table 12 Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 50 Rev. 1.1, 2015-09-25
Output enable time (falling CSN to
SO valid)
tSO(en) ––1 s
1)
VDD = VS = 3.0 V
CL = 20 pF at SO
pin
P_10.4.32
Output disable time (rising CSN to
SO tristate)
tSO(dis) ––1 s
1)
VDD = VS = 3.0 V
CL = 20 pF at SO
pin
P_10.4.33
Serial clock frequency fSCLK ––1 MHz
1)
VDD = VS = 3.0 V
P_10.4.34
Serial clock period tSCLK(P) 1–– s1)
VDD = VS = 3.0 V
P_10.4.35
Serial clock “high” time tSCLK(H) 375 – – ns 1)
VDD = VS = 3.0 V
P_10.4.36
Serial clock “low” time tSCLK(L) 375 – – ns 1)
VDD = VS = 3.0 V
P_10.4.37
Data setup time (required time SI to
falling SCLK)
tSI(su) 100 – – ns 1)
VDD = VS = 3.0 V
P_10.4.38
Data hold time (falling SCLK to SI) tSI(h) 100 – – ns 1)
VDD = VS = 3.0 V
P_10.4.39
Output data valid time with
capacitive load
tSO(v) ––500ns
1)
VDD = VS = 3.0 V
CL = 20 pF at SO
pin
P_10.4.40
1) Not subject to production test, specified by design
Table 12 Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 51 Rev. 1.1, 2015-09-25
10.5 SPI Protocol
The relationship between SI and SO content during SPI communication is shown in Figure 27. SI line represents
the frame sent from the µC and SO line is the answer provided by TLE75004-ELD.
Figure 27 Relationship between SI and SO during SPI communication
The SPI protocol provides the answer to a command frame only with the next trasmission triggered by the µC.
Although the biggest majority of commands and frames implemented in TLE75004-ELD can be decoded without
the knowledge of what happened before, it is advisable to consider what the µC sent in the previous transmission
to decode TLE75004-ELD response frame completely.
More in detail, the sequence of commands to “read” and “write” the content of a register looks as follows:
Figure 28 Register content sent back to µC
There are 3 special situations where the frame sent back to the µC is not related directly to the previous received
frame:
• in case an error in transmission happened during the previous frame (for instance, the clock pulses were not
multiple of 8 with a minimum of 16 bits), shown in Figure 29
• when TLE75004-ELD logic supply comes out of Power-On reset condition or after a Software Reset, as shown
in Figure 30
• in case of command syntax errors
– “write” command starting with “11” instead of “10”
– “read” command starting with “00” instead of “01”
– “read” or “write” commands on registers which are “reserved” or “not used”
SI
SO
frame A frame B
(previous
response)
response to
frame A
frame C
response to
frame B
SPI_ SI2SO.emf
SI
SO
write register A read register A
Standard
diagnostic
register A
content
(new command )
SPI_RWseq.emf
(previous
response)
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 52 Rev. 1.1, 2015-09-25
Figure 29 TLE75004-ELD response after a error in transmission
Figure 30 TLE75004-ELD response after coming out of Power-On reset at VDD
Figure 31 TLE75004-ELD response after a command syntax error
A summary of all possible SPI commands is presented in Table 13, including the answer that TLE75004-ELD
sends back at the next transmission.
frame A
(error in transmission )
SPI_SO_TER.emf
SI
SO
(new command)
Standard diagnostic + TER(previous response )
SI
SO
frame A frame B
(SO = „Z“)
frame C
response to frame B
INST register + TER
(8680h)
V
DD
≥ V
DD(PO)
SPI _SO_POR.emf
SI
SO
frame A
(syntax or addressing error ) (new command)
Standard diagnostic(previous response )
SPI_SO_Syn taxError.emf
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 53 Rev. 1.1, 2015-09-25
Table 13 SPI Command summary1)
1) “a” = address bits for ADDR0 field, “b” = address bit for ADDR1 field, “c” = register content, “d” = diagnostic bit
Requested Operation Frame sent to SPIDER+ (SI pin) Frame received from SPIDER+ (SO
pin) with the next command
Read Standard Diagnosis 0xxxxxxxxxxxxx01B
(“xxxxxxxxxxxxB” = don´t care)
0dddddddddddddddB
(Standard Diagnosis)
Write 8 bit register 10aaaabbccccccccB
where:
“aaaaB” = register address ADDR0
“bbB” = register address ADDR1
“ccccccccB” = new register content
0dddddddddddddddB
(Standard Diagnosis)
Read 8 bit registers 01aaaabbxxxxxx10B
where:
“aaaaB” = register address ADDR0
“bbB” = register address ADDR1
“xxxxxxB” = don´t care
10aaaabbccccccccB
where:
“aaaaB” = register address ADDR0
“bbB” = register address ADDR1
“ccccccccB” = register content
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 54 Rev. 1.1, 2015-09-25
10.6 SPI Registers Overview
10.6.1 Standard Diagnosis
Table 14 Standard Diagnosis
1514131211109876543210Default
0UVR
VS
LOP
VDD
MODE TER 0 OL
OFF
0000ERR 7800
H
Field Bits Type Description
UVRVS 14 r VS Undervoltage Monitor
0BNo undervoltage condition on VS detected (see Chapter 6.2.1
for more details)
1B(default) There was at least one VS Undervoltage condition since
last Standard Diagnosis readout
LOPVDD 13 r VDD Lower Operating Range Monitor
0BVDD is above VDD(LOP)
1B(default) There was at least one “VDD = VDD(LOP)” condition since
last Standard Diagnosis readout
MODE 12:11 r Operative Mode Monitor
00B(reserved)
01BLimp Home Mode
10BActive Mode
11B(default) Idle Mode
TER 10 r Transmission Error
0BPrevious transmission was successful
(modulo 16 + n*8 clocks received, where n = 0, 1, 2...)
1B(default) Previous transmission failed
The first frame after a reset is TER set to “high” and the INST register.
The second frame is the Standard Diagnosis with TER set to “low” (if
there was no fail in the previous transmission).
OLOFF 8rOpen Load in OFF Diagnosis
0B(default) All channels in OFF state (which have DIAG_IOL.OUTn
bit set to “1”) have VDS > VDS(OL)
1BAt least one channel in OFF state (with DIAG_IOL.OUTn bit set
to “1”) has VDS < VDS(OL)
Channels in ON state are not considered
ERRn
n = 3 to 0
n:0 r Over Load / Over Temperature Diagnosis of channel n
0B(default) No failure detected
1BOver Temperature or Over Load
bits 7:4 - reserved (default: 0B)
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 55 Rev. 1.1, 2015-09-25
10.6.2 Register structure
The register banks the digital part have following structure:
Table 16 summarizes the available registers with their addresing space and size
Table 15 Register structure - all registers
1514131211109876543210Default
r = 0
w = 1
r = 1
w = 0
ADDR0 ADDR1 DATA XXXXH
Table 16 Register addressing space
Register name ADDR0 ADDR1 Size Type Purpose
OUT
n = 3 to 0
0000B00Bnr/wPower output control register
bits OUT.OUTn
0B(default) Output is OFF
1BOutput is ON
bits 7:4 - reserved (default: 0B)
MAPIN0
n = 3 to 0
0001B00Bnr/wInput Mapping (Input Pin 0)
bits MAPIN0.OUTn
0B(default) The output is not connected to the input pin
1BThe output is connected to the input pin
Note: Channel 2 has the corresponding bit set to “1” by
default
bits 7:4 - reserved (default: 0B)
MAPIN1
n = 3 to 0
0001B01Bnr/wInput Mapping (Input Pin 1)
bits MAPIN1.OUTn
0B(default) The output is not connected to the input pin
1BThe output is connected to the input pin
Note: Channel 3 has the corresponding bit set to “1” by
default
bits 7:4 - reserved (default: 0B)
INST 0001B10B8r Input Status Monitor
bit TER
0BPrevious transmission was successful
(modulo 16 + n*8 clocks received, where n = 0, 1, 2...)
1B(default) Previous transmission failed
bits INST.RES (6:2) - reserved
bits INST.INn (1:0)
0B(default) The input pin is set to “low”
1BThe input pin is set to “high”
First register transmitted after a reset of the logic
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 56 Rev. 1.1, 2015-09-25
10.6.3 Register summary
All registers with addresses not mentioned in Table 17 have to be considered as “reserved”. “Read” operations
performed on those registers return the Standard Diagnosis. The column “Default” indicates the content of the
register (8 bits) after a reset.
DIAG_IOL
n = 3 to 0
0010B00Bnr/wOpen Load diagnostic current control
bits DIAG_IOL.OUTn
0B(default) Diagnosis current not enabled
1BDiagnosis current enabled
bits 7:4 - reserved (default: 0B)
DIAG_OSM
n = 3 to 0
0010B01Bnr Output Status Monitor
bits DIAG_OSM.OUTn
0B(default) VDS > VDS(OL)
1BVDS < VDS(OL)
bits 7:4 - reserved (default: 0B)
HWCR 0011B00B8r/wHardware Configuration Register
bit HWCR.ACT (7) (Active Mode)
0B(default) Normal operation or device leaves Active
Mode
1BDevice enters Active Mode
(see Chapter 6.1 for a description of the possible operative
mode transitions)
bit HWCR.RST (6) (Reset)
0B(default) Normal operation
1BExecute Reset command (self clearing)
bits HWCR.PAR (1:0) (channels operating in parallel)
0B(default) Normal operation
1Btwo neighbour channels have Over Load and Over
Temperature synchronized (see Chapter 7.2 for more
details)
bits 5:2 - reserved (default: 0B)
HWCR_OCL
n = 3 to 0
0011B01Bnw Output Clear Latch
bits HWCR_OCL.OUTn
0B(default) Normal operation
1BClear the error latch for the selected output
bits 7:4 - reserved (default: 0B)
Table 17 Addressable registers
151413-109876543210Default
r = 0
w = 1
r = 1
w = 0
0000 00 (reserved) OUT.OUTn 00H
r = 0
w = 1
r = 1
w = 0
0001 00 (reserved) MAPIN0.OUTn 04H
Table 16 Register addressing space (cont’d)
Register name ADDR0 ADDR1 Size Type Purpose
TLE75004-ELD
Serial Peripheral Interface (SPI)
Data Sheet 57 Rev. 1.1, 2015-09-25
10.6.4 SPI command quick list
A summary of the most used SPI commands (read and write operations on all registers) is shown in Table 18
r = 0
w = 1
r = 1
w = 0
0001 01 (reserved) MAPIN1.OUTn 08H
0 1 0001 10 TER (reserved) INST.INn 00H
r = 0
w = 1
r = 1
w = 0
0010 00 (reserved) DIAG_IOL.OUTn 00H
0 1 0010 01 (reserved) DIAG_OSM.OUTn 00H
r = 0
w = 1
r = 1
w = 0
0011 00 HWCR
.ACT
HWCR
.RST
(reserved) HWCR.PAR 00H
r = 0
w = 1
r = 1
w = 0
0011 01 (reserved) HWCR_OCL.OUTn 00H
Table 18 SPI command quick list
Register “read” command” “write” command content written
OUT 4002H80XXHXXH = xxxxxxxxB
MAPIN0 4402H84XXHXXH = xxxxxxxxB
MAPIN1 4502H85XXHXXH = xxxxxxxxB
INST 4602Hn.a. (read-only) –
DIAG_IOL 4802H88XXHXXH = xxxxxxxxB
DIAG_OSM 4902Hn.a. (read-only) –
HWCR 4C02H8CXXHXXH = xxxxxxxxB
HWCR_OCL 4D02H8DXXHXXH = xxxxxxxxB
Table 17 Addressable registers
151413-109876543210Default
TLE75004-ELD
Application Information
Data Sheet 58 Rev. 1.1, 2015-09-25
11 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 32 TLE75004-ELD Application Diagram
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
Table 19 Suggested Component values
Reference Value Purpose
RIN 4.7 kProtection of the micro-controller during Over Voltage and Reverse Polarity
Guarantee TLE75004-ELD channels OFF during Loss of Ground
RIDLE 4.7 kProtection of the micro-controller during Over Voltage and Reverse Polarity
Guarantee TLE75004-ELD channels OFF during Loss of Ground
RCSN 500 Protection of the micro-controller during Over Voltage and Reverse Polarity
RSCLK 500 Protection of the micro-controller during Over Voltage and Reverse Polarity
RSI 500 Protection of the micro-controller during Over Voltage and Reverse Polarity
RSO 500 Protection of the micro-controller during Over Voltage and Reverse Polarity
RVDD 100 Logic supply voltage spikes filtering
CVDD 100 nF Logic supply voltage spikes filtering
CVS 68 nF Analog supply voltage spikes filtering
V
BA TT
Z
VS
IDLE
IN1
SO
GND
V
DD
C
VDD
IN0_LH
IN1_LH
LI MP HO ME
R
IN
GPO
VDD
R
IN
R
IDLE
R
CSN
R
SCLK
R
SI
R
SO
SI
CSN
VDD
SCL K
IN0
VS
GPO
GPO
GPO
GPO
GPO
GPI
GND
C
OUT
C
OUT
C
OUT
C
OUT
OUT3_LS
OUT2_LS
OUT1_LS
OUT0_LS
Z
OUT2
Z
OUT3
C
VS
Application_4LS.emf
R
VDD
R
LH
R
OUT 1
TLE75004-ELD
Application Information
Data Sheet 59 Rev. 1.1, 2015-09-25
11.1 Further Application Information
• Please contact us for information regarding the Pin FMEA
• For further information you may contact http://www.infineon.com/
ZVS P6SMB30 Protection of device during Over Voltage. Zener diode
COUT 10 nF Protection of TLE75004-ELD against ESD and BCI
Table 19 Suggested Component values (cont’d)
Reference Value Purpose
TLE75004-ELD
Package Outlines
Data Sheet 60 Rev. 1.1, 2015-09-25
12 Package Outlines
Figure 33 PG-SSOP-14-5 Package drawing
Figure 34 TLE75004-ELD Package pads and stencil
PG-SSOP-14-1,-2,-3, -5-PO V05
17
14 8
14
17
8
14x
0.25
!0.05
!0.05
2)
M
0.15 DC A-B
0.65 C
STAND OFF
0.05
(1.45)
1.7 MAX.
0.08 C
A
B
4.9
!0.11)
A-BH0.1 2x
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
Bottom View
!0.2
3
!0.2
2.65
!0.2
D
H
614x
0.64
!0.25
3.9
!0.11)
0.35 x 45"
0.1 HD2x
0.2 C
+0.06
0.19
8
"
MAX.
Index
Marking
Exposed
Diepad
SEATING
PLANE
6 x 0.65 = 3.9
0.45 0.65
1.31
2.65
3
5.69
PG-SSOP-14-1,-2,-3, -5-FP V01
TLE75004-ELD
Package Outlines
Data Sheet 61 Rev. 1.1, 2015-09-25
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-
free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
TLE75004-ELD
Revision History
Data Sheet 62 Rev. 1.1, 2015-09-25
13 Revision History
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Page or Item Changes since previous revision
Rev. 1.1, 2015-09-25
All
TLE75004-ELD Figure 33 changed
Rev. 1.0, 2015-07-27
TLE75004-ELD Data Sheet released
Edition 2015-09-25
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
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For further information on technology, delivery terms and conditions and prices, please contact the nearest
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Due to technical requirements, components may contain dangerous substances. For information on the types in
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