1998-2019 Microchip Technology Inc. DS20001203W-page 1
24AA256/24LC256/24FC256
Device Selection Table
Features
• Single Supply with Operation Down to 1.7V for
24AA256 and 24FC256 Devices, 2.5V for
24LC256 Devices
• Low-Power CMOS Technology:
- Write current: 3 mA, maximum
- Standby current: 1 µA maximum (I-temp.)
• Two-Wire Serial Interface, I2C Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz, 400 kHz and 1 MHz Compatibility
• Page Write Time: 5 ms, maximum
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• RoHS Compliant
• Temperature Ranges:
• Automotive AEC-Q100 Qualified
Packages
• 8-Lead DFN, 8-Lead MSOP, 8-Lead PDIP,
8-Lead SOIC, 8-Lead SOIJ, 8-Lead TDFN,
8-Lead TSSOP and 8-Ball CSP
Description
The Microchip Technology Inc. 24XX256(1) is a 32K x 8
(256 Kbit) Serial Electrically Erasable PROM, capable
of operation across a broad voltage range (1.7V to
5.5V). It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device also has a page write capability
of up to 64 bytes of data. This device is capable of both
random and sequential reads up to the 256K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 2 Mbit address space.
Package Types
Part Number VCC Range Max. Clock Frequency Temp. Ranges Available Packages
24AA256 1.7V-5.5V 400 kHz(1)I, E MF, MS, P, SN, SM, MNY, ST, CS
24LC256 2.5V-5.5V 400 kHz I, E MF, MS, P, SN, SM, MNY, ST
24FC256 1.7V-5.5V 1 MHz(2)I MF, MS, P, SN, SM, MNY, ST
Note 1: 100 kHz for VCC <2.5V.
2: 400 kHz for VCC <2.5V.
- Industrial (I): -40C to +85C
- Extended (E): -40C to +125C
Note 1: 24XX256 is used in this document as a
generic part number for the 24AA256/
24LC256/24FC256 devices.
8-Ball CSP
123
45
678
VCC A1 A0
WP A2
SDA SCL VSS
1
2
3
4
8
7
6
5
8-Lead SOIC/SOIJ/TSSOP
8-Lead DFN/TDFN
VSS
WP
SCL
SDA
VCC
(Top View)
(Top View)
1
2
3
4
8
7
6
5
8-Lead PDIP/MSOP
(Top View)
WP
SCL
SDA
VCC
1
2
3
4
8
7
6
5
WP
SCL
SDA
VCC
1
2
3
4
8
7
6
5
A0
A1
A2
VSS
A0
A1
A2
VSS
A0
A1
A2
24XX256
24XX256
24XX256
(Top View)
Note 1: Pins A0 and A1 are no connects for the MSOP package only.
(1)
256K I2C Serial EEPROM
24AA256/24LC256/24FC256
DS20001203W-page 2 1998-2019 Microchip Technology Inc.
Block Diagram
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
R/W Control
Memory
Control
Logic
I/O
Control
Logic
I/O
A0 A1A2
SDA
SCL
VCC
VSS
WP
1998-2019 Microchip Technology Inc. DS20001203W-page 3
24AA256/24LC256/24FC256
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins 4kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Extended (E): VCC = +1.7V to 5.5V TA = -40°C to +125°C
Param.
No. Symbol Characteristic Min. Max. Units Conditions
D1 VIH High-Level Input Voltage 0.7 VCC —V
D2 VIL Low-Level Input Voltage — 0.3 VCC
0.2 VCC
V
V
VCC 2.5V
VCC < 2.5V
D3 VHYS Hysteresis of Schmitt Trigger
Inputs (SDA, SCL pins)
0.05 VCC —VVCC 2.5V (Note)
D4 VOL Low-Level Output Voltage — 0.40 V IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
D5 ILI Input Leakage Current — ±1 µA VIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D6 ILO Output Leakage Current — ±1 µA VOUT = VSS or VCC
D7 CIN,
COUT
Pin Capacitance
(all inputs/outputs)
—10pFVCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
D8 ICC Read Operating Current — 400 µA VCC = 5.5V, SCL = 400 kHz
ICC Write — 3 mA VCC = 5.5V
D9 ICCS Standby Current — 1 µA SDA = SCL = VCC =3.6V
A0, A1, A2, WP = VSS, I-Temp.
— 1.5 µA SDA = SCL = VCC =5.5V
A0, A1, A2, WP = VSS, I-Temp.
— 5 µA SDA = SCL = VCC =5.5V
A0, A1, A2, WP = VSS, E-Temp.
Note: This parameter is periodically sampled and not 100% tested.
24AA256/24LC256/24FC256
DS20001203W-page 4 1998-2019 Microchip Technology Inc.
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Extended (E): VCC = +1.7V to 5.5V TA = -40°C to +125°C
Param.
No. Symbol Characteristic Min. Max. Units Conditions
1FCLK Clock Frequency — 100 kHz 1.7V VCC 2.5V
—400kHz2.5V VCC 5.5V
—400kHz1.7V VCC 2.5V (24FC256)
— 1000 kHz 2.5V VCC 5.5V (24FC256)
2THIGH Clock High Time 4000 — ns 1.7V VCC 2.5V
600 — ns 2.5V VCC 5.5V
600 — ns 1.7V VCC 2.5V (24FC256)
500 — ns 2.5V VCC 5.5V (24FC256)
3T
LOW Clock Low Time 4700 — ns 1.7V VCC 2.5V
1300 — ns 2.5V VCC 5.5V
1300 — ns 1.7V VCC 2.5V (24FC256)
500 — ns 2.5V VCC 5.5V (24FC256)
4T
RSDA and SCL Rise Time — 1000 ns 1.7V VCC 2.5V (Note 1)
— 300 ns 2.5V VCC 5.5V (Note 1)
— 300 ns 1.7V VCC 5.5V (24FC256)
(Note 1)
5TFSDA and SCL Fall Time — 300 ns All except 24FC256 (Note 1)
— 100 ns 1.7V VCC 5.5V (24FC256)
(Note 1)
6THD:STA Start Condition Hold Time 4000 — ns 1.7V VCC 2.5V
600 — ns 2.5V VCC 5.5V
600 — ns 1.7V VCC 2.5V (24FC256)
250 — ns 2.5V VCC 5.5V (24FC256)
7T
SU:STA Start Condition Setup Time 4700 — ns 1.7V VCC 2.5V
600 — ns 2.5V VCC 5.5V
600 — ns 1.7V VCC 2.5V (24FC256)
250 — ns 2.5V VCC 5.5V (24FC256)
8T
HD:DAT Data Input Hold Time 0 — ns Note 2
9TSU:DAT Data Input Setup Time 250 — ns 1.7V VCC 2.5V
100 — ns 2.5V VCC 5.5V
100 — ns 1.7V VCC 5.5V (24FC256)
10 TSU:STO Stop Condition Setup Time 4000 — ns 1.7V VCC 2.5V
600 — ns 2.5V VCC 5.5V
600 — ns 1.7V VCC 2.5V (24FC256)
250 — ns 2.5V VCC 5.5V (24FC256)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s website
at www.microchip.com.
1998-2019 Microchip Technology Inc. DS20001203W-page 5
24AA256/24LC256/24FC256
11 TSU:WP WP Setup Time 4000 — ns 1.7V VCC 2.5V
600 — ns 2.5V VCC 5.5V
600 — ns 1.7V VCC 5.5V (24FC256)
12 THD:WP WP Hold Time 4700 — ns 1.7V VCC 2.5V
1300 — ns 2.5V VCC 5.5V
1300 — ns 1.7V VCC 5.5V (24FC256)
13 TAA Output Valid from Clock — 3500 ns 1.7 V VCC 2.5V (Note 2)
— 900 ns 2.5 V VCC 5.5V (Note 2)
— 900 ns 1.7V VCC 2.5V (24FC256)
(Note 2)
— 400 ns 2.5 V VCC 5.5V (24FC256)
(Note 2)
14 TBUF Bus Free Time: The time the
bus must be free before a new
transmission can start
4700 — ns 1.7V VCC 2.5V
1300 — ns 2.5V VCC 5.5V
1300 — ns 1.7V VCC 2.5V (24FC256)
500 — ns 2.5V VCC 5.5V (24FC256)
15 TOF Output fall time from VIH
minimum to VIL maximum
CB 100 pF
10 + 0.1CB250 ns All except 24FC256 (Note 1)
250 ns All except 24FC256 (Note 1)
16 TSP Input Filter Spike Suppression
(SDA and SCL pins)
— 50 ns All except 24FC256
(Notes 1 and 3)
17 TWC Write Cycle Time
(byte or page)
—5ms
18 Endurance 1,000,000 — cycles 25°C, 5.5V, Page mode (Note 4)
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS (Continued)
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Extended (E): VCC = +1.7V to 5.5V TA = -40°C to +125°C
Param.
No. Symbol Characteristic Min. Max. Units Conditions
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s website
at www.microchip.com.
24AA256/24LC256/24FC256
DS20001203W-page 6 1998-2019 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
89
13
D3 4
10
11 12
14
1998-2019 Microchip Technology Inc. DS20001203W-page 7
24AA256/24LC256/24FC256
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX256 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
Name DFN(1)MSOP PDIP SOIC SOIJ TDFN(1)TSSOP CSP Function
A0 1 — 1 1 1 1 1 3 User Configurable Chip Select
A1 2 — 2 2 2 2 2 2 User Configurable Chip Select
A2 3 3 3 3 3 3 3 5 User Configurable Chip Select
VSS 4 4 4 4 4 4 4 8 Ground
SDA 5 5 5 5 5 5 5 6 Serial Address/Data I/O
SCL 6 6 6 6 6 6 6 7 Serial Clock
WP 7 7 7 7 7 7 7 4 Write-Protect Input
VCC 8 8 8 8 8 8 8 1 Power Supply
Note 1: Exposed pad on DFN/TDFN can be connected to VSS or left floating.
Note: For the MSOP package only, pins A0 and
A1 are not connected.
24AA256/24LC256/24FC256
DS20001203W-page 8 1998-2019 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
The 24XX256 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX256 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high, determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line, while the clock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (although only the last 64 will be
stored when doing a write operation). When an over-
write does occur it will replace data in a first-in-first-out
(FIFO) principle.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable-low during the high period of
the Acknowledge-related clock pulse. Moreover, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX256) will leave the data line high to enable
the master to generate the Stop condition.
Note: The 24XX256 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
1998-2019 Microchip Technology Inc. DS20001203W-page 9
24AA256/24LC256/24FC256
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2: ACKNOWLEDGE TIMING
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(A) (B) (D) (D) (C) (A)
SCL 987654321123
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
Data from transmitter
24AA256/24LC256/24FC256
DS20001203W-page 10 1998-2019 Microchip Technology Inc.
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device. The control byte
consists of a 4-bit control code. For the 24XX256, this
is set as ‘1010’ binary for read and write operations.
The next three bits of the control byte are the Chip
Select bits (A2, A1, A0). The Chip Select bits allow the
use of up to eight 24XX256 devices on the same bus
and are used to select which device is accessed. The
Chip Select bits in the control byte must correspond to
the logic levels on the corresponding A2, A1 and A0
pins for the device to respond. These bits, in effect, are
the three Most Significant bits of the word address. The
combination of the 4-bit control code and the next three
bits are called the slave address.
For the MSOP package, the A0 and A1 pins are not
connected. During device addressing, the A0 and A1
Chip Select bits (Figures 5-1 and 5-2) should be set
to ‘0’. Only two 24XX256 MSOP packages can be
connected to the same bus.
The last bit of the control byte is the Read/Write (R/W)
bit and it defines the operation to be performed. When
set to ‘1’, a read operation is selected. When set to ‘0’,
a write operation is selected. The next two bytes
received define the address of the first data byte
(Figure 5-2). Because only A14…A0 are used, the
upper address bits are a “don’t care.” The upper
address bits are transferred first, followed by the Least
Significant bits.
Following the Start condition, the 24XX256 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX256 will select a read
or write operation.
FIGURE 5-1: CONTROL BYTE
FORMAT
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 2 Mbit
by adding up to eight 24XX256 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A15; A1 as address bit A16; and A2
as address bit A17. It is not possible to sequentially
read across device boundaries.
For the MSOP package, up to two 24XX256 devices
can be added for up to 512 Kbit of address space. In
this case, software can use A2 of the control byte as
address bit A17. Bits A0 (A15) and A1 (A16) of the
control byte must always be set to a logic ‘0’ for the
MSOP.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
1010A2 A1 A0
SACKR/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
1 010A
2
A
1A
0R/W xA
11
A
10 A
9
A
7
A
0
A
8••••••
A
12
Control Byte Address High Byte Address Low Byte
Control
Code
Chip
Select
Bits
x = “don’t care” bit
A
13
A
14
1998-2019 Microchip Technology Inc. DS20001203W-page 11
24AA256/24LC256/24FC256
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24XX256. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX256, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX256 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX256 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command. After a byte
write command, the internal address counter will point
to the address location following the one that was just
written.
6.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX256 in much the same
way as in a byte write. The exception is that instead of
generating a Stop condition, the master transmits up to
63 additional bytes, which are temporarily stored in the
on-chip page buffer, and will be written into memory
once the master has transmitted a Stop condition.
Upon receipt of each word, the six lower Address
Pointer bits, which form the byte counter, are internally
incremented by one. If the master should transmit more
than 64 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an inter-
nal write cycle will begin (Figure 6-2). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command.
6.3 Write Protection
The WP pin allows the user to write-protect the entire
array (0000-7FFF) when the pin is tied to VCC. If tied to
VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every write command
(Figure 1-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note: When doing a write of less than 64 bytes,
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
Note: Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of page size – 1. If a
page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is, therefore, necessary for
the application software to prevent page
write operations that would attempt to
cross a page boundary.
24AA256/24LC256/24FC256
DS20001203W-page 12 1998-2019 Microchip Technology Inc.
FIGURE 6-1: BYTE WRITE
FIGURE 6-2: PAGE WRITE
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput). Once the Stop condition for a write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a write command (R/W =0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be resent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for
flow diagram.
FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
x
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte Data
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
x = “don’t care” bit
S1010 0
A
2A
1A
0P
x
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte Data Byte 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte 63
A
C
K
x = “don’t care” bit
S1010 0
A
2A
1A
0P
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
1998-2019 Microchip Technology Inc. DS20001203W-page 13
24AA256/24LC256/24FC256
8.0 READ OPERATION
Read operations are initiated in much the same way as
write operations, with the exception that the R/W bit of
the control byte is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX256 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX256 issues an Acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX256 discontinues transmission (Figure 8-1).
FIGURE 8-1: CURRENT ADDRESS
READ
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XX256 as part of a write operation (R/W bit set
to ‘0’). Once the word address is sent, the master gen-
erates a Start condition following the Acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a one.
The 24XX256 will then issue an Acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, though it does generate a
Stop condition, which causes the 24XX256 to discon-
tinue transmission (Figure 8-2). After a random read
command, the internal address counter will point to the
address location following the one that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX256 transmits
the first data byte, the master issues an Acknowledge
(as opposed to the Stop condition used in a random
read). This Acknowledge directs the 24XX256 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an Acknowledge,
but will generate a Stop condition.
To provide sequential reads, the 24XX256 contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation. The internal Address
Pointer will automatically roll over from address 7FFF
to address 0000 if the master acknowledges the byte
received from the array address 7FFF.
FIGURE 8-2: RANDOM READ
Bus Activity
Master
SDA Line
Bus Activity
P
S
S
T
O
P
Control
Byte
S
T
A
R
T
Data
A
C
K
N
O
A
C
K
1100
AAA1
Byte
210
x
Bus Activity
Master
SDA Line
Bus Activity
A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Control
Byte
Data
Byte
S
T
A
R
T
x = “don’t care” bit
S1010AAA0
210 S1010AAA
1
210 P
24AA256/24LC256/24FC256
DS20001203W-page 14 1998-2019 Microchip Technology Inc.
FIGURE 8-3: SEQUENTIAL READ
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte Data (n) Data (n + 1) Data (n + 2) Data (n + x)
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
1998-2019 Microchip Technology Inc. DS20001203W-page 15
24AA256/24LC256/24FC256
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example
8-Lead SOIC (3.90 mm) Example
XXXXXXXX
XXXXYYWW
NNN
8-Lead SOIJ (5.28 mm) Example
24LC256
192613F
I/SM
24AA256
I/P 13F
1926
XXXXXXXX
YYWWNNN
XXXXXXXX
24LC256I
SN 1926
13F
3
e
3
e
3
e
8-Lead DFN-S Example
XXXXXXX
XXXXXXX
YYWW
24LC256
I/MF
1926
13F
NNN
3
e
8-Lead MSOP Example
XXXXXX
YWWNNN
4L256I
92613F
24AA256/24LC256/24FC256
DS20001203W-page 16 1998-2019 Microchip Technology Inc.
Package Marking Information (Continued)
8-Lead TSSOP Example
XXXX
XYWW
NNN
4LD
I926
13F
8-Lead Chip Scale
XXX
XYYW
Example
249
613F
WNNN
A192
8-Lead TDFN Example
XXX
YWW
EF4
1926
13
NN
Part
No.
1st Line Marking Codes
DFN MSOP PDIP SOIC SOIJ TDFN TSSOP CSP
I-Temp. E-Temp.
24AA256 24AA256 4A256T(1)24AA256 24AA256T(1)24AA256 EF6 EF5 4AD 249
24LC256 24LC256 4L256T(1)24LC256 24LC256T(1)24LC256 EF4 EF3 4LD —
24FC256 24FC256 4F256T(1)24FC256 24FC256T(1)24FC256 EF8 — 4FD —
Note 1: T = Temperature grade (I, E)
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
* Standard OTP marking consists of Microchip part number, year code, week code and
traceability code.
Note: For very small packages with no room for the JEDEC® designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
1998-2019 Microchip Technology Inc. DS20001203W-page 17
24AA256/24LC256/24FC256
!"#
$
$
NOTE 2
A1
A
A3
NOTE 1 12
E
N
D
EXPOSED PAD
NOTE 1
21
E2
L
N
e
b
K
BOTTOM VIEW
TOP VIEW
D2
24AA256/24LC256/24FC256
DS20001203W-page 18 1998-2019 Microchip Technology Inc.
$
1998-2019 Microchip Technology Inc. DS20001203W-page 19
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203W-page 20 1998-2019 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2019 Microchip Technology Inc. DS20001203W-page 21
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203W-page 22 1998-2019 Microchip Technology Inc.
B
A
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
eB
E
A
A1
A2
L
8X b
8X b1
D
E1
c
C
PLANE
.010 C
12
N
NOTE 1
TOP VIEW
END VIEWSIDE VIEW
e
1998-2019 Microchip Technology Inc. DS20001203W-page 23
24AA256/24LC256/24FC256
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e.100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c.008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b.014 .018 .022
Overall Row Spacing eB - - .430
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
3.
1.
protrusions shall not exceed .010" per side.
2.
4.
Notes:
§
--
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Pin 1 visual index feature may vary, but must be located within the hatched area.
§ Significant Characteristic
Dimensioning and tolerancing per ASME Y14.5M
e
DATUM A DATUM A
e
b
e
2
b
e
2
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
24AA256/24LC256/24FC256
DS20001203W-page 24 1998-2019 Microchip Technology Inc.
0.25 CA–B D
C
SEATING
PLANE
TOP VIEW
SIDE VIEW
VIEW A–A
0.10 C
0.10 C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2
8X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
12
N
h
h
A1
A2
A
A
B
e
D
E
E
2
E1
2
E1
NOTE 5
NOTE 5
NX b
0.10 CA–B
2X
H0.23
(L1)
L
R0.13
R0.13
VIEW C
SEE VIEW C
NOTE 1
D
1998-2019 Microchip Technology Inc. DS20001203W-page 25
24AA256/24LC256/24FC256
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Foot Angle 0° - 8°
15°-5°Mold Draft Angle Bottom
15°-5°
Mold Draft Angle Top
0.51-0.31
b
Lead Width
0.25-0.17
c
Lead Thickness
1.27-0.40LFoot Length
0.50-0.25hChamfer (Optional)
4.90 BSCDOverall Length
3.90 BSCE1Molded Package Width
6.00 BSCEOverall Width
0.25-0.10
A1
Standoff
--1.25A2Molded Package Thickness
1.75--AOverall Height
1.27 BSC
e
Pitch
8NNumber of Pins
MAXNOMMINDimension Limits
MILLIMETERSUnits
protrusions shall not exceed 0.15mm per side.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
4. Dimensioning and tolerancing per ASME Y14.5M
Notes:
§
Footprint L1 1.04 REF
5. Datums A & B to be determined at Datum H.
24AA256/24LC256/24FC256
DS20001203W-page 26 1998-2019 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Microchip Technology Drawing C04-2057-SN Rev B
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Contact Pitch
MILLIMETERS
1.27 BSC
MIN
E
MAX
5.40
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
1.55
0.60
NOM
E
X1
C
Y1
SILK SCREEN
1998-2019 Microchip Technology Inc. DS20001203W-page 27
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203W-page 28 1998-2019 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2019 Microchip Technology Inc. DS20001203W-page 29
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203W-page 30 1998-2019 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2019 Microchip Technology Inc. DS20001203W-page 31
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203W-page 32 1998-2019 Microchip Technology Inc.
%&'() !*#
$
1998-2019 Microchip Technology Inc. DS20001203W-page 33
24AA256/24LC256/24FC256
*+,"+-,".,"*/(/ !*"".#
$
$
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
24AA256/24LC256/24FC256
DS20001203W-page 34 1998-2019 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2019 Microchip Technology Inc. DS20001203W-page 35
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203W-page 36 1998-2019 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2019 Microchip Technology Inc. DS20001203W-page 37
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203W-page 38 1998-2019 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Revision W (08/2019)
Updated content throughout for clarification.
Revision V (08/2018)
Updated First Line Marking Codes table.
Revision U (11/2013)
Updated ICCS.
Revision T (04/2013)
Added TDFN Package.
Revision S (12/2012)
Revise Automotive E-temp.
Revision R (07/2011)
Added Chip Scale package.
Revision Q (05/10)
Revised Table 1-1, Table 1-2, Section 6.1; Updated
Package Drawings.
Revision P
Revised Features; Changed 1.8V voltage to 1.7V;
Replaced Package Drawings; Revised markings (8-lead
SOIC); Revised Product ID System.
Revision N
Revised Sections 2.1 and 2.4. Removed 14-Lead
TSSOP Package.
Revision M
Added 1.8V 400 kHz option for 24FC256.
Revision L
Corrections to Section 1.0, Electrical Characteristics.
1998-2019 Microchip Technology Inc. DS20001203W-page 39
24AA256/24LC256/24FC256
THE MICROCHIP WEBSITE
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
•Product Support – Data sheets and errata, appli-
cation notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registra-
tion instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representa-
tive or Field Application Engineer (FAE) for support.
Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the website
at: http://microchip.com/support
1998-2019 Microchip Technology Inc. DS20001203W-page 40
24AA256/24LC256/24FC256
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: 24AA256: 1.7V, 256-Kbit I2C Serial EEPROM
24LC256: 2.5V, 256-Kbit I2C Serial EEPROM
24FC256: 1.7V, High Speed, 256-Kbit I2C Serial
EEPROM
Tape and Reel
Option:
Blank = Standard packaging (tube or tray)
T = Tape and Reel(1)
Temperature
Range:
I= -40C to +85C (Industrial)
E= -40C to +125C (Extended)
Package: MF = Plastic Dual Flat, No Lead Package –
5x6x0.85 mm Body, 8-lead (DFN-S)
MS = Plastic Micro Small Outline Package, 8-lead
(MSOP)
P = Plastic Dual In-Line – 300 mil Body, 8-lead
(PDIP)
SN = Plastic Small Outline - Narrow, 3.90 mm
Body, 8-lead (SOIC)
SM = Plastic Small Outline - Medium, 5.28 mm
Body, 8-lead (SOIJ)
MNY = Plastic Dual Flat, No Lead Package -
2x3x0.8 mm Body, 8-lead (TDFN)
ST = Plastic Thin Shrink Small Outline – 4.4 mm,
8-lead (TSSOP)
CS16K(2) = Chip Scale, 8-lead (CSP)
Examples:
a) 24AA256-I/P: Industrial Temp., 1.7V,
PDIP package.
b) 24AA256T-I/SN: Tape and Reel, Industrial
Temp., 1.7V, SOIC
package.
c) 24AA256-I/ST: Industrial Temp., 1.7V,
TSSOP package.
d) 24AA256-I/MS: Industrial Temp., 1.7V,
MSOP package.
e) 24LC256-E/P: Extended Temp., 2.5V,
PDIP package.
f) 24LC256-I/SN: Industrial Temp., 2.5V,
SOIC package.
g) 24LC256T-I/SN: Tape and Reel, Industrial
Temp., 2.5V, SOIC
package.
h) 24LC256-I/MS: Industrial Temp., 2.5V,
MSOP package.
i) 24FC256-I/P: Industrial Temp., 1.7V, High
Speed, PDIP package.
j) 24FC256-I/SN: Industrial Temp., 1.7V, High
Speed, SOIC package.
k) 24FC256T-I/SN: Tape and Reel, Industrial
Temp., 1.7V, High Speed,
SOIC package.
l) 24AA256T-CS16K: Tape and Reel, Industrial
Temp., 1.7V, Chip Scale
package.
m)24AA256T-E/SN: Tape and Reel, Extended
Temp., 1.7V, SOIC pack-
age.
PART NO. -X /XX
PackageTemperature
Range
Device
[X]
Tape and Reel
Option
(1)
Note 1: Tape and Reel identifier only appears
in the catalog part number descrip-
tion. This identifier is used for order-
ing purposes and is not printed on the
device package. Check with your
Microchip Sales Office for package
availability with the Tape and Reel
option.
2: 16K indicates 160K technology.
3: Contact Microchip for Automotive
grade ordering part numbers.
1998-2019 Microchip Technology Inc. DS20001203W-page 41
24AA256/24LC256/24FC256
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1998-2019, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-4882-2
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
1998-2019 Microchip Technology Inc. DS20001203W-page 42
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
ASIA/PACIFIC
Australia - Sydney
Tel: 61-2-9868-6733
China - Beijing
Tel: 86-10-8569-7000
China - Chengdu
Tel: 86-28-8665-5511
China - Chongqing
Tel: 86-23-8980-9588
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
China - Hong Kong SAR
Tel: 852-2943-5100
China - Nanjing
Tel: 86-25-8473-2460
China - Qingdao
Tel: 86-532-8502-7355
China - Shanghai
Tel: 86-21-3326-8000
China - Shenyang
Tel: 86-24-2334-2829
China - Shenzhen
Tel: 86-755-8864-2200
China - Suzhou
Tel: 86-186-6233-1526
China - Wuhan
Tel: 86-27-5980-5300
China - Xian
Tel: 86-29-8833-7252
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
India - New Delhi
Tel: 91-11-4160-8631
India - Pune
Tel: 91-20-4121-0141
Japan - Osaka
Tel: 81-6-6152-7160
Japan - Tokyo
Tel: 81-3-6880- 3770
Korea - Daegu
Tel: 82-53-744-4301
Korea - Seoul
Tel: 82-2-554-7200
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Malaysia - Penang
Tel: 60-4-227-8870
Philippines - Manila
Tel: 63-2-634-9065
Singapore
Tel: 65-6334-8870
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Thailand - Bangkok
Tel: 66-2-694-1351
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-72400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
05/14/19
