1
®
FN8225.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL90460
Single Volatile 32-Tap XDCP™
Digitally Controlled Potentiometer (XDCP)
The Intersil ISL90460 is a digitally controlled potentiometer
(XDCP). Configured as a variable resistor, the device
consists of a resistor array, wiper switches, a control section,
and volatile memory. The wiper position is controlled by a 2-
pin Up/Down interface.
The potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS and U/D inputs.
The device can be used in a wide variety of applications
including:
• LCD contrast control
• Parameter and bias adjustments
• Industrial and automotive control
• Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
• Laser Diode driver biasing
• Gain control and offset adjustment
Features
• Volatile Solid-State Potentiometer
• 2-pin UP/DN Interface
• DCP Terminal Voltage, 2.7V to 5.5V
• Tempco 35ppm/°C Typical
• 32 Wiper Tap Points
• Low Power CMOS
- Active current 25µA max.
- Supply current 0.3µA
• Available RTOTAL Values = 10kΩ, 50kΩ, 100kΩ
• Temp Range -40°C to +85°C
• Packages
- 5 lead SC-70, SOT-23
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL90460
(5-PIN SOT-23, SC-70)
TOP VIEW
Ordering Information
PART NUMBER RTOTAL PACKAGE
TEMP RANGE
(°C)
ISL90460TIE527 100K SC-70 -40 to +85
ISL90460TIE527Z
(See Note)
100K SC-70
(Pb-free)
-40 to +85
ISL90460UIE527 50K SC-70 -40 to +85
ISL90460UIE527Z
(See Note)
50K SC-70
(Pb-free)
-40 to +85
ISL90460WIE527 10K SC-70 -40 to +85
ISL90460WIE527Z
(See Note)
10K SC-70
(Pb-free)
-40 to +85
ISL90460TIH527 100K SOT-23 -40 to +85
ISL90460TIH527Z
(See Note)
100K SOT-23
(Pb-free)
-40 to +85
ISL90460UIH527 50K SOT-23 -40 to +85
ISL90460UIH527Z
(See Note)
50K SOT-23
(Pb-free)
-40 to +85
ISL90460WIH527 10K SOT-23 -40 to +85
ISL90460WIH527Z
(See Note)
10K SOT-23
(Pb-free)
-40 to +85
Add “-TK” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
VDD
GND
U/D
RH
CS
Data Sheet June 6, 2005
2FN8225.2
June 6, 2005
Block Diagram
Pin Descriptions
SOT-23/SC-70
5-PIN SYMBOL DESCRIPTION
1 VDD Supply voltage
2 GND Ground
3U/D
Up - Down
4CSChip select
5 RH High terminal/Wiper terminal
CONTROL
AND
MEMORY
UP/DOWN
(U/D)
DEVICE SELECT
(CS)
GND (GROUND)
RH
GENERAL
VCC
ISL90460
3FN8225.2
June 6, 2005
Absolute Maximum Ratings Recommended Operating Conditions
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, U/D and VCC with respect to GND . . . . . -1V to +7V
Lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . . 300°C
IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Power rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mW
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation
of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Potentiometer Specifications Over recommended operating conditions unless otherwise stated
SYMBOL PARAMETER CONDITIONS MIN
TYP
(Note 4) MAX UNIT
RTOT End to end resistance W version 8 10 12 kΩ
U version 40 50 60 kΩ
T version 80 100 120 kΩ
VRRH, RL terminal voltages 0 VCC V
Noise Ref: 1kHz -120 dBV
RWWiper Resistance 600 Ω
IWWiper Current 0.6 mA
Resolution 32 Taps
Absolute linearity (Note 1) RH(n)(actual)–RH(n)(expected) ±1 MI
(Note 3)
Relative linearity (Note 2) RH(n+1)–[RH(n)+MI]±0.5MI
(Note 3)
RTOTAL temperature coefficient ±35 ppm/°C
CH/CL/CWPotentiometer capacitances See circuit #3 10/10/25 pF
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (RH(n)(actual)–RH(n)(expected)) = ±1 Ml Maximum.
n = 1 .. 29 only.
2. Relative linearity is a measure of the error in step size between taps = RH(n+1)—[RH(n) + Ml] = ±0.5 Ml, n = 1 .. 29 only.
3. 1 Ml = Minimum Increment = RTOT/31.
4. Typical values are for TA = 25°C and nominal supply voltage.
DC Electrical Specifications Over recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(Note 4) MAX UNIT
ICC VCC active current (Increment) CS = 0V, U/D = fclock = 1MHz and
VCC =3V
25 µA
ISB Standby supply current CS = VCC, U/D = VSS or VCC = 3V 0.3 1 µA
ILI CS input leakage current VIN = VSS to VCC ±1 µA
ILI U/D input leakage current VIN = VSS to VCC ±1 µA
VIH CS, U/D input HIGH voltage VCC x 0.7 V
VIL CS, U/D input LOW voltage VCC x 0.3 V
CIN CS, U/D input capacitance VCC = 3V, VIN = VSS, TA= 25°C,
f=1MHz
10 pF
ISL90460
4FN8225.2
June 6, 2005
Timing Specifications Over recommended operating conditions unless otherwise specified) (Figures 1 and 2)
SYMBOL PARAMETER MIN TYP (Note 4) MAX UNIT
tCU U/D to CS setup 25 ns
tCI CS to U/D setup 50 ns
tIC CS to U/D hold 25 ns
tlL U/D LOW period 300 ns
tlH U/D HIGH period 300 ns
fTOGGLE Up/Down toggle rate 1 MHz
tSETTLE Output settling time 1 µs
CS
U/D
RH
tCU
tCI
tIL
tIH
tIC
tSETTLE
FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM, INCREMENT
CS
U/D
RH
tCU
tCI tIL
tIH
tIC
tSETTLE
FIGURE 2. SERIAL INTERFACE TIMING DIAGRAM, DECREMENT
ISL90460
5FN8225.2
June 6, 2005
Pin Descriptions
RH
The ISL90460 contains a digital potentiometer connected as
a rheostat or variable resistor. The wiper and one terminal of
the digital potentiomerter is tied to the RH pin, and the other
terminal of the potentiometer is tied to the ground pin (GND).
The resistance from the RH pin to ground will vary with the
potentiometer setting; at the highest setting, the resistance
will be the maximum (Rtot), at the lowest setting it will be a
minimum.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in volatile memory when CS
is returned HIGH. When CS is high, the device is placed in
low power standby mode.
Principles of Operation
There are two sections of the ISL90460: the input control,
counter and decode section; and the resistor array. The input
control section operates just like an up/down counter. The
output of this counter is decoded to turn on a single
electronic switch connecting a point on the resistor array to
the wiper output. The resistor array is comprised of 31
individual resistors connected in series. At either end of the
array and between each resistor is an electronic switch that
transfers the connection at that point to the wiper. The wiper
is connected to the RH terminal, forming a variable resistor
from RH to GND.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
If the wiper is moved several positions, multiple taps are
connected to the wiper for tIW (U/D to VW change). The
2-terminal resistance value for the device can temporarily
change by a significant amount if the wiper is moved several
positions.
ISL90460
6FN8225.2
June 6, 2005
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
0.10 R
12° REF.
0.575 REF.
0.108 (2.75) BSC
5-Lead, SOT23, Package Code G5
.019 (0.50)
.012 (0.30)
NOTES:
12
0.065 (1.65)
0.061 (1.55)
0.054 (1.38) BSC
0.075 (1.90) BSC
4X 0.35 HA-BD
2X N/2 TIPS
0.35 CA-BD
C
L
0.007 (0.20)
B
0.0006 (0.15)
B
TYP.
SEATING PLANE
0–8°C
0.20 in
0.10 R MIN.
0.118 (3.00)
0.110 (2.80)
0.038 (0.95)
BSC
Parting Line
Seating Plane
0.0008 (0.02)
0.0040 (0.10)
0.033 (0.85)
0.035 (0.90)
0.043 (1.10) MAX
3. DIMENSIONING AND TOLERANCES PER ASME, Y14.5-1994
4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-193.
MIN.
5. THIS PART IS FULL COMPLIANCE TO EIAJ SPECIFICATION SC-74
ISL90460
7
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8225.2
June 6, 2005
ISL90460
Small Outline Transistor Plastic Packages (SC70-5)
D
e1
E
E1
C
L
C
C
L
eb
C
L
A2
AA1
C
L
0.20 (0.008) M
0.10 (0. 004) C
C
-C-
SEATING
PLANE
45
123
VIEW C
VIEW C
L
R1
R
4X θ1
4X θ1
GAUGE PLANE
L1
SEATING
αL2
C
PLANE
c
B ASE METAL
WITH
c1
b1
PLATING
b
SC70-5
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.031 0.043 0.80 1.10 -
A1 0.000 0.004 0.00 0.10 -
A2 0.031 0.039 0.80 1.00 -
b 0.006 0.012 0.15 0.30 -
b1 0.006 0.010 0.15 0.25
c 0.003 0.009 0.08 0.22 6
c1 0.003 0.009 0.08 0.20 6
D 0.071 0.087 1.80 2.20 3
E 0.071 0.094 1.80 2.40 -
E1 0.045 0.053 1.15 1.35 3
e 0.0256 Ref 0.65 Ref -
e1 0.0512 Ref 1.30 Ref -
L 0.010 0.018 0.26 0.46 4
L1 0.017 Ref. 0.420 Ref. -
L2 0.006 BSC 0.15 BSC
α0° 8° 0° 8° -
N555
R0.004 - 0.10 -
R1 0.004 0.010 0.15 0.25
NOTES:
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
3. Dimensions D and E1 are exclusive of mold flash, protrusions, or
gate burrs.
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
