DEMO MANUAL DC1564A LTC2158-14, LTC2158-12, LTC2157-14, LTC2157-12, LTC2156-14, LTC2156-12, LTC2155-14, LTC2155-12 12-Bit/14-Bit, 170Msps to 310Msps Dual ADCs Description Demonstration circuit 1564A supports a family of 12-/14-bit 170Msps to 310Msps ADCs. Each assembly features one of the following devices: LTC(R)2158-14/ LTC2158-12, LTC2157-14/LTC2157-12, LTC2156-14/ LTC2156-12, LTC2155-14/LTC2155-12, high speed, dual ADCs. The versions of the 1564A demo board are listed in Table 1. Depending on the required resolution and sample rate, the DC1564 is supplied with the appropriate ADC. The circuitry on the analog inputs is optimized for analog input frequencies from 5MHz to 140MHz. Refer to the data sheet for proper input networks for different input frequencies. Design files for this circuit board are available at http://www.linear.com/demo L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Table 1. DC1564A Variants DC1564A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY 1564A-A LTC2157-14 14-Bit 250Msps 5MHz to 140MHz 1564A-B LTC2156-14 14-Bit 210Msps 5MHz to 140MHz 1564A-C LTC2155-14 14-Bit 170Msps 5MHz to 140MHz 1564A-D LTC2157-12 12-Bit 250Msps 5MHz to 140MHz 1564A-E LTC2156-12 12-Bit 210Msps 5MHz to 140MHz 1564A-F LTC2155-12 12-Bit 170Msps 5MHz to 140MHz 1564A-G LTC2158-14 14-Bit 310Msps 5MHz to 140MHz 1564A-H LTC2158-12 12-Bit 310Msps 5MHz to 140MHz Performance Summary (TA = 25C) PARAMETER CONDITION Supply Voltage - DC1564A Depending on Sampling Rate and the A/D Converter Optimized for 3.6V [3V 6.0V Min/Max] Provided, This Supply Must Provide Up to 500mA. VALUE Analog input range Depending on SENSE Pin Voltage 1.5VP-P or 1.32VP-P Logic Input Voltages Minimum Logic High 1.3V Maximum Logic Low 0.6V Logic Output Voltages (Differential) Nominal Logic Levels (100 Load, 3.5mA Mode) 350mV/1.25V Common Mode Minimum Logic Levels (100 Load, 3.5mA Mode) 247mV/1.25V Common Mode Sampling Frequency (Convert Clock Frequency) See Table 1 Encode Clock Level Differential Encode Mode (ENC- Not Tied to GND) Resolution See Table 1 0.2V to 1.9V dc1564afa 1 DEMO MANUAL DC1564A PERFORMANCE SUMMARY (TA = 25C) Input Frequency Range See Table 1 SFDR See Applicable Data Sheet SNR See Applicable Data Sheet Quick Start Procedure Demonstration circuit 1564A is easy to set up to evaluate the performance of the LTC2157 A/D converter family. Refer to Figure 1 for proper measurement equipment setup and follow the procedure below: DC1564A Demonstration Circuit Board Jumpers Setup JP1 - PAR/SER: Selects Parallel or Serial Programming Mode. (Default: Serial) If a DC1371 Data Acquisition and Collection System was supplied with the DC1564A demonstration circuit, follow the DC1371 Quick Start Guide to install the required software and for connecting the DC1371 to the DC1564A and to a PC. The DC1564A demonstration circuit board should have the following jumper settings as default positions: (as per Figure 1) Applying Power and Signals to the DC1564A Demonstration Circuit The DC1371 is used to acquire data from the DC1564A, the DC1371 must first be connected to a powered USB port and have 5V applied power before applying 3.6V to 3.6V TO 6V TO PROVIDED POWER SUPPLY PARALLEL/SERIAL ANALOG INPUTS TO PROVIDED USB CABLE CHANNEL 1 CHANNEL 2 SINGLE-ENDED ENCODE CLOCK (USE A LOW JITTER SIGNAL GENERATOR WITH PROPER FILTERING) Figure 1. DC1564A Setup (Zoom for Detail) dc1564afa 2 DEMO MANUAL DC1564A quick start procedure 6.0V across the pins marked V+ and GND on the DC1564A. The DC1564 requires 3.6V for proper operation. Regulators on the board produce the voltages required for the ADC. The DC1564A demonstration circuit requires up to 500mA depending on the sampling rate and the A/D converter supplied. The DC1564A should not be removed, or connected to the DC1371 while power is applied. Analog Input Network For optimal distortion and noise performance the RC network on the analog inputs may need to be optimized for different analog input frequencies. For input frequencies above 140MHz, refer to the respective ADC data sheet for a proper input network. Other input networks may be more appropriate for input frequencies less that 5MHz. In almost all cases, filters will be required on both analog input and encode clock to provide data sheet SNR. The filters should be located close to the inputs to avoid reflections from impedance discontinuities at the driven end of a long transmission line. Most filters do not present 50 outside the passband. In some cases, 3dB to 10dB pads may be required to obtain low distortion. If your generator cannot deliver full-scale signals without distortion, you may benefit from a medium power amplifier based on a Gallium Arsenide Gain block prior to the final filter. This is particularly true at higher frequencies where IC-based operational amplifiers may be unable to deliver the combination of low noise figure and high IP3 point required. A high order filter can be used prior to this final amplifier, and a relatively lower Q filter used between the amplifier and the demo circuit. Apply the analog input signal of interest to the SMA connectors on the DC1564A demonstration circuit board marked J2 AINA and J3 AINB. These inputs correspond with channels one and two of the ADC respectively. These inputs are capacitively coupled to Balun transformers ETC1-1-13 (lead free part number: MABA007159-000000). Encode Clock Note: Apply an encode clock to the SMA connector on the DC1564A demonstration circuit board marked J4 CLK+. As a default the DC1564A is populated to have a single-ended input. For the best noise performance, the encode input must be driven with a very low jitter, sine wave source. The amplitude should be large, up to 3VP-P or 13dBm. Using bandpass filters on the clock and the analog input will improve the noise performance by reducing the wideband noise power of the signals. Data sheet FFT plots are taken with 10-pole LC filters made by TTE (Los Angeles, CA) to suppress signal generator harmonics, non-harmonically related spurs and broadband noise. Low phase noise Agilent 8644B generators are used for both the clock input and the analog input. Digital Outputs The data outputs, data clock, and frame clock signals are available on J1 of the DC1564A. This connector follows the VITA-57/FMC standard, but all signals should be verified when using an FMC carrier card other than the DC1371. Software The DC1371 is controlled by the PScopeTM system software provided or downloaded from the Linear Technology website at http://www.linear.com/software/. To start the data collection software, if PScope.exe is installed (by default) in \Program Files\LTC\PScope\, double click the PScope icon or bring up the run window under the start menu and browse to the PScope directory and select PScope. If the DC1564A demonstration circuit is properly connected to the DC1371, PScope should automatically detect the DC1564A, and configure itself accordingly. If everything is hooked up properly, powered, and a suitable convert clock is present, clicking the Collect button will result in time and frequency plots displayed in the PScope window. Additional information and help for PScope is available in the DC1371 Quick Start Guide and in the online help available within the PScope program itself. dc1564afa 3 DEMO MANUAL DC1564A quick start procedure Serial Programming Figure 2. PScope Toolbar PScope has the ability to program the DC1564A board serially through the DC1371. There are several options available in the LTC2158 family that are only available through serially programming. PScope allows all of these features to be tested. These options are available by first clicking on the Set Demo Bd Options icon on the PScope toolbar (Figure 2). This will bring up the menu shown in Figure 3. This menu allows any of the options available for the LTC2158 family to be programmed serially. The LTC2158 family has the following options: Sleep Mode - Selects between normal operation, sleep mode: * Off (Default) - Entire ADC is powered and active * On - The entire ADC is powered down NAP - Selects between normal operation and nap mode. * Off (Default) - Channel one is active * On - Channel one is in nap mode Power Down B - Selects between normal operation and putting channel B in nap mode. * Off (Default) - Channel two is active * On - Channel two is in nap mode Clock Inversion - Selects the polarity of the CLKOUT signal: * Normal (Default) - Normal CLKOUT polarity * Inverted - CLKOUT polarity is inverted Clock Delay - Selects the phase delay of the CLKOUT signal: * None (Default) - No CLKOUT delay Figure 3. Demobd Configuration Options * 45 deg - CLKOUT delayed by 45 degrees * 90 deg - CLKOUT delayed by 90 degrees * 135 deg - CLKOUT delayed by 135 degrees Clock Duty Cycle - Enable or disables duty cycle stabilizer. * Stabilizer off (Default) - Duty cycle stabilizer disabled * Stabilizer on - Duty cycle stabilizer enabled dc1564afa 4 DEMO MANUAL DC1564A quick start procedure Output Current - Selects the LVDS output drive current. Alternate Bit - Alternate bit polarity mode. * 1.75mA (Default) - LVDS output driver current * Off (Default) - Disables alternate bit polarity * 2.1mA - LVDS output driver current * On - Enables alternate bit polarity (Before enabling ABP, be sure the part is in offset binary mode) * 2.5mA - LVDS output driver current * 3.0mA - LVDS output driver current * 3.5mA - LVDS output driver current * 4.0mA - LVDS output driver current * 4.5mA - LVDS output driver current Internal Termination - Enables LVDS internal termination. * Off (Default) - Disables internal termination * On - Enables internal termination Outputs - Enables digital outputs * Enabled (Default) - Enables digital outputs * Disabled - Disables digital outputs Test Pattern - Selects digital output test patterns. * All out = 0 (default) - All digital outputs are 0 TP Enable - Selects Digital output test patterns. The desired test pattern can be entered into the text boxes provided. * Off (default) - ADC input data is displayed * On - Test pattern is displayed Randomizer - Enables data output randomizer. * Off (Default) - Disables data output randomizer * On - Enables data output randomizer Two's Complement - Enables two's complement mode. * Off (Default) - Selects offset binary mode * On - Selects two's complement mode Once the desired settings are selected hit OK and PScope will automatically update the register of the device on the DC1564 demo board. * All out = 1 - All digital outputs are 1 * Checkerboard - OF, and D13-D0 Alternate between 101 0101 1010 0101 and 010 1010 0101 1010 on alternating samples. * Alternating - Digital outputs alternate between all 1's and all 0's on alternating samples dc1564afa 5 DEMO MANUAL DC1564A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER LTC215XCUPX Family 1 4 C1, C2, C25, C26 CAP., X7R, 0.01F, 50V, 10% 0603 AVX, 06035C103KAQ2A 2 2 C3, C27 CAP., C0G, 1pF, 50V, 5% 0402 AVX, 04025A1R0JAT2A 3 11 C4, C5, C7, C11, C12, C13, C14, C29, C52, C69, C71 CAP., X5R, 0.1F, 10V, 10% 0402 AVX, 0402ZD104KAQ2A 4 4 C8, C9, C31, C32 CAP., C0G, 3.9pF, 50V, 5% 0402 AVX, 04025A3R9JAT2A 5 2 C17, C62 CAP., X5R, 2.2F, 10V, 20% 0603 AVX, 0603ZD225MAT2A 6 3 C39, C59, C60 CAP., X5R, 1F, 10V, 10% 0402 AVX, 0402ZD105KAT2A 7 4 C43, C44, C45, C49 CAP., X7R, 0.01F, 16V, 10% 0402 AVX, 0402YC103KAQ2A 8 11 C48, R57, R58, R59, R60, R61, R62, R64, R65, R76, R77 OPT 402 9 1 C63 CAP., TANT, 100F, 10% 6032 AVX, TAJW107K010R 10 1 C64 CAP., X7R, 47F, 10V, 10%, 1210 MURATA, GRM32ER71A476KE15L 11 4 C65, C66, C67, C68 CAP., C0G, 47pF, 16V, 10% 0402 AVX, 0402YA470KA 12 3 E1, E2, E3 TESTPOINT, TURRET, 0.094" MILL-MAX, 2501-2-00-80-00-00-07-0 13 1 JP1 3-PIN 0.079" SINGLE ROW HEADER SAMTEC, TMM103-02-L-S 14 1 JP2 HEADER, 2-PIN 0.079" SINGLE ROW SAMTEC, TMM-102-02-L-S SHUNT, 0.079" CENTER SAMTEC, 2SN-BK-G 16 1 J1 BGA CONNECTOR, 40x10 SAMTEC, SEAM-40-02.0-S-10-2-A 17 1 J1 UNUSED CON-SEAM-10X40PIN 18 2 J2, J3 CON., SMA 50 EDGE-LANCH E.F.JOHNSON, 142-0701-851 19 2 J4, J5 CON., SMA 50 STRAIGHT MOUNT CONNEX., 132134 20 2 L1, L4 INDUCTOR, 18nH 0603 MURATA, LQP18MN18NG02D 21 1 L7 OPT, 0603 22 2 L9, L11 FERRITE BEAD, 1206 MURATA, BLM31PG330SN1L 23 4 R1, R2, R26, R29 RES., CHIP, 33.2, 1/16W, 1% 0402 VISHAY, CRCW040233R2FKED 24 4 R6, R7, R33, R34 RES., CHIP, 10, 1/16W, 5% 0402 VISHAY, CRCW040210R0JNED 25 3 R8, R12, R56 RES., CHIP, 100, 1/16W, 5% 0402 VISHAY, CRCW0402100RJNED 26 2 R9, R35 RES., CHIP, 43.2, 1/16W, 1% 0402 VISHAY, CRCW040243R2FKED 27 4 R10, R11, R37, R38 RES., CHIP, 43.2, 1/16W, 1% 0603 VISHAY, CRCW060343R2FNEA 28 6 R14, R39, R72, R73, R74, R75 RES., CHIP, 1k 1/16W, 1% 0402 VISHAY, CRCW04021K00FKED 29 3 R36, R44, R45 RES., CHIP, 5.1k 1/16W, 1%, 0402 VISHAY,CRCW04025K10FKED 30 2 R40, R41 RES., CHIP, 49.9, 1/16W, 1% 0402 VISHAY, CRCW040249R9FKED 31 2 R42, R43 RES., CHIP, 5.1, 1/16W, 5% 0402 VISHAY, CRCW04025R10JNED 32 3 R63, R78, R79 RES., CHIP, 0, 1/16W, 0402 VISHAY, CRCW04020000Z0ED 33 1 R66 RES., CHIP, 182k, 1/16W, 1% 0402 VISHAY, CRCW0402182KFKED 34 1 R67 RES., CHIP, 3.01k 1/16W, 1%, 0402 VISHAY,CRCW04023K010FKED 35 2 R68, R69 RES., CHIP, 49.9, 1/16W, 5% 0402 VISHAY, CRCW040249R9JNED 36 2 T1, T8 TRANSFORMER, WBC1-1L COILCRAFT, WBC1-1L 37 3 T2, T5, T9 TRANSFORMER, MABA-007159-000000 M/A-COM, MABA-007159-000000 38 1 U3 I.C. LT3080EDD, DFN 3X3 LINEAR TECH., LT3080EDD 39 1 U6 I.C., Serial EEPROM TSSOP-8 MICROCHIP, 24LC32A-I/ST 40 4 (STAND-OFF) STAND-OFF, NYLON 0.25" KEYSTONE, 8831(SNAP ON) 15 dc1564afa 6 DEMO MANUAL DC1564A parts list ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER LTC2157CUP-14/DC1564A-A 1 1 DC1564A GENERAL BOM 2 1 U1 I.C. LTC2157CUP-14, 64-PIN QFN-9X9 LINEAR, LTC2157CUP-14 3 1 FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1564A LTC2156CUP-14/DC1564A-B 1 1 DC1564A GENERAL BOM 2 1 U1 I.C. LTC2156CUP-14, 64-PIN QFN-9X9 LINEAR, LTC2156CUP-14 3 1 FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1564A LTC2155CUP-14/DC1564A-C 1 1 DC1564A GENERAL BOM 2 1 U1 I.C. LTC2155CUP-14, 64-PIN QFN-9X9 LINEAR, LTC2155CUP-14 3 1 FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1564A LTC2157CUP-12/DC1564A-D 1 1 DC1564A GENERAL BOM 2 1 U1 I.C. LTC2157CUP-12, 64-PIN QFN-9X9 LINEAR, LTC2157CUP-12 3 1 FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1564A LTC2156CUP-12/DC1564A-E 1 1 DC1564A GENERAL BOM 2 1 U1 I.C. LTC2156CUP-12, 64-PIN QFN-9X9 LINEAR, LTC2156CUP-12 3 1 FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1564A LTC2155CUP-12/DC1564A-F 1 1 DC1564A GENERAL BOM 2 1 U1 I.C. LTC2155CUP-12, 64-PIN QFN-9X9 LINEAR, LTC2157CUP-12 3 1 FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1564A LTC2158CUP-14/DC1564A-G 1 1 DC1564A-A GENERAL BOM 2 1 U1 I.C. LTC2158CUP-14, 64-PIN QFN-9X9 LINEAR, LTC2158CUP-14 3 1 FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1564A LTC2158CUP-12/DC1564A-H 1 1 DC1564A-A GENERAL BOM 2 1 U1 I.C. LTC2158CUP-12, 64-PIN QFN-9X9 LINEAR, LTC2158CUP-12 3 1 FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1564A dc1564afa 7 A B C D E1 E2 C64 47uF CLK- CLK+ AINB AINA SENSE SER PAR J5 J4 J3 J2 E3 JP1 2 PAR/SER GND V+ 3V-6V 1 3 5 0.01uF 0603 C1 0.01uF 0603 C25 R39 1K C26 0.01uF 0603 3 2 1 C9 3.9pF C8 3.9pF 0 OPT R63 R62 R61 3 2 1 OPT C2 0.01uF 0603 4 5 C43 0.01uF 0.01uF C44 T1 WBC1-1L 6 4 T8 WBC1-1L 6 4 4 9 3 2 1 4 T5 C71 0.1uF R77 OPT C69 0.1uF R76 OPT 1. ALL RESISTORS ARE IN 0402 ALL CAPACITORS ARE IN 0402 4 C62 2.2uF 0603 OPT R64 4 5 3 2 1 OPT R65 C45 0.01uF R69 50 R68 50 C63 + 100uF MABA-007159-000000 1 2 3 1 2 3 C60 0.1uF R66 182K NOTE: UNLESS OTHERWISE SPECIFIED R11 43.2 0603 C49 0.01uF 4 5 T2 MABA-007159-000000 18nH R10 0603 43.2 0603 L1 43.2 C32 3.9pF R9 U3 LT3080EDD SET OUT OUT OUT OUT T9 MABA-007159-000000 VCTRL IN C31 3.9pF 5 8 R38 43.2 0603 L4 43.2 C39 1.0uF IN 18nH R37 0603 43.2 0603 R35 VDD C59 1.0uF 7 6 NC 5 R40 49.9 R41 49.9 R2 60.4 R1 60.4 R29 60.4 R26 60.4 5.1 R7 0 R33 0 C27 1.0pF R34 0 R6 0 3 OPT C48 R59 OPT 100 R56 OPT 0603 L7 VDD VDD VDD VDD GND R79 0 R78 0 VDD 15 16 65 VDD VDD VDD GND AINA+ AINAGND SENSE VREF GND VCM GND AINBAINB+ GND CUSTOMER NOTICE R57 OPT R58 OPT OPT R60 AINB- AINB+ C29 0.1uF 2.2uF C4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDD R14 1K CS SCK SDI SDO 2 VDD U1* APPROVALS THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 2 SCALE = NONE LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. AK VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APP ENG. CLARENCE M. APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. R12 100 R8 100 SENSE C14 0.1uF C17 2.2uF 0603 SENSE C13 0.1uF OVDD VDD C52 0.1uF L11 33 Ohm FB C3 1.0pF R42 5.1 R43 R67 3K 3 L9 0 OHhm RES 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LTC2157CUP-12 -D DATE: N/A SIZE BITS OF+ DB0_1+ DB2_3+ DB4_5+ DB6_7+ DB8_9+ DB10_11+ DB12_13+ CLKOUT+ DA0_1+ DATE 310 310 170 210 250 170 210 250 OF- DB0_1- DB2_3- DB4_5- DB6_7- DB8_9- DB10_11- DB12_13- CLKOUT- DA0_1- DA2_3- DA4_5- DA6_7- DA8_9- DA10_11- DA12_13- 1 DEMO CIRCUIT 1564A SHEET 1 LTC215XCUP FAMILY OF 2 3 REV. 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only 12 14 12 12 12 14 14 MSPS DA6_7+ DA8_9+ DA10_11+ DA12_13+ DA2_3+ 14 APPROVED CLARENCE M. 8-18-11 LOW POWER DUAL ADC FAMILY Thursday, August 18, 2011 IC NO. 1 DA4_5+ C12 0.47uF TECHNOLOGY LTC2158CUP-12 LTC2158CUP-14 -G -H LTC2155CUP-12 -F LTC2156CUP-12 LTC2155CUP-14 -C -E LTC2156CUP-14 LTC2157CUP-14 U1 C11 0.1uF 3RD PROTOTYPE DESCRIPTION REVISION HISTORY -B -A ASSY OVDD OGND DA4_5+ DA4_5DA2_3+ DA2_3DA0_1+ DA0_1CLKOUT+ CLKOUTDB12_13+ DB12_13DB10_11+ DB10_11DB8_9+ DB8_9OGND C7 0.47uF 3 REV TITLE: SCHEMATIC * __ ECO OVDD C5 0.1uF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDD PAR_SER CS SCK SDI SDO GND DA12_13+ DA12_13DA10_11+ DA10_11DA8_9+ DA8_9DA6_7+ DA6_7OVDD VDD GND CLK+ CLKGND OFOF+ DBO_1DBO_1+ DB2_3DB2_3+ DB4_5DB4_5+ DB6_7DB6_7+ OVDD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 8 V+ A B C D DEMO MANUAL DC1564A Schematic Diagram dc1564afa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. A B C D GND DP1_M2C_P DP1_M2C_N GND GND DP2_M2C_P DP2_M2C_N GND GND DP3_M2C_P DP3_M2C_N GND GND DP4_M2C_P DP4_M2C_N GND GND DP5_M2C_P DP5_M2C_N GND GND DP1_C2M_P DP1_C2M_N GND GND DP2_C2M_P DP2_C2M_N GND GND DP3_C2M_P DP3_C2M_N GND GND DP4_C2M_P DP4_C2M_N GND GND DP5_C2M_P DP5_C2M_N GND SEAM-10X40PIN J1A DB2_3- DB6_7- DB10_11- DA2_3- DA6_7- DA10_11- A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 5 RES1 GND GND DP9_M2C_P DP9_M2C_N GND GND DP8_M2C_P DP8_M2C_N GND GND DP7_M2C_P DP7_M2C_N GND GND DP6_M2C_P DP6_M2C_N GND GND GBTCLK1_M2C_P GBTCLK1_M2C_N GND GND DP9_C2M_P DP9_C2M_N GND GND DP8_C2M_P DP8_C2M_N GND GND DP7_C2M_P DP7_C2M_N GND GND DP6_C2M_P DP6_C2M_N GND GND RES0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 SEAM-10X40PIN VREF_A_M2C PRSNT_M2C_N GND CLK0_M2C_P CLK0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N GND LA32_P LA32_N GND VADJ J1H SEAM-10X40PIN J1B DB2_3+ DB6_7+ DB10_11+ DA2_3+ DA6_7+ DA10_11+ H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 PG_M2C GND GND HA00_P_CC HA00_N_CC GND HA04_P HA04_N GND HA08_P HA08_N GND HA12_P HA12_N GND HA15_P HA15_N GND HA19_P HA19_N GND HB02_P HB02_N GND HB04_P HB04_N GND HB08_P HB08_N GND HB12_P HB12_N GND HB16_P HB16_N GND HB19_P HB19_N GND VADJ SEAM-10X40PIN J1F OF- DB0_1- DB4_5- DB8_9- DB12_13- DA0_1- DA4_5- DA8_9- DA12_13- 4 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 VDD OF+ DB0_1+ DB4_5+ DB8_9+ DB12_13+ DA0_1+ DA4_5+ DA8_9+ DA12_13+ GND HA01_P_CC HA01_N_CC GND GND HA05_P HA05_N GND HA09_P HA09_N GND HA13_P HA13_N GND HA16_P HA16_N GND HA20_P HA20_N GND HB03_P HB03_N GND HB05_P HB05_N GND HB09_P HB09_N GND HB13_P HB13_N GND HB21_P HB21_N GND HB20_P HB20_N GND VADJ GND E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 SEAM-10X40PIN GND CLK0_C2M_P CLK0_C2M_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND J1G SEAM-10X40PIN J1E G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 3 GND CLK1_C2M_P CLK1_C2M_N GND GND HA03_P HA03_N GND HA07_P HA07_N GND HA11_P HA11_N GND HA14_P HA14_N GND HA18_P HA18_N GND HA22_P HA22_N GND HB01_P HB01_N GND PB07_P HB07_N GND HB11_P HB11_N GND HB15_P HB15_N GND HB18_P HB18_N GND VIO_B_M2C GND SEAM-10X40PIN J1J VREF_B_M2C GND GND CLK1_M2C_P CLK1_M2C_N GND HA02_P HA02_N GND HA06_P HA06_N GND HA10_P HA10_N GND HA17_P_CC HA17_N_CC GND HA21_P HA21_N GND HA23_P HA23_N GND HB00_P_CC HB00_N_CC GND HB06_P_CC HB06_N_CC GND HB10_P HB10_N GND HB14_P HB14_N GND HB17_P_CC HB17_N_CC GND VIO_B_M2C K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40 CS THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 2 SCALE = NONE 6 5 7 3 2 1 2 R45 5K 1K R75 C67 47pF 1K DATE: N/A SIZE 1 1 DEMO CIRCUIT 1564A SHEET 2 LTC215XCUP FAMILY LOW POWER DUAL ADC FAMILY OF 2 3 REV. 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only SEAM-10X40PIN GND DP0_C2M_P DP0_C2M_N GND GND DP0_M2C_P DP0_M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND J1C Wednesday, December 08, 2010 IC NO. R36 5K C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 TECHNOLOGY WP JP2 R44 5K 1K R74 R73 1K R72 TITLE: SCHEMATIC SCL SDA WP A2 A1 A0 C65 47pF C66 47pF C68 47pF SCK SDI SDO APPROVALS U6 24LC32A-I /ST SEAM-10X40PIN PG_C2M GND GND GBTCLK0_M2C_P GBTCLK0_M2C_N GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_N GA1 3P3V GND 3P3V GND 3P3V J1D CUSTOMER NOTICE SEAM-10X40PIN J1K CLKOUT+ D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 2 LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. AK VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APP ENG. CLARENCE M. APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 CLKOUT- 3 8 VCC VSS 4 4 1 5 A B C D DEMO MANUAL DC1564A Schematic Diagram dc1564afa 9 DEMO MANUAL DC1564A DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright (c) 2004, Linear Technology Corporation dc1564afa 10 Linear Technology Corporation LT 1211 REV A * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2011