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80C186EC/80C188EC AND 80L186EC/80L188EC

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

XFully Static Operation

XTrue CMOS Inputs and Outputs

YIntegrated Feature Set:

Ð Low-Power, Static, Enhanced 8086

CPU Core

Ð Two Independent DMA Supported

UARTs, each with an Integral Baud

Rate Generator

Ð Four Independent DMA Channels

Ð 22 Multiplexed I/O Port Pins

Ð Two 8259A Compatible

Programmable Interrupt Controllers

Ð Three Programmable 16-Bit Timer/

Counters

Ð 32-Bit Watchdog Timer

Ð Ten Programmable Chip Selects with

Integral Wait-State Generator

Ð Memory Refresh Control Unit

Ð Power Management Unit

Ð On-Chip Oscillator

Ð System Level Testing Support

(ONCE Mode)

YDirect Addressing Capability to 1 Mbyte

Memory and 64 Kbyte I/O

YLow-Power Operating Modes:

Ð Idle Mode Freezes CPU Clocks but

Keeps Peripherals Active

Ð Powerdown Mode Freezes All

Internal Clocks

Ð Powersave Mode Divides All Clocks

by Programmable Prescalar

YAvailable in Extended Temperature

Range (b40§Ctoa

85§C)

YSupports 80C187 Numerics Processor

Extension (80C186EC only)

YPackage Types:

Ð 100-Pin EIAJ Quad Flat Pack (QFP)

Ð 100-Pin Plastic Quad Flat Pack

(PQFP)

Ð 100-Pin Shrink Quad Flat Pack

(SQFP)

YSpeed Versions Available (5V):

Ð 25 MHz (80C186EC25/80C188EC25)

Ð 20 MHz (80C186EC20/80C188EC20)

Ð 13 MHz (80C186EC13/80C188EC13)

YSpeed Version Available (3V):

Ð 16 MHz (80L186EC16/80L188EC16)

Ð 13 MHz (80L186EC13/80L188EC13)

The 80C186EC is a member of the 186 Integrated Processor Family. The 186 Integrated Processor Family

incorporates several different VLSI devices all of which share a common CPU architecture: the 8086/8088.

The 80C186EC uses the latest high density CHMOS technology to integrate several of the most common

system peripherals with an enhanced 8086 CPU core to create a powerful system on a single monolithic

silicon die.

80C186EC/80C188EC and 80L186EC/80L188EC

16-BIT HIGH-INTEGRATION

EMBEDDED PROCESSOR

CONTENTS PAGE

INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4

80C186EC CORE ARCHITECTURE ÀÀÀÀÀÀÀ 4

Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4

Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4

80C186EC PERIPHERAL

ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

Programmable Interrupt Controllers ÀÀÀÀÀÀÀÀÀ 7

Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Serial Communications Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

DMA Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Chip-Select Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

I/O Port Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Watchdog Timer Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Power Management Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

80C187 Interface (80C186EC only) ÀÀÀÀÀÀÀÀÀ 8

ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

Prefix Identification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

Pinout ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

Package Thermal Specifications ÀÀÀÀÀÀÀÀÀÀÀ 24

ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 25

Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

CONTENTS PAGE

Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26

ICC versus Frequency and Voltage ÀÀÀÀÀÀÀÀÀ 29

PDTMR Pin Delay Calculation ÀÀÀÀÀÀÀÀÀÀÀÀÀ 29

AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

AC CharacteristicsÐ80C186EC25 ÀÀÀÀÀÀÀÀÀ 30

AC CharacteristicsÐ80C186EC20/13 ÀÀÀÀÀ 32

AC CharacteristicsÐ80L186EC13 ÀÀÀÀÀÀÀÀÀ 33

AC CharacteristicsÐ80L186EC16 ÀÀÀÀÀÀÀÀÀ 34

Relative Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35

Serial Port Mode 0 Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36

AC TEST CONDITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37

AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37

DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40

RESET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40

BUS CYCLE WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43

EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50

INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 51

ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57

REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57

80C186EC/188EC, 80L186EC/188EC

272434–1

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC

Figure 1. 80C186EC/80L186EC Block Diagram

80C186EC/188EC, 80L186EC/188EC

INTRODUCTION

Unless specifically noted, all references to the

80C186EC apply to the 80C188EC, 80L186EC, and

80L188EC. References to pins that differ between

the 80C186EC/80L186EC and the 80C188EC/

80L188EC are given in parentheses. The ‘‘L’’ in the

part number denotes low voltage operation. Physi-

cally and functionally, the ‘‘C’’ and ‘‘L’’ devices are

identical.

The 80C186EC is one of the highest integration

members of the 186 Integrated Processor Family.

Two serial ports are provided for services such as

interprocessor communication, diagnostics and mo-

dem interfacing. Four DMA channels allow for high

speed data movement as well as support of the on-

board serial ports. A flexible chip select unit simpli-

fies memory and peripheral interfacing. The three

general purpose timer/counters can be used for a

variety of time measurement and waveform genera-

tion tasks. A watchdog timer is provided to insure

system integrity even in the most hostile of environ-

ments. Two 8259A compatible interrupt controllers

handle internal interrupts, and, up to 57 external in-

terrupt requests. A DRAM refresh unit and 24 multi-

plexed I/O ports round out the feature set of the

80C186EC.

The future set of the 80C186EC meets the needs of

low-power, space-critical applications. Low-power

applications benefit from the static design of the

CPU and the integrated peripherals as well as low

voltage operation. Minimum current consumption is

achieved by providing a powerdown mode that halts

operaton of the device and freezes the clock cir-

cuits. Peripheral design enhancements ensure that

non-initialized peripherals consume little current.

The 80L186EC is the 3V version of the 80C186EC.

The 80L186EC is functionally identical to the

80C186EC embedded processor. Current

80C186EC users can easily upgrade their designs to

use the 80L186EC and benefit from the reduced

power consumption inherent in 3V operation.

Figure 1 shows a block diagram of the 80C186EC/

80C188EC. The execution unit (EU) is an enhanced

8086 CPU core that includes: dedicated hardware to

speed up effective address calculations, enhanced

execution speed for multiple-bit shift and rotate in-

structions and for multiply and divide instructions,

string move instructions that operate at full bus

bandwidth, ten new instructions and fully static oper-

ation. The bus interface unit (BIU) is the same as

that found on the original 186 family products, ex-

cept the queue-status mode has been deleted and

buffer interface control has been changed to ease

system design timings. An independent internal bus

is used for communication between the BIU and on-

chip peripherals.

80C186EC CORE ARCHITECTURE

Bus Interface Unit

The 80C186EC core incorporates a bus controller

that generates local bus control signals. In addition,

it employs a HOLD/HLDA protocol to share the local

bus with other bus masters.

The bus controller is responsible for generating 20

bits of address, read and write strobes, bus cycle

status information and data (for write operations) in-

formation. It is also responsible for reading data

from the local bus during a read operation. A ready

input pin is provided to extend a bus cycle beyond

the minimum four states (clocks).

The bus controller also generates two control sig-

nals (DEN and DT/R) when interfacing to external

transceiver chips. This capability allows the addition

of transceivers for simple buffering of the multi-

plexed address/data bus.

Clock Generator

The 80C186EC provides an on-chip clock generator

for both internal and external clock generation. The

clock generator features a crystal oscillator, a divide-

by-two counter and three low-power operating

modes.

The oscillator circuit is designed to be used with ei-

ther a parallel resonant fundamental or third-over-

tone mode crystal network. Alternatively, the oscilla-

tor circuit may be driven from an external clock

source. Figure 2 shows the various operating modes

of the oscillator circuit.

The crystal or clock frequency chosen must be twice

the required processor operating frequency due to

the internal divide-by-two counter. This counter is

used to drive all internal phase clocks and the exter-

nal CLKOUT signal. CLKOUT is a 50% duty cycle

processor clock and can be used to drive other sys-

tem components. All AC timings are referenced to

CLKOUT.

The following parameters are recommended when

choosing a crystal:

Temperature Range: Application Specific

ESR (Equivalent Series Res.): 40Xmax

C0 (Shunt Capacitance of Crystal): 7.0 pF max

CL(Load Capacitance): 20 pF g2pF

Drive Level: 1 mW (max)

80C186EC/188EC, 80L186EC/188EC

272434–2

NOTE:

1. The LC network is only required when using a third overtone crystal.

Figure 2. 80C186EC Clock Connections

80C186EC PERIPHERAL

ARCHITECTURE

The 80C186EC integrates several common system

peripherals with a CPU core to create a compact, yet

powerful system. The integrated peripherals are de-

signed to be flexbile and provide logical interconnec-

tions between supporting units (e.g., the DMA unit

can accept requests from the Serial Communica-

tions Unit).

The list of integrated peripherals includes:

Ð Two cascaded, 8259A compatible, Programma-

ble Interrupt Controllers

Ð 3-Channel Timer/Counter Unit

Ð 2-Channel Serial Communications Unit

Ð 4-Channel DMA Unit

Ð 10-Output Chip-Select Unit

Ð 32-bit Watchdog Timer Unit

Ð I/O Port Unit

Ð Refresh Control Unit

Ð Power Management Unit

The registers associated with each integrated pe-

ripheral are contained within a 128 x 16-bit register

file called the Peripheral Control Block (PCB). The

base address of the PCB is programmable and can

be located on any 256 byte address boundary in ei-

ther memory or I/O space.

Figure 3 provides a list of the registers associated

with the PCB. The Register Bit Summary individually

lists all of the registers and identifies each of their

programming attributes.

80C186EC/188EC, 80L186EC/188EC

PCB Function

Offset

00H Master PIC Port 0

02H Master PIC Port 1

04H Slave PIC Port 0

06H Slave PIC Port 1

08H Reserved

0AH SCU Int. Req. Ltch.

0CH DMA Int. Req. Ltch.

0EH TCU Int. Req. Ltch.

10H Reserved

12H Reserved

14H Reserved

16H Reserved

18H Reserved

1AH Reserved

1CH Reserved

1EH Reserved

20H WDT Reload High

22H WDT Reload Low

24H WDT Count High

26H WDT Count Low

28H WDT Clear

2AH WDT Disable

2CH Reserved

2EH Reserved

30H T0 Count

32H T0 Compare A

34H T0 Compare B

46H T0 Control

38H T1 Count

3AH T1 Compare A

3CH T1 Compare B

3EH T1 Control

PCB Function

Offset

40H T2 Count

42H T2 Compare

44H Reserved

46H T2 Control

48H Port 3 Direction

4AH Port 3 Pin State

4CH Port 3 Mux Control

4EH Port 3 Data Latch

50H Port 1 Direction

52H Port 1 Pin State

54H Port 1 Mux Control

56H Port 1 Data Latch

58H Port 2 Direction

5AH Port 2 Pin State

5CH Port 2 Mux Control

5EH Port 2 Data Latch

60H SCU 0 Baud

62H SCU 0 Count

64H SCU 0 Control

66H SCU 0 Status

68H SCU 0 RBUF

6AH SCU 0 TBUF

6CH Reserved

6EH Reserved

70H SCU 1 Baud

72H SCU 1 Count

74H SCU 1 Control

76H SCU 1 Status

78H SCU 1 RBUF

7AH SCU 1 TBUF

7CH Reserved

7EH Reserved

PCB Function

Offset

80H GCS0 Start

82H GCS0 Stop

84H GCS1 Start

86H GCS1 Stop

88H GCS2 Start

8AH GCS2 Stop

8CH GCS3 Start

8EH GCS3 Stop

90H GCS4 Start

92H GCS4 Stop

94H GCS5 Start

96H GCS5 Stop

98H GCS6 Start

9AH GCS6 Stop

9CH GCS7 Start

9EH GCS7 Stop

A0H LCS Start

A2H LCS Stop

A4H UCS Start

A6H UCS Stop

A8H Relocation Register

AAH Reserved

ACH Reserved

AEH Reserved

B0H Refresh Base Addr.

B2H Refresh Time

B4H Refresh Control

B6H Refresh Address

B8H Power Control

BAH Reserved

BCH Step ID

BEH Powersave

PCB Function

Offset

C0H DMA 0 Source Low

C2H DMA 0 Source High

C4H DMA 0 Dest. Low

C6H DMA 0 Dest. High

C8H DMA 0 Count

CAH DMA 0 Control

CCH DMA Module Pri.

CEH DMA Halt

D0H DMA 1 Source Low

D2H DMA 1 Source High

D4H DMA 1 Dest. Low

D6H DMA 1 Dest. High

D8H DMA 1 Count

DAH DMA 1 Control

DCH Reserved

DEH Reserved

E0H DMA 2 Source Low

E2H DMA 2 Source High

E4H DMA 2 Dest. Low

E6H DMA 2 Dest. High

E8H DMA 2 Count

EAH DMA 2 Control

ECH Reserved

EEH Reserved

F0H DMA 3 Source Low

F2H DMA 3 Source High

F4H DMA 3 Dest. Low

F6H DMA 3 Dest. High

F8H DMA 3 Count

FAH DMA 3 Control

FCH Reserved

FEH Reserved

Figure 3. Peripheral Control Block Registers

80C186EC/188EC, 80L186EC/188EC

Programmable Interrupt Controllers

The 80C186EC utilizes two 8259A compatible Pro-

grammable Interrupt Controllers (PIC) to manage

both internal and external interrupts. The 8259A

modules are configured in a master/slave arrange-

ment.

Seven of the external interrupt pins, INT0 through

INT6, are connected to the master 8259A module.

The eighth external interrupt pin, INT7, is connected

to the slave 8259A module.

There are a total of 11 internal interrupt sources

from the integrated peripherals: 4 Serial, 4 DMA and

3 Timer/Counter.

Timer/Counter Unit

The 80C186EC Timer/Counter Unit (TCU) provides

three 16-bit programmable timers. Two of these are

highly flexible and are connected to external pins for

external control or clocking. The third timer is not

connected to any external pins and can only be

clocked internally. However, it can be used to clock

the other two timer channels. The TCU can be used

to count external events, time external events, gen-

erate non-repetitive waveforms or generate timed in-

terrupts.

Serial Communications Unit

The 80C186EC Serial Communications Unit (SCU)

contains two independent channels. Each channel is

identical in operation except that only channel 0 is

directly supported by the integrated interrupt control-

ler (the channel 1 interrupts are routed to external

interrupt pins). Each channel has its own baud rate

generator and can be internally or externally clocked

up to one half the processor operating frequency.

Both serial channels can request service from the

DMA unit thus providing block reception and trans-

mission without CPU intervention.

Independent baud rate generators are provided for

each of the serial channels. For the asynchronous

modes, the generator supplies an 8x baud clock to

both the receive and transmit shifting register logic.

A 1x baud clock is provided in the synchronous

mode.

DMA Unit

The four channel Direct Memory Access (DMA) Unit

is comprised of two modules with two channels

each. All four channels are identical in operation.

DMA transfers can take place from memory to mem-

ory, I/O to memory, memory to I/O or I/O to I/O.

DMA requests can be external (on the DRQ pins),

internal (from Timer 2 or a serial channel) or soft-

ware initiated.

The DMA Unit transfers data as bytes only. Each

data transfer requires at least two bus cycles, one to

fetch data and one to deposit. The minimum clock

count for each transfer is 8, but this will vary depend-

ing on synchronization and wait states.

Chip-Select Unit

The 80C186EC Chip-Select Unit (CSU) integrates

logic which provides up to ten programmable chip-

selects to access both memories and peripherals. In

addition, each chip-select can be programmed to

automatically insert additional clocks (wait states)

into the current bus cycle, and/or automatically ter-

minate a bus cycle independent of the condition of

the READY input pin.

I/O Port Unit

The I/O Port Unit on the 80C186EC supports two

8-bit channels and one 6-bit channel of input, output

or input/output operation. Port 1 is multiplexed with

the chip select pins and is output only. Port 2 is mul-

tiplexed with the pins for serial channels 1 and 2. All

Port 2 pins are input/output. Port 3 has a total of 6

pins: four that are multiplexed with DMA and serial

port interrupts and two that are non-multiplexed,

open drain I/O.

Refresh Control Unit

The Refresh Control Unit (RCU) automatically gen-

erates a periodic memory read bus cycle to keep

dynamic or pseudo-static memory refreshed. A 9-bit

counter controls the number of clocks between re-

fresh requests.

A 12-bit address generator is maintained by the RCU

and is presented on the A12:1 address lines during

the refresh bus cycle. Address bits A19:13 are pro-

grammable to allow the refresh address block to be

located on any 8 Kbyte boundary.

Watchdog Timer Unit

The Watchdog Timer Unit (WDT) allows for graceful

recovery from unexpected hardware and software

upsets. The WDT consists of a 32-bit counter that

decrements every clock cycle. If the counter reach-

es zero before being reset, the WDTOUT pin is

80C186EC/188EC, 80L186EC/188EC

pulled low for four clock cycles. Logically ANDing

the WDTOUT pin with the power-on reset signal al-

lows the WDT to reset the device in the event of a

WDT timeout. If a less drastic method of recovery is

desired. WDTOUT can be connected directly to NMI

or one of the INT input pins. The WDT may also be

used as a general purpose timer.

Power Management Unit

The 80C186EC Power Management Unit (PMU) is

provided to control the power consumption of the

device. The PMU provides four power management

modes: Active, Powersave, Idle and Powerdown.

Active Mode indicates that all units on the

80C186EC are operating at ½the CLKIN frequency.

Idle Mode freezes the clocks of the Execution and

Bus units at a logic zero state (all peripherals contin-

ue to operate normally).

The Powerdown Mode freezes all internal clocks at

a logic zero level and disables the crystal oscillator.

In Powersave Mode, all internal clock signals are di-

vided by a programmable prescalar (up to 1/64 the

normal frequency). Powersave Mode can be used

with Idle Mode as well as during normal (Active

Mode) operation.

80C187 Interface (80C186EC only)

The 80C186EC supports the direct connection of

the 80C187 Numerics Processor Extension. The

80C187 can dramatically improve the performance

of calculation intensive applications.

ONCE Test Mode

To facilitate testing and inspection of devices when

fixed into a target system, the 80C186EC has a test

mode available which forces all output and input/

output pins to be placed in the high-impedance

state. ONCE stands for ‘‘ON Circuit Emulation’’,

The ONCE mode is selected by forcing the

A19/S6/ONCE pin low during a processor reset

(this pin is weakly held high during reset to prevent

inadvertant entrance into ONCE Mode).

PACKAGE INFORMATION

This section describes the pin functions, pinout and

thermal characteristics for the 80C186EC in the

Plastic Quad Flat Pack (JEDEC PQFP), the EIAJ

Quad Flat Pack (QFP) and the Shrink Quad Flat

Pack (SQFP). For complete package specifications

and information, see the Intel Packaging Outlines

and Dimensions Guide (Order Number: 231369).

Prefix Identification

Table 1 lists the prefix identifications.

Table 1: Prefix Identification

Prefix Note Package Temperature

Type Range

QFP (EIAJ) Extended

1 PQFP Extended/Commercial

1 SQFP Extended/Commercial

1 QFP (EIAJ) Commercial

NOTE:

1. The 5V 25 MHz version is only available in commercial

temperature range corresponding to 0˚C to a70°C am-

bient.

Pin Descriptions

Each pin or logical set of pins is described in Table

2, There are four columns for each entry in the Pin

Description Table. The following sections describe

each column.

Column 1. Pin Name

In this column is a mnemonic that de-

scribes the pin function. Negation of the

signal name (i.e. RESIN) implies that the

signal is active low.

Column 2. Pin Type

A pin may be either power (P), ground

(G), input only (I), output only (O) or in-

put/output (I/O). Please note that some

pins have more than 1 function.

A19/S6/ONCE , for example, is normally

an output but functions as an input dur-

ing reset. For this reason

A19/S6/ONCE is classified as an input/

output pin.

Column 3. Input Type (for I and I/O types only)

There are two different types of input

pins on the 80C186EC: asynchronous

and synchronous. Asynchronous pins

require that setup and hold times be met

only to

guarantee recognition

.Synchro-

nous input pins require that the setup

and hold times be met to

guarantee

proper operation

. Stated simply, missing

a setup or hold on an asynchronous pin

will result in something minor (i.e. a timer

count will be missed) whereas missing a

setup or hold on a synchronous pin will

result in system failure (the system will

‘‘lock up’’).

An input pin may also be edge or level

sensitive.

1. To address the fact that many of the package prefix variables

have changed, all package prefix variables in this document

are now indicated with an "x".

80C186EC/188EC, 80L186EC/188EC

Column 4: Output States (for O and I/O types

only)

The state of an output or I/O pin is de-

pendent on the operating mode of the

device. There are four modes of opera-

tion that are different from normal active

mode: Bus Hold, Reset, Idle Mode, Pow-

erdown Mode. This column describes

the output pin state in each of these

modes.

The legend for interpreting the information in the Pin

Descriptions is shown in Table 1.

As an example, please refer to the table entry for

AD12:0. The ‘‘I/O’’ signifies that the pins are bidirec-

tional (i.e. have both an input and output function).

The ‘‘S’’ indicates that, as an input the signal must

be synchronized to CLKOUT for proper operation.

The ‘‘H(Z)’’ indicates that these pins will float while

the processor is in the Hold Acknowledge state.

R(Z) indicates that these pins will float while RESIN

is low. P(0) and I(0) indicate that these pins will drive

0 when the device is in either Powerdown or Idle

Mode.

Some pins, the I/O Ports for example, can be pro-

grammed to perform more than one function. Multi-

function pins have a ‘‘/’’ in their signal name be-

tween the different functions (i.e. P3.0/RXI1). If the

input pin type or output pin state differ between func-

tions, then that will be indicated by separating the

state (or type) with a ‘‘/’’ (i.e. H(X)/H(Q)). In this

example when the pin is configured as P3.0 then its

hold output state is H(X); when configured as RXI1

its output state is H(Q).

All pins float while the processor is in the ONCE

Mode (with the exception of OSCOUT).

Table 1. Pin Description Nomenclature

Symbol Description

P Power Pin (apply aVCC voltage)

G Ground (connect to VSS)

I Input only pin

O Output only pin

I/O Input/Output pin

S(E) Synchronous, edge sensitive

S(L) Synchronous, level sensitive

A(E) Asynchronous, edge sensitive

A(L) Asynchronous, level sensitive

H(1) Output driven to VCC during bus hold

H(0) Output driven to VSS during bus hold

H(Z) Output floats during bus hold

H(Q) Output remains active during bus hold

H(X) Output retains current state during bus hold

R(WH) Output weakly held at VCC during reset

R(1) Output driven to VCC during reset

R(0) Output driven to VSS during reset

R(Z) Output floats during reset

R(Q) Output remains active during reset

R(X) Output retains current state during reset

I(1) Output driven to VCC during Idle Mode

I(0) Output driven to VSS during Idle Mode

I(Z) Output floats during Idle Mode

I(Q) Output remains active during Idle Mode

I(X) Output retains current state during Idle Mode

P(1) Output driven to VCC during Powerdown Mode

P(0) Output driven to VSS during Powerdown Mode

P(Z) Output floats during Powerdown Mode

P(Q) Output remains active during Powerdown Mode

P(X) Output retains current state during Powerdown Mode

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions

Pin Name Pin Input Output Pin Description

Type Type States

VCC PÐ ÐPOWER a5V g10% power supply connection

VSS GÐ ÐGROUND

CLKIN I A(E) Ð CLocK INput is the external clock input. An external

oscillator operating at two times the required processor

operating frequency can be connected to CLKIN. For

crystal operation, CLKIN (along with OSCOUT) are the

crystal connections to an internal Pierce oscillator.

OSCOUT O Ð H(Q) OSCillator OUTput is only used when using a crystal to

generate the internal clock. OSCOUT (along with CLKIN)

R(Q)

are the crystal connections to an internal Pierce oscillator.

I(Q)

This pin can not be used as 2X clock output for non-

P(X) crystal applications (i.e. this pin is not connected for non-

crystal applications).

CLKOUT O Ð H(Q) CLocK OUTput provides a timing reference for inputs and

outputs of the processor, and is one-half the input clock

R(Q)

(CLKIN) frequency. CLKOUT has a 50% duty cycle and

I(Q)

transitions every falling edge of CLKIN.

P(X)

RESIN I A(L) Ð RESet IN causes the processor to immediately terminate

any bus cycle in progress and assume an initialized state.

All pins will be driven to a known state, and RESOUT will

also be driven active. The rising edge (low-to-high)

transition synchronizes CLKOUT with CLKIN before the

processor begins fetching opcodes at memory location

0FFFF0H.

RESOUT O Ð H(0) RESet OUTput that indicates the processor is currently in

the reset state. RESOUT will remain active as long as

R(1)

RESIN remains active.

I(0)

P(0)

PDTMR I/O A(L) H(WH) Power-Down TiMeR pin (normally connected to an

external capacitor) that determines the amount of time the

R(Z)

processors waits after an exit from Powerdown before

P(WH)

resuming normal operation. The duration of time required

I(WH) will depend on the startup characteristics of the crystal

oscillator.

NMI I A(E) Ð Non-Maskable Interrupt input causes a TYPE-2 interrupt

to be serviced by the CPU. NMI is latched internally.

TEST/BUSY I A(E) Ð TEST is used during the execution of the WAIT instruction

to suspend CPU operation until the pin is sampled active

(TEST)

(LOW). TEST is alternately known as BUSY when

interfacing with an 80C187 numerics coprocessor

(80C186EC only).

A19/S6/ONCE I/O A(L) H(Z) This pin drives address bit 19 during the address phase of

the bus cycle. During T2 and T3 this pin functions as

R(WH)

status bit 6. S6 is low to indicate CPU bus cycles and high

I(0)

to indicate DMA or refresh bus cycles. During a processor

P(0) reset (RESIN active) this pin becomes the ONCE input

pin. Holding this pin low during reset will force the part into

ONCE Mode.

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Pin Name Pin Input Output Pin Description

Type Type States

A18/S5 I/O A(L) H(Z) These pins drive address information during the address

phase of the bus cycle. During T2 and T3 these pins drive

A17/S4 R(WH)

status information (which is always 0 on the 80C186EC).

A16/S3 I(0) These pins are used as inputs during factory test; driving

(A15:8) P(0) these pins low during reset will cause unspecified operation.

On the 80C188EC, A15:8 provide valid address information

for the entire bus cycle.

AD15/CAS2 I/O S(L) H(Z) These pins are part of the multiplexed ADDRESS and DATA

bus. During the address phase of the bus cycle, address bits

AD14/CAS1 R(Z)

15 through 13 are presented on these pins and can be

AD13/CAS0 I(0) latched using ALE. Data information is transferred during the

P(0) data phase of the bus cycle. Pins AD15:13/CAS2:0 drive the

82C59 slave address information during interrupt

acknowledge cycles.

AD12:0 I/O S(L) H(Z) These pins provide a multiplexed ADDRESS and DATA bus.

During the address phase of the bus cycle, address bits 0

(AD7:0) R(Z)

through 12 (0 through 7 on the 80C188EC) are presented on

I(0) the bus and can be latched using ALE. Data information is

P(0) transferred during the data phase of the bus cycle.

S2:0 O Ð H(Z) Bus cycle Status are encoded on these pins to provide bus

transaction information. S2:0 are encoded as follows:

R(1)

I(1)

P(1) S2 S1 S0 Bus Cycle Initiated

0 0 0 Interrupt Acknowledge

0 0 1 Read I/O

0 1 0 Write I/O

0 1 1 Processor HALT

1 0 0 Instruction Queue Fetch

1 0 1 Read Memory

1 1 0 Write Memory

1 1 1 Passive (No bus activity)

ALE O Ð H(0) Address Latch Enable output is used to strobe address

information into a transparent type latch during the address

R(0)

phase of the bus cycle.

I(0)

P(0)

BHE O Ð H(Z) Byte High Enable output to indicate that the bus cycle in

progress is transferring data over the upper half of the data

(RFSH) R(Z)

bus. BHE and A0 have the following logical encoding:

I(1)

P(1)

A0 BHE Encoding (for 80C186EC/

80L186EC only)

0 0 Word transfer

0 1 Even Byte transfer

1 0 Odd Byte transfer

1 1 Refresh operation

On the 80C188EC/80L188EC, RFSH is asserted low to

indicate a refresh bus cycle.

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Pin Name Pin Input Output Pin Description

Type Type States

RD O Ð H(Z) ReaD output signals that the accessed memory or I/O

device should drive data information onto the data bus.

R(Z)

I(1)

P(1)

WR O Ð H(Z) WRite output signals that data available on the data bus are

to be written into the accessed memory or I/O device.

R(Z)

I(1)

P(1)

READY I A(L) Ð READY input to signal the completion of a bus cycle. READY

must be active to terminate any 80C186EC bus cycle, unless

S(L)

it is ignored by correctly programming the Chip-Select unit.

(Note 1)

DEN O Ð H(Z) Data ENable output to control the enable of bi-directional

transceivers in a buffered system. DEN is active only when

R(Z)

data is to be transferred on the bus.

I(1)

P(1)

DT/R O Ð H(Z) Data Transmit/Receive output controls the direction of a bi-

directional buffer in a buffered system.

R(Z)

I(X)

P(X)

LOCK I/O A(L) H(Z) LOCK output indicates that the bus cycle in progress is not

interruptable. The processor will not service other bus

R(Z)

requests (such as HOLD) while LOCK is active. This pin is

I(X) configured as a weakly held high input while RESIN is active

P(X) and must not be driven low.

HOLD I A(L) Ð HOLD request input to signal that an external bus master

wishes to gain control of the local bus. The processor will

relinquish control of the local bus between instruction

boundaries that are not LOCKed.

HLDA O Ð H(1) HoLD Acknowledge output to indicate that the processor

has relinquished control of the local bus. When HLDA is

R(0)

asserted, the processor will (or has) floated its data bus and

I(0) control signals allowing another bus master to drive the

P(0) signals directly.

NCS O Ð H(1) Numerics Coprocessor Select output is generated when

acessing a numerics coprocessor. This signal does not exist

R(1)

on the 80C188EC/80L188EC.

I(1)

P(1)

ERROR I A(L) Ð ERROR input that indicates the last numerics processor

extension operation resulted in an exception condition. An

interrupt TYPE 16 is generated if ERROR is sampled active

at the beginning of a numerics operation. Systems not using

an 80C187 must tie ERROR to VCC. This signal does not

exist on the 80C188EC/80L188EC.

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Pin Name Pin Input Output Pin Description

Type Type States

PEREQ I A(L) Ð Processor Extension REQuest signals that a data

transfer between an 80C187 Numerics Processor

Extension and Memory is pending. Systems not using an

80C187 must tie this pin to VSS. This signal does not exist

on the 80C188EC/80L188EC.

UCS O Ð H(1) Upper Chip Select will go active whenever the address of

a memory or I/O bus cycle is within the address range

R(1)

programmed by the user. After reset, UCS is configured to

I(1) be active for memory accesses between 0FFC00H and

P(1) 0FFFFFH.

LCS O Ð H(1) Lower Chip Select will go active whenever the address of

a memory or I/O bus cycle is within the address range

R(1)

programmed by the user. LCS is inactive after a reset.

I(1)

P(1)

P1.0/GCS0 O Ð H(X)/H(1) These pins provide a multiplexed function. If enabled,

each pin can provide a General purpose Chip Select

P1.1/GCS1 R(1)

output which will go active whenever the address of a

P1.2/GCS2 I(X)/I(1) memory or I/O bus cycle is within the address limitations

P1.3/GCS3 P(X)/P(1) programmed by the user. When not programmed as a

P1.4/GCS4 Chip-Select, each pin may be used as a general purpose

P1.5/GCS5 output port.

P1.6/GCS6

P1.7/GCS7

T0OUT O Ð H(Q) Timer OUTput pins can be programmed to provide single

clock or continuous waveform generation, depending on

T1OUT R(1)

the timer mode selected.

I(Q)

P(X)

T0IN I A(L) Ð Timer INput is used either as clock or control signals,

depending on the timer mode selected. This pin may be

T1IN A(E)

either level or edge sensitive depending on the

programming mode.

INT7:0 I A(L) Ð Maskable INTerrupt input will cause a vector to a specific

Type interrupt routine. The INT6:0 pins can be used as

A(E)

cascade inputs from slave 8259A devices. The INT pins

can be configured as level or edge sensitive.

INTA O Ð H(1) INTerrupt Acknowledge output is a handshaking signal

used by external 82C59A Programmable Interrupt

R(1)

Controllers.

I(1)

P(1)

P3.5 I/O A(L) H(X) Bidirectional, open-drain port pins.

P3.4 R(Z)

I(X)

H(X)

P3.3/DMAI1 O Ð H(X) DMA Interrupt output goes active to indicate that the

channel has completed a transfer. DMAI1 and DMAI0 are

P3.2/DMAI0 R(0)

multiplexed with output only port functions.

I(Q)

P(X)

NOTE:

Pin names in parentheses apply to the 80C188EC/80L188EC.

80C186EC/188EC, 80L186EC/188EC

Table 2. Pin Descriptions (Continued)

Pin Name Pin Input Output Pin Description

Type Type States

P3.1/TXI1 O Ð H(X)/H(Q) Transmit Interrupt output goes active to indicate that

serial channel 1 has completed a transfer. TXI1 is

R(0)

multiplexed with an output only Port function.

I(Q)

P(X)

P3.0/RXI1 O Ð H(X)/H(Q) Receive Interrupt output goes active to indicate that

serial channel 1 has completed a reception. RXI1 is

R(0)

multiplexed with an output only port function.

I(Q)

P(X)

WDTOUT O Ð H(Q) WatchDog Timer OUTput is driven low for four clock

cycles when the watchdog timer reaches zero. WDTOUT

R(1)

may be ANDed with the power-on reset signal to reset the

I(Q) processor when the watchdog timer is not properly reset.

P(X)

P2.7/CTS1 I/O A(L) H(X) Clear-To-Send input is used to prevent the transmission

of serial data on the TXD signal pin. CTS1 and CTS0 are

P2.3/CTS0 R(Z)

multiplexed with an I/O Port function.

I(X)

P(X)

P2.6/BCLK1 I/O A(L)/ H(X) Baud CLocK input can be used as an alternate clock

source for each of the integrated serial channels. The

P2.2/BCLK0 A(E) R(Z)

BCLK inputs are multiplexed with I/O Port functions. The

I(X) BCLK input frequency cannot exceed (/2 the operating

P(X) frequency of the processor .

P2.5/TXD1 I/O A(L) H(Q) Transmit Data output provides serial data information.

The TXD outputs are multiplexed with I/O Port functions.

P2.1/TXD0 R(Z)

During synchronous serial communications, TXD will

I(X)/I(Q) function as a clock output.

P(X)

P2.4/RXD1 I/O A(L) H(X)/H(Q) Receive Data input accepts serial data information. The

RXD pins are multiplexed with I/O Port functions. During

P2.0/RXD0 R(Z)

synchronous serial communications, RXD is bi-directional

I(X)/I(Q) and will become an output for transmission of data (TXD

P(X) becomes the clock).

DRQ3:0 I A(L) Ð DMA ReQuest input pins are used to request a DMA

transfer. The timing of the request is dependent on the

programmed synchronization mode.

NOTES:

1. READY is A(E) for the rising edge of CLKOUT, S(E) for the falling edge of CLKOUT.

2. Pin names in parentheses apply to the 80C188EC/80L188EC.

80C186EC/188EC, 80L186EC/188EC

Pinout

Tables 3 and 4 list the pin names with package loca-

tion for the 100-pin Plastic Quad Flat Pack (PQFP)

component. Figure 4 depicts the PQFP package as

viewed from the top side of the component (i.e. con-

tacts facing down).

Tables 5 and 6 list the pin names with package loca-

tion for the 100-pin EIAJ Quad Flat Pack (QFP) com-

ponent. Figure 5 depicts the QFP package as viewed

from the top side of the component (i.e. contacts

facing down).

Tables 7 and 8 list the pin names with package loca-

tion for the 100-pin Shrink Quad Flat Pack (SQFP)

component. Figure 6 depicts the SQFP package as

viewed from the top side of the component (i.e., con-

tacts facing down).

Table 3. PQFP Pin Functions with Location

AD Bus

Name Pin

AD0 73

AD1 72

AD2 71

AD3 70

AD4 66

AD5 65

AD6 64

AD7 63

AD8 (A8) 60

AD9 (A9) 59

AD10 (A10) 58

AD11 (A11) 57

AD12 (A12) 56

AD13/CAS0 55

(A13/CAS0)

AD14/CAS1 54

(A14/CAS1)

AD15/CAS2 53

(A15/CAS2)

A16/S3 77

A17/S4 76

A18/S5 75

A19/S6/ONCE 74

Bus Control

Name Pin

ALE 52

BHE (RFSH)51

S0 78

S1 79

S2 80

RD 50

WR 49

READY 85

DEN 47

DT/R 46

LOCK 48

HOLD 44

HLDA 45

INTA 34

Power and Ground

Name Pin

VCC 13

VCC 14

VCC 38

VCC 62

VCC 67

VCC 69

VCC 86

VSS 12

VSS 15

VSS 37

VSS 39

VSS 61

VSS 68

VSS 87

Processor Control

Name Pin

RESIN 8

RESOUT 7

CLKIN 10

OSCOUT 11

CLKOUT 6

TEST/BUSY 83

(TEST)

PEREQ (VSS)81

NCS (N.C.) 35

ERROR (VCC)84

PDTMR 9

NMI 82

INT0 30

INT1 31

INT2 32

INT3 33

INT4 40

INT5 41

INT6 42

INT7 43

I/O

Name Pin

UCS 88

LCS 89

P1.7/GCS7 90

P1.6/GCS6 91

P1.5/GCS5 92

P1.4/GCS4 93

P1.3/GCS3 94

P1.2/GCS2 95

P1.1/GCS1 96

P1.0/GCS0 97

P2.7/CTS1 23

P2.6/BCLK1 22

P2.5/TXD1 21

P2.4/RXD1 20

P2.3/CTS0 19

P2.2/BCLK0 18

P2.1/TXD0 17

P2.0/RXD0 16

P3.5 29

P3.4 28

P3.3/DMAI1 27

P3.2/DMAI0 26

P3.1/TXI1 25

P3.0/RXI1 24

T0IN 3

T0OUT 2

T1IN 5

T1OUT 4

DRQ0 98

DRQ1 99

DRQ2 100

DRQ3 1

WDTOUT 36

80C186EC/188EC, 80L186EC/188EC

Table 4. PQFP Pin Locations with Pin Name

Pin Name

1 DRQ3

2 T0OUT

3 T0IN

4 T1OUT

5 T1IN

6 CLKOUT

7 RESOUT

8 RESIN

9 PDTMR

10 CLKIN

11 OSCOUT

12 VSS

13 VCC

14 VCC

15 VSS

16 P2.0/RXD0

17 P2.1/TXD0

18 P2.2/BCLK0

19 P2.3/CTS0

20 P2.4/RXD1

21 P2.5/TXD1

22 P2.6/BCLK1

23 P2.7/CTS1

24 P3.0/RXI1

25 P3.1/TXI1

Pin Name

26 DMAI0/P3.2

27 DMAI1/P3.3

28 P3.4

29 P3.5

30 INT0

31 INT1

32 INT2

33 INT3

34 INTA

35 NCS (N.C.)

36 WDTOUT

37 VSS

38 VCC

39 VSS

40 INT4

41 INT5

42 INT6

43 INT7

44 HOLD

45 HLDA

46 DT/R

47 DEN

48 LOCK

49 WR

50 RD

Pin Name

51 BHE (RFSH)

52 ALE

53 AD15 (A15)

54 AD14 (A14)

55 AD13 (A13)

56 AD12 (A12)

57 AD11 (A11)

58 AD10 (A10)

59 AD9 (A9)

60 AD8 (A8)

61 VSS

62 VCC

63 AD7

64 AD6

65 AD5

66 AD4

67 VCC

68 VSS

69 VCC

70 AD3

71 AD2

72 AD1

73 AD0

74 A19/S6/ONCE

75 A18/S5

Pin Name

76 A17/S4

77 A16/S3

78 S0

79 S1

80 S2

81 PEREQ (VSS)

82 NMI

83 TEST

84 ERROR (VCC)

85 READY

86 VCC

87 VSS

88 UCS

89 LCS

90 P1.7/GCS7

91 P1.6/GCS6

92 P1.5/GCS5

93 P1.4/GCS4

94 P1.3/GCS3

95 P1.2/GCS2

96 P1.1/GCS1

97 P1.0/GCS0

98 DRQ0

99 DRQ1

100 DRQ2

80C186EC/188EC, 80L186EC/188EC

272434–3

NOTE:

This is the FPO number location (indicated by X’s).

Figure 4. 100-Pin Plastic Quad Flat Pack Package (PQFP)

80C186EC/188EC, 80L186EC/188EC

Table 5. QFP Pin Names with Package Location

AD Bus

Name Pin

AD0 76

AD1 75

AD2 74

AD3 73

AD4 69

AD5 68

AD6 67

AD7 66

AD8 (A8) 63

AD9 (A9) 62

AD10 (A10) 61

AD11 (A11) 60

AD12 (A12) 59

AD13/CAS0 58

(A13/CAS0)

AD14/CAS1 57

(A14/CAS1)

AD15/CAS2 56

(A15/CAS2)

A16/S3 80

A17/S4 79

A18/S5 78

A19/S6/ONCE 77

Bus Control

Name Pin

ALE 55

BHE (RFSH)54

S0 81

S1 82

S2 83

RD 53

WR 52

READY 88

DEN 50

DT/R 49

LOCK 51

HOLD 47

HLDA 48

INTA 37

Power and Ground

Name Pin

VCC 16

VCC 17

VCC 41

VCC 65

VCC 70

VCC 72

VCC 89

VSS 15

VSS 18

VSS 40

VSS 42

VSS 64

VSS 71

VSS 90

Processor Control

Name Pin

RESIN 11

RESOUT 10

CLKIN 13

OSCOUT 14

CLKOUT 9

TEST/BUSY 86

(TEST)

PEREQ (VSS)84

NCS (N.C.) 38

ERROR (VCC)87

PDTMR 12

NMI 85

INT0 33

INT1 34

INT2 35

INT3 36

INT4 43

INT5 44

INT6 45

INT7 46

I/O

Name Pin

UCS 91

LCS 92

P1.7/GCS7 93

P1.6/GCS6 94

P1.5/GCS5 95

P1.4/GCS4 96

P1.3/GCS3 97

P1.2/GCS2 98

P1.1/GCS1 99

P1.0/GCS0 100

P2.7/CTS1 26

P2.6/BCLK1 25

P2.5/TXD1 24

P2.4/RXD1 23

P2.3/CTS0 22

P2.2/BCLK0 21

P2.1/TXD0 20

P2.0/RXD0 19

P3.5 32

P3.4 31

P3.3/DMAI1 30

P3.2/DMAI0 29

P3.1/TXI1 28

P3.0/RXI1 27

T0IN 6

T0OUT 5

T1IN 8

T1OUT 7

DRQ0 1

DRQ1 2

DRQ2 3

DRQ3 4

WDTOUT 39

80C186EC/188EC, 80L186EC/188EC

Table 6. QFP Package Location with Pin Names

Pin Name

1 DRQ0

2 DRQ1

3 DRQ2

4 DRQ3

5 T0OUT

6 T0IN

7 T1OUT

8 T1IN

9 CLKOUT

10 RESOUT

11 RESIN

12 PDTMR

13 CLKIN

14 OSCOUT

15 VSS

16 VCC

17 VCC

18 VSS

19 P2.0/RXD0

20 P2.1/TXD0

21 P2.2/BCLK0

22 P2.3/CTS0

23 P2.4/RXD1

24 P2.5/TXD1

25 P2.6/BCLK1

Pin Name

26 P2.7/CTS1

27 P3.0/RXI1

28 P3.1/TXI1

29 DMAI0/P3.2

30 DMAI1/P3.3

31 P3.4

32 P3.5

33 INT0

34 INT1

35 INT2

36 INT3

37 INTA

38 NCS (N.C.)

39 WDTOUT

40 VSS

41 VCC

42 VSS

43 INT4

44 INT5

45 INT6

46 INT7

47 HOLD

48 HLDA

49 DT/R

50 DEN

Pin Name

51 LOCK

52 WR

53 RD

54 BHE (RFSH)

55 ALE

56 AD15 (A15)

57 AD14 (A14)

58 AD13 (A13)

59 AD12 (A12)

60 AD11 (A11)

61 AD10 (A10)

62 AD9 (A9)

63 AD8 (A8)

64 VSS

65 VCC

66 AD7

67 AD6

68 AD5

69 AD4

70 VCC

71 VSS

72 VCC

73 AD3

74 AD2

75 AD1

Pin Name

76 AD0

77 A19/S6/ONCE

78 A18/S5

79 A17/S4

80 A16/S3

81 S0

82 S1

83 S2

84 PEREQ (VSS)

85 NMI

86 TEST

87 ERROR (VCC)

88 READY

89 VCC

90 VSS

91 UCS

92 LCS

93 P1.7/GCS7

94 P1.6/GCS6

95 P1.5/GCS5

96 P1.4/GCS4

97 P1.3/GCS3

98 P1.2/GCS2

99 P1.1/GCS1

100 P1.0/GCS0

80C186EC/188EC, 80L186EC/188EC

272434–4

NOTE:

This is the FPO number location (indicated by X’s).

Figure 5: Quad Flat Pack (EIAJ) Pinout Diagram

80C186EC/188EC, 80L186EC/188EC

Table 7. SQFP Pin Functions with Location

AD Bus

AD0 73

AD1 72

AD2 71

AD3 70

AD4 66

AD5 65

AD6 64

AD7 63

AD8 (A8) 60

AD9 (A9) 59

AD10 (A10) 58

AD11 (A11) 57

AD12 (A12) 56

AD13 (A13) 55

AD14 (A14) 54

AD15 (A15) 53

A16 77

A17 76

A18 75

A19/ONCE 74

Bus Control

ALE 52

BHE (RFSH)51

S0 78

S1 79

S2 80

RD 50

WR 49

READY 85

DT/R 46

DEN 47

LOCK 48

HOLD 44

HLDA 45

Processor Control

RESIN 8

RESOUT 7

CLKIN 10

OSCOUT 11

CLKOUT 6

TEST/BUSY 83

NMI 82

INT0 30

INT1 31

INT2 32

INT3 33

INT4 40

INT5 41

INT6 42

INT7 43

INTA 34

PEREQ (VSS)81

ERROR (VCC)84

NCS (N.C.) 35

PDTMR 9

Power and Ground

VCC 13

VCC 14

VCC 38

VCC 62

VCC 67

VCC 69

VCC 86

VSS 12

VSS 15

VSS 37

VSS 39

VSS 61

VSS 68

VSS 87

I/O

UCS 88

LCS 89

P1.0/GCS0 97

P1.1/GCS1 96

P1.2/GCS2 95

P1.3/GCS3 94

P1.4/GCS4 93

P1.5/GCS5 92

P1.6/GCS6 91

P1.7/GCS7 90

P2.0/RXD0 16

P2.1/TXD0 17

P2.2/BCLK0 18

P2.3/CTS0 19

P2.4/RXD1 20

P2.5/TXD1 21

P2.6/BCLK1 22

P2.7/CTS1 23

P3.0/RXI1 24

P3.1/TXI1 25

P3.2/DMAI0 26

P3.3/DMAI1 27

P3.4 28

P3.5 29

DRQ0 98

DRQ1 99

DRQ2 100

DRQ3 1

T0IN 3

T0OUT 2

T1IN 5

T1OUT 4

WDTOUT 36

80C186EC/188EC, 80L186EC/188EC

Table 8. SQFP Pin Locations with Pin Names

Pin Name

1 DRQ3

2 T0OUT

3 T0IN

4 T1OUT

5 T1IN

6 CLKOUT

7 RESOUT

8 RESIN

9 PDTMR

10 CLKIN

11 OSCOUT

12 VSS

13 VCC

14 VCC

15 VSS

16 P2.0/RXD0

17 P2.1/TXD0

18 P2.2/BCLK0

19 P2.3/CTS0

20 P2.4/RXD1

21 P2.5/TXD1

22 P2.6/BCLK1

23 P2.7/CTS1

24 P3.0/RXI1

25 P3.1/TXI1

Pin Name

26 P3.2/DMAI0

27 P3.3/DMAI1

28 P3.4

29 P3.5

30 INT0

31 INT1

32 INT2

33 INT3

34 INTA

35 NSC (N.C.)

36 WDTOUT

37 VSS

38 VCC

39 VSS

40 INT4

41 INT5

42 INT6

43 INT7

44 HOLD

45 HLDA

46 DT/R

47 DEN

48 LOCK

49 WR

50 RD

Pin Name

51 BHE (RFSH)

52 ALE

53 AD15 (A15)

54 AD14 (A14)

55 AD13 (A13)

56 AD12 (A12)

57 AD11 (A11)

58 AD10 (A10)

59 AD9 (A9)

60 AD8 (A8)

61 VSS

62 VCC

63 AD7 (A7)

64 AD6 (A6)

65 AD5

66 AD4

67 VCC

68 VSS

69 VCC

70 AD3

71 AD2

72 AD1

73 AD0

74 A19/ONCE

75 AD18

Pin Name

76 A17

77 A16

78 S0

79 S1

80 S2

81 PEREQ (VSS)

82 MNI

83 TEST/BUSY

(TEST)

84 ERROR (VCC)

85 READY

86 VCC

87 VSS

88 UCS

89 LCS

90 P1.7/GCS7

91 P1.6/GS6

92 P1.5/GCS5

93 P1.4/GCS4

94 P1.3/GCS3

95 P1.2/GCS2

96 P1.1/GCS1

97 P1.0/GCS0

98 DRQ0

99 DRQ1

100 DRQ2

80C186EC/188EC, 80L186EC/188EC

272434–5

NOTE:

This is the FPO number location (indicated by X’s)

Figure 6: 100-Pin Shrink Quad Flat Pack Package (SQFP)

80C186EC/188EC, 80L186EC/188EC

Package Thermal Specifications

The 80C186EC/80L186EC is specified for operation

when TC(the case temperature) is within the range

of b40§Ctoa

100§C. TCmay be measured in any

environment to determine whether the processor is

within the specified operating range. The case tem-

perature must be measured at the center of the top

surface.

TA(the ambient temperature) can be calculated

from iCA (thermal resistance from the case to ambi-

ent) with the following equation:

TAeTCbP*iCA

Typical values for iCA at various airflows are given

in Table 9. P (the maximum power consumptionÐ

specified in Watts) is calculated by using the maxi-

mum ICC and VCC of 5.5V.

Table 9. Thermal Resistance (iCA) at Various Airflows (in §C/Watt)

Airflow in ft/min (m/sec)

0 200 400 600 800 1000

(0) (1.01) (2.03) (3.04) (4.06) (5.07)

iCA (PQFP) 27.0 22.0 18.0 15.0 14.0 13.5

iCA (QFP) 64.5 55.5 51.0 TBD TBD TBD

iCA (SQFP) 62.0 TBD TBD TBD TBD TBD

80C186EC/188EC, 80L186EC/188EC

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

Storage Temperature ÀÀÀÀÀÀÀÀÀÀb65§Ctoa

150§C

Case Temperature Under BiasÀÀÀb65§Ctoa

100§C

Supply Voltage

with Respect to VSS ÀÀÀÀÀÀÀÀÀÀÀb0.5V to a6.5V

Voltage on Other Pins

with Respect to VSS ÀÀÀÀÀÀb0.5V to VCC a0.5V

NOTICE: This data sheet contains preliminary infor-

mation on new products in production. The specifica-

tions are subject to change without notice. Verify with

your local Intel Sales office that you have the latest

data sheet before finalizing a design.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

Recommended Connections

Power and ground connections must be made to

multiple VCC and VSS pins. Every 80C186EC-based

circuit board should include separate power (VCC)

and ground (VSS) planes. Every VCC pin must be

connected to the power plane, and every VSS pin

must be connected to the ground plane. Liberal de-

coupling capacitance should be placed near the

processor. The processor can cause transient pow-

er surges when its output buffers transition, particu-

larly when connected to large capacitive loads.

Low inductance capacitors and interconnects are

recommended for best high frequency electrical per-

formance. Inductance is reduced by placing the de-

coupling capacitors as close as possible to the proc-

essor VCC and VSS package pins.

Always connect any unused input to an appropriate

signal level. In particular, unused interrupt inputs

(NMI, INT0:7) should be connected to VSS through a

pull-down resistor. Leave any unused output pin un-

connected.

80C186EC/188EC, 80L186EC/188EC

DC SPECIFICATIONS (80C186EC/80C188EC)

Symbol Parameter Min Max Units Notes

VCC Supply Voltage 4.5 5.5 V

VIL Input Low Voltage b0.5 0.3 VCC V

VIH Input High Voltage 0.7 VCC VCC a0.5 V

VOL Output Low Voltage 0.45 V IOL e3 mA (Min)

VOH Output High Voltage VCC b0.5 V IOH eb

2 mA (Min)

VHYR Input Hysteresis on RESIN 0.5 V

ILI Input Leakage Current for Pins: g15 mA0

IN sVCC

AD15:0 (AD7:0, A15:8), READY,

HOLD, RESIN,

CLKIN, TEST/BUSY, NMI, INT7:0,

T0IN, T1IN, P2.7– P2.0, P3.5– P3.0,

DRQ3:0, PEREQ, ERROR

ILIU Input Leakage for Pins with Pullups b0.275 b5mAV

IN e0.7 VCC

Active During Reset: (Note 1)

A19:16, LOCK

ILO Output Leakage for Floated Output g15 mA 0.45 sVOUT sVCC

Pins (Note 2)

ICC Supply Current Cold (in RESET)

80C186EC25 125 mA (Notes 3, 7)

80C186EC20 100 mA (Note 3)

80C186EC13 70 mA (Note 3)

IID Supply Current in Idle Mode

80C186EC25 92 mA (Notes 4, 7)

80C186EC20 76 mA (Note 4)

80C186EC13 50 mA (Note 4)

IPD Supply Current in Powerdown Mode

80C186EC25 100 mA (Notes 5, 7)

80C186EC20 100 mA (Note 5)

80C186EC13 100 mA (Note 5)

CIN Input Pin Capacitance 0 15 pF TFe1 MHz

COUT Output Pin Capacitance 0 15 pF TFe1 MHz (Note 6)

NOTES:

1. These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active. Sourcing more

current than specified (on any of these pins) may invoke a factory test mode.

2. Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD.

3. Measured with the device in RESET and at worst case frequency, VCC, and temperature with ALL outputs loaded as

specified in AC Test Conditions, and all floating outputs driven to VCC or GND.

4. Measured with the device in HALT (IDLE Mode active) and at worst case frequency, VCC, and temperature with ALL

outputs loaded as specified in AC Test Conditions, and all floating outputs driven to VCC or GND.

5. Measured with the device in HALT (Powerdown Mode active) and at worst case frequency, VCC, and temperature with

ALL outputs loaded as specified in AC Test Conditions, and all floating outputs driven to VCC or GND.

6. Output Capacitance is the capacitive load of a floating output pin.

7. Operating conditions for 25 MHz is 0§Ctoa

70§C, VCC e5.0 g10%.

80C186EC/188EC, 80L186EC/188EC

DC SPECIFICATIONS (80L186EC13/80L188EC13)

Symbol Parameter Min Max Units Notes

VCC Supply Voltage 2.7 5.5 V

VIL Input Low Voltage b0.5 0.3 VCC V

VIH Input High Voltage 0.7 VCC VCC a0.5 V

VOL Output Low Voltage 0.45 V IOL e3 mA (Min)

VOH Output High Voltage VCC b0.5 V IOH eb

2 mA (Min)

VHYR Input Hysteresis on RESIN 0.5 V

ILI Input Leakage Current for Pins: g15 mA0

IN sVCC

AD15:0 (AD7:0, A15:8), READY,

HOLD, RESIN, CLKIN,

TEST/BUSY, NMI, INT7:0,

T0IN, T1IN, P2.7– P2.0, P3.5– P3.0,

DRQ3:0, PEREQ, ERROR

ILIU Input Leakage for Pins with Pullups b0.275 b5mAV

IN e0.7 VCC

Active During Reset: (Note 1)

A19:16, LOCK

ILO Output Leakage for Floated Output g15 mA 0.45 sVOUT sVCC

Pins (Note 2)

ICC Supply Current Cold (in RESET) (Note 3)

80L186EC-13 36 mA

IID Supply Current in Idle Mode (Note 4)

80L186EC-13 24 mA

IPD Supply Current in Powerdown Mode (Note 5)

80L186EC-13 30 mA