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AN1301
APPLICATION NOTE
April 2002
1.0 GENERAL DESCRIPTIO N
The STE 100P, als o referred t o as STEPHY 1, i s a high perf ormance Fast Ethernet phy si cal l ayer i nterf ace f or
10BASE-T and 100BASE-TX applications. It was designed with advanced CMOS technology to provide a Media
Independent Interface (MII) for eas y attachm ent to 10/100 Med ia Access Controllers (M AC) and a p hysic al me-
dia inter face f or 100BASE-T X and 10BASE -T. The twis ted pair i nterface di rectly drives a 10/100 t wi sted pai r
connection. STE100P is an excellent device perfectly suited for hub, switch, router and other embedded Ether-
net applications.
The system diagram is as shown below:
Figure 1. System Diagram of the STE100P Appli cation
2.0 FEATURES
■Integrates the whole physic al layer functions of the 100BASE- TX and 10B ASE-T
■3.3V low power operat ion
■The hardware control pins set the init ial state of the ST E 100P at power-up
■Designed with a power down feature, which can s ave the power consu mption significantly
■Can operate for either full d uplex or half duplex network applications.
■MI I interfac e
■Provides auto-negotiation, parallel detection or manual control for mode set ting
■Provides MLT-3 transceiver with DC restoration for Bas e-l ine wander compens ation
Boot RO M 25 M Hz
Crystal
RJ-45
STE100P
STEPHY1
Serial
EEPROM LEDs
PCI In te rfac e
MA C
Dev ic e
Transformer
STE100P - SING LE PORT FAS T ETHERNET TRANSCEIVER
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AN1301 APPLICATION NOTE
■Provides transmit wave-shaper, receive f i lters, and adaptive equalizer
■Provides loop-back modes for diagnostic testing
■Builds in Stream Cipher Scrambler/Descrambler and 4B /5B encode r/decode r
■Supports external transmit transforme r with turn rat io 1:1
■Supports external receive transformer with turn ratio 1:1
3.0 DESI GN AND LAYOU T GUI D EL IN ES
3.1 G ener al Guidelin es
■Verify that all components mee t application requirem ent s.
■Design in filters for the analog power circuits.
■Use bulk capacitors (10-22uF) between the power and ground planes t o minimize switching noise, par-
ticularly near high-speed busses (>25 MH z).
■Use an ample supply of 0.1uF decoupling capacitors t o reduce high-frequency noise on the power and
ground planes.
■Use a single analog power and ground plane for multiple devices. Keep ferrite bead currents under 65%
of the rated load
■Avoid breaks in the ground plane, especial ly in areas where it i s shielding hig h-frequenc y signals.
■Keep power and ground noi se levels below 50mV
■Keep high-spee d signals out of the area between STE100P and the magnet ics
■Ensure that the power supply is rated for the load and that output ripple is minimal (<50mV)
■Route high-speed signals next to a continuous, unbrok en ground plane .
■Provide impedanc e m atching on long traces to prevent reflections.
■Do not route any digital signals between the STE100P and the RJ-45 connectors at the edge of the
board
■It is recommended to fill in unused areas of the signal planes with solid copper and attach them wi t h
vias to a Vcc or ground plane that is not locat ed adja cent to the signal layer.
3.2 Differenti al Signal Layou t Guidel ines
■Route differential pairs cl ose together and away from everything else
■Keep both traces of each differential pair as close to the same length as possible.
■Avoid v ias and layer changes
■Keep transmit and receive pairs away from each other. Run orthogonally, or s epa rate with a ground
plane layer.
3.3 Power and Ground
In order to obtain high s peed communications design, the power and ground pl anes may be conceptually di vid-
ed into three regions (the analog and digital power planes and the signal ground plane)
The anal og power region extends fr om the magneti cs back to the STE100P, whereas t he digit al power region
extends from the MII interfaces of the STE100P through t he rest of the board. Only components and si gnals
pertaining to the partic ular interface should be placed or routed through each respective region. The digital sec-
tion supplies power to the digital Vcce/i pin and to the external components. The analog section su pplies p ower
to Vcca pins of the STE100P.
The s i gnal ground region is one cont i nuous, unbroken plane that extends from the magneti cs through the rest
AN1301 APP LICATION NOTE
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of the board. The signal ground pl ane may be combi ned with c hassis ground or isolated f rom it. I f the ground
planes are c ombined, an isolation area is not required. When layi ng out ground planes, spec ial care must be
taken to avoid creating loop antenna effect. S om e guidelines are as fol lows-
■Run all ground plane as solid square or recta ngular regio ns
■Avoid c reating loops with ground planes around other planes
3.4 Recommendations
The following recommendations apply to design and layout of the power and ground planes and w ill pre vent the
most common signal and noise issues.
■Divide the Vcc plane into two sections - analog and digital. The break between the planes sho uld run
under the device.
■When dividing t he V cc plane, it is not necessary to add extra layers to the board. Simply crate moat s or
cutout regions in existing layers.
■Place a high-frequency bypass cap (0.1uF) near each analog Vc c pin
■Join the digital and analog sections at one or more points by ferric b eads . Ensure that the maxim um
current rating of the bead is a t least 150% of the nomin al current that is expected to flow through it.
(250mA per STE100P)
■Place a bulk capacitor (22uF) on each side of each ferrite bead to stop switching noise from travelling
through the ferrite.
For designs with multipl e STE100P’ s , it i s acceptable to supply all f rom one analog Vcc plane. This plane can
be joined to the digital Vcc plane at multiple points, with a ferrite bead at each one.
4.0 TWISTED PAIR INTERFACE
4.1 Transmit In terface Circuitry
Figure 2 shows a typical transmit i nterface circuitry. Current is sourced by the AVddt output to the centertap of
the primary side of the winding. Current flows from the centertap to TX+ and TX-. Othe r com ponents are as fol-
lows:
■R1 and R2 are 49.9 ohm resistors that provide impedance m atching to the line, which has a nominal
impedan ce of 100 ohm .
■C1 shunts any common-m ode energy present in the output to ground.
■The magne tics consists of the main winding and a common-m ode c hoke.
■The common-mode choke stops common mode energy from reaching the line. I t works toget her with
capacitor C1 to di rect common-mode energy away from the line.
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AN1301 APPLICATION NOTE
Figure 2. Transmit Interface Circuitry
4.2 Receive Termination Circui try
The receive termination circuit as shown in Figure 3 is a simple 100 ohm, 1% resistor across t he RX+/
RX- pa ir. The receive circuit c onsists of magnetics, which include a main winding and a common-m ode
choke, and termination resistance to match the line impedance. The common-mode choke can be
located on either t he primary or secondary side of the winding. Some vendors place the receive com-
mon-mod e choke on the line-side (primary) of the m ain winding while others place it on the device s ide
(secondary). Either location is acceptable.
Figure 3. Receive Interface Circuitry
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4.3 Standard termination
ST recommends a standard termination for the unused pairs on the twisted-pair interface as shown in
Figure 4. The termination basically looks like a 100 ohm load, matched to the line, which is by pas sed to
chassis ground. This termination is added for robustness and noise reduction.
Figu re 4. Suggested Termi nat i on Circuit
5.0 CRYSTAL REQUIREMENTS
The following table shows the c rystal specifications
Table 1
6.0 LE D PINS
The LED display, consists of fiv e LED s having the following charac teristics :
❥Speed LED: 100 Mbps(on ) or 10Mbps(off)
Parameter Units Min Max Nom
Frequency MHz - - 25.0
Frequency Stability ppm - +_ 100 -
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❥Receiv e LE D : Blin ks at 10Hz when r ece iving, but not co lliding
❥ Transmit LED: Blinks at 10Hz when transmitting, but not coll iding
❥ Link LED: On when 100M or 10M link ok
❥ Collis ion LED: Blinks at 20 Hz to in dic a t e a col lis ion
7.0 TYPICAL APPLICATION
While the STE100P may be used in a variety of appl ications such as multi-por t repeat ers or s witches, the
application shown below giv es a very simple way of evaluating and using the STE100P wit h minimum cir-
cuitry. (Ref e r to B ill o f Materials in Table 2 )
A typical application of the STE100P present ed here would be in designing a Fast Ethern et transceiver
with a standard M II interface and a 10/100 Mbps twisted pair connector. (Refer to Fig. 5)
In this application,
■ STE100P is the only IC needed.
■ It c onn ec ts directly to t he indust ry standard 40-pin MII connec tor.
■ It als o connec ts to the RJ-45 jack via a standard Fast Ethernet transformer.
■ 5, 4-position DIP switches are used to select the PHY address. (More details on the PHY address reg-
isters, etc. are available on the S T E10 0P datasheet)
■2, 10-position DIP switches are used for determin ation of all of t he pin-sele ctable optio ns of the
STE100P such as duplex mode, dat a rate and auto negotiation.
■STE100P also support s the MII MDIO access to all of it s intern al registers.
■LEDs are included to indicate status information such as speed, duplex mode, t ransmit and receive ac-
tivity and link status.
■There are registers with 16 bits each supported for STE100P. (More details on these registers are avail-
able in the STE100P datas heet).
■There are also 4 special registers f or advanced chip control and status information.
7.1 Schematics
The schematics for the sample application can be found on the ST website at:
http://www.st.com/stonline/prodpres/dedicate/connect/datacom/ste100p/ste100p.htm
7.2 Bill of M aterials
Following are the Bill of Material s for the STE100P sampl e applicati on.
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to change without notice. This publication supersedes and repl aces all information previously supplied. STMicroel ectronics products are not
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