AY/. M48T35 M48T35Y, M48T35Y 256 Kbit (32Kb x 8) TIMEKEEPER SRAM # INTEGRATED ULTRALOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT and BATTERY a BYTEWIDE RAM-LIKE CLOCK ACCESS = BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES and SECONDS m FREQUENCY TEST OUTPUT for REAL TIME CLOCK # AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION a WRITE PROTECT VOLTAGES (VpeFp = Power-fail Deselect Voltage): M48T35: 4.5V < Vprp< 4.75V M48T35Y: 4.2V < Vpro<s 4.5V M48T35V: 2.7V < Vpro< 3.0V a SELF-CONTAINED BATTERY and CRYSTAL in the GAPHAT DIP PACKAGE = PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT TOP {to be Ordered Separately) a SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP CONTAINS the BATTERY and CRYSTAL a PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 32K x 8 SRAMs DESCRIPTION The M48T35/35Y/35V TIMEKEEPER RAM is a 32 Kbit x 8 non-volatile static RAM and real time clock. The monolithic chipis available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution. Table 1. Signal Names SNAPHAT (SH) Battery/Crystal PCDIP28 (PC) Battery/Crystal CAPHAT SOH28 (MH) Figure 1. Logic Diagram Voc AO-A14 M48T35 M48Tasy M48T35V my weet Vss Alo1620C AO-Al4 Address Inputs DQ0-DQ7 Data Inputs / Outputs E Chip Enable G Output Enable W Write Enable Voc Supply Voltage Vss Ground July 1998 17M48T35, M48T35Y, M48T35V Figure 2A. DIP Pin Connections Figure 2B. SOIC Pin Connections Ai4q1 2811Voc ACM 28 Ea Voc A122 27) W A122 27 WwW A7]3 267] A13 A743 26 E Ai3 A6q4 25 7] Aa Ab 4 25 CF A8 A5Q5 241] A9 A545 24 [1 AS A46 237) A11 A416 23 A111 A307 wastas 227G ASC57 ma4aatasy 22[9G A208 M4sT3asy 21] Ai0 A218 M48T35V 21 Co Aio Aigjg 20JE Aims 209E AO[] 10 19] DQ7 AO T= 10 19 5 DQ? Dao] 11 187] Da6 DQ0 CE 11 18 F5 DOs DQ1g}i2 177] Das DQ1 5 12 17 FE DOs DQe2q 13 16 [] DO4 DQ2 13 16 5 DO4 Ves 14 15 [] DQ3 ss 14 15 5 DOs Al01621B Al01622C Table 2. Absolute Maximum Ratings Symbol Parameter Value Unit Ta Ambient Operating Temperature 0 to 70 C Tste Storage Temperature (Vcc Off, Oscillator Off) 40 to 85 C Tsp Lead Solder Temperature for 10 seconds 260 C Vio Input or Output Voltages 0.3 to 7 Vv Veco Supply Voltage 0.3107 Vv lo Output Current 20 mA Pp Power Dissipation 1 WwW Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This isa stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). CAUTION: Negative undershoots below 0.3 volis are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC fo avoid damaging SNAPHAT sockeis. DESCRIPTION (cont'd) The M48T35/35Y/35V is a non-volatile pin and function equivalent to any JEDEC standard 32K x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28 pin 600mil DIP CAPHAT houses the M48T35/35Y/35V silicon with a quartz crystal and a long life lithium butten cell in a single package. a7 The 28 pin 330mil SOIC provides sockets with gald plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures re- quired for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. kyM48T35, M48T35Y, M48T35V Table 3. Operating Modes "? Mode Voc E G Ww DQo-DQa7 Power Deselect Vi x x High Z Standby 4.75V ta 5.5V Write or VIL x VIL Dn Active 4.5 to 5.5V Read or Vit Vit Vin Dour Active 3.0V to 3.6V Read Vit Vin Vie High Z Active Deselect Vigo to Vprp (min) * x Xx x High Z CMOS Standby Deselect = Vso x High Z Battery Back-up Mode Notes: 1. X = Vi or Vil; Vso = Battery Back-up Switchover Voltage. 2. See Table 7 for details. Figure 3. Block Diagram : ft it OSCILLATORAND [AN og spiporr co: ; CLOCKCHAIN, = K-saaM ARRAY | so7eale to a Jovetetetetetctneees 1 CRYSTAL ! 3] AD-Al4 i ot POWER _ : i it 4 ) DQ0-Da7 : mt 32,760 x 8 . t ro SRAM ARRAY 1 LITHIUM +! ' _ CELL + 3 O-t+E : to VOLTAGE SENSE 1 w tote ft} AND VprD p> : tt SWITCHING " b i = 1 4 CIRCUITRY ' G Vec Vss Alo1 623 The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28 lead SOIC, the battery/crystal package (i.e. SNAPHAT) part number is "M4T28- BR12SH1". As Figure 3 shows, the static memory array and the quartz controlled clock oscillator of the M48T35/35Y/35V are integrated on one silicon chip. The two circuits are interconnected at the ky Upper eight memory locations to provide user ac- cessible BYTEWIDE clock information in the bytes with addresses 7FF8h-7FFFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. Byte 7FF8h is the clock control register. This byte con- trols user access to the clock information and also stores the clock calibration setting. 3/17M48T35, M48T35Y, M48T35V Table 4. AC Measurement Conditions Input Rise and Fall Times <5ns Input Pulse Voltages Oto 3V Input and Output Timing Ref. Voltages | 1.5V Note that Output Hi-Z is defined as the point where data is no longer driven. Figure 4, AC Testing Load Circuit DEVICE 6450 UNDER TEST C = 100pF 1.75V (or 5pF) _ includes JIG capacitance Al02586 DESCRIPTION (conta) The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BIPORT read/write memory cells. The M48T35/35Y/35V includes a clock control cir- cuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T35/35Y/35V also has its own Power-fail Detect circuit. The control circuitry constantly moni- tors the single 5V supply for an out of tolerance condition. When Vcc is out of tolerance, the circuit write protects the SRAM, providing a high degree 4N7 of data security in the midst of unpredictable sys- tem operation brought on by low Vcc. As Vcc falls below approximately 3V, the control circuitry con- nects the battery which maintains data and clock operation until valid power returns. READ MODE The M48T35/35Y/35V is in the Read Mode when- ever W (Write Enable) is high and E (Chip Enable) is low. The unique address specified by the 15 Address Inputs detines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Ac- cess time (tavav) after the last address input signal is stable, providing that the E and G access times are also satistied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (teLqv) or Output Enable Access time (teLav). The state of the eight three-state Data I/O signals is controlled by E and G. It the outputs are activated before tavayv, the data lines will be driven to an indeterminate state until tavav. I_the Address In- puts are changed while E and G remain active, output data will remain valid for Qutput Data Hold time (taxax) but will go indeterminate until the next Address Access. WRITE MODE The M48T35/35Y/35V is in the Write Mode when- ever W and E are low. The start of a write is referenced from the latter occurring falling edge of W or E. Awrite is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of teHax from Chip Enable or twHax from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tpvwu prior to the end of write and remain valid for twHpx atter- ward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and_G, alow on W will disable the outputs twLaz after W falls. 4]M48T35, M48T35Y, M48T35V Table 5. Capacitance ": 2) (Ta = 25 C, f= 1 MHz ) Symbol Parameter Test Condition Min Max Unit Cn Input Capacitance Vin = OV 10 pF Co Input / Output Capacitance Vout = OV 10 pF Notes: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected Table 6A. DC Characteristics (Ta = 0 to 70C; Veco = 4.75V to 5.5V or 4.5 to 5.5V) Symbol Parameter Test Condition Min Max Unit lu ) Input Leakage Current OV < Vin <= Vec +1 pA Ito Output Leakage Current OV < Vour < Vec +5 nA lec Supply Current Outputs open 50 mA leet Supply Current (Standby) TTL E=Vn 3 mA lec Supply Current (Standby) CMOS E=Vec -0.2V 3 mA Vi Input Low Voltage -0.3 0.8 Vv Vin Input High Voltage 2.2 Veco + 0.3 Vv VoL Output Low Voltage lol = 2.1mA 0.4 Vv Vou Output High Voltage lon = -1mMA 24 Vv Notes: 1. Outputs Deselected. 2. Negative spikes of -1V allowed for up to 10ns once per Cycle. Table 6B. DC Characteristics (Ta = 0 to 70C; Veo = 3.0V to 3.6V) Symbol Parameter Test Condition Min Max Unit a? Input Leakage Current OV<Vn<= Veco +1 pA Lo Output Leakage Current OV < Vour = Vec 45 WA lec Supply Current Outputs open 30 mA lect Supply Current (Standby) TTL E=Vin 2 mA lece Supply Current (Standby) CMOS E =Vec -0.2V 2 mA vil Input Low Voltage -0.3 0.8 Vv Vin Input High Voltage 2.2 Veo + 0.3 Vv VoL Output Low Voltage lot = 2.1mA 0.4 Vv Vou Output High Voltage lon = 1mMA 2.4 Vv Notes: 2 Nodative spikes of c1V allowed for up to 10ns once per Cycle. ky 5/17M48T35, M48T35Y, M48T35V Table 7. Power Down/Up Trip Points DC Characteristics ) (Ta =0 to 70C) Symbol Parameter Min Typ Max Unit Verb Power-fail Deselect Voltage (M48T35) 4.5 46 4.75 V Verb Power-fail Deselect Voltage (M48T35Y) 4.2 4.35 45 V Verb Power-fail Deselect Voltage (M48T35V)} 2.7 29 3.0 V Vso Battery Back-up Switchover Voltage (M48T35/35Y) 3.0 Vv Vso Battery Back-up Switchover Voltage (M48T35V) Veep 100mV Vv tor Expected Data Retention Time 10 YEARS Notes: 1. All voltages referenced to Vss. 2. At 25C. 3. CAPHAT only, SNAPHAT tor = 7yrs. Table 8. Power Down/Up Mode AC Characteristics (Ta =0 to 70C) Symbol Parameter Min Max Unit tpp EorWat Vin before Power Down 0 ps tp Verp (max) ta Veep (min) Vcc Fall Time 300 Ls ten ?) Vprp (min) to Vso Veo Fall Time 10 us ir Veep{min) to Vprp (max) Veco Rise Time 10 ps tre Vso to Vprp (min) Vee Rise Time 1 ps tREC Vprp{max) to Inputs Recognized 40 200 ms Notes: 1. Verp (max) to Vero (min) fall time of less than t- may result in deselection/write protection not occurring until 200 ys after Vcc passes Vero (min). 2. Verb (min) to Vso fall time of less than tra may cause corruption of RAM data. Figure 5. Power Down/Up Mode AC Waveforms Voc VPFp (max) VpFpD (min) Vso OUTPUTS tPD INPUTS RECOGNIZED VALID jf (PER CONTROL INPUT} iRB DON'T CARE HIGH-Z Pht 4 iREC RECOGNIZED VALID (PER CONTROL INPUT} Al01168B 6/17 4]M48T35, M48T35Y, M48T35V Table 9. Read Mode AC Characteristics (Ta =0 to 70C; Vcc = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V) M48T35 /M48T35Y M48T35V Symbol Parameter 70 100 Unit Min Max Min Max tavay Read Cycle Time 70 100 ns tavov Address Valid to Output Valid 70 100 ns terav Chip Enable Low to Output Valid 70 100 ns tetav Output Enable Low to Output Valid 35 50 ns terax @ Chip Enable Low to Output Transition 5 10 ns tetax Output Enable Low to Output Transition 5 5 ns tenaz 7 Chip Enable High to Cutput Hi-Z 25 50 ns tenaz Output Enable High to Output Hi-Z 25 49 ns taxax Mm Address Transition to Output Transition 10 10 ns sores Ge = Spr eee gure 4). Figure 6. Read Mode AC Waveforms tAVAV - AO-A14 VALID k le tAVOV > 4#- 1AXOX tELQVY 1EHQZ - - tELQX * i_- iGLoV > 1GHOQZ * ?- 1GLOxX - DQo-DQ7 4 VALID - Aloge25 Note: Write Enable (W) = High ky TAZM48T35, M48T35Y, M48T35V Table 10. Write Mode AC Characteristics (Ta =0 to 70C; Vcc = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V) M48T35 / M48T35Y M48T35V Symbol Parameter 70 100 Unit Min Max Min Max tavav Write Cycle Time 70 100 ns TtAVWL Address Valid to Write Enable Low Q 0 ns TAVEL Address Valid to Chip Enable Low 0 0 ns twoWwH Write Enable Pulse Width 50 80 ns tELEH Chip Enable Low to Chip Enable High 55 80 ns twHax Write Enable High to Address Transition Q 10 ns teEHAX Chip Enable High to Address Transition 0 10 ns tovwH Input Valid to Write Enable High 30 50 ns toveH Input Valid to Ghip Enable High 30 50 ns twHDx Write Enable High to Input Transition 5 5 ns tEHDXx Chip Enable High te Input Transition 5 5 ns twiaz"*) | Write Enable Low to Output Hi-Z 25 50 ns tavWH Address Valid to Write Enable High 60 80 ns tavEH Address Valid to Chip Enable High 60 80 ns twHax 7) | Write Enable High to Output Transition 5 10 ns Notes: 1. C_ = 5pF (see Figure 4). 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. DATA RETENTION MODE With valid Vec applied, the M48T35/35Y/35V oper- ates as a conventional BYTEWIDE static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when Vcc falls within the Vprp(max), Verp(min) window. All outputs become high imped- ance, and all inputs are treated as "dont care." Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAMs content. At voltages below Vprp(min}, the user can be assured the memory will be in a write protected state, provided the Vcc fall time is not less than tr. The M48T35/35Y/35V may respond te transient noise spikes on Vcc that reach into the deselect window during the time the device is sampling Vec. Therefore, decoupling of the power supply lines is recommended. 8/17 When Vcc drops below Vso, the control circuit switches power to the internal battery which pre- serves data and powers the clock. The internal button cell will maintain data in the M487T35/35Y/35V for an accumulated pericd of at least 7 years when Vccis less than Vso. As system power returns and Vcc rises above Vso, the battery is disconnected, and the power supply is switched to external Vcc. Write protection continues until Voc reaches Vprp (min) plus trRec (min). E should be kept high as Vcc rises past VpFp(min) to prevent inadvertent write cycles prior to processor stabili- zation. Normal RAM operation can resume trec after Vec exceeds Vprp(max}. For more information on Battery Storage Lite reter to the Application Note AN1012. 4]M48T35, M48T35Y, M48T35V Figure 7. Write Enable Controlled, Write AC Waveforms AO-A14 E Ww tWHDX DQ0-BQ7 DATA INPUT tDVWH Aloog26 Figure 8. Chip Enable Controlled, Write AC Waveforms _ tAVAV AO-A14 VALID tAVEH P iAVEL LEH - tEHAX __ a / _="" ! W i / fe tEHDX DQ0-BQ7 DATA INPUT p. iDVEH * | Alogg27 4] 97M48T35, M48T35Y, M48T35V CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BIPORT TIME- KEEPER cells in the RAM array are only data registers, and not the actual clock counters, updat- ing the registers can be halted without disturbing the clock itself. Updating is halted when a 1 is written to the READ bit, D6 inthe Control Register 7FF8h. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated si- multaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a O. Setting the Clock Bit D7 of the Control Register 7FF8h is the WRITE bit. Setting the WRITE bit to a 1, like ihe READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 11}. Resetting the WRITE bit to a 0 then transfers the values of all time registers 7FF9h-7FFFh to the actual TIMEKEEPER counters and allows normal Table 11. Register Map operation toresume. The FT bit and the bits marked as 0 in Table 11 must be written to 0 to allow for normal TIMEKEEPER and RAM operation. After the WRITE bit is reset, the next clock update will occur in approximately one second. See the Application Note AN923 "TIMEKEEPER rolling into the 21st century" on the ST Web site for information on Century Rollover. Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be tumed off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to al stops the oscillator. The M48T35/35Y/35V is shipped trom ST Microelectronics with the STOP bit set to a 1. When reset to a 0, the M487T35/35Y/35V oscillator star's within 1 second. Calibrating the Clock The M48T35/35Y/35V is driven by a quartz control- led oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm {parts per million) oscillator frequency error at 25C, which equates to about + 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T35/35Y/35V improves to better than +4 ppm at 25C. Data Function/Range Address BCD Format D7 D6 D5 D4 D3 D2 D1 Do 7FFFH 10 Years Year Year 00-99 7FFEh 0 0 0 10M. Month Month 01-12 7FFDh 0 0 10 Date Date Date 01-31 7FFCh 0 FT CEB CB 0 Day Century/Day 0-1/01-07 7FFBh 0 0 10 Hours Hours Hour 00-23 7FFAN 0 10 Minutes Minutes Minutes 00-59 7FF9h ST 10 Seconds Seconds Seconds 00-59 7FF8h W R $ Calibration Control Keys: S =SIGN Bit FT =FREQUENCY TEST Bit (Must be set to 0 upon power, for normal clock operation) R_ =READ Bit W = WRITE Bit ST =STOP Bit CEB= CENTURY ENABLE Bit CB =CENTURY Bit 0 = Must be set to 0 Note: When CEB is set to1, CB will toggle from 0 to1 or from 1 to O at the turn of the cantury (dependent upon the initial value set). When CEB is sat to 0, CB will not toggle. The WRITE Bit does not need to be sat to write to CEB and CE. 10/17 kyM48T35, M48T35Y, M48T35V The oscillation rate of any crystal changes with temperature (see Figure 10). Most clock chips com- pensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The M48T35/35Y/35V design, however, employs peri- odic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 9. The number of times pulses are blanked (sub- tracted, negative calibration} or split (added, posi- tive calibration) depends upon the value loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, sub- tracting counts slows the clock down. The Calibration byte occupies the five lower order bits (D4-D0)} in the Control Register 7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit DS is a Sign bit; 1 indicates positive calibration, 0 indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. It a binary 1is loaded inte the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is, +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or - 5.35 seconds per month which corresponds to a total range of +5.5 or - 2.75 minutes per month. Figure 9. Clock Calibration Two methods are available for ascertaining how much calibration a given M48T35/35Y/35V may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has te do is provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manu- facturing environment, and involves the use of some test equipment. When the Frequency Test {FT) bit, the seventh-most significant bit in the Day Register is set to a 1, and D7 of the Seconds Register is a 0' (Oscillator Running), DQO will toggle at 512Hz during a read of the Seconds Register. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 PPM oscillator Trequency error, requiring a -10 (WRO01010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The FT bit MUST be reset to '0 in order to read the seconds register. A valid read mode (G and E enabled, W disabled) must be set in order to see the 512Hz signal on DQ6. The FT bit is autemat- ically Reset on power-up. For more information on calibration, see the Appli- cation Note AN934 "TIMEKEEPER Calibration". NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION JI Lt LP LS Le J LIJUU LL JL LL Aloos94B 4] 11/17M48T35, M48T35Y, M48T35V Figure 10. Crystal Accuracy Across Temperature ppm 20 -20 4 -40 4 -60 _ -80 4 T,=25C = -0.038 PEM (T-T,y+ 10% Cc? -100 35 40 45 50 55 60 65 70 C Alo2124 Figure 11. Supply Voltage Protection = 0.1 pF A Veco Vgs DEVICE Alog2169 12/17 POWER ON DEFAULTS Upon application of power to the device, the follow- ing register bits are set to a 0 state: FT, W, R. POWER SUPPLY DECOUPLING and UNDER- SHOOT PROTECTION Icc transients, including those produced by output switching, can produce voltage fluctuations, result- ing in spikes on the Vcc bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the Vcc bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capaci- tor value of 0.1pF (as shown in Figure 11) is rec- ommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on Vcc that drive it to values below Vss by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommeded to connect a schottky diode from Vcc to Vss (cathode connected to Vcc, anode to Vss). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. kyM48T35, M48T35Y, M48T35V ORDERING INFORMATION SCHEME Example: M48T35 -70 MH 1 TR Supply Voltage and Write Speed Package Temp.Range Shipping Method Protect Voltage for SOIC 35") Veco = 4.75V to 5.5V -70 7Ons PC PCDIP28 1 Oto 70C blank Tubes Verb = 4.5V to 4.75V (M48T35/Y} MH @ SOH28 TR Tape & Reel 35Y Vcc = 4.5V to 5.5V -10 100ns Vprp = 4.2V to 4.5V (M48T35V) 35V Vee = 3.0V to 3.6V Veep = 2.7V to 3.0V Notes: 1. The M48T35 part is offered with the PCDIP28 (i.6. CAPHAT) package only. 2. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number M4T28-BR12SH1" in plastic tube or M4728-BR12SH1TR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery/crystal package "M4T28-BR12SH1" in conductive foam since this will drain the lithium button-cell battery. For alist of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 4] 13/17M48T35, M48T35Y, M48T35V PCDIP28 - 28 pin Plastic DIP, battery CAPHAT inches Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 aA a A2| A I x i ! aA a \ | | MY BiH be B Le 3 eA < e a D al N a ) E @ PCDIP Drawing is not to scale. 14/17 4]M48T35, M48T35Y, M48T35V SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT inches Min Drawing is not to scale. kyr 15/17M48T35, M48T35Y, M48T35V SH - SNAPHAT Housing for 28 lead Plastic Small Outline inches Min Al A2 eA B + eB Drawing is not to scale. 16/17 4]M48T35, M48T35Y, M48T35V Information tumished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subjact to change without notice. This publication supersedes and replaces all information previously supplied. STMicroslectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1998 ST Microelectronics - All Rights Reserved TIMEKEEPER and SNAPHAT are registered trademarks of STMicroelectronics CAPHAT, BYTEWIDE and BiPORT are trademarks of STMicroelectronics STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. kyr 177