September 2006
Advance Information
Copyright © Alliance Memory. All rights reserved.
AS7C1029
5V 256K X 4 CMOS SRAM (Center power and ground)
12/5/06, v. 1.0 Alliance Memory P. 1 of 9
®
Features
• Industrial (-40o to 85oC) temperature.
• Organization: 262,144 x 4 bits
•High speed
- 12 ns address access time
- 6 ns output enable access time
• Low power consumption via chip deselect
• Easy memory expansion with
CE
,
OE
inputs
• Center power and ground
• TTL/LVTTL-compatible, three-state I/O
• JEDEC-standard package
- 32-pin, 400 mil SOJ
• ESD protection ≥ 2000 volts
Logic block diagram
A
11
A
10
262,144 x 4
Array
(262,144)
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A
12 A
13 A
14 A
15 A
16
I/O0
I/O3
VCC
GND
OE
CE
WE
Address decoder
Address decoder
Control
circuit
Sense amp
A8
A9
A
17
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A17
A16
A15
OE
I/O3
GND
VCC
I/O2
A12
A11
A10
A9
A8
NC
NC
A0
A1
A2
A3
CE
I/O0
VCC
GND
I/O1
WE
A4
A5
A6
A7
NC
AS7C1029
32-pin SOJ (400 mil)
A13
A14
AS7C1029
12/5/06, v. 1.0 Alliance Memory P. 2 of 9
®
Functional description
The AS7C1029 is a 5V high-performan ce CMOS 1,048,576-bit S tatic Random Access Memory (SRAM) devices or ganized as
262,144 x 4 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are
desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high-
performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory
systems.
When CE is high, th e device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is
static, then full standby power is reached (ISB1).
A write cycle is accomplished by asserting write enable (
WE
) and chip enable (
CE
). Data on the inpu t pins I/O0 through I/O7
is written on the rising edge of
WE
(write cycle 1) or
CE
(write cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outpu ts have been disabled with output enable (
OE
) or write enable (
WE
).
A read cycle is accomplished by asserting output enable (
OE
) and chip enable (
CE
), with write enable (
WE
) high. The chips
drive I/O pins with the d ata word referenced by th e in put address. When either chip enable or ou tput enable is inactive or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1029 is packaged in
common industry standard packages.
Notes:
Stresses greater than those listed under Absolute Maximum Rating s may cause permanent damage to the device. This is a stress rating only and functi onal
operation of the devic e at these or any other conditions outside th ose indicated in the operational sections of this sp ecification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Key: X = don’t care, L = low, H = high.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.50 +7.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC + 0.5 V
Power dissipation PD–1.25W
Storage temperature (plastic) Tstg –55 +125 o C
Ambient temperature with VCC applied Tbias –55 +125 o C
DC current into outputs (low) IOUT –50mA
Truth table
CE WE OE
Data Mode
H X X High Z Standby (ISB, ISB1)
L H H High Z Output disabl e (I CC)
LHL D
OUT Read (ICC)
LLX D
IN Write (ICC)
AS7C1029
12/5/06, v. 1.0 Alliance Memory P. 3 of 9
®
Notes:
VIL min = -1.5V for pulse width less than 5n s, onc e per cycle.
VIH max = VCC+2.0V for pulse width less than 5ns, once per cycle .
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
Input voltage VIH 2.2 – VCC + 0.5 V
VIL –0.5 – 0.8 V
Ambient operating temperature (Industrial) TA–40 – 85 o C
DC operating characteristics (over the operating range)1
Parameter Symbol Test conditions
AS7C1029-12
UnitMin Max
Input leakage current | ILI | VCC = Max, VIN = GND to VCC –5μA
Output leakage current | ILO | VCC = Max, CE = VIH,
Vout = GND to VCC –5μA
Operating power supply current ICC VCC = Max
CE ≤ VIL, f = fMax, IOUT = 0 mA – 160 mA
Standby power supply current1ISB VCC = Max
CE ≥ VIH, f = fMax –40mA
ISB1
VCC = Max
CE ≥ VCC–0.2 V,
VIN ≤ 0.2 V or VIN ≥ VCC –0.2 V,
f = 0
10 mA
Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 V
VOH IOH = –4 mA, VCC = Min 2.4 – V
Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A,
CE
,
WE
,
OE
VIN = 3dV 8 pF
I/O capacitance CI/O I/O VIN = VOUT = 3dV 8 pF
Note:
This parameter is guaranteed by device cha racte riza tion, but is not production tested.
AS7C1029
12/5/06, v. 1.0 Alliance Memory P. 4 of 9
®
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CE and OE controlled)3,6,8,9
Read cycle (over the operating range)3,9
Parameter Symbol
AS7C1029-12
Unit NotesMin Max
Read cycle time tRC 12 – ns
Address access time tAA –12ns3
Chip enable (
CE
) access time tACE –12ns3
Output enable (
OE
) access time tOE –6ns
Output hold from address change tOH 4–ns5
CE
low to output in low Z tCLZ 3 – ns 4, 5
CE
low to output in high Z tCHZ 0 6 ns 4, 5
OE
low to output in low Z tOLZ 0 – ns 4, 5
OE
high to output in high Z tOHZ 0 5 ns 4, 5
Power up time tPU 0 – ns 4, 5
Power down time tPD –12ns4, 5
Undefined/don’t careFalling inputRising input
A
ddress
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
Data valid
t
RC1
CE
t
OHZ
AS7C1029
12/5/06, v. 1.0 Alliance Memory P. 5 of 9
®
Write waveform 1 (WE controlled)10,11
Write waveform 2 (CE controlled)10,11
Write cycle (over the operating range)11
Parameter Symbol
AS7C1029-12
Unit NotesMin Max
Write cycle time tWC 12 – ns
Chip enable (
CE
) to write end tCW 10 – ns
Address setup to write end tAW 10 – ns
Address setup time tAS 0–ns
Write pulse width tWP 10 – ns
Write recovery time tWR 0–ns
Address hold from end of write tAH 0–ns
Data valid to write end tDW 7–ns
Data hold time tDH 0 – ns 4, 5
Write enable to output in high Z tWZ 0 5 ns 4, 5
Output active from write end tOW 3 – ns 4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
t
AW
Address
CE
WE
D
OUT
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
Data valid
D
IN
t
WR
AS7C1029
12/5/06, v. 1.0 Alliance Memory P. 6 of 9
®
AC test conditions
Notes:
1 During VCC power-up, a pull-up resistor to VCC on
CE
is required to meet ISB specification.
2 This parameter is sampled, but not 100% teste d.
3 For test conditions, see AC Test Conditions, Figures A and B.
4t
CLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±200 mV from steady-state voltage.
5 This parameter is guarante ed, but not 100% tested.
6
WE
is high for read cycle.
7
CE
and
OE
are low for read cycle.
8 Address is valid prior to or coincident with
CE
transition low.
9 All read cycle timings are reference d from the last valid addre ss to the first transitioning address.
10 N/A
11 All write cycle timings are referenced fro m the last valid addre ss to the first transitioning addre ss.
12 N/A.
13 C = 30 pF, except all high Z a nd low Z parameters where C = 5 pF.
– Output load: see Figure B.
– Input pulse level: GND to 3. 0 V. See Figure A.
– Input rise and fall times: 3 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
168
Ω
Thevenin equivalent:
D
OUT
+1.728 V
255
Ω
C
13
480
Ω
D
OUT
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
3 ns
AS7C1029
12/5/06, v. 1.0 Alliance Memory P. 7 of 9
®
Package dimensions
eD
E1
Pin 1
b
B
A1
A2 c
E
Seating
plane
E2
A
32-pin SOJ
400 mil
Symbol
32-pin SOJ
400 mil
Min Max
A0.132 0.146
A1 0.025 -
A2 0.105 0.115
B0.026 0.032
b0.015 0.020
c0.007 0.013
D0.820 0.830
E0.354 0.378
E1 0.395 0.405
E2 0.435 0.445
e0.050 BSC
Note: This part is compatible with both pin numbering
conventions used by various manufacturers.
AS7C1029
12/5/06, v. 1.0 Alliance Memory P. 8 of 9
®
Ordering Codes
Package Volt/Temp 12 ns
Plastic SOJ, 400 mil 5V industrial AS7C1029-12JIN
Part numbering system
AS7C 1029C –XX X X X
SRAM prefix Device
number Access time Package:
J = SOJ 400 mil
Temperature range
I = industrial, -40°
C to 85° C
N = LEAD FREE
PART
Alliance Memory, Inc.
1116 South Amphlett
San Mateo, CA 94402
Tel: 650-525-3737
Fax: 650-525-0449
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS7C1029
Document Version: v. 1.0
© Copyright 2003 Alliance Mem ory, Inc. A ll rights reserved. Our three-point logo, our name and Intelliwa tt are trademarks or registered trademarks of
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document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein repres ents Alli ance's b est data a nd/or e stimat es at th e time of issuan ce. Allianc e reserve s the right t o cha nge or correct this data at any
time, without n otice. If the produ ct described h erein is under develop ment, significant c hanges to the se specifications are p ossible. The information in
this product data sheet is intended to be general de scriptive inform ation for potential custo mers and users, and is not intended to operate as, o r provide,
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claims arising from such use.
AS7C1029
®
®
