CPC7581 Line Card Access Switch Features Description * Small 16-pin SOIC or micro-leadframe package * MLP package printed-circuit board footprint is 60 percent smaller than the SOIC version, 40 percent smaller than fourth generation EMR solutions. * Monolithic IC reliability * Low, matched RON * Eliminates the need for zero-cross switching * Flexible switch timing for transition from ringing mode to idle/talk mode. * Clean, bounce-free switching * Tertiary protection consisting of integrated current limiting, thermal shutdown for SLIC protection * 5 V operation with power consumption < 10 mW * Intelligent battery monitor * Latched logic-level inputs, no external drive circuitry required * SOIC package pin-compatible with Legerity product The CPC7581 is a monolithic solid-state four-pole switch in a 16-pin package. It provides the necessary functions to replace a 2-Form-C electromechanical relay on traditional analog and integrated voice and data (IVD) line cards found in central office, access, and PBX equipment. The CPC7581 contains solid-state switches for tip and ring lead line break and ringing injection/ringing return. The device requires only a +5 V supply and offers break-before-make and make-beforebreak operation using simple logic-level inputs. The CPC7581xA versions include an SCR that provides protection to the SLIC and subsequent circuitry during a fault condition. The CPC7581xC versions are functionally identical to the CPC7581xA versions, but with higher SCR hold current. Ordering Information Applications * * * * * * * * Specify CPC7581Bx for SOIC package in tubes. Specify CPC7581Mx for MLP package in tubes. Add -TR to the part number for tape and reel packaging. Central office (CO) Digital Loop Carrier (DLC) PBX Systems Digitally Added Main Line (DAML) Hybrid Fiber Coax (HFC) Fiber in the Loop (FITL) Pair Gain System Channel Banks Part Number Description CPC7581xA CPC7581xB Four-pole with protection SCR, tubed Four-pole without protection SCR, tubed Four-pole with protection SCR and higher protection SCR hold current, tubed CPC7581xC Figure 1. CPC7581 Block Diagram +5 Vdc 6 TRING 7 VDD CPC7581 SW3 Tip TLINE X 3 2 TBAT X SW1 Secondary Protection Ring SLIC 15 RBAT SW2 RLINE 14 X SW4 SCR and Trip Circuit (CPC7581xA/C) X 12 VBAT 300 (min.) 1 FGND VREF L A T C H Switch Control Logic 16 VBAT 9 DGND 10 11 INRINGING LATCH 8 TSD RINGING DS-CPC7581-R3.0 12/6/2002 www.clare.com 1 CPC7581 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Absolute Maximum Ratings (at 25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Electrical Characteristics, TA = -40 C to +85 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 4 4 4 4 5 6 7 7 9 2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.1 Make-Before-Break Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2 Break-Before-Make Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 TSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.9 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 www.clare.com 13 13 13 13 14 14 14 15 15 15 16 16 16 16 R3.0 12/6/2002 CPC7581 1. Specifications 1.1 Package Pinout CPC7581 FGND 1 16 VBAT TBAT 2 15 RBAT TLINE 3 14 RLINE NC 4 13 NC NC 5 12 RRINGING T RINGING 6 11 LATCH VDD 7 10 INRINGING 8 9 DGND TSD 1.2 Pinout Pin Name 1 FGND Fault ground 2 TBAT Connect to tip on SLIC side 3 TLINE Connect to tip on line side 4 NC Not connected 5 NC Not connected 6 TRINGING 7 VDD +5 V supply 8 TSD Temperature shutdown pin. Bi-directional I/O with internal pullup to VDD. Output function indicates status of thermal shutdown circuitry. Input function can be used to set the all-off mode using an open-drain or open-collector type output. 9 DGND 10 INRINGING 11 LATCH 12 RRINGING 13 NC 14 RLINE Connect to ring on the line side 15 RBAT Connect to ring on the SLIC side 16 VBAT Battery voltage supply. Must be capable of sourcing the trigger current for proper operation of the protection SCR. Rev. 3.0 12/6/2002 Description Connect to ringing generator return Digital ground Logic-level switch control input Data latch control, active high, transparent low Connect to ringing generator current limiting resistor Not connected www.clare.com 3 CPC7581 1.3 Absolute Maximum Ratings (at 25 C) Parameter Minimum Maximum Unit Operating temperature -40 +110 C Storage temperature -40 +150 C Operating relative humidity 5 95 % Pin soldering temperature (10 seconds max) - +220 C -0.3 7 V - -85 V -0.3 VDD + 0.3 V Logic input to switch output isolation - 330 V Switch open contact isolation (SW1, SW2, SW3) - 330 V Switch open contact isolation (SW4) - 480 V +5 V power supply Battery Supply Logic input voltage Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability. 1.4.1 Power Supply Specifications Supply Minimum Typical Maximum Unit VDD +4.5 +5.0 +5.5 V VBAT1 -19 - -72 V 1 VBAT is used only for internal protection circuitry. If VBAT rises above -10 V, the device will enter the all-off state and will remain in the all-off state until the battery drops below -15 V. 1.4 Electrical Characteristics, TA = -40 C to +85 C ESD Rating (Human Body Model) 1000 V Unless otherwise specified, minimum and maximum values are production testing requirements. Typical values are characteristic of the device and are the result of engineering evaluations. Typical values are provided for information purposes only and are not part of the testing requirements. 1.4.2 Break Switches, SW1 and SW2 Parameter Conditions Symbol Minimum Typical Maximum Unit 1 A Off-state leakage current +25 C VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V +85 C VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V -40 C VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V 0.1 ISW - 0.3 0.1 RON +25 C +85 C -40 C RON match 4 ISW = 10 mA, 40 mA, RBAT and TBAT = -2 V Per on-resistance test condition of SW1, SW2. Magnitude RON SW1-RON SW2 RON RON www.clare.com - - 14.5 - 20.5 28 10.5 - 0.15 0.8 Rev. 3.0 12/6/2002 CPC7581 Parameter Conditions Symbol Minimum Typical Maximum Unit DC current limit +25 C +85 C VSW (on) = 10 V -40 C ISW Dynamic current limit (t = <0.5 s) Break switches on, all other switches off, apply 1 kV at 10/1000 s pulse, with appropriate protection in place. - 300 - 80 160 - - 400 425 - 2.5 - A 1 A 200 - V/s Typical Maximum Unit 1 A mA Logic input to switch output isolation +25 C VSW (TLINE, RLINE) = 320 V, logic inputs = gnd +85 C VSW (TLINE, RLINE) = 330 V, logic inputs = gnd -40 C VSW (TLINE, RLINE) = 310 V, logic inputs = gnd dv/dt sensitivity - 0.1 ISW - 0.3 0.1 - 1.4.3 Ringing Return Switch, SW3 Parameter Conditions Symbol Minimum Off-state leakage current +25 C VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V +85 C VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V -40 C VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V 0.1 ISW - 0.3 0.1 RON +25 C +85 C ISW (on) = 0 mA, 10 mA RON - -40 C 60 - 85 100 45 - DC current limit +25 C +85 C VSW (on) = 10 V -40 C Dynamic current limit (t = <0.5 s) - 135 70 85 210 ISW Ringing switches on, all other switches off, apply 1 kV at 10/1000 s pulse, with appropriate protection in place. - mA - 2.5 A Logic input to switch output isolation +25 C VSW (TRINGING, TLINE) = 320 V, logic inputs = gnd +85 C VSW (TRINGING, TLINE) = 330 V, logic inputs = gnd -40 C VSW (TRINGING, TLINE) = 310 V, logic inputs = gnd dv/dt sensitivity - Rev. 3.0 12/6/2002 0.1 ISW - 0.3 1 A - V/s 0.1 - www.clare.com 200 5 CPC7581 1.4.4 Ringing Switch, SW4 Parameter Conditions Symbol Minimum Typical Maximum Unit 1 A 1.5 3 V 0.1 0.25 mA ISW - 150 mA - - 2 A IRINGING 300 - A RON 10 15 1 A 200 - V/s Unit Off-state leakage current +25 C VSW (differential) = -255 V to +210 V VSW (differential) = +255 V to -210 V +85 C VSW (differential) = -270 V to +210 V VSW (differential) = +270 V to -210 V -40 C VSW (differential) = -245 V to +210 V VSW (differential) = +245 V to -210 V On Voltage ISW (on) = 1 mA 0.05 ISW 0.1 0.05 - Ringing generator current to ground during VDD = 5 V, INRINGING = 0 ringing - IRINGING On steady-state current* Inputs set for ringing mode Surge current* Ringing switches on, all other switches off, apply 1 kV at 10/1000 s pulse, with appropriate protection in place. Release current - RON ISW (on) = 70 mA, 80 mA Logic input to switch output isolation +25 C VSW (RRINGING, RLINE) = 320 V, logic inputs = gnd +85 C VSW (RRINGING, RLINE) = 330 V, logic inputs = gnd -40 C VSW (RRINGING, RLINE) = 310 V, logic inputs = gnd dv/dt sensitivity - 0.1 ISW - 0.3 0.1 - *Secondary protection and ringing source current limiting must prevent exceeding this parameter. 1.5 Additional Electrical Characteristics Parameter Conditions Symbol Minimum Typical Maximum Digital input characteristics Input low voltage - VIL - 2.2 1.5 Input high voltage - VIH 3.5 2.3 - Input leakage current (high) VDD = 5.5 V, VBAT = -75 V, VIH = 5 V IIH - 0.1 1 Input leakage current (low) VDD = 5.5 V, VBAT = -75 V, VIL = 0 V IIL - 0.1 1 VDD = 5 V, VBAT = -48 V, measure IDD and IBAT - 5.5 10 P 6.5 10 V A Power requirements Power consumption in talk and all-off states Power consumption in ringing state 6 www.clare.com mW Rev. 3.0 12/6/2002 CPC7581 Parameter Conditions VDD current in talk and all-off states VDD current in ringing state VDD = 5 V, VBAT = -48 V VBAT current in any state Symbol Minimum Typical Maximum - 1.1 2.0 IDD IBAT Unit mA - 1.3 2.0 - 0.1 10 110 125 150 A Temperature Shutdown Requirements (temperature shutdown flag is active low) Shutdown activation temperature Shutdown circuit hysteresis - - C 10 - 25 Temperature shutdown requirements are not production tested, but rather guaranteed by design. Rev. 3.0 12/6/2002 www.clare.com 7 CPC7581 1.6 Protection Circuitry Electrical Specifications Parameter Conditions Symbol Minimum Typical Maximum Voltage drop at Apply dc current limit of break continuous current (50/ switches 60 Hz) Forward Voltage - 2.1 3 Voltage drop at surge current Forward Voltage - Unit Parameters Related to the Diodes in the Diode Bridge Apply dynamic current limit of break switches V 5 - - * A - mA Parameters Related to the Protection SCR - Surge current 60 (CPC7581xA) 70 (CPC7581xC) Trigger current (+25 C) ITRIG - Trigger current (+85 C) - 110 (CPC7581xA) 135 (CPC7581xC) Hold current (+25 C) IHOLD Hold current (+85 C) Gate trigger voltage IGATE = ITRIGGER** Reverse leakage current VBAT = -48 V On-state voltage 0.5 A, t = 0.5 ms 2.0 A, t = 0.5 ms 35 (CPC7581xA) 40 (CPC7581xC) 70 60 (CPC7581xA) (CPC7581xA) 115 110 (CPC7581xC) (CPC7581xC) VTBAT or VRBAT VBAT -4 - VBAT -2 V IVBAT - - 1.0 A VTBAT or VRBAT- - -3 - V - -5 - V *Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place. **VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate. 8 www.clare.com Rev. 3.0 12/6/2002 CPC7581 1.7 Truth Table State INRINGING Talk 0 Ringing 1 Latched X All-Off X TSD1 Latch 0 1 or floating Break Switches Ringing Switches On Off Off On 1 Unchanged 02 X Off Off 1The thermal shutdown mechanism is active with TSD either floating or equal to 5 V. It cannot be disabled. 2Forcing T SD to ground overrides the logic input pins and forces an all-off state. 2. Functional Description 2.1 Introduction potentials are also reduced by the current limiting and thermal shutdown circuits. The CPC7581 has three states: * Talk. Line break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open. * Ringing. Ringing switches SW3 and SW4 closed, line break switches SW1 and SW2 open. * All-off. All switches open. See "Truth Table" on page 9 for more information. The CPC7581 offers break-before-make and makebefore-break switching from the ringing state to the talk state with simple logic-level input control. Solidstate switch construction means no impulse noise is generated when switching during ring cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State control is via logic-level input so no additional driver circuitry is required. The line break switches SW1 and SW2 are linear switches that have exceptionally low RON and excellent matching characteristics. The ringing switch SW4 has a breakdown voltage rating of 480 V. This is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ringing generator). Integrated into the CPC7581 is a over voltage clamping circuit, active current limiting, and a thermal shutdown mechanism to provide protection to the SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and hazardous potentials are steered to ground via diodes and, in CPC7581xA and CPC7581xC parts, an integrated SCR. Power-cross Rev. 3.0 12/6/2002 To protect the CPC7581 from an overvoltage fault condition, the use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip and ring terminals to a level below the maximum breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7581 will meet all relevant ITU, LSSGR, TIA/EIA and IEC protection requirements. The CPC7581 operates from a +5 V supply only. This gives the device extremely low idle and active power consumption and allows use with virtually any range of battery voltage. Battery voltage is also used by the CPC7581 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7581 enters the all-off state. 2.2 Switch Logic The CPC7581 provides, when switching from the ringing state to the talk state, the ability to control the release timing of the ringing switches SW3 and SW4 relative to the state of the line break switches SW1 and SW2 using simple logic-level input. This is called make-before-break or break-before-make operation. When the line break switch contacts (SW1 and SW2) are closed (or made) before the ringing switch contacts (SW3 and SW4) are opened (or broken), this is called make-before-break operation. Break-beforemake operation occurs when the ringing contacts www.clare.com 9 CPC7581 (SW3 and SW4) are opened (broken) before the line break contacts (SW1 and SW2) are closed (made). the operational sequence shown in "Make-Before-Break Operation (Ringing to Talk Transition)" on page 10 to occur. To use make-before-break ringing switch release timing, assert INRINGING during ringing. This causes 2.2.1 Make-Before-Break Operation (Ringing to Talk Transition) Timing Ringing Return Switch (SW3) Ringing Switch (SW4) State INRINGING Ringing 1 - Off On On Makebeforebreak 0 SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of the ringing cycle. In this transition state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. On Off On Talk 0 Zero-cross current has occurred On Off Off Latch 0 TSD Break Switches 1 or Floating To use break-before-make ringing switch release timing, assert TSD during ringing. This causes the operational sequence shown in "Break-Before-Make Operation (Ringing to Talk Transition)" on page 10 to occur. 2.2.2 Break-Before-Make Operation (Ringing to Talk Transition) State INRINGING Ringing 1 All-off 1 All-off 1 Talk 0 Latch 0 Ringing Return Switch (SW3) Ringing Switch (SW4) TSD Timing Break Switches 1 or floating - Off On On Hold this state for one-half of the ringing cycle. SW4 waiting for zero current to turn off. Off Off On Zero current has occurred. SW4 has opened Off Off Off Release break switches On Off Off 0 1 or floating Logic states and explanations are given in "Truth Table" on page 9. in input as long as the latch is at logic 1. The TSD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and the TSD input will override state control. 2.3 Data Latch The CPC7581 has an integrated data latch. The latch operation is controlled by logic-level input pin 11 (LATCH). The data input of the latch is pin 10 (INRINGING), while the output of the data latch is an internal node used for state control. When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected in a change is switch state. When the LATCH control pin is at logic 1, the data latch is active and a change in input control will not affect switch state. The switches will remain in the position they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes 10 2.4 TSD The thermal shutdown mechanism activates when the device die temperature reaches a minimum of 110 C, placing the device in the all-off state regardless of logic input. During thermal shutdown mode, pin 8 (TSD) will read a nominal 0 V. Normal output of TSD is typically equal to VDD. If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross event, the device temperature will rise and the thermal www.clare.com Rev. 3.0 12/6/2002 CPC7581 shutdown will activate forcing the switches to the all-off state. At this point the current measured through the break switches (SW1 and SW2) will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the de-activation level of the thermal shutdown circuit. This permits the device to return to normal operation. If the transient has not passed, current will flow at the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. The TSD pin is a pull-up current source with a nominal value of 300 A biased from VDD. For applications using low-voltage logic devices (lower than VDD), Clare recommends the use of an open-drain type output to control TSD. This avoids sinking the TSD bias current to ground during normal operation when the all-off state is not required. 2.5 Ringing Switch Zero-Cross Current Turn Off After the application of a logic input to turn SW4 off, the ringing switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter the logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing switches. See Clare application note AN-144, Impulse Noise Benefits of Line Card Access Switches for more information. The attributes of ringing switch SW4 may make it possible to eliminate the need for a zerocross switching scheme. A minimum impedance of 300 in series with the ring generator is recommended. 2.6 Power Supplies Both a +5 V supply and battery voltage are connected to the CPC7581. CPC7581 switch state control is powered exclusively by the +5 V supply. As a result, Rev. 3.0 12/6/2002 the CPC7581 exhibits extremely low power dissipation during both active and all-off states. The battery voltage is not used for switch control but rather as a supply for the integrated secondary protection circuitry. The integrated SCR is designed to trigger when pin 2 (TBAT) or pin 15 (RBAT) drops 2 to 4 V below the voltage on pin 16 (VBAT). This trigger prevents a fault-induced overvoltage event at the TBAT or RBAT nodes. 2.7 Battery Voltage Monitor The CPC7581 also uses the VBAT voltage to monitor battery voltage. If system battery voltage is lost, the CPC7581 immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the system battery voltage rises above -10 V and remains in the all-off state until the battery voltage drops below -15 V. This battery monitor feature draws a small current from the battery (less than 1 A typical) and adds slightly to the device's overall power dissipation. Due to the nature of the internal protection circuitry, the VBAT pin can be biased via potentials applied to TBAT or RBAT. This allows the CPC7581 switches to operate, but offers no transient protection. The supply Voltage applied to VBAT should therefor be the same supply Voltage applied to the line driver device. 2.8 Protection 2.8.1 Diode Bridge/SCR The CPC7581 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground via FGND. Voltage is clamped to a diode drop above ground. During a negative transient of 2 to 4 V more negative than the battery, the SCR conducts and faults are shunted to FGND via the SCR or the diode bridge. In order for the SCR to crowbar (or foldback), the on voltage (see "Protection Circuitry Electrical Specifications" on page 8) of the SCR must be less negative than the battery reference voltage. If the battery voltage is less negative than the SCR on www.clare.com 11 CPC7581 voltage, or if the VBAT supply is unable to source the trigger current, the SCR will not crowbar. State Subscriber Line Interfaces" for equations related to the specifications of external secondary protectors, fused resistors and PTCs. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to a diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the battery reference voltage by two to four volts, steering the current to ground. Note: The CPC7581xB does not contain the protection SCR. 2.8.2 Current Limiting function If a lightning strike transient occurs when the device in the talk state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of break switches SW1 and SW2. When a 1000V 10/1000 s pulse (GR1089-CORE lightning) is applied to the line though a properly clamped external protector, the current seen through the break switches will be a pulse with a typical magnitude of 2.5 A and a duration of less than 0.5 s. If a power-cross fault occurs with the device in the talk state, the current is passed though the break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80 mA and 425 mA, and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to power cross fault, the measured current through the break switches (SW1 and SW2) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will enter the all-off state. 2.9 External Protection Elements The CPC7581 requires only overvoltage secondary protection on the loop side of the device. The integrated protection feature described above negates the need for protection on the other (usually SLIC) side. The secondary protector limits voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7581. A foldback or crowbar type protector is recommended to minimize stresses on the device. Consult Clare's application note, AN-100, "Designing Surge and Power Fault Protection Circuits for Solid 12 www.clare.com Rev. 3.0 12/6/2002 CPC7581 3. Manufacturing Information 3.1 Mechanical Dimensions 3.1.1 SOIC 16 Pin SOIC (JEDEC Package) 10.11 MIN / 10.31 MAX (.398 MIN / .406 MAX) 1.27 (.050) 0.23 MIN / 0.32 MAX (.0091 MIN / .0125 MAX) 2.44 MIN / 2.64 MAX (.096 MIN / .104 MAX) 7.40 MIN / 7.60 MAX (.291 MIN / .299 MAX) 10.11 MIN / 10.51 MAX (.398 MIN / .414 MAX) 0.51 MIN / 1.01 MAX (.020 MIN / .040 MAX) 0.36 MIN / 0.46 MAX (.014 MIN / .018 MAX) 3.1.2 MLP 7 6 INDEX AREA TOP VIEW 0.2 0.80 (0.10) SEATING PLANE SIDE VIEW 0.02 (+0.05, -0) 0.23 0.55 0.33 (+0.07, -0.05) 1 2 EXPOSED PAD 0.55 4.0 (0.05) 0.55 (0.1) 16 6.0 (0.05) 0.80 Terminal Tip BOTTOM VIEW Dimensions in mm Rev. 3.0 12/6/2002 www.clare.com 13 CPC7581 3.2 Printed-Circuit Board Layout 3.2.1 SOIC PC Board Pattern (Top View) 1.270 (.050) 9.728 .051 (.383 .002) 1.193 (.047) .787 (.031) 3.2.2 MLP 5.75 0.75 on center 0.65 0.38 5.35 on center 6.1 Detail A 6.13 Detail A All dimensions in mm Not drawn to scale 0.66 0.47 0.65 0.38 NOTE: For optimum solder joint size, MLP package printed-circuit board pads should extend no more than .05 mm past the chip post on the short sides, and no more than .025 mm past the chip posts on the long sides. As the metallic pad on the bottom of the MLP package is connected to the substrate of the die, Clare recommends that no printed circuit board traces or vias be placed under this area to maintain minimum creepage and clearance values. 14 www.clare.com Rev. 3.0 12/6/2002 CPC7581 3.3 Tape and Reel Packaging 3.3.1 SOIC A0 6.50 3.00 R = .50 2.00 K1 B0 2.30 6.80 1.30 16.00 K0 2.70 7.50 12.00 4.00 2.00 1.50 A0 = 6.5 mm B0 = 10.3 mm 2.3 mm 2.7 mm K0 = K1 = NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS LISTED ON PAGE 5 OF EIA-481-2. 3.3.2 MLP A0 6.4 R = .50 K1 B0 7.40 16.00 K0 1.4 1.4 12.00 4.00 1.50 A0 = 6.4 mm B0 = 7.4 mm K0 = 1.4 mm K1 = 1.4 mm Rev. 3.0 12/6/2002 2.00 NOTES:1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS LISTED ON PAGE 5 OF EIA-481-2. www.clare.com 15 3.4 Soldering 3.4.1 Moisture Reflow Sensitivity Clare has characterized the moisture reflow sensitivity of LCAS products using IPC/JEDEC standard J-STD-020A. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-020A per the labelled moisture sensitivity level (MSL), level 1 for the SOIC package, and level 3 for the MLP package. 3.4.2 Reflow Profile The maximum ramp rates, dwell times, and temperatures of the assembly reflow profile should not exceed those specified in IPC standard IPC-9502, table 2. Soldering processes are limited to 220 C component body temperature. 3.5 Washing Clare does not recommend ultrasonic cleaning of LCAS parts. For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC7581-R3.0 (c) Copyright 2002, Clare, Inc. All rights reserved. Printed in USA. 12/6/2002