1
FEATURES
DESCRIPTION
APPLICATIONS
TPS2412 /13
A
C
VoltageSource
CommonVoltageRail
VDD
NOTE:R isOptional
(SET)
AC
C(BYP)
R(SET)
BYP
GND
GATE
RSET
RSVD
TPS2412
TPS2413
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.......................................................................................................................................... SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008
N+1 and ORing Power Rail Controller
•Control External FET for N+1 and ORing•Wide Supply Voltage Range of 3 V to 16.5 V
The TPS2412/13 controller, in conjunction with an•Controls Buses From 0.8 V to 16.5 V
external N-channel MOSFET, emulates the function•Linear or On/Off Control Method
of a low forward voltage diode. The TPS2412/13 canbe used to combine multiple power supplies to a•Internal Charge Pump for N-Channel MOSFET
common bus in an N+1 configuration, or to combine•Rapid Device Turnoff Protects Bus Integrity
redundant input power buses. The TPS2412 provides•Positive Gate Control on Hot Insertion
a linear turn-on control while the TPS2413 has anon/off control method.•Soft Turn on Reduces Bus Transients•Industrial Temperature Range: – 40 ° C to 85 ° C
Applications for the TPS2412/13 include a wide rangeof systems including servers and telecom. These•8-Pin TSSOP and SOIC Packages
applications often have either N+1 redundant powersupplies, redundant power buses, or both. Redundantpower sources must have the equivalent of a diode•N+1 Power Supplies
OR to prevent reverse current during faults and•Server Blades
hotplug. A TPS2412/13 and N-channel MOSFET•Telecom Systems
provide this function with less power loss than aschottky diode.•High Availability Systems
Accurate voltage sensing and a programmableturn-off threshold allows operation to be tailored for awide range of implementations and buscharacteristics. The TPS2412/13 are lower pin count,reduced feature versions of the TPS2410/11.
Table 1. Family Features
TPS2410 TPS2411 TPS2412 TPS2413
Linear gate control √ √
ON/OFF gate √ √control
Adjustable turn-off √√√√threshold
Fast comparator √ √filtering
Voltage monitoring √ √
Enable control √ √
Mosfet fault √ √monitoring
Status pin √ √
Figure 1. Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
TPS2412
TPS2413
SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008 ..........................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT INFORMATION
(1)
MOSFET GATEDEVICE TEMPERATURE PACKAGE
(1)
MARKINGCONTROL
PW (TSSOP-8) TPS2412TPS2412 LINEARD (SO-8) TPS2412– 40 ° C to 85 ° C
PW (TSSOP-8) TPS2413TPS2413 ON/OFFD (SO-8) TPS2413
(1) For package and ordering information, see the Package Option Addendum at the end of thisdocument, or see the TI Web site at www.ti.com .
over operating free-air temperature range, voltage are referenced to GND (unless otherwise noted)
VALUE UNIT
A, C, FLTR, V
DD
, voltage – 0.3 to 18 VA above C voltage 7.5 VC above A voltage 18 VGATE
(2)
, BYP voltage – 0.3 to 30 VBYP to A voltage – 0.3 to 13 VGATE above BYP
(2)
voltage 0.3 VRSET
(2)
voltage – 0.3 to 7 VGATE short to A or C or GND IndefiniteHuman body model 2 kVESD
Charged device model 500 VT
J
Maximum junction temperature Internally limited ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) Voltage should not be applied to these pins.
POWER RATINGPACKAGE θ
JA
– Low k ° C/W θ
JA
– High k ° C/W High kT
A
= 85 ° C (mW)
PW (TSSOP) 258 159 250D (SO) 176 97.5 410
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
(1) (2) (3) (4) (5) (6)
TPS2412
TPS2413
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.......................................................................................................................................... SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008
voltages are referenced to GND (unless otherwise noted)
MIN NOM MAX UNIT
V
DD
= V
)
(1)
3 16.5A, C Input voltage range TPS2412 V3≤V
DD
≤16.5 V 0.8 16.5A to C Operational voltage 5 VR
(RSET)
Resistance range
(2)
1.5 ∞kΩ
C
(BYP)
Capacitance Range
(2) (3)
800 2200 10k pFT
J
Operating junction temperature – 40 125 ° CT
A
Operating free-air temperature – 40 85 ° C
(1) V
DD
must exceed 3 V to meet gate drive specification(2) Voltage should not be applied to these pins.(3) Capacitors should be X7R, 20% or better
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(A)
, V
(C)
, V
DD
V
DD
rising 2.25 2.5V
DD
UVLO VHysteresis 0.25| I
(A)
|, Gate in active region 0.66 1A current mA| I
(A)
|, Gate saturated high 0.1C current | I
(C)
|, V
(AC)
≤0.1 V 10 µAWorst case, gate in active region 4.25 6V
DD
current mAGate saturated high 1.2
TURN ON
TPS2412 forward turn-on and regulation
7 10 13 mVvoltage
TPS2412 forward turn-on / turn-off difference R
(RSET)
= open 7 mVTPS2413 forward turn-on voltage 7 10 13 mV
TURN OFF
Gate sinks > 10 mA at V
(GATE-A)
= 2 V
135V
(A-C)
falling, R
(RSET)
= openFast turn-off threshold voltage mVV
(A-C)
falling, R
(RSET)
= 28.7 k Ω-17 -13.25 -10V
(A-C)
falling, R
(RSET)
= 3.24 k Ω-170 -142 -114V
(A)
= 12 V, V
(A-C)
: 20 mV →– 20 mV,Turn-off delay 70 nsV
(GATE-A)
begins to decreaseV
(A)
= 12 V, C
(GATE-GND)
= 0.01 µF, V
(A-C)
:Turn-off time 20 mV →– 20 mV, measure the period to 130 nsV
(GATE)
= V
(A)
GATE
V
DD
= 3 V, V
(A-C)
= 20 mV 6 7 8Gate positive drive voltage, V
(GATE-A)
V5 V ≤V
DD
≤18 V, V
(A-C)
= 20 mV 9 10.2 11.5Gate source current V
(A-C)
= 50 mV, V
(GATE-A)
= 4 V 250 290 350 µASoft turn-off sink current (TPS2412) V
(A-C)
= 4 mV, V
(GATE-A)
= 2 V 2 5 mA
(1) [3 V ≤V
(A)
≤18 V and V
(C)
= V
DD
] or [0.8 V ≤V
(A)
≤3 V and 3 V ≤V
DD
≤18 V](2) C
(BYP)
= 2200 pF, R
(RSET)
= open(3) – 40 ° C ≤T
J
≤125 ° C(4) Positive currents are into pins(5) Typical values are at 25 ° C(6) All voltages are with respect to GND.
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C
+
-
+
-
AGATE
HVUV
EN
HVUV
RSET
A
BYP
C
GND EN
A
RSVD
EN
FAST
COMP.
T >135°C
V(DD)
V(DD)
V(BIAS)
0.5V
3mV
10mV
10V
‘12: AMP
‘13:COMP
BIAS
and
Control
ChargePump
andBiasSupply
TPS2412
TPS2413
SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008 ..........................................................................................................................................
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ELECTRICAL CHARACTERISTICS (continued)over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(A-C)
= – 0.1 VV
(GATE)
= 8 V 1.75 2.35 AFast turn-off pulsed current, I
(GATE)
V
(GATE)
= 5 V 1.25 1.75Period 7.5 12.5 µsV
(A-C)
= – 0.1 V, V
(C)
≤V
DD
, 3 V ≤V
DD
≤18 V,Sustain turn-off current, I
(GATE)
15 19.5 mA2 V ≤V
(GATE)
≤18 V
MISCELLANEOUS
Thermal shutdown temperature Temperature rising, T
J
135 ° CThermal hysteresis 10 ° C
FUNCTIONAL BLOCK DIAGRAM
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A
GND
RSVD
BYP
C
GATE
1
4
8
VDD
RSET
5
TPS2412
TPS2413
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.......................................................................................................................................... SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008
PW and D PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
Input power for the gate drive charge pump and internal controls. V
DD
must be connected to a supply voltageV
DD
1 PWR
≥3 V.Connect a resistor to ground to program the turn-off threshold. Leaving RSET open results in a slightlyRSET 2 I
positive V
(A-C)
turn-off threshold.RSVD 3 PWR This pin must be connected to GND.GND 4 PWR Device ground.GATE 5 O Connect to the gate of the external MOSFET. Controls the MOSFET to emulate a low forward-voltage diode.Voltage sense input that connects to the simulated diode cathode. Connect to the MOSFET drain in theC 6 I
typical configuration.
Voltage sense input that connects to the simulated diode anode. A also serves as the reference for theA 7 I
charge-pump bias supply on BYP. Connect to the MOSFET source in the typical configuration.BYP 8 I/O Connect a storage capacitor from BYP to A to filter the gate drive supply voltage.
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DETAILED DESCRIPTION
-470.02
R(RSET) V - 0.00314
(OFF)
æ ö
ç ÷
=ç ÷
è ø
(1)
TPS2412
TPS2413
SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008 ..........................................................................................................................................
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The following descriptions refer to the pinout and the functional block diagram.
A, C: The A pin serves as the simulated diode anode and the C as the cathode. GATE is driven high when V
(AC)exceeds 10 mV. Both devices provide a strong GATE pull-down when V
(AC)
is less than the programmable fastturn-off threshold. The TPS2412 has a soft pull-down when V
(AC)
is less than 10 mV but above the fast turn-offthreshold.
Several internal comparator and amplifier circuits monitor these two pins. The inputs are protected from excessdifferential voltage by a clamp diode and series resistance. If C falls below A by more than about 0.7 V, a smallcurrent flows out of C. Protect the internal circuits with an external clamp if C can be more than 6 V lower than A.
The internal charge pump output, which provides bias power to the comparators and voltage to drive GATE, isreferenced to A. Some charge pump current appears on A due to this topology. The A and C pins should beKelvin connected to the MOSFET source and drain. A and C connections should also be short and lowimpedance, with special attention to the A connection. Residual noise from the charge pump can be reduced witha bypass capacitor at A if the application permits.
BYP: BYP is the internal charge pump output, and the positive supply voltage for internal comparator circuits andGATE driver. A capacitor must be connected from BYP to A. While the capacitor value is not critical, a 2200-pFceramic is recommended. Traces to this part must be kept short and low impedance to provide adequate filtering.Shorting this pin to a voltage below A damages the TPS2412/13.
GATE: Gate controls the external N channel MOSFET gate. GATE is driven positive with respect to A by a driveroperating from the voltage on BYP. A time-limited high current discharge source pulls GATE to GND when thefast turn-off comparator is activated. The high-current discharge is followed by a sustaining pull-down. Theturn-off circuits are disabled by the thermal shutdown, leaving a resistive pull-down to keep the gate from floating.The gate connection should be kept low impedance to maximize turn-off current.
GND: This is the input supply reference. GND should have a low impedance connection to the ground plane. Itcarries several Amperes of rapid-rising discharge current when the external MOSFET is turned off, and alsocarries significant charge pump currents.
RSET: A resistor connected from this pin to GND sets the fast V
(A-C)
comparator turn-off threshold. The thresholdis slightly positive when the RSET pin is left open. Current drawn by the resistor programs the turn-off voltage toincreasing negative values. The TPS2413 must have a negative threshold programmed to avoid an unstablecondition at light load. The expression for R
(RSET)
in terms of the trip voltage, V
(OFF)
, follows.
The units of the numerator are (V × V/A). V
(OFF)
is positive for V
(A)
greater than V
)
, V
(OFF)
is less than 3 mV, andR
(RSET)
is in ohms.
RSVD: Connect to ground.
V
DD
:V
DD
is the primary supply for the gate drive charge pump and other internal circuits. This pin must beconnected a source that is 3 V or greater when the external MOSFET is to be turned on. V
DD
may be greater orlower than the controlled bus voltage.
A 0.01- µF bypass capacitor, or 10- Ωand a 0.01- µF filter, is recommended because charge pump currents aredrawn through V
DD
.
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TYPICAL CHARACTERISTICS
0.5
1.5
2.0
2.5
3.0
0 2 4 6 8 10
I(GATE) − A
V − V
(GATE - GND)
1.0
0.0
T =125 C
J
o
T =85 C
J
o
T =25 C
J
o
T =-40 C
J
o
8.5
9.5
10.5
11.5
12.0
−40 −20 0 20 40 60 80 100 120
V(AC) − mV
T − JunctionT
Jemperature − C
o
11.0
10.0
9.0
8.0
R =Open
(RSET)
1.5
2.5
3.5
4.5
5.0
−40 −20 0 20 40 60 80 100 120
V(AC) − mV
T − JunctionT
Jemperature − C
o
4.0
3.0
2.0
1.0
T =125 C
J
o
T =25 C
J
o
T =-40 C
J
o
10
20
40
50
60
2 4 6 8 10 12 14 16 18
Delay − sm
V − V
DD
30
0
T =-40 C
J
o
T =125 C
J
o
T =25 C
J
o
0.5
1.0
2.0
2.5
3.0
2 4 6 8 10 12 14 16 18
I(VDD) −mA
V − V
DD
1.5
0.0
TPS2412
TPS2413
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.......................................................................................................................................... SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008
TPS2412 V
(AC)
REGULATION
VOLTAGE FAST TURNOFF THRESHOLD PULSED GATE SINKING CURRENTvs vs vsTEMPERATURE TEMPERATURE GATE VOLTAGE
Figure 2. Figure 3. Figure 4.
TURNON DELAY
vs V
DD
CURRENTV
DD
vs(POWER APPLIED UNTIL GATE IS V
DD
VOLTAGEACTIVE) (GATE SATURATED HIGH)
Figure 5. Figure 6.
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V(AC)
GATE
V (Right)
(GATE)
at5V/div
V (Left)
(GATE)
at5V/div
V (Left)
(AC)
at20mV/div
50ns/div
V (Left)
(AC)
at10mV/div
V (Right)
(GATE)
at10V/div V (Left)
(GATE)
at10V/div
V (Right)
(IN)
at20mVac/div
500 μs/div
V(AC)
GATE
V(IN)
TPS2412
TPS2413
SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008 ..........................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)TYPICAL TURNOFF WITH TWO ORED DEVICES ACTIVE(V
DD
= 12 V, I
(LOAD)
= 5 A, IRL3713,TRANSIENT APPLIED TO LEFT SIDE)
Figure 7.
TYPICAL TURNOFF AND RECOVERY WITH TWO ORED DEVICES ACTIVE(V
DD
= 3 V, V
A
= 18 V, I
(LOAD)
= 5 A, IRL3713,TRANSIENT APPLIED TO LEFT SIDE)
Figure 8.
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V
at2V/div
(GATE)
I
at2A/div
(GATE)
Delay=70ns,V =1Vat113ns
(GATE)
V
at20mV/div
(AC)
20ns/div
V(AC)
GATE
I(GATE
TPS2412
TPS2413
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.......................................................................................................................................... SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)TURNOFF TIME WITHC
(GATE)
= 10 nF and V
(AC)
= -20 mV (V
DD
= V
A
= 12 V)
Figure 9.
TURNOFF TIME WITHC
(GATE)
= 10 nF and V
(AC)
= -20 mV (V
DD
= 5, V
A
= 1 V)
Figure 10.
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Product Folder Link(s): TPS2412 TPS2413
APPLICATION INFORMATION
OVERVIEW
Gate
ON
Gate
OFF
Programmable
FastTurn-off
Threshold
Gnd
Programmable
FastTurn-off
Threshold
Active
Regulation
SlowTurn-off
Range
TPS2413
(SeeText)
TPS2412
(SeeText)
V +10V
(A)
V +V
(A) (T)
V(AC) V(AC)
V(GATE)
10mV
V(GATE)
3mV
10mV
3mV
TPS2412
TPS2413
SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008 ..........................................................................................................................................
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The TPS2412/13 is designed to allow an output ORing in N+1 power supply applications (see Figure 12 ), and aninput-power bus ORing in redundant source applications (see Figure 13 ). The TPS2412/13 and externalMOSFET emulate a discrete diode to perform this unidirectional power combining function. The advantage to thisemulation is lower forward voltage drop and the ability to tune the operation.
The TPS2412 turns the MOSFET on with a linear control loop that regulates V
(AC)
to 10 mV as shown inFigure 11 . With the gate low, and V
(AC)
increasing to 10 mV, the amplifier drives GATE high with all availableoutput current until regulation is reached. The regulator controls V
(GATE)
to maintain V
(AC)
at 10 mV as long as theMOSFET r
DS(on)
× I
(DRAIN)
is less than this the regulated voltage. The regulator drives GATE high, turning theMOSFET fully ON when the r
DS(on)
× I
(DRAIN)
exceeds 10 mV; otherwise, V
(GATE)
will be near V
(A)
plus theMOSFET gate threshold voltage. If the external circuits force V
(AC)
below 10 mV and above the programmed fastturnoff, GATE is slowly turned off. GATE is rapidly pulled to ground if V
(AC)
falls to the RSET programmed fastturn-off threshold.
The TPS2413 turns the MOSFET on and off like a comparator with hysteresis as shown in Figure 11 . GATE isdriven high when V
(AC)
exceeds 10 mV, and rapidly turned off if V
(AC)
falls to the RSET programmed fast turn-offthreshold.
System designs should account for the inherent delay between a TPS2412/13 circuit becoming forward biased,and the MOSFET actually turning ON. The delay is the result of the MOSFET gate capacitance charge fromground to its threshold voltage by the 290 µA gate current. If there are no additional sources holding the ORedrail voltage up, the MOSFET internal diode will conduct and maintain voltage on the ORed output, but there willbe some voltage droop. This condition is analogous to the power source being ORed in this case. The DC/DCconverter output voltage droops when its load increases from zero to a high value. Load sharing techniques thatkeep all ORed sources active solve this condition.
Figure 11. TPS2412/13 Operation
The operation of the two parts is summarized in Table 2 .
Table 2. Operation as a Function of V
AC
Turnoff Threshold
(1)
≤V
AC
≤10 mVV
(AC)
≤Turnoff Threshold
(1)
V
(AC)
> 10 mV(MOSFETV
(AC)
Forced < 10 mV
r
DS(on)
× I
LOAD
)≤10 mV
Weak GATE pull-downTPS2412 Strong GATE pull-down (OFF) V
(AC)
regulated to 10 mV GATE pulled high (ON)(OFF)TPS2413 Strong GATE pull-down (OFF) Depends on previous state (Hysteresis region) GATE pulled high (ON)
(1) Turnoff threshold is established by the value of RSET.
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TPS2412 vs TPS2413 – MOSFET CONTROL METHODS
N+1 POWER SUPPLY – TYPICAL CONNECTION
CommonBus
Concept
VDD
A
C
GND
GATE
Power Conversion Block
Input
Voltage
Power
Bus
Implementation
C(BYP)
BYP
DC/DC
Converter
DC/DC
Converter
TPS2412
TPS2413
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.......................................................................................................................................... SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008
The TPS2412 control method yields several benefits. First, the low-current GATE driver provides a gentle turn-onand turn-off for slowly rising and falling input voltage. Second, it reduces the tendency for on/off cycling of acomparator based solution at light loads. Third, it avoids reverse currents if the fast turn-off threshold is leftpositive. The drawback to this method is that the MOSFET appears to have a high resistance at light load whenthe regulation is active. A momentary output voltage droop occurs when a large step load is applied from alight-load condition. The TPS2412 is a better solution for a mid-rail bus that is re-regulated.
The TPS2413 turns the MOSFET on if V
(AC)
is greater than 10 mV, and the rapid turn-off is activated at theprogrammed negative threshold. There is no linear control range and slow turn-off. The disadvantage is that theturn-off threshold must be negative (unless a minimum load is always present) permitting a continuous reversecurrent. Under a dynamic reverse voltage fault, the lower threshold voltage may permit a higher peak reversecurrent. There are a number of advantages to this control method. Step loads from a light load condition arehandled without a voltage droop beyond I × R. If the redundant converter fails, applications with redundantsynchronous converters may permit a small amount of reverse current at light load in order to assure that theMOSFET is all ready on. The TPS2413 is a better solution for low-voltage buses that are not re-regulated, andthat may see large load steps transients.
These applications recommendations are meant as a starting point, with the needs of specific implementationsover-riding them.
The N+1 power supply configuration shown in Figure 12 is used where multiple power supplies are paralleled foreither higher capacity, redundancy or both. If it takes N supplies to power the load, adding an extra, identical unitin parallel permits the load to continue operation in the event that any one of the N supplies fails. The suppliesare ORed together, rather than directly connected to the bus, to isolate the converter output from the bus when itis plugged-in or fails short. The TPS2412/13 with an external MOSFET emulates the function of the ORing diode.
It is possible for a malfunctioning converter in an ORed topology to create a bus overvoltage if the loading is lessthan the converter's capacity (e.g. N = 1). The ORed topology shown cannot protect the bus from this condition,even if the ORing MOSFET can be turned off. One common solution is to use two MOSFETs in a back-to-backconfiguration to provide bidirectional blocking. The TPS2412/13 does not have a provision for forcing the gate offwhen the overvoltage condition occurs, use of the TPS2410/11 is recommended.
ORed supplies are usually designed to share power by various means, although the desired operation couldimplement an active and standby concept. Sharing approaches include both passive, or voltage droop, andactive methods. Not all of the output ORing devices may be ON depending on the sharing control method, busloading, distribution resistances, and TPS2412/13 settings.
Figure 12. N+1 Power Supply Example
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INPUT ORing – TYPICAL CONNECTION
Optional Connection
Plug-In Unit
STAT
STAT
SYSTEM DESIGN AND BEHAVIOR WITH TRANSIENTS
RECOMMENDED OPERATING RANGE
TPS2412
TPS2413
SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008 ..........................................................................................................................................
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Figure 13 shows how redundant buses may be ORed to a common point to achieve higher reliability. It ispossible to have both MOSFETs ON at once if the bus voltages are matched, or the combination of toleranceand regulation causes both TPS2412/13 circuits to see a forward voltage. The ORing MOSFET disconnects thelower-voltage bus, protecting the remaining bus from potential overload by a fault.
Figure 13. Example ORing of Input Power Buses
The power system, perhaps consisting of multiple supplies, interconnections, and loads, is unique for everyproduct. A power distribution has low impedance, and low loss, which yields high Q by its nature. While theaddition of lossy capacitors helps at low frequencies, their benefit at high frequencies is compromised byparasitics. Transient events with rise times in the 10 ns range may be caused by inserting or removing units, loadfluctuations, switched loads, supply fluctuations, power supply ripple, and shorts. These transients cause thedistribution to ring, creating a situation where ORing controllers may trip off unnecessarily. In particular, when anORing device turns off due to a reverse current fault, there is an abrupt interruption of the current, causing a fastringing event. Since this ringing occurs at the same point in the topology as the other ORing controllers, they arethe most likely to be effected.
The ability to operate in the presence of noise and transients is in direct conflict with the goal of precise ORingwith rapid response to actual faults. A fast response reduces peak stress on devices, reduces transients, andpromotes un-interrupted system operation. However, a control with small thresholds and high speed is mostlikely to be falsely tripped by transients that are not the result of a fault. The power distribution system should bedesigned to control the transient voltages seen by fast-responding devices such as ORing and hotswap devices.
While some applications may find it possible to use RSET to avoid false tripping, the TPS2410/11 providesfeatures beyond the TPS2412/13 including fast-comparator input filtering and STAT to dynamically shift theturn-off threshold.
The maximum recommended bus voltage is lower than the absolute maximum voltage ratings on A, C, and V
DDsolely to provide some margin for transients on the bus. Most power systems experience transient voltagesabove the normal operating level. Short transients, or voltage spikes, may be clamped by the ORing MOSFET toan output capacitor and/or voltage rail depending on the system design. Transient protection, e.g. a TVS diode(transient voltage suppressor, a type of Zener diode), may be required on the input or output if the system designdoes not inherently limit transient voltages below the TPS2412/13 absolute maximum ratings. If a TVS isrequired, it must protect to the absolute maximum ratings at the worst case clamping current. The TPS2412/13will operate properly up to the absolute maximum voltage ratings on A, C, and V
DD
.
12 Submit Documentation Feedback Copyright © 2007 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2412 TPS2413
TPS2412 REGULATION-LOOP STABILITY
MOSFET SELECTION AND R
(RSET)
-470.02
R(RSET) V - 0.00314
(OFF)
æ ö
ç ÷
=ç ÷
è ø
(2)
TPS2412
TPS2413
www.ti.com
.......................................................................................................................................... SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008
The TPS2412 uses an internal linear error amplifier to keep the external MOSFET from saturating at light load.This feature has the benefits of setting a turn-off above 0 V, providing a soft turn-off for slowly decaying inputvoltages, and helps droop-sharing redundancy at light load.
Although the control loop has been designed to accommodate a wide range of applications, there are a fewguidelines to be followed to assure stability.•Select a MOSFET C
(ISS)
of 1 nF or greater•Use low ESR bulk capacitors on the output C terminal, typically greater than 100 µF with less than 50 m ΩESR
•Maintain some minimum operational load (e.g. 10 mA or more)
Symptoms of stability issues include V
(AC)
undershoot and possible fast turn-off on large-transient recovery, anda worst-case situation where the gate continually cycles on and off. These conditions are solved by following therules above. Loop stability should not be confused with tripping the fast comparator due to V
(AC)
tripping the gateoff.
Although not common, a condition may arise where the dc/dc converter transient response may cause the GATEto cycle on and off at light load. The converter experiences a load spike when GATE transitions from OFF to ONbecause the ORed bus capacitor voltage charges abruptly by as much as a diode drop. The load spike maycause the supply output to droop and overshoot, which can result in the ORed capacitor peak charging to theovershoot voltage. When the supply output settles to its regulated value, the ORed bus may be higher than thesource, causing the TPS2412/13 to turn the GATE off. While this may not actually cause a problem, itsoccurrence may be mitigated by control of the power supply transient characteristic and increasing its outputcapacitance while increasing the ORed load to capacitance ratio. Adjusting the TPS2412/13 turn-off threshold todesensitize the redundant ORing device may help as well. Careful attention to layout and charge-pump noisearound the TPS2412/13 helps with noise margin.
The linear gate driver has a pull-up current of 290 µA and pull-down current of 3 mA typical.
MOSFET selection criteria include voltage rating, voltage drop, power dissipation, size, and cost. The voltagerating consists of both the ability to withstand the rail voltage with expected transients, and the gate breakdownvoltage. The MOSFET gate rating should be the minimum of 12 V, or the controlled rail voltage. Typically thisrequires a ± 20-V GATE voltage rating.
While r
DS(on)
is often chosen with the power dissipation, voltage drop, size and cost in mind, there are severalother factors to be concerned with in ORing applications. When using the TPS2412, the minimum voltage acrossthe device is 10 mV. A device that would have a lower voltage drop at full-load would be overspecified. Whenusing a TPS2413 or TPS2412 with RSET programmed to a negative voltage, the permitted static reverse currentis equal to the turn-off threshold divided by the r
DS(on)
. While this current may actually be desirable in somesystems, the amount may be controlled by selection of r
DS(on)
and RSET. The practical range of r
DS(on)
for asingle MOSFET runs from the low milliohms to 40 m Ωfor a single MOSFET.
MOSFETs may be paralleled for lower voltage drop (power loss) at high current. For TPS2412 operation, oneshould plan for only one of the MOSFETs to carry current until the 10 mV regulation point is exceeded and theloop forces GATE fully ON. TPS2413 operation does not rely on linear range operation, so the MOSFETs are allON or OFF together except for short transitional times. Beyond the control issues, current sharing depends onthe resistance match including both the r
DS(on)
and the connection resistance.
The TPS2412 may be used without a resistor on RSET. In this case, the turnoff V
(AC)
threshold is about 3 mV.The TPS2413 may only be operated without an RSET programming resistor if the loading provides a higherV
(AC)
. A larger negative turnoff threshold reduces sensitivity to false tripping due to noise on the bus, but permitslarger static reverse current. Installing a resistor from RSET to ground creates a negative shift in the fast turn-offthreshold per Equation 2 .
Copyright © 2007 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS2412 TPS2413
I(TURN_OFF) =- 1 A
V(THRESHOLD)
rDS(on)
-10mV
10mW
I(TURN_OFF) =
I(TURN_OFF) =
(3)
GATE DRIVE, CHARGE PUMP AND C
(BYP)
V
DD
, BYP, and POWERING OPTIONS
VDD
A
C
GND
GATE
Input
Voltage
3.3V-18V
Common
Bus
CommonBusPowering
*OptionalFiltering
10*
VDD
A
C
GND
GATE
Input
Voltage
0.8V-18V
Common
Bus
SeparateBusPowering
*OptionalFiltering
5V
2200pF BYP
2200pF BYP
0.01 Fm
0.01 Fm
10*
TPS2412
TPS2413
SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008 ..........................................................................................................................................
www.ti.com
To obtain a -10 mV fast turnoff ( V
(A)
is less than V
(C)
by 10 mV ), R
(RSET)
= ( – 470.02/ ( – 0.01 – 0.00314) ) ≈35,700 Ω. If a 10 m Ωr
DS(on)
MOSFET was used, the reverse turnoff current would be calculated as follows.
The sign indicates that the current is reverse, or flows from the MOSFET drain to source ( C to A ).
The turn-off speed of a MOSFET is influenced by the effective gate-source and gate-drain capacitance
ISS
).Since these capacitances vary a great deal between different vendor parts and technologies, they should beconsidered when selecting a MOSFET where the fastest turn-off is desired.
Gate drive of 270 µA typical is generated by an internal charge pump and current limiter. A separate supply, V
DD
,is provided to avoid having the large charge pump currents interfere with voltage sensing by the A and C pins.The GATE drive voltage is referenced to V
(A)
as GATE will only be driven high when V
(A)
> V
)
. The recommendedcapacitor on BYP (bypass) must be used in order to form a quiet supply for the internal high-speed comparator.V
(GATE)
must not exceed V
(BYP)
.
The separate V
DD
pin provides flexibility for operational power and controlled rail voltage. While the internalUVLO has been set to 2.5 V, the TPS2412/13 requires at least 3 V to generate the specified GATE drive voltage.Sufficient BYP voltage to run internal circuits occurs at V
DD
voltages between 2.5 V and 3 V. There are threechoices for power, A, C, or a separate supply, two of which are demonstrated in Figure 14 . One choice forvoltage rails over 3.3 V is to power from C, since it is typically the source of reliable power. Voltage rails below3.3 V nominal, e.g. 2.5 V and below, should use a separate supply such as 5 V. A separate V
DD
supply can beused to control voltages above it, for example 5 V powering V
DD
to control a 12-V bus.
V
DD
is the main source of power for the internal control circuits. The charge pump that powers BYP draws mostof its power from V
DD
. The input should be low impedance, making a bypass capacitor a preferred solution. A10- Ωseries resistor may be used to limit inrush current into the bypass capacitor, and to provide noise filteringfor the supply.
BYP is the interconnection point between a charge pump, V
(AC)
monitor amplifiers and comparators, and the gatedriver. C
(BYP)
must be used to filter the charge pump. A 2200 pF is recommended, but the value is not critical.
Figure 14. V
DD
Powering Examples
14 Submit Documentation Feedback Copyright © 2007 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2412 TPS2413
ORing Examples
Input1
Input2 Output
2200pF
VDD
C
GATE
A
GND
BYP
TPS2412
TPS2413
www.ti.com
.......................................................................................................................................... SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008
Applications with the TPS2412/13 are not limited to ORing of identical sections. The TPS2412/13 and externalMOSFET form a general purpose function block. Figure 15 shows a circuit with ORing between a discrete diodeand a TPS2412/MOSFET section. This circuit can be used to combine two different voltages in cases where theoutput is regulated, and the additional voltage drop in the Input 1 path is not a concern. An example is ORing ofan ac adapter on Input 1 with a lower voltage on Input 2.
Figure 15. ORing Circuit
The TPS2412 may be a better choice in applications where inputs may be removed, causing an open-circuitinput. If the MOSFET was ON when the input is removed, V
AC
will be virtually zero. If the reverse turn-offthreshold is programmed negative, the TPS2412/13 will not pull GATE low. A system interruption could then becreated if a short is applied to the floating input. For example, if an ac adapter is first connected to the unit, andthen connected to the ac mains, the adapter's output capacitors will look like a momentary short to the unit. ATPS2412 with RSET open will turn the MOSFET OFF when the input goes open circuit.
Copyright © 2007 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS2412 TPS2413
SUMMARIZED DESIGN PROCEDURE
Layout Considerations
TPS2412
TPS2413
SLVS728B – JANUARY 2007 – REVISED SEPTEMBER 2008 ..........................................................................................................................................
www.ti.com
The following is a summarized design procedure:1. Choose between the TPS2412 or 2413, see TPS2412 vs TPS2413 – MOSFET Control Methods2. Choose the V
DD
source. Table 3 provides a guide for where to connect V
DD
that covers most cases. V
DD
maybe directly connected to the supply, but an R
(VDD)
and C
(VDD)
of 10 Ωand 0.01 µF is recommended.
Table 3. V
DD
Connection Guide
V
A
< 3 V 3 V ≤V
A
≤3.6 V V
A
> 3.6 V
Bias Supply > 3 V V
A
or Bias Supply > 3 V. V
C
if always > 3 V V
C
, V
A
, or Bias for special configurations
3. Noise voltage and impedance at the A pin should be kept low. C
(A)
may be required if there is noise on thebus, or A is not low impedance. If either of these is a concern, a C
(A)
of 0.01 µF or more may be required.4. Select C
(BYP)
as 2200 pF, X7R, 25-V or 50-V ceramic capacitor.5. Select the MOSFET based on considerations of voltage drop, power dissipated, voltage ratings, and gatecapacitance. See sections: MOSFET Selection and RSET and TPS2412 Regulation-Loop Stability.6. Select R
(RSET)
based on which MOSFET was chosen and reverse current considerations – see MOSFETSelection and RSET. If the noise and transient environment is not well known, make provision for R
(RSET)even when using the TPS2412.7. Make sure to connect RSVD to ground
1. The TPS2412/13, MOSFET, and associated components should be used over a ground plane.2. The GND connection should be short, with multiple vias to ground.3. C
(VDD)
should be adjacent to the V
DD
pin with a minimal ground connection length to the plane.4. The GATE connection should be short and wide (e.g., 0.025" minimum).5. The C pin should be Kelvin connected to the MOSFET.6. The A pin should be a short, wide, Kelvin connection to the MOSFET.7. R
(SET)
should be kept immediately adjacent to the TPS2412/13 with short leads.8. C
(BYP)
should be kept immediately adjacent to the TPS2412/13 with short leads.
16 Submit Documentation Feedback Copyright © 2007 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2412 TPS2413
PACKAGE OPTION ADDENDUM
www.ti.com 1-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2412D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2412DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2412DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2412DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2412PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2412PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2412PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2412PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2413D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2413DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2413DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2413DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2413PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2413PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2413PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2413PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 1-Aug-2011
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2412DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2412PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS2413DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2413PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2412DR SOIC D 8 2500 340.5 338.1 20.6
TPS2412PWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS2413DR SOIC D 8 2500 340.5 338.1 20.6
TPS2413PWR TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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