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MT9M032_LDS_2 - Rev. B 11/07 EN 4©2007 Micron Technology, Inc. All rights reserved.
MT9M032: 1/4.5-Inch 1.6Mp CMOS Digital Image Sensor
Signal Descriptions
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Signal Descriptions
Table 3 provides signal descriptions for the MT9M032.
Table 3: Signal Descriptions
Pin
Numbers Name Type Description
26 SCLK Input Serial clock. Pull to VDD_IO with a 1.5kΩ resistor (depending on bus loading).
21 RESET_BAR Input Master reset signal, active LOW.
33 EXTCLK Input Input clock signal 8–49.5 MHz.
5 TRIGGER Input Snapshot trigger. Used to trigger one frame of output in snapshot modes.
23, 25 TEST Input Enables manufacturing test modes. Tie to digital GND for functional
operation.
45 SADDR0 Input Serial address. Pull to VDD_IO or DGND to set serial address.
28 SADDR1 Input Serial address. Pull to VDD_IO or DGND to set serial address.
27 SDATA I/O Serial data. Pull to VDD_IO with a 1.5kΩ resistor (depending on bus loading).
1 STROBE Output Snapshot strobe. Driven HIGH when all pixels are exposing in snapshot
modes.
4D
OUT[0] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
48 DOUT[1] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
46 DOUT[2] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
20 DOUT[3] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
22 DOUT[4] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
24 DOUT[5] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
37 DOUT[6] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
35 DOUT[7] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
34 DOUT[8] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
38 DOUT[9] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
40 DOUT[10] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
41 DOUT[11] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each
pixel, to be captured on the falling edge of PIXCLK.
47 PIXCLK Output Pixel clock. Used to qualify the LINE_VALID (LV), FRAME_VALID (FV), and
DOUT(11:0). These outputs should be captured on the falling edge of this
signal.
3 FRAME_VALID Output Frame valid. Qualified by PIXCLK. Driven HIGH during active pixels and
horizontal blanking of each frame and LOW during vertical blanking.
2 LINE_VALID Output Line valid output. Qualified by PIXCLK. Driven HIGH with active pixels of each
line and LOW during horizontal blanking periods. External pull-down resistor
to DGND (typical 10kΩ–100kΩ) required for proper initialization sequence.
29, 44 VDD Supply Digital power 1.8V nominal.