Copyright © 2012 Cirrus Logic, Inc. FEB 2012
All Rights Reserved DS752PP11
High Definition Audio Decoder DSP Family
with Dual 32-bit Engine Technology
CS4970x4 Data Sheet
Preliminary Product Information This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
FEATURES
Multi-standard 32-bit high-definition audio decoding plus
post-processing
Supports high-definition audio formats including:
— Dolby Digital® Plus
— Dolby® TrueHD
—DTS-HD
® High Resolution Audio
—DTS-HD
Master Audio™
— DTS Express™ 5.1
Supports legacy audio formats and a wide array of post-
processing
— Dolby Digital® EX, Dolby Pro Logic® II, IIx, IIz 7.1, Dolby
Headphone® 2, Dolby Virtual Speaker® 2, Dolby
Volume® (original), Dolby Volume 258 (lite), Audistry®
— DTS-ES 96/24™ Discrete 7.1, DTS-ES™ Discrete 7.1,
DTS-ES™ Matrix 6.1, DTS Neo:6®, DTS Neural
Surround™ DTS Surround Sensation Speaker
— MPEG-2 AAC™ LC 5.1
—SRS
® Circle Surround® II, SRS Circle Surround Auto,
SRS Circle Surround Decoder Optimized, SRS
TruVolume™ 7.1 (V 2.1.0.0), SRS TruSurround
HD/HD4®, SRS WOW HD™, SRS CS Headphone™,
SRS Circle Cinema 3D™, SRS Studio Sound HD™
—THX
® Ultra2™, THX Select2™
Cirrus Logic’s Applications Library
— Cirrus Original Multi-Channel Surrou nd 2 (COMS2),
Cirrus Band XpandeR™, Cirrus Virtualization
Technology (CVT), Cirrus Intelligent Room Calibration 2
(IRC2), Cirrus Bass Enhancement (CBE)
— Crossbar Mixer, Signal Generator
— Advanced Post-Processors including: 7.1 Bass Manager
Quadruple Crossover, Tone Control, 11- Band
Parametric EQ, Delay, 2:1/4:1 Decimator, 1:2/1:4
Upsampler
Up to 12 Channels of 32-bit Serial Audio Input
Customer Software Security Keys
16 Ch x 32-bit PCM Out with Dual 192 kHz S/PDIF Tx
Two SPI™/I2C™ ports
Large On-chip X, Y, and Program RAM & ROM
SDRAM and Serial Flash Memory Support
The CS4970x4 DSP family is an enhanced version of the
CS4953xx DSP family with higher overall performance. In
addition to all the mainstream audio processing codes in on-
chip ROM that the CS4953xx DSP offers, the CS4970x4 device
family also supports the decoding of major high-definition audio
formats. Additionally, the CS4970x4, a dual-core device,
performs the high-definition audio decoding on the first core,
leaving the second core available for audio post-processing and
audio enhancement. The CS4970x4 device supports the most
demanding audio post processing requirements. It provides an
easy upgrade path to systems currently using the CS495xx or
CS4953xx device with minor (or no) hardware and software
changes.
Ordering Information
See page 27 for ordering information.
Coyote 32-bit
DSP A
D
M
A
Coyote 32-bit
DSP B
Ext. Memory Controller
P
S/PDIF
X Y P X Y
Serial
Control 1
16 Ch PCM
Audio Out
Serial
Control 2 Parallel
Control GPIO Debug
STC
TMR1
TMR2
PLL
S/PDIF
12 Ch. Audio In /
6 Ch. SA CD In
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 2
Table of Contents
1 Document ation Strategy ............................................................................................................4
2 Overview .....................................................................................................................................4
2.1 Migrating from CS495xx(2) to CS4970x4 .................................................................................................5
2.2 Licensing ............... ................. ... ................ ... ................ .... ................ ... ................ ... ..................................5
3 Code Overlays ............. ...............................................................................................................5
4 Hardware Functional Description ............................................................................................6
4.1 Coyote DSP Core ............... .... ... ... ... .... ................ ... ................ ... .... ................ ... ........................................6
4.1.1 DSP Memory ...... ... ................. ... ... ... ................ .... ... ................ ... ... .... ................ ... ... ... ..................6
4.1.2 DMA Controller ...... .... ... ... ... .... ... ... ... ... ................. ... ... ... ................ .... ... ... ................ .....................7
4.2 On-chip DSP Peripherals .........................................................................................................................7
4.2.1 Digital Audio Input Port (DAI) .......................................................................................................7
4.2.2 Digital Audio Output Port (DAO) ..................................................................................................7
4.2.3 Serial Cont ro l Port 1 & 2 (I2C or SPI) ..........................................................................................7
4.2.4 Parallel Control Port ........ ... .... ... ... ... ... .... ... ... ... ................. ... ... ... ................ .... ... ...........................7
4.2.5 External Memory Interface .............. ... .... ................ ... ... .... ... ... ... ... .... ................ ... ... ... .... ..............7
4.2.6 General Purpose Input/Output (GPIO) ........................................................................................7
4.2.7 Phase-locked Loop (PLL)-based Clock Generator ......................................................................8
4.3 DSP I/O Description .................................................................................................................................8
4.3.1 Multiplexed Pins ........... ................ ... ... ................. ... ... ... ................ .... ... ... ................ .....................8
4.3.2 Termination Requirements ...........................................................................................................8
4.3.3 Pads ......... .... ... ... ... .... ................ ... ................ ................ .... ................ ................ ...........................8
4.4 Application Code Security ........................................................................................................................8
5 Characteristics and Specifications ..........................................................................................8
5.1 Absolute Maximum Ratings ......................................................................................................................8
5.2 Recommended Operating Conditions ......................................................................................................9
5.3 Digital DC Characteristics ........................................................................................................................9
5.4 Power Supply Characteristics ................................ ... ... .... ... ................ ... ... .... ... ... ................ .....................9
5.5 Thermal Data (144-Pin LQFP) .. ... ... ................ .... ... ... ................ .... ... ................ ... ... .... ............................10
5.6 Thermal Data (128-pin LQFP) ................................................................................................................10
5.7 Switching Char ac te rist ics—RESET ......................................................................................................... 11
5.8 Switching Characteristics — XTI ............................................................................................................ 11
5.9 Switching Characteristics — Internal Clock ............................................................................................12
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode ........ .... ... ... ... .... ... ... ... ... .... ... ... ......12
5.11 Switching Characteristics — Serial Control Port - SPI Master Mode ...................................................13
5.12 Switching Characteristics — Serial Control Port - I2C Slave Mode ......................................................14
5.13 Switching Characteristics — Serial Control Port - I2C Master Mode ....................................................15
5.14 Switching Characteristics — Parallel Control Port - Intel Slave Mode .............. ... ................ .... ... ... ... ...16
5.15 Switching Characteristics — Parallel Control Port - Motorola Slave Mode .........................................18
5.16 Switching Characteristics — Digital Audio Slave Input Port .................................................................20
5.17 Switching Characteristics — Digital Audio Output Port ........................................................................21
5.18 Switching Characteristics — SDRAM Interface ....................................................................................22
6 Ordering Information ...............................................................................................................26
7 Environment al, Manufacturing, a nd Handling Inform ation .................................................26
8 Device Pin-Out Diagram ..........................................................................................................27
8.1 128-Pin LQFP Pin-Out Diagram .............................................................................................................27
8.2 144-Pin LQFP Pin-Out Diagram ............................................................................................................28
9 Package Mechanical Drawings ...............................................................................................29
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 3
9.1 128-Pin LQFP Package Drawing ...........................................................................................................29
9.2 144-Pin LQFP Package Drawing ...........................................................................................................30
10 Revision History .....................................................................................................................31
List of Figures
Figure 1. RESET Timing .........................................................................................................................................11
Figure 2. XTI Timing ..............................................................................................................................................11
Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................13
Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................14
Figure 5. Serial Control Port - I2C Slave Mode Timing ..........................................................................................15
Figure 6. Serial Control Port - I2C Master Mode Timing ..... ... ... ... .... ... ... ... .... ... ... ... ... ................. ... ... ... ... .... ... ... ... ...16
Figure 7. Parallel Control Port - Intel“ Slave Mode Read Cycle .............................................................................17
Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle ..............................................................................17
Figure 9. Parallel Control Port - Motorola“ Slave Mode Read Cycle Timing ....... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ......19
Figure 10. Parallel Control Port - Motorola Slave Mode Write Cyc le Timing .........................................................19
Figure 11. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................20
Figure 12. DAI Slave Timing Diagram ...................................................................................................................20
Figure 13. Digital Audio Port Output Timing Master Mode .....................................................................................21
Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) ........... .... ... ... ... ... .... ... ... ... ...22
Figure 15. External Memory Interface - SDRAM Burst Read Cycle .......................................................................23
Figure 16. External Memory Interface - SDRAM Burst Write Cycle .......................................................................23
Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle .............. ... ................ ... .... ................ ... .........24
Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................25
Figure 19. 128-Pin LQFP Pin-Out Diagram ...........................................................................................................27
Figure 20. 144-Pin LQFP Pin-Out Diagram ...........................................................................................................28
Figure 21. 128-Pin LQFP Package Drawing ..........................................................................................................29
Figure 22. 144-Pin LQFP Package Drawing ..........................................................................................................30
List of Tables
Table 1. CS4970x4 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. CS4970x4 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 5. Environmental, Manufacturing, & Handling In formation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. 144-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 4
1 Documentation Strategy
The CS4970x4 data sheet describes the CS4970x4 family of multichannel audio decoders. This document
should be used in conjunction with the following documents when evaluating or designing a system around the
CS4970x4 family of processors.
The scope of the CS4970x4 data sheet is primarily to provide hardware specifications of the CS4970x4 family
of devices. This includes hardware functionality, characteristic data, pinout, and packaging information.
The intended audience for the CS4970x4 data sheet is the system PCB designer, MCU programmer, and the
quality control engineer.
2 Overview
The CS4970x4 DSP Family, combined with Cirrus Logic’s comprehensive library of audio processing
algorithms, enables the development of next-generation high-definition audio solutions. Cirrus Logic also
provides a broad array of digital interface products and audio converters to meet your audio system-level
design requ ire m en ts.
Note: The CS4970x4 is available in 144-pin and 128-pin LQFP packages. The CS497004-CQZ and
CS497024-CVZ have since been placed on the Not Recommended for New Designs (NRND) list.
The CS497014 is a recomme nded device. These devices are only available in a 128-pin LQFP.
The audio processing features of the CS4970x4 product family are a superset of audio features available in
the CS4953xx prod uct family.
Refer to Table 2 on page 5 for the speed and firmware features of the CS4970x4 product family.
Table 1. CS4970x4 Related Documentation
Document Name Description
CS4970x4 Data Sheet This document
CS495314/CS4970x4 System Designer’s Guide
A new consolidated documentation set that includes:
• Detailed system design information including
Typical Connection Diagrams, Boot-Procedures,
Pin Descriptions, Etc. Also describes use of DSP
Condenser tool.
• Detailed firmware design information including
signal processing flow diagra ms and control API
information
AN288 - CS4953xx/CS4970x4 Firmware User’s Manual Includes detailed firmware design information
including signal processing flow diagrams and control
API information
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 5
2.1 Migrating from CS495xx(2) to CS4970x4
CS4970x4 was designed to provide an easy upgrade path from the CS495xx and CS4953x. Although 144-pin
versions of the two devices are virtually identical with respect to external system connection, there are some
small differences the hardware designer should be aware of:
• The PLL supply voltage on the CS4970x4 is 3.3V vs. 1.8V on the CS495xx.
• The PLL filter topology is simpler when using the CS4970x4 rather than the CS495xx.
• The CS4970x4 adds support for Time-division multiplexing (TDM) mode on both audio input and output
ports.
• The CS4970x4 does not support external static random access memory (SRAM) operation.
• The CS4970x4 external Synchronous dynamic random access memory (SDRAM) bus speed is fixed at
150 MHz vs. the 120 MHz maximum bus speed for the CS495xx. Some firmwar e modules also support a
75 MHz CS4970x4 SDRAM bus speed. Refer to AN304 for details.
• The CS4970x4 CLKOUT pin can output XTALI or XTALI/2. The CS495xx can only output XTALI.
2.2 Licensing
Licenses are required for all of the third party audio decoding/processing algorithms listed below, including the
application notes. Contact your local Cirrus Sales representative for more information.
3 Code Overlays
The suite of software available for the CS4970x4 family consists of operating systems (OS) and a library of
overlays. The overlays have been divided into three main groups: decoders, matrix processors, and
postprocessors. All software components are defined in the following list:
Table 2. Device and Firmware Selection Guide
Device De code Processor
(DSP-A)1Matrix Processor Module
(DSP-A)1
1. Additional processing (MPMA, MPMB, VPM, PPM) post any of the HD audio decoders may be limited. Contact your Cirrus Logic
FAE for the latest concurrency matrix.
Virtualizer Processor
Module
(DSP-B)1
Post Processor
Module
(DSP-B)1
CS497014
300MACS
Stereo PCM
(4:1/2:1 Down-sampling and
1:2/1:4 U-sampling Options)2
Multichannel PCM
(4:1/2:1 Down-sampling and
1:2/1:4 Up-sampling Options)2
Dolby Digital
MPEG-2 AAC LC 5.1
Dolby Digital Plus
Dolby TrueHD3
2. Downsampling and Upsampling functionality is located in the operating system. The Cirrus Decimator (Down-Sampler) is also
available as a separate post-processing module that is described in the application note AN288PPI.
3. The indicated HD audio decoder algorithms require external SDRAM. Consult your Cirrus Logic FAE for the recommended
SDRAM size for your design.
Dolby Pro Logic II / IIx / IIz 7.1
SRS Circle Surround II / Circle
Surround Auto / Circle
Surround Decoder Optimized
(Stereo In)
Cirrus Original Multi-Channel
Surround 2 (Effects / Reverb
Processor)
Crossbar (Down-mix / Up-mix)
(Simultaneous Process)
Cirrus Virtualizer
Technology
Dolby Headphone 2
Dolby Virtual Speaker 2
SRS CS Headphone
SRS TruSurround HD/HD4
APP
(Advanced Post-
processing)
–Tone Control
–Select 2
–PEQ (up to 11 Bands)
–Delay
(Speaker to Listening
Position Alignment
and/or Lip Sync)
–7.1 Bass Manager
–Audio Manager
–4:1/2;1 Down-sampling2
SRS TruVolume 7.1
Multichannel
Dolby Volume
Multichannel
CS497004
300MACS
CS497024
300MACS
Same as CS497014 +
DTS, DTS-ES, DTS96/24
DTS-HD Master Audio3
DTS-HD High Res Audio3
DTS Express 5.1
Same as CS497014 +
DTS Neo:6, DTS Neural Sound
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 6
•OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory,
processing ho st me ss ag e s, c alling aud io- pr ocessing subroutines, auto-detection, error concealment, etc.
•Decoders - Any module th at initially writes dat a into the audio I/O buf fers, e.g. AC-3™, DTS, PCM, etc. All
the decoding/processing algorithms listed require delivery of PCM or IEC61937- packed, compressed dat a
via I2S- or LJ-formatted digital audio to the CS4970x4 from A/D converters, SPDIF Rx, HDMI Rx, etc.
•Matrix-processors - Any module that processes audio I/O buffer PCM data in-place before the Post-
processors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer
through processes like Virtualization (n2 channels) or Matrix Decoding (2n channels). Examples are
Dolby ProLogic IIx and DTS Neo:6.
•Virtualizer-processor - Any module that en codes PCM data into fewer ou tpu t ch an ne ls th an inpu t
channels (n2 chan nels) with the effect of providing “phantom” speakers to represent the physical audio
channels that were eliminated. Exa mples are Dolby Head phone 2 and Dolby V i rtual Speaker 2. Gener ally
speaking, these modules reduce the number of valid channels in the audio I/O buffer.
•Post-processors - Any module that processes audio I/O buffer PCM data in-place after the matrix
processors. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific
effects, Dolby Headphone/Virtual Speaker, etc.
The overlay structure reduces the time required to reconfigure the DSP when a processing change is
requested. Each overlay can be reloaded independently without disturbing the other overlays. For example,
when a new decoder is selected, the OS, matrix-, and post-processors do not need to be reloaded — only the
new decoder (the same is true for the other overlays).
4 Hardware Functional Description
4.1 Coyote DSP Core
The CS4970x4 is a dual-core Coyote DSP with separate X and Y dat a and P code mem ory spaces. Each core
is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply
accumulate (MAC) op erations per clock cycle . Each core has eight 72-bit accumulators, fou r X- and four Y-dat a
registers, and 12 index registers.
Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals
such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core
memory, all without the intervention of the DSP. The DMA engine of floads dat a move in structions from the DSP
core, leaving more MIPS available for signal processing instructions.
CS4970x4 functionality is controlled by application codes that are stored in on-board ROM or downloaded to
the CS4970x4 from a host MCU or external FLASH/EEPROM. Users can choose to use standard audio
decoder and post-processor modules which are available from Cirrus Logic.
The CS4970x4 is suitable for audio decoder, audio post-processor, audio encoder, DVD audio/video player,
and digital broadcast decoder applications.
4.1.1 DSP Memory
Each DSP core ha s its own on-chip data and prog ram RAM and ROM and does not require external memory
for any of today’s popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES
96/24, and THX Ultra2. However, if the end-system design requires support of the new high-definition audio
formats, external SDRAM will be needed to support Dolby TrueHD and DTS-HD master audio.
The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 7
4.1.2 DMA Control le r
The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its
own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external mem ory; and the
peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment
controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable.
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
The 12-channel (6 -line) DAI port sup port s a wide var iety of dat a input format s. The port is cap able of accepting
PCM or IEC61937. Up to 32-bit word lengths are supported. Additionally, support is provided for audio data
input to the DSP via the DAI from an HDMI receiver.
The port has two independent slave-only clock domains. Each data input can be independently assigned to a
clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which
off- loads the t ask of moni toring the SPDIF re ceiver fr om the h ost. A time-st amping feature allows the input dat a
to be sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data
rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or
the ratio of the two clo cks can be set to even multiple s of each other in master mo de. The two port s can also be
ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a
192-kHz SPDIF transmitter (data with embedded clock on a single line).
4.2.3 Serial Control Port 1 & 2 (I2C or SPI)
There are tw o on-chip ser ial control po rts that are capable of operating as master or slave in either I2C or SPI
modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external
clock up to 50 MHz in SPI mode. This high clock speed enables very fast code download, control or data
delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for
audio sub-system control.
4.2.4 Parallel Control Port
The CS4970x4 parallel port supports both Motorola® and Intel® interfaces. It can be used for both control and
data delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin
package.
4.2.5 External Me mo ry Inte rf a ce
The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus.
4.2.6 General Purpose Input/Output (GPIO)
Many of the CS4970x4 periph eral pins ar e multiplexed with GPIO. Each GPIO can be configured as an output,
an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge,
active-low, or active-high.
Table 3. CS4970x4 DSP Memory Sizes
Memory
Type DSP A DSP B
X 16K SRAM, 32K ROM 10K SRAM, 8K ROM
Y 24K SRAM, 32K ROM 16K SRAM, 16K ROM
P 8K SRAM, 32K ROM 8K SRAM, 24K ROM
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 8
4.2.7 Phase-locked Loop (PLL)-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the
DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on
the DAO port for driving audio converters. The CS4970x4 defaults to running from the external reference
frequency and can be switched to use the PLL output after overlays have been loaded and configured, either
through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a
buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.
4.3 DSP I/O Description
4.3.1 Multipl ex ed Pin s
Many of the CS4970x4 pins are multi-functional. For details on pin functionality please refer to the CS4970x4
System Designer’s Guide.
4.3.2 Termination Requirements
Open-drain pins on the CS4970x4 must be pulled high for proper operation. Please refer to the CS4970x4
System Designer’s Guide to identify which pins are open- drain and what value of pull-up resistor is r equired for
proper operation.
Mode select pins on the CS4970x4 are used to select the boot mode upon the rising edge of reset. A detailed
explanation of termination requirements for each communication mode select pin can be found in the
CS4970x4 System Designer’s Guide.
4.3.3 Pads
The CS4970x4 I/O operates from th e 3.3 V supply and is tolerant within 5 V.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may
contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the
device.
5 Characteristics and Specifications
Note: All data sh eet minimum and maximum timing parameters are guaranteed over the rated voltage
and temperature. All data sheet typical parameters are measured under the following conditions:
T=25°C, C
L = 20 pF, VDD = 1.8 V, VDDA = VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
CAUTION: Operation at or beyond these limits may re sult in perman ent damage to th e device. Normal op eration is
not guarant ee d at these extrem es .
Parameter Symbol Min Max Unit
DC power supplies: Core supply
PLL supply
I/O supply
|VDDA – VDDIO|
VDD
VDDA
VDDIO
–0.3
–0.3
–0.3
—
2.0
3.6
3.6
0.3
V
V
V
V
Input pin current, any pin except supplies Iin —+/- 10mA
Input voltage on PLL_REF_RES Vfilt -0.3 3.6 V
Input voltage on I/O pins Vinio -0.3 5.0 V
Storage temperature Tstg -65 150 °C
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 9
5.2 Recommended Operating Conditions
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
5.3 Digital DC Characteristics
(Measurements performed under static conditions.)
5.4 Power Supply Characteristics
(Measurements performed under operating conditions.)
Parameter Symbol Min Typ Max Unit
DC power supplies: Core supply
PLL supply
I/O supply
|VDDA – VDDIO|
VDD
VDDA
VDDIO
1.71
3.13
3.13
1.8
3.3
3.3
0
1.89
3.46
3.46
V
V
V
V
Ambient operating temperature Commercial Grade (CQZ/CVZ) TA0 +25 + 70
°C
Commercial Tj0+125ºC
Parameter Symbol Min Typ Max Unit
High-level input voltage VIH 2.0 — — V
Low-level input voltage, except XTI VIL ——0.8 V
Low-level input voltage, XTI VILXTI ——0.6 V
Input Hysteresis Vhys —0.4— V
High-level output voltage (IO = -4mA), except XTI, SDRAM
pins VOH VDDIO * 0.9 — — V
Low-level output voltage (IO = 4mA), except XTI, SDRAM
pins VOL ——VDDIO * 0.1V
SDRAM High-level output voltage (IO = -8mA) VOH VDDIO * 0.9 — — V
SDRAM Low-level output voltage (IO = 8mA) VOL ——VDDIO * 0.1V
Input leakage current (all digital pins with internal pull-up
resistors disabled) IIN —— 5 μA
Input leakage current (all digital pins with internal pull-up
resistors enabled, and XTI) IIN-PU ——70 μA
Parameter Min Typ Max Unit
Power supply current:
Core and I/O operating: VDD1
PLL operating: VDDA
With external memory and most ports operating: VDDIO
1.Dependent on application firmware and DSP clock speed.
—
—
—
350
3.5
120
—
—
—
mA
mA
mA
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 10
5.5 Thermal Data (144-Pin LQFP)
5.6 Thermal Data (128-pin LQFP)
Notes: 1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and
bottom layers.
2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20% of the top and
bottom layers and 0.5-oz. copper covering 90% of the internal power plane and ground plane layers.
3. To calculate the die temperature for a given power dissipation
Τj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ]
4. To calculate the case temperature for a given power dissipation
Τc = Τj - [ (Power Dissipation in Watts) * ψjt
Parameter Symbol Min Typ Max Unit
Thermal Resistance (Junction to Ambient) Two-layer Board1
Four-layer Board2
θja —
—48
40 —
—
°C / Watt
Thermal Resistance (Junction to Top of Package)
Two-layer Board1
Four-layer Board2
ψjt —
—.39
.33 —
—
°C / Watt
Parameter Symbol Min Typ Max Unit
Thermal Resistance (Junction to Ambient) Two -layer Board1
Four-layer Board2
θja —
—53
44 —
—
°C / Watt
Thermal Resistance (Junction to Top of Package)
Two -layer Board1
Four-layer Board2
ψjt —
—.45
.39 —
—
°C / Watt
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 11
5.7 Switching Characteristics—RESET
Figure 1. RESET Timing
5.8 Switching Characteristics — XTI
Figure 2. XTI Timing
Parameter Symbol Min Max Unit
RESET minimum pulse width low Trstl 1—μs
All bidirectional pins high-Z after RESET low Trst2z — 100 ns
Configuration pins setup before RESET high Trstsu 50 — ns
Configuration pins hold after RESET high Trsthld 20 — ns
Parameter Symbol Min Max Unit
External Crystal operating frequency1
1. Part characterized with the following crystal frequency values: 12.288 and 24.576 MHz.
Fxtal 12.288 24.576 MHz
XTI period Tclki 41 81.4 ns
XTI high time Tclkih 16.4 — ns
XTI low time Tclkil 16.4 — ns
External Crystal Load Capacitance (parallel resonant)2
2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside this range
should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s recommendation for load capacitor
selection.
CL10 18 pF
External Crystal Equivalent Series Resistance ESR — 50 Ω
RESET#
Trst2z
Trstl
Trstsu Trsthld
HS[3:0]
All Bidirectional
Pins
tclkih tclkil
Tclki
XTI
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 12
5.9 Switching Characteristics — Internal Clock
Parameter Symbol Min Max Unit
Internal DCLK frequency1
1. After initial power-on reset, Fdclk = Fxtal. After initial kick-start commands, the PLL is locked to max F dclk and remains locked until
the next power-on reset.
Fdclk — –MHz
CS497004-CQZ
CS497004-CQZR
CS497024-CVZ
CS497024-CVZR
CS497014-CVZ
CS497014-CVZR
CS497024-CVZ
CS497024-CVZR
Fxtal 131
Internal DCLK period1DCLKP — – ns
CS497004-CQZ
CS497004-CQZR
CS497024-CVZ
CS497024-CVZR
CS497014-CVZ
CS497014-CVZR
CS497024-CVZ
CS497024-CVZR
7.63 1/Fxtal
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 13
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode
Figure 3. Serial C ontrol Port - SPI Slave Mode Timing
Parameter Symbol Min Typical Max Units
SCP_CLK frequency1,2
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin
should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3.
2. When SCP1 is in SPI slave mode, very slow rise and fall times of the SCP_CLK edges may make the edges of the SCP_CLK
more susceptible to noise, resulting in non-smooth edges. Any glitch at the threshold levels of the SCP port input signals could
result in abnormal operation of the port. In systems that have noise coupling onto SCP_CLK, slow rise and fall times may cause
host communication problems. Increasing rise time makes host communication more reliable.
fspisck —— 25MHz
SCP_CS falling to SCP_CLK ri sing 2tspicss 24 — — ns
SCP_CLK low time2tspickl 20 — — ns
SCP_CLK high time2tspickh 20 — — ns
Setup time SCP_MOSI input tspidsu 5— —ns
Hold time SCP_MOSI input tspidh 5— —ns
SCP_CLK low to SCP_MISO output valid2tspidov —— 11ns
SCP_CLK falling to SCP_IRQ rising2tspiirqh — — 20 ns
SCP_CS rising to SCP_IRQ falling2 tspiirql 0— —ns
SCP_CLK low to SCP_CS rising2tspicsh 24 — — ns
SCP_CS rising to SCP_MISO output high-Z tspicsdz —20 —ns
SCP_CLK rising to SCP_BSY falling2tspicbsyl —3
*DCLKP+20 — ns
SCP_BSY#
SCP_CS#
SCP_CLK
SCP_MOSI
SCP_MISO
SCP_IRQ#
012670567
t
spicss
t
spickl
t
spickh
t
spidsu
t
spidh
t
spidov
A6 A5 A0 R/W MSB LSB
MSB LSB
t
spicsh
t
spibsyl
t
spiirql
t
spiirqh
f
spisck
t
spicsdz
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 14
5.11 Switching Characteristics — Serial Control Port - SPI Master Mode
.
Figure 4. Serial Control Port - SPI Master Mode Timing
Parameter Symbol Min Typical Max Units
SCP_CLK frequency1, 2
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application.
2. See Section 5.8.
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter.
fspisck —— F
xtal/2 MHz
SCP_CS falling to SCP_CLK ri sing 3tspicss — 11*DCLKP +
(SCP_CLK PERIOD) /2 —ns
SCP_CLK low time tspickl 16.9 — — ns
SCP_CLK high time tspickh 16.9 — — ns
Setup time SCP_MISO input tspidsu 11 — — ns
Hold time SCP_MISO input tspidh 5— —ns
SCP_CLK low to SCP_MOSI output valid tspidov —— 11ns
SCP_CLK low to SCP_CS falling tspicsl 7— —ns
SCP_CLK low to SCP_CS rising tspicsh — 11*DCLKP +
(SCP_CLK PERIOD) /2 —ns
Bus free time between active SCP_CS tspicsx — 3*DCLKP — ns
SCP_CLK falling to SCP_MOSI output high-Z tspidz ——20 ns
EE_CS#
SCP_CLK
SCP_MISO
SCP_MOSI
012670567
tspicss
tspickl
tspickh
tspidsu tspidh tspidov
A6 A5 A0 R/W MSB LSB
MSB LSB
tspicsh
tspicsx
fspisck
tspidz
tspicsl
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 15
5.12 Switching Characteristics — Serial Control Port - I2C Slave Mode
Figure 5. Serial Control Port - I2C Slave Mode Timing
Parameter Symbol Min Typical Max Units
SCP_CLK frequency1
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin
should be implemented to prevent overflow o f the input data buffer.
fiicck —— 400kHz
SCP_CLK low time tiicckl 1.25 — — µs
SCP_CLK high time tiicckh 1.25 — — µs
SCP_SCK rising to SCP_SDA rising or falling for START or
STOP condition tiicckcmd 1.25 — — µs
START condition to SCP_CLK falling tiicstscl 1.25 — — µs
SCP_CLK falling to STOP condition tiicstp 2.5 — — µs
Bus free time between STOP and START conditions tiicbft 3— —µs
Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 — — ns
Hold time SCP_SDA input after SCP_CLK falling2
2. This parameter is measured from the ViL level at the falling edge of the clock.
tiich 0— —ns
SCP_CLK low to SCP_SDA out valid tiicdov —— 18ns
SCP_CLK falling to SCP_IRQ rising tiicirqh ——3
*DCLKP + 40 ns
NAK condition to SCP_IRQ low tiicirql —3
*DCLKP + 20 — ns
SCP_CLK rising to SCB_BSY low tiicbsyl —3
*DCLKP + 20 — ns
SCP_BSY#
SCP_CLK
SCP_SDA
SCP_IRQ#
01 67801 7
tiicckl
tiicckh
tiicsu tiich
A6 A0 R/W ACK LSB
tiicirqh tiicirql
8
ACK
MSB
tiicstp
6
tiiccbsyl
tiicdov tiicbft
tiicstscl
tiicckcmd
fiicck
tiicckcmd
tiicf
tiicr
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 16
5.13 Switching Characteristics — Serial Control Port - I2C Master Mode
Figure 6. Seri al Control Port - I2C Master Mode Timing
5.14 Switching Characteristics — Parallel Control Port - Intel Slave Mode
Parameter Symbol Min Max Units
SCP_CLK frequency1
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application.
fiicck — 400 kHz
SCP_CLK low time tiicckl 1.25 — µs
SCP_CLK high time tiicckh 1.25 — µs
SCP_SCK rising to SCP_SDA rising or falling for START or STOP
condition tiicckcmd 1.25 — µs
START condition to SCP_CLK falling tiicstscl 1.25 — µs
SCP_CLK falling to STOP condition tiicstp 2.5 — µs
Bus free time between STOP and START conditions tiicbft 3—µs
Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 — ns
Hold time SCP_SDA input after SCP_CLK falling2
2. This parameter is measured from the ViL level at the falling edge of the clock.
tiich 0—ns
SCP_CLK low to SCP_SDA out valid tiicdov —36ns
Parameter Symbol Min Typical Max Unit
Address setup before PCP_CS and PCP_RD low or PCP_CS and
PCP_WR low tias 5——ns
Address hold time after PCP_CS and PCP_RD low or PCP_CS and
PCP_WR high tiah 5——ns
Read
SCP_CLK
SCP_SDA
01 67801 7
t
iicckl
t
iicckh
t
iicsu
t
iich
A6 A0 R/W ACK LSB
8
ACK
MSB
t
iicstp
6
t
iicdov
t
iicb
t
iicstscl
t
iicckcmd
f
iicck
t
iicckcmd
t
iicf
t
iicr
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 17
Figure 7. Parallel Control Port - Intel® Slave Mode Read Cycle
Delay between PCP_RD then PCP_CS low or PCP_CS then
PCP_RD low ticdr 0——ns
Data valid after PCP_CS and PCP_RD low tidd ——18ns
PCP_CS and PCP_RD low for read tirpw 24 — — ns
Data hold time after PCP_CS or PCP_RD high tidhr 8——ns
Data high-Z after PCP_CS or PCP_RD high tidis ——18ns
PCP_CS or PCP_RD high to PCP_CS and PCP_RD low for next
read1tird 30 — — ns
PCP_CS or PCP_RD high to PCP_CS and PCP_WR low for next
write1tirdtw 30 — — ns
PCP_RD rising to PCP_IRQ rising tirdirqhl ——12ns
Write
Delay between PCP_WR then PCP_CS low or PCP_CS then
PCP_WR low ticdw 0——ns
Data setup before PCP_CS or PCP_WR high tidsu 8——ns
PCP_CS and PCP_WR low for write tiwpw 24 — — ns
Data hold after PCP_CS or PCP_WR high tidhw 8——ns
PCP_CS or PCP_WR high to PCP_CS and PCP_RD low for next
read1tiwtrd 30 — — ns
PCP_CS or PCP_WR high to PCP_CS and PCP_WR low for next
write1tiwd 30 — — ns
PCP_WR rising to PCP_BSY falling tiwrbsyl — 2*DCLKP + 20 — ns
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware
application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing the input data buffer.
CS4953x4/CS4970x4 System Designer’s Guide should be consulted for the firmware speed limitations.
Parameter Symbol Min Typical Max Unit
PCP_A[3:0]
PCP_D[7:0] tias
ticdr
tiah
tidd
tirpw
tidhr
tidis
tird tirdtw
PCP_CS#
PCP_WR#
PCP_RD#
PCP_IRQ# t
irdirqh
LSP MSP
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 19
5.15 Switching Characteristics — Parallel Control Port - Motorola Slave Mode
Parameter Symbo
lMin Typical MaxUnit
Address setup before PCP_CS and PCP_DS low tmas 5——ns
Address hold time after PCP_CS and PCP_DS low tmah 5——ns
Read
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS low tmcdr 0——ns
Data valid after PCP_CS and PCP_DS low with PCP_R/W high tmdd — — 19 ns
PCP_CS and PCP_DS low for read tmrpw 24 — — ns
Data hold time after PCP_CS or PCP_DS high after read tmdhr 8——ns
Data high-Z after PCP_CS or PCP_DS high after read tmdis — — 18 ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
read1
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware
application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing the input data buffer.
CS4953x4/CS4970x4 System Designer’s Guide should be consulted for the firmware speed limitations.
tmrd 30 — — ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
write1tmrdtw 30 — — ns
PCP_RW rising to PCP_IRQ falling tmrwirqh — — 12 ns
Write
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS low tmcdw 0——ns
Data setup before PCP_CS or PCP_DS high tmdsu 8——ns
PCP_CS and PCP_DS low for write tmwpw 24 — — ns
PCP_R/W setup before PCP_CS AND PCP_DS low tmrwsu 24 — — ns
PCP_R/W hold time after PCP_CS or PCP_DS high tmrwhld 8——ns
Data hold after PCP_CS or PCP_DS high tmdhw 8——ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low with
PCP_R/W high for next read1tmwtrd 30 — — ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
write1tmwd 30 — — ns
PCP_RW rising to PCP_BSY falling tmrwbsyl —2*DCLKP + 20—ns
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 20
Figure 9. Parallel Control Port - Motorola® Slave Mode Read Cycle Timing
Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing
t
mas
t
mcdr
t
mah
t
mdd
t
mrpw
t
mdhr
t
mdis
t
mrd
t
mrdtw
t
mrwsu
t
mrwhld
PCP_A[3:0]
PCP_AD[7:0]
PCP_CS#
PCP_WR#
PCP_DS#
PCP_IRQ# t
mrwirqh
LSP MSP
t
mas
t
mdsu
t
mdhw
t
mwd
t
mwtrd
t
mwpw
t
mcdw
t
mrwsu
t
mrwhld
mah
t
PCP_A[3:0]
PCP_AD[7:0]
PCP_CS#
PCP_WR#
PCP_DS#
PCP_IRQ# t
mrwirql
LSP MSP
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 21
5.16 Switching Characteristics — Digital Audio Slave Input Port
Note: In these diagrams, falling edge is the inactive edge of DAI_SCLK.
Figure 11. Digital Audio Input (DAI) Port Timing Diagram
Figure 12. DAI Slave Timing Diagram
Parameter Symbol Min Max Unit
DAI_SCLK period Tdaiclkp 40 — ns
DAI_SCLK duty cycle —4555%
DAI_LRCLK transition from DAI_SCLK active edge tdaisstlr 10 — ns
DAI_SCLK active edge from DAI_LRCLK transition tdaislrts 10 — ns
Setup time DAI_DATAn tdaidsu 10 — ns
Hold time DAI_DATAn tdaidh 5—ns
DAI_SCLK
DAI_DATAn
tdaidh
tdaidsu
DAI_SCLK
DAI_LRCLK
DAIn_DATAn
tdaislrts
Tdaiclkp
DAI_SCLK
DAI_LRCLK
tdaisstlr
Tdaiclkp
DAIn_DATAn
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 22
5.17 Switching Characteristics — Digital Audio Output Port
Figure 13. Digital Audio Port Output Timing Master Mode
Parameter Symbol Min Max Unit
DAO_MCLK period Tdaomclk 40 —ns
DAO_MCLK duty cycle —45 55 %
DAO_SCLK period for Master or Slave mode1
1. Master mode timing specifications are characterized, not production tested.
Tdaosclk 40 —ns
DAO_SCLK duty cycle for Master or Slave mode1—40 60 %
Master Mode (Output A1 Mode)1,2
2. Master mode is defined as the CS4970x4 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce
DAO_SCLK, DAO_LRCLK.
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input tdaomsck —19 ns
DAO_SCLK delay from DAO_LRCLK transition3tdaomlrts —8ns
DAO_LRCLK delay from DAO_SCLK transition 3
3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the
data is valid.
tdaomstlr —8ns
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition3tdaomdv —10 ns
Slave Mode (Output A0 Mode)4
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
DAO_SCLK active edge to DAO_LRCLK transition tdaosstlr 10 — ns
DAO_LRCLK transition to DAO_SCLK active edge tdaoslrts 10 — ns
DAO_Dx delay from DAO_SCLK inactive edge tdaosdv — 12.5 ns
DAO_MCLK
DAO_SCLK
DAO_LRCLK
DAOn_DATAn
tdaomlclk
tdaomsck
tdaomdv
tdaomlrts
DAO_MCLK
DAO_SCLK
DAO_LRCLK
DAOn_DATAn
tdaomlclk
tdaomsck
tdaomdv
tdaomlrts
Note: In these diagrams, falling edge is the inactive edge of DAO_SCLK.
DS752PP11 23
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
5.18 Switching Characteristics — SDRAM Interface
Refer to Figure 15 through Figure 18.
(SD_CLKOU T = SD_CLKIN)
Parameter Symbol Min Typical Max Unit
SD_CLKIN high time tsdclkh 2.3 ——ns
SD_CLKIN low time tsdclkl 2.3 ——ns
SD_CLKOUT rise/fall time tsdclkrf ——1ns
SD_CLKOUT Frequency ——150 —MHz
SD_CLKOUT duty cycle —45 —55 %
SD_CLKOUT rising edge to signal valid tsdcmdv ——3.8 ns
Signal hold from SD_CLKOUT rising edge tsdcmdh —1.1 —ns
SD_CLKOUT rising edg e to SD_DQMn valid tsddqv —3.8 —ns
SD_DQMn hold from SD_CLKOUT rising edge tsddqh 1.38 ——ns
SD_DATA valid setup to SD_CLKIN rising edge tsddsu 1.3 ——ns
SD_DATA vali d hold to SD_CLKIN rising edge tsddh 2.1 ——ns
SD_CLKOUT rising edge to ADDRn valid tsdav —3.8 —ns
DAO_SCLK
DAO_LRCLK
DAO_Dx
tdaoslrts
tdaosclk
DAO_SCLK
DAO_LRCLK
tdaosstlr tdaosdv
tdaosclk
DAO_Dx
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
DS752PP11 24
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
Figure 15. External Memory Interfac e - SDRAM Burst Read Cycle
Figure 16. External Memory Interface - SDRAM Burst Write Cycle
SD_CLKOUT
SD_CS#
SD_RAS#
SD_CAS#
SD_WE#
SD_DQMn
SD_An
SD_Dn
tsddsu
tsdclkrf
tsdcmdv
tsdav
tsddqv
tsdcmdh
tsddh
tsddqh
CAS=2 LSP0 MSP0 LSP3 MSP3
SD_CLKIN
tsdclkl tsdclkh
00 11
LSP1 MSP1 LSP2 MSP2
SD_CLKOUT
SD_CS#
SD_RAS#
SD_CAS#
SD_WE#
tsdcmdv tsdcmdh
SD_Dn LSP0 MSP0 LSP1 MSP1 LSP2 MSP2 LSP3 MSP3
SD_An
SD_DQMn
tsddqh
00 11
tsddqv
tsdav
DS752PP11 25
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle
SD_CLKOUT
SD_CS#
SD_RAS#
SD_CAS#
SD_WE#
SD_DQMn
SD_An
SD_Dn
tsdcmdv tsdcmdh
tsdcmdv
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 27
6 Ordering Information
The CS4970x4 family part number is described as follows:
CS497NNI-XYZ
where
NN - Product Number Variant
I - ROM ID Number
X - Product Grade
Y - Package Type
Z - Lead (Pb) Free
Note: Please contact the factory for availability of the -D (automotive grade) package.
7 Environmental, Manufacturing, and Handling Information
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
Table 4. Ordering Information
Part No. Status Grade Temp. Range Package
CS497004-CQZ EOL Commercial 0 to +70 °C 144-pin LQFP
CS497004-CQZR1
1. R = Tape and reel
EOL Commercial 0 to +70 °C
CS497014-CVZ Active Commercial 0 to +70 °C 128-pin LQFP
CS47014-CVZR1Active Commercial 0 to +7 0 °C
CS497024-CVZ NRND Commercial 0 to +70 °C 128-pin LQFP
CS497024-CVZR1NRND Commercial 0 to +70 °C
Table 5. Environmental, Manufacturing, & Handling Information
Model Number Peak Reflow Temp MSL Rating* Max Floor Life
CS497004-CQZ 260 °C 3 7 Days
CS497004-CQZR 260 °C 3 7 Days
CS497014-CVZ 260 °C 3 7 Days
CS47014-CVZR 260 °C 3 7 Days
CS497024-CVZ 260 °C 3 7 Days
CS497024-CVZR 260 °C 3 7 Days
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 28
8 Device Pin-Out Diagram
8.1 128-Pin LQFP Pin-Out Diagram
Figure 19. 128-Pin LQFP Pin-Out Diagram
GPIO2
GPIO1
GPIO0, EE_CS#
XTO
VDD7
GND7
VDDIO7
XTI
GNDIO7
GNDA
PLL_REF_RES
VDDA (3.3V)
VDD8
GND8
GPIO13, DAI1_DATA2, TM2, DSD2
GPIO14, DAI1_DATA3, TM3, DSD3
DAI1_DATA0, TM0, DSD0
GPIO12, DAI1_DATA1, TM1, DSD1
GPIO6, PCP_CS#, SCP2_CS#
GPIO38, PCP_WR# / DS#, SCP2_CLK
VDD6
GND6
GPIO10, PCP_A2 / A10, SCP2_MOSI
GPIO8, PCP_IRQ#, SCP2_IRQ#
GPIO37, SCP1_BSY#, PCP_BSY#
VDDIO6
GPIO11, PCP_A3, AS#, SCP2_MISO / SDA
GNDIO6
GPOI9, SCP1_IRQ#
GPIO34, SCP1__MISO / SDA
GPIO33, SCP1_MOSI
GPIO35, SCP1_CLK
VDD5
VDDIO5
GND5
GNDIO5
SD_CAS#
SD_RAS#
SD_A3, EXT_A3
SD_A2, EXT_A2
SD_A1, EXT_A1
SD_A0, EXT_A0
SD_A10, EXT_A10
SD_A11, EXT_A11
VDD4
GND4
SD_CS#
SD_A4, EXT_A4
SD_A5, EXT_A5
SD_A6, EXT_A6
SD_A7, EXT_A7
SD_A8, EXT_A8
SD_CLKEN
SD_A9, EXT_A9
VDDIO4
GNDIO4
SD_CLKOUT
SD_CLKIN
SD_D10, EXT_D10
SD_D11, EXT_D11
SD_D12, EXT_D12
VDD3
GND3
SD_D13, EXT_D13
SD_D14, EXT_D14
SD_D15, EXT_D15
SD_DQM1
SD_D7, EXT_D7
SD_D6, EXT_D6
VDDIO3
GNDIO3
SD_D5, EXT_D5
SD_DQM0
SD_D4, EXT_D4
SD_D3, EXT_D3
SD_D2, EXT_D2
GPIO17, DAO1_DATA3 / XMTA
GPIO15, DAO1_DATA1, HS1
DAO1_DATA0, HS0
DAO1_LRCLK
DAI1_LRCLK, DSD4
DAO_MCLK
GPIO20, DAO2_DATA2
DAI1_SCLK, DSD_CLK
VDD1
GND1
DAO1_SCLK
GPIO16, DAO1_DATA2, HS2
GPIO23,
DAO2_LRCLK RESET#
VDDIO1
GPIO22, DAO2_SCLK
GNDIO1
GPIO18, DAO2_DATA0, HS3
GPIO19, DAO2_DATA1, HS4
VDD2
GND2
GPIO26, DAO2_DATA3 / XMTB
VDDIO2
GNDIO2
SD_WE#
SD_D0, EXT_D0
SD_D1, EXT_D1
SD_D8, EXT_D8
SD_D9, EXT_D9
SD_A12, EXT_A12
SD_BA1, EXT_A14
SD_BA0, EXT_A13
GPIO7, SCP1_CS#, IOWAIT
VDDIO8
GNDIO8
EXT_A15
EXT_A16
EXT_A17
EXT_A18
EXT_A19
EXT_CS1#
EXT_OE#
EXT_WE#
GPIO3, DDAC
TEST
DBDA
DBCK
XTAL_OUT
GPIO43, BDI_CLK, DAI2_SCLK
GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY#
BDI_DATA, DAI2_DATA, DSD5
EXT_CS2#
10
15
20
25
30
5
35
1
125
120
115
110
105
95
90
85
80
75
70
65
100
40
45
50
55
60
CS497xx4
128-Pin LQFP
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 29
8.2 144-Pin LQFP Pin-Out Diagram
Figure 20. 144-Pin LQFP Pin-Out Diagram
GPIO11, PCP_A3, AS#, SCP2_MISO / SDA
SD_A11, EXT_A11
GPIO26
GPIO21, DAO2_DATA3 / XMTB
SD_A12, EXT_A12
GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY#
113
116
119
122
126
129
130
133
136
139
109
110
115
120
125
135
140
144
CS497xx4
144-Pin LQFP
GPIO25, EE_CS#
GPIO24
GPIO31
SD_D7, EXT_D7
SD_D6, EXT_D6
SD_D5, EXT_D5
SD_DQM0
SD_D4, EXT_D4
SD_D3, EXT_D3
SD_D2, EXT_D2
GPIO17, DAO1_DATA3 / XMTA
GPIO15, DAO1_DATA1, HS1
DAO1_DATA0, HS0
DAO1_LRCLK
DAO_MCLK
GPIO20, DAO2_DATA2
VDD1
GND1
DAO1_SCLK
GPIO16, DAO1_DATA2, HS2
GPIO23, DAO2_LRCLK
VDDIO1
GPIO22, DAO2_SCLK
GNDIO1
GPIO18, DAO2_DATA0, HS3
GPIO19, DAO2_DATA1, HS4
VDD2
GND2
VDDIO2
GNDIO2
GPIO28, DDAC
GPIO29, XMTA_IN
TEST
DBDA
DBCK
1
5
9
10
13
18
21
24
27
33
36
15
25
30
35
SD_A3, EXT_A3
SD_A2, EXT_A2
SD_A1, EXT_A1
SD_A0, EXT_A0
VDD4
GND4
SD_A4, EXT_A4
SD_A5, EXT_A5
SD_A6, EXT_A6
SD_A7, EXT_A7
SD_A8, EXT_A8
SD_CLKEN
SD_A9, EXT_A9
VDDIO4
GNDIO4
SD_CLKOUT
SD_CLKIN
SD_D10, EXT_D10
SD_D11, EXT_D11
SD_D12, EXT_D12
VDD3
GND3
SD_D13, EXT_D13
SD_D14, EXT_D14
SD_D15, EXT_D15
SD_DQM1
VDDIO3
GNDIO3
SD_D0, EXT_D0
SD_D1, EXT_D1
SD_D8, EXT_D8
SD_D9, EXT_D9
EXT_CS2#
EXT_WE#
69
66
63
60
57
54
47
44
37
40
45
50
55
65
70
72
GPIO39, PCP_CS#, SCP2_CS#
GPIO38, PCP_WR# / DS#, SCP2_CLK
VDD6
GPIO40, PCP_RD# / RW#
GND6
GPIO10, PCP_A2 / A10, SCP2_MOSI
GPIO41, PCP_IRQ#, SCP2_IRQ#
GPIO37, SCP1_BSY#, PCP_BSY#
VDDIO6
GNDIO6
GPOI36, SCP1_IRQ#
GPIO34, SCP1__MISO / SDA
GPIO33, SCP1_MOSI
GPIO35, SCP1_CLK
VDD5
VDDIO5
GND5
GNDIO5
SD_CAS#
SD_RAS#
SD_A10, EXT_A10
SD_CS#
RESET#
SD_WE#
SD_BA1, EXT_A14
SD_BA0, EXT_A13
GPIO32, SCP1_CS#, IOWAIT
EXT_A15
EXT_A16
EXT_A17
EXT_A18
EXT_A19
EXT_CS1#
EXT_OE#
GPIO30, XMTB_IN
101
98
94
91
86
83
76
73
75
80
85
90
95
100
105
108
GPIO1, PCP_AD1 / D1
GPIO0, PCP_AD0 / D0
XTO
VDD7
GND7
VDDIO7
XTI
GNDIO7
GNDA
NC
PLL_REF_RES
VDDA (3.3V)
VDD8
GND8
GPIO13, DAI1_DATA2, TM2, DSD2
GPIO14, DAI1_DATA3, TM3, DSD3
DAI1_DATA0, TM0, DSD0
GPIO12, DAI1_DATA1, TM1, DSD1
GPIO2, PCP_AD2 / D2
GPIO3, PCP_AD3 / D3
GPIO4, PCP_AD4 / D4
GPIO5, PCP_AD5 / D5
GPIO6, PCP_AD6 / D6
GPIO7, PCP_AD7 / D7
GPIO9, PCP_A1 / A9
DAI1_LRCLK, DSD4
DAI1_SCLK, DSD_CLK
VDDIO8
GNDIO8
GPIO8, PCP_A0 / A8
GPIO27
XTAL_OUT
GPIO43, BDI_CLK, DAI2_SCLK
BDI_DATA, DAI2_DATA, DSD5
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 30
9 Package Mechanical Drawings
9.1 128-Pin LQFP Package Drawing
Figure 21. 128-Pin LQFP Package Drawing
Table 6. 128-Pin LQFP Package Cha racteristics
DIM MILLIMETERS INCHES
MIN NOM MAX MIN NOM MAX
A — — 1.60 — — .063”
A1 0.05 — 0.15 .002” — .006”
b 0.17 0.22 0.27 .007” .009” .011”
D 22.00 BSC .866”
D1 20.00 BSC .787”
E 16.00 BSC .630”
E1 14.00 BSC .551”
e 0.50 BSC .020”
q 0° 3.5 7° 0° 3.5 7°
L 0.45 0.60 0.75 .018” .024” .030”
L1 1.00 REF .039” REF
TOLERANCES OF FORM AND POSITION
ddd 0.08 .003”
D1
D
E1
E
1
e
L
∝
b
A1
A
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 31
9.2 144-Pin LQFP Package Drawing
Figure 22. 144-Pin LQFP Package Drawing
Table 7. 144-Pin LQFP Package Cha racteristics
DIM MILLIMETERS INCHES
MIN NOM MAX MIN NOM MAX
A — — 1.60 — — .063”
A1 0.05 — 0.15 .002” — .006”
b 0.17 0.22 0.27 .007” .009” .011”
D 22.00 BSC .866”
D1 20.00 BSC .787”
E 22.00 BSC .866”
E1 20.00 BSC .787”
e 0.50 BSC .020”
q 0° — 7° 0° — 7°
L 0.45 0.60 0.75 .018” .024” .030”
L1 1.00 REF .039” REF
TOLERANCES OF FORM AND POSITION
ddd 0.08 .003”
D1D
e
L
θ
b
A1
A
L1
Notes:
Controlling dimension is millimeter.
Dimensioning and tolerancing per
ASME Y14.5M-1994.
E1
E
M
B
SEATING PLANE
ddd B
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 32
10 Revision History
Revision Date Changes
A1 February, 2007 Advance Release.
PP1 May, 2007 Removed Advanced Produ ct watermark, corrected logo, and ad ded “Preliminary
Product Information” on first page and modified legal information to reflect
Preliminary Pro du ct status.
PP2 July, 2007 Ad ded notice about status of DTS-HD license on page 1 and 7.
PP3 October, 2007
Updated the Tspidsu, Tspickl, and Tspickh timing parameters for master mode SPI.
This applies to both SPI ports. Removed DTS-HD license notice inserted in version
PP2. The license for the DTS-HD decoder is now in place.
Updated Pin Assignments in 144-Pin LQFP Pin-Out Diagram, removing EE_CS
from Pin 7 and adding EE_CS to Pin 25.
PP4 December, 2007
Updated DAO timing specifications and timing diagrams. Changed product naming
conventions in Table 4 and Table 5. Changed re ferences to CS4970x4 Hardw a re
User’s Manual to CS4970x4 System Desi gner’s Guide. Changed references to
CS4970x4 Firmware User’s Manual to CS4970x4 System Designer’s Guide
PP5 May, 2008 Added 128-Pin LQFP Pin-Out and Package drawings. Changed part numbering in
Section 6 and Section 7 Added device and firmware sele ction guide in Table 2.
PP6 August, 2008
Added typical crystal frequency values in Table Footnote 1 and the Max and Min
values of Fxtal in Section 5.8. Redefined Master mode clock speed for SCP_CLK in
Section 5.11. Redefined DC leakage characterization data in Section 5.3,
correcting units of measurement. Modified Footnote 1 under Section 5.10.
Changed product family numbering from CS497xx to CS4970x4. Corre c ted
product listings in table under Section 5.9 “Switching Characteristics — Internal
Clock” on page 12.
PP7 September, 2008 Removed references to External Parallel Flash / SRAM Interface.
PP8 November, 2009
Updated the feature descriptions on the first page of this data sheet. Removed
references to UART port. Removed references to 11.2896, 18.432, and 27 MH z
frequency clocks in Note 1 in Section 5.8 “Switching Characteristics — XTI” on
page 11 and the Min and Max External Crystal Operating Frequency values in that
same section. Added Section 5.6 “Thermal Data (128-pin LQFP)” on page 10.
Updated Figure 9 and Figure 10. Updated (now removed) section. Updated Figure
15 and Figure 16. In Section 5.3, the parameter, “Input leakage current (all digital
pins with internal pull-up resistors enabled, and XTI)”, Max value changes from 50
mA to 70 mA. In Section 5.13, the parameter SCP_CLK low to SCP_SDA out valid
with symbol “tiicdov” Max value changes from 18 ns to 36 ns. Added CS497014 to
Section 6 “Ordering Information” on page 27 and to Section 7 “Envi r onmental,
Manufacturing, and Handling Information” on page 27. Updated Table 2, “Device
and Firmware Selection Guide,” on page 5.
PP9 November, 2010 Added “Status” column and footnote 1 to Table 4.
PP10 March, 2011
Added Tj conditions to Section 5.2.
Changed 500 ma to 350 ma in Section 5.4.
Updated Section 5.16 “Switchin g Characteris tics — Digit al Audio Slave I nput Port”
on page 21.
Updated Section 5.17 “Switching Characteristic s — Digital Audio Ou tput Port” on
page 22.
PP11 February, 2012 Added max internal DCLK frequency and min internal DCLK period to Section 5.9.
Added notes to Section 5.10. Updated tspickl and tspickh values in Section 5.11.
Updated tdaosdv max value in Section 5.17.
CS4970x4 Data Sheet
32-bit High Definition Audio Decod er DSP Family
DS752PP11 33
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
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Cirrus Logic, Cirrus, Cirrus Logic logo designs, Cirrus Framework, and DSP Condenser are trademarks of Cirrus Logic, Inc. All other brand and product names in this
document may be tradem arks o r service marks of their respective owne rs.
THX is a registered trademark of THX, Ltd. THX Select 2 and THX Ultra 2 are trademarks of THX, Ltd.
Dolby, Dol by Digi tal , Dolby Headphone, Virt ual Sp eaker, Pro Log ic, Aud istry , and Dol by Vol ume are re giste red tr ademarks of Dolb y Labo rator ies, I nc. AA C, AC-3 ,
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imply a right u nder any pate nt, or any o ther industrial or Intellectual P roperty Right of Dolby Labora tories, to use th e Impleme ntation in any finished en d-user or re ady-
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DTS and DTS Neo:6 are registered trademarks of the Digital Theater Systems, Inc. DTS-ES 96/24, DTS-ES, DTS 6.1, DTS 96/24, DTS Neural Surrou nd, and DTS
Express ar e trademarks of Digital Theat er Systems, In c. It is her eby notified that a thir d-party lice nse from DTS is nece ssary to distribute software of DTS in any
finished end-user or ready-to-use final product.
SRS, SRS 3D, SRS CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS
Headphone , SRS H ea dp ho ne 360, SRS HPF, SRS StudioSo un d HD, SRS TruEQ, SRS TruM ed ia , SR S TruS ur ro un d, SRS TruSurround XT, SR S TruSurround HD,
SRS TruSurro un d HD4, S RS T ru Vol ume, SR S VI P+, SRS WOW, SRS WOW XT, S RS WOW HD ar e ei th er tr ad emar ks or r egi st er ed t r ademar k s of SRS Lab s, In c.
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Headphone , SRS H ea dp ho ne 360, SRS HPF, SRS StudioSo un d HD, SRS TruEQ, SRS TruM ed ia , SR S TruS ur ro un d, SRS TruSurround XT, SR S TruSurround HD,
SRS TruSurround HD4, SRS TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD technologies are incorporated under license from SRS Labs, Inc.
SRS, SRS 3D, SRS CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS
Headphone , SRS H ea dp ho ne 360, SRS HPF, SRS StudioSo un d HD, SRS TruEQ, SRS TruM ed ia , SR S TruS ur ro un d, SRS TruSurround XT, SR S TruSurround HD,
SRS TruSurro und HD4 , SRS TruV ol u me, SRS V I P+, SRS WOW, SRS WOW XT , SRS WOW HD t e chnol og i es i nco rp or at ed in t he Cirr us Log ic CS4 953xx products
are owned b y SRS L ab s, a U.S. Corpor ation and l ice nse d to Ci rr u s Lo gi c, In c . P ur cha ser of Cir r us Log ic CS49 53xx prod uc ts mus t s i gn a l i cen s e f or use of t h e ch ip
and display of the SRS Labs trademarks. Any products incorporating the Cirrus Logic CS4953xx products must be sent to SRS Labs for review. SRS, SRS 3D, SRS
CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS Headphone, SRS Headphone
360, SRS HPF, SRS Studio-Sou nd HD, SRS TruEQ, SRS TruMedia, SRS T ruSurround, SRS TruSurround XT, SRS TruSurround HD, SRS TruSur round HD4, SRS
TruVolu me, SRS VIP+, SRS WOW, SRS WOW XT, SR S WOW HD technologies ar e protected un der US and foreign patents issue d and/or pending. Neither the
purchase of the Cirrus Logic CS4953xx products, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings
made with any SRS technology/solution. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual.
Motorola is a registered trademark of Motorola, Inc. SPI is a trademark of Motorola, Inc.
Intel is a registered trademark of Intel Corporation .
I
2
C is a trademark of Philips Semiconductor.
