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June, 2011 − Rev. 8

1Publication Order Number:

MC14503B/D

MC14503B

Hex Non-Inverting 3-State

Buffer

The MC14503B is a hex non−inverting buffer with 3−state outputs,

and a high current source and sink capability. The 3−state outputs

make it useful in common bussing applications. Two disable controls

are provided. A high level on the Disable A input causes the outputs of

buffers 1 through 4 to go into a high impedance state and a high level

on the Disable B input causes the outputs of buffers 5 and 6 to go into a

high impedance state.

Features

•3−State Outputs

•TTL Compatible — Will Drive One TTL Load Over Full

Temperature Range

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Two Disable Controls for Added Versatility

•Pin for Pin Replacement for MM80C97 and 340097

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1)

Parameter Symbol Value Unit

DC Supply Voltage Range VDD −0.5 to +18.0 V

Input or Output Voltage Range

(DC or Transient)

Vin, Vout −0.5 to VDD

+ 0.5

V

Input Current (DC or Transient) per Pin Iin ±10 mA

Output Current (DC or Transient) per Pin Iout ±25 mA

Power Dissipation, per Package (Note 2) PD500 mW

Ambient Temperature Range TA−55 to +125 °C

Storage Temperature Range −65 to +150 °C

Lead Temperature (8−Second Soldering) 260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Maximum Ratings are those values beyond which damage to the device may

occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G = Pb−Free Package

MARKING

DIAGRAMS

PDIP−16

P SUFFIX

CASE 648

SOIC−16

D SUFFIX

CASE 751B 1

16

14503BG

AWLYWW

SOEIAJ−16

F SUFFIX

CASE 966

1

16

MC14503B

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

16

1

MC14503BCP

AWLYYWWG

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1

MC14503B

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2

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

IN 5

OUT 6

IN 6

VDD

OUT 4

IN 4

OUT 5

IN 2

OUT 1

IN 1

DIS A

VSS

OUT 3

IN 3

OUT 2

DIS B

LOGIC DIAGRAM

TRUTH TABLE

Appropriate

Disable

InnInput Outn

00 0

10 1

X 1 High

Impedance

X = Don’t Care

DISABLE B

OUT 5

15

12

14

2

4

6

10

1

IN 5

IN 6

IN 1

IN 2

IN 3

IN 4

DISABLE A

OUT 6

OUT 1

OUT 2

OUT 3

OUT 4

11

13

3

5

7

9

VDD = PIN 16

VSS = PIN 8

CIRCUIT DIAGRAM

*INn

*DISABLE

*INPUT

TO OTHER BUFFERS

VSS

VDD

OUTn

*Diode protection on all inputs (not shown)

ONE OF TWO/FOUR BUFFERS

ORDERING INFORMATION

Device Package Shipping†

MC14503BCPG PDIP−16

(Pb−Free) 500 / Rail

MC14503BDG SOIC−16

(Pb−Free) 48 / Rail

MC14503BDR2G SOIC−16

(Pb−Free) 2500 / Tape & Reel

MC14503BFELG

SOEIAJ−16

(Pb−Free) 2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC14503B

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎÎ

− 55_C

ÎÎÎÎÎÎÎÎ

25_C

ÎÎÎÎÎÎ

125_C

ÎÎ

Unit

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 3)

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = 0

“1” Level

Vin = VDD

ÎÎÎ

VOL

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎÎ

0

ÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎÎ

0.05

ÎÎ

Vdc

ÎÎÎ

VOH

ÎÎÎ

5.0

10

15

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

−

ÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 3.6 or 1.4 Vdc)

(VO = 7.2 or 2.8 Vdc)

(VO = 11.5 or 3.5 Vdc)

“1” Level

(VO = 1.4 or 3.6 Vdc)

(VO = 2.8 or 7.2 Vdc)

(VO = 3.5 or 11.5 Vdc)

ÎÎÎ

VIL

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎÎ

2.25

4.50

6.75

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎÎ

1.5

3.0

4.0

ÎÎ

Vdc

ÎÎÎ

VIH

ÎÎÎ

5.0

10

15

ÎÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎÎ

2.75

5.50

8.25

ÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎÎ

−

ÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 2.5 Vdc)

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc)

Sink

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎ

IOH

ÎÎÎ

4.5

5.0

10

15

ÎÎÎÎ

– 4.3

– 5.8

– 1.2

– 3.1

– 8.2

ÎÎÎ

−

ÎÎÎ

– 3.6

– 4.8

– 1.02

– 2.6

– 6.8

ÎÎÎÎ

– 5.0

– 6.1

– 1.4

– 3.7

– 14.1

ÎÎÎ

−

ÎÎÎ

– 2.5

– 3.0

– 0.7

– 1.8

– 4.8

ÎÎÎÎ

−

ÎÎ

mAdc

ÎÎÎ

IOL

ÎÎÎ

4.5

5.0

10

15

ÎÎÎÎ

2.2

2.6

6.5

19.2

ÎÎÎ

−

ÎÎÎ

1.8

2.1

5.5

16.1

ÎÎÎÎ

2.1

2.3

6.2

25

ÎÎÎ

−

ÎÎÎ

1.2

1.3

3.8

11.2

ÎÎÎÎ

−

ÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎÎ

−

ÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎÎ

±0.00001

ÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎÎ

± 1.0

ÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Capacitance, (Vin = 0)

ÎÎÎ

Cin

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

5.0

ÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎÎ

Quiescent Current, (Per Package)

ÎÎÎ

IQ

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

1.0

2.0

4.0

ÎÎÎ

−

ÎÎÎÎ

0.002

0.004

0.006

ÎÎÎ

1.0

2.0

4.0

ÎÎÎ

−

ÎÎÎÎ

30

60

120

ÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (Note 4, 5)

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs)

(All outputs switching,

50% Duty Cycle)

ÎÎÎ

IT

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (2.5 mA/kHz) f + IDD

IT = (6.0 mA/kHz) f + IDD

IT = (10 mA/kHz) f + IDD

ÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

3−State Output Leakage Current

ÎÎÎ

ITL

ÎÎÎ

15

ÎÎÎÎ

−

ÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎÎ

± 0.0001

ÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎÎ

± 3.0

ÎÎ

mAdc

3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

4. The formulas given are for the typical characteristics only at 25_C.

5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,

V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006.

MC14503B

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4

SWITCHING CHARACTERISTICS (Note 6) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎ

VDD

VCC

ÎÎÎÎÎÎ

All Types

ÎÎÎ

Unit

ÎÎÎÎ

Typ

(Note 7)

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise Time

tTLH = (0.5 ns/pF) CL + 20 ns

tTLH = (0.3 ns/pF) CL + 8.0 ns

tTLH = (0.2 ns/pF) CL + 8.0 ns

ÎÎÎÎÎ

tTLH

ÎÎÎ

5.0

10

15

ÎÎÎÎ

45

23

18

ÎÎÎ

90

45

35

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Fall Time

tTHL = (0.5 ns/pF) CL + 20 ns

tTHL = (0.3 ns/pF) CL + 8.0 ns

tTHL = (0.2 ns/pF) CL + 8.0 ns

ÎÎÎÎÎ

tTHL

ÎÎÎ

5.0

10

15

ÎÎÎÎ

45

23

18

ÎÎÎ

90

45

35

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Turn−Off Delay Time, all Outputs

tPLH = (0.3 ns/pF) CL + 60 ns

tPLH = (0.15 ns/pF) CL + 27 ns

tPLH = (0.1 ns/pF) CL + 20 ns

ÎÎÎÎÎ

tPLH

ÎÎÎ

5.0

10

15

ÎÎÎÎ

75

35

25

ÎÎÎ

150

70

50

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Turn−On Delay Time, all Outputs

tPHL = (0.3 ns/pF) CL + 60 ns

tPHL = (0.15 ns/pF) CL + 27 ns

tPHL = (0.1 ns/pF) CL + 20 ns

ÎÎÎÎÎ

tPHL

ÎÎÎ

5.0

10

15

ÎÎÎÎ

75

35

25

ÎÎÎ

150

70

50

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

3−State Propagation Delay Time

Output “1” to High Impedance

ÎÎÎÎÎ

tPHZ

ÎÎÎ

5.0

10

15

ÎÎÎÎ

75

40

35

ÎÎÎ

150

80

70

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output “0” to High Impedance

ÎÎÎÎÎ

tPLZ

ÎÎÎ

5.0

10

15

ÎÎÎÎ

80

40

35

ÎÎÎ

160

80

70

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

High Impedance to “1” Level

ÎÎÎÎÎ

tPZH

ÎÎÎ

5.0

10

15

ÎÎÎÎ

65

25

20

ÎÎÎ

130

50

40

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

High Impedance to “0” Level

ÎÎÎÎÎ

tPZL

ÎÎÎ

5.0

10

15

ÎÎÎÎ

100

35

25

ÎÎÎ

200

70

50

ÎÎÎ

ns

6. The formulas given are for the typical characteristics only at 25_C.

7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Switching Time Test Circuit and Waveforms

(tTLH, tTHL, tPHL, and tPLH)

PULSE

GENERATOR

DISABLE

INPUT

VDD

16

VSS CL

OUTPUT

20 ns 20 ns

VDD

VSS

VOH

VOL

tPHL

tTHL

tTLH

tPLH

90% 50% 10%

OUTPUT

INPUT

tPLH tPHL

90% 50% 10%

MC14503B

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5

Figure 2. 3−State AC Test Circuit and Waveforms

(tPLZ, tPHZ, tPZH, tPZL)

PULSE

GENERATOR

DISABLE INPUT

16

VSS

1 k

OUTPUT

20 ns 20 ns

VDD

50% 90%

VDD

1k

8

INPUT

tPHZ, tPZH CIRCUIT

PULSE

GENERATOR

DISABLE INPUT

tPLZ, tPZL CIRCUIT

OUTPUT

VSS

8

16

INPUT

CLCL

VDD

VSS

VOH

VOL

≈ VOL + 0.05 V

≈ VOH - 0.15 V

10%

90%

10%

90%

10%

tPLZ

tPHZ tPZH

tPZL

OUTPUT FOR tPZH, tPZL CIRCUIT

OUTPUT FOR tPHZ, tPLZ CIRCUIT

DISABLE INPUT

MC14503B

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PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

B

FC

S

H

GD

J

L

M

16 PL

SEATING

18

916

K

PLANE

−T−

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

PDIP−16

CASE 648−08

ISSUE T

SOEIAJ−16

CASE 966−01

ISSUE A

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 0.78 --- 0.031

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005) 0.10 (0.004)

1

16 9

8

D

Z

E

A

b

c

D

E

e

L

M

Z

MC14503B

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7

PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

16

89

8X

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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USA/Canada

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Phone: 81−3−5773−3850

MC14503B/D

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