UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance of
−55°C to 125°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product Change Notification
DQualification Pedigree†
DOptimized for Off-line and DC-to-DC
Converters
DLow Start Up Current (<0.5 mA)
DTrimmed Oscillator Discharge Current
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
DAutomatic Feed Forward Compensation
DPulse-by-Pulse Current Limiting
DEnhanced Load Response Characteristics
DUnder-Voltage Lockout With Hysteresis
DDouble Pulse Suppression
DHigh Current Totem Pole Output
DInternally Trimmed Bandgap Reference
D500 kHz Operation
DLow RO Error Amp
description
The UC1842A/3A/4A/5A family of control ICs is a pin-for-pin compatible improved version of the UC3842/3/4/5
family. Providing the necessary features to control current mode switched mode power supplies, this family has
the following improved features. Start up current is guaranteed to be less than 0.5 mA. Oscillator discharge is
trimmed to 8.3 mA. During under voltage lockout, the output stage can sink at least 10 mA at less than 1.2 V
for VCC over 5 V.
The difference between members of this family are shown in the table below.
PART NUMBER UVLO ON UVLO OFF MAXIMUM DUTY CYCLE
UC1842A 16 V 10 V <100%
UC1843A 8.5 V 7.9 V <100%
UC1844A 16 V 10 V <50%
UC1845A 8.5 V 7.9 V <50%
ORDERING INFORMATION‡
TAPACKAGE‡ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−55°C to 125°CSOP − D Tape and reel UC1842AMDREP 1842AME
−55°C to 125°CSOP − D Tape and reel UC1843AMDREP 1843AME
−55°C to 125°CSOP − D Tape and reel UC1844AMDREP 1844AME
−55°C to 125°CSOP − D Tape and reel UC1845AMDREP 1845AME
‡Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright © 2006, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
COMP
VFB
ISENSE
RT/CT
VREF
VCC
OUTPUT
GND
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
block diagram
NOTES: 1. Toggle flip flop used only in 1844A and 1845A.
Ordering Information
UC 4M
PACKAGE
D = Plastic SOIC
PRODUCT OPTION
2 through 5
MILITARY TEMPERATURE RANGE INDICATOR
D
TAPE and REEL INDICATOR
R
184 EP
ENHANCED PLASTIC INDICATOR
A
IMPROVED PERFORMANCE INDICATOR
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†‡
VCC voltage (low impedance source) 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC voltage (ICC mA) self limiting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ±1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output energy (capacitive load) 5 μJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Inputs (pins 2, 3) −0.3 V to 6.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Amp Output Sink current 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation at TA < 25_C 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals.
NOTE 1: Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction
of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
electrical characteristics, TA = −55_C to 125_C for the UC184xAM-EP, VCC = 15 V (see Note 1),
RT = 10 kΩ, CT = 3.3 nF, and TA = TJ (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Reference Section
Output voltage TJ = 25_C, IO = 1 mA 4.95 5 5.05 V
Line regulation voltage VIN = 12 V to 25 V 6 20 mV
Load regulation voltage IO = 1 mA to 20 mA 6 25 mV
Temperature stability See Notes NO TAG and NO TAG 0.2 0.4 mV/_C
Total output variation voltage Line, Load, Temp. 4.9 5.1 V
Output noise voltage f = 10 Hz to 10 kHz,
See Note NO TAG TJ = 25_C50 μV
Long term stability 1000 hours, See Note 2 TA = 125_C5 25 mV
Output short-circuit current −30 −100 −180 mA
Oscillator Section
Initial accuracy See Note NO TAG TJ = 25_C47 52 57 kHz
Voltage stability VCC = 12 V to 25 V 0.2% 1%
Temperature stability TA = MIN to MAX, See Note 2 5%
Amplitude peak-to-peak V pin 4, See Note 2 1.7 V
Discharge current
V pin 4 2 V See Note 3
TJ = 25_C7.8 8.3 8.8
mA
Discharge current V pin 4 = 2 V, See Note 3 TJ = Full range 7.5 8.8 mA
NOTES: 1. Adjust VCC above the start threshold before setting at 15 V.
2. Not production tested.
3. This parameter is measured with RT = 10 kΩ to VREF
. This contributes approximately 300 μA of current to the measurement. The
total current flowing into the RT/C pin will be approximately 300 μA higher than the measured value.
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, TA = −55_C to 125_C for the UC184xAM-EP, VCC = 15 V (see Note 1),
RT = 10 kΩ, CT = 3.3 nF, and TA = TJ (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Error Amplifier Section
Input voltage COMP = 2.5 V 2.45 2.5 2.55 V
Input bias current −0.3 −1μA
Open loop voltage gain (AVOL) VO = 2 V to 4 V 65 90 dB
Unity gain bandwidth See Note 2 TJ = 25_C0.7 1 MHz
PSRR VCC = 12 V to 25 V 60 70 dB
Output sink current FB = 2.7 V, COMP = 1.1 V 2 6 mA
Output source current FB = 2.3 V, COMP = 5 V −0.5 −0.8 mA
VOUT high FB = 2.3 V, RL = 15 kΩ to GND 5 6 V
VOUT low FB = 2.7 V, RL = 15 kΩ to VREF 0.7 1.1 V
Current Sense Section
Gain See Note 3 and Note 4 2.85 3 3.15 V/V
Maximum input signal COMP = 5 V, See Note 3 0.9 1 1.1 V
PSRR VCC = 12 V to 25 V, See Note 3 70 dB
Input bias current −2−10 μA
Delay to output ISENSE = 0 V to 2 V, See Note 2 150 300 ns
Output Section (OUT)
Low level output voltage
IOUT = 20 mA 0.1 0.4
V
Low-level output voltage IOUT = 200 mA 15 2.2 V
High level output voltage
IOUT = −20 mA 13 13.5
V
High-level output voltage IOUT = −200 mA 12 13.5 V
Rise time CL = 1 nF, See Note 2 TJ = 25_C50 150 ns
Fall time CL = 1 nF, See Note 2 TJ = 25_C50 150 ns
UVLO saturation VCC = 5 V, IOUT = 10 mA 0.7 1.2 V
Undervoltage Lockout Section
Start threshold
UC1842A,
UC1844A 15 16 17
V
Start threshold UC1843A,
UC1845A 7.8 8.4 9
V
Minimum operation voltage after turn on
UC1842A,
UC1844A 9 10 11
V
Minimum operation voltage after turn on UC1843A,
UC1845A 7 7.6 8.2
V
NOTES: 1. Adjust VCC above the start threshold before setting at 15 V.
2. Not production tested.
3. Parameter measured at trip point of latch with VFB at 0 V.
4. Gain is defined by: A = DVCOMP
DVSENSE
; 0 v VSENSE v 0.8 V.
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, TA = −55_C to 125_C for the UC184xAM-EP, VCC = 15 V (see Note 1),
RT = 10 kΩ, CT = 3.3 nF, and TA = TJ (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
PWM Section
Maximum duty cycle
UC1842A, UC1843A 94% 96% 100%
Maximum duty cycle UC1844A, UC1845A 47% 48% 50%
Minimum duty cycle 0%
Total Standby Current
Start-up current 0.3 0.5 mA
Operating supply current FB = 0 V, SENSE = 0 V 11 17 mA
VCC internal zener voltage ICC = 25 mA 30 34 V
NOTES: 1. Adjust VCC above the start threshold before setting at 15 V.
PARAMETER MEASUREMENT INFORMATION
Error Amp can source and sink up to 0.5 mA and sink up to 2 mA.
Figure 1. Error Amp Configuration
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
During UVLO, the Output is low.
Figure 2. Under Voltage Lockout
Peak Current (Is) is determined by the following formula:
IsmaxȀ1V
RS
A small RC filter may be required to suppress switch transients.
Figure 3. Current Sense Circuit
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 4
Output Saturation Characteristics
Figure 5
Error Amplifier Open-Loop Frequency Response
APPLICATION INFORMATION
Oscillator Frequency vs Timing Resistance Maximum Duty Cycle vs Timing Resistor
Figure 6. Oscillator
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be
connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an
adjustable ramp to pin 3.
Figure 7. Open-Loop Laboratory Text Fixture
A fraction of the oscillator ramp can be resistively summed
with the current sense signal to provide slope compensation
for converters requiring duty cycles over 50%.
Note that capacitor, C, forms a filter with R2 to suppress the
leading edge switch spikes.
Figure 8. Slope Compression
UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP
CURRENT-MODE PWM CONTROLLER
SGLS134D − SEPTEMBER 2002 − REVISED JANUARY 2013
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Power Supply Specifications
1. Input Voltage 95VAC to 130VAC (50 Hz/60 Hz)
2. Line Isolation 3750 V
3. Switching Frequency 40 kHz
4. Efficiency, Full Load 70%
5. Output Voltage:
A. +5V, ±5%; 1A to 4A Load
B. +12V, ±3%; 0.1A to 0.3A Load Ripple voltage: 100 mV P-P Max
C. −12V, ±3%; 0.1A to 0.3A Load Ripple voltage: 100 mV P-P Max
Figure 9. Off-Line Flyback Regulator
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UC1842AMDREP ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1842AME
UC1843AMDREP ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1843AME
UC1844AMDREP ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1844AME
UC1845AMDREP ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1845AE
UC1845AMDREPG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1845AE
V62/03625-01YE ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1842AME
V62/03625-02YE ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1843AME
V62/03625-03YE ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1844AME
V62/03625-04YE ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 1845AE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP :
•Catalog: UC1842A, UC1843A, UC1844A, UC1845A
•Space: UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UC1842AMDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 4.0 12.0 Q1
UC1843AMDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 4.0 12.0 Q1
UC1844AMDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 4.0 12.0 Q1
UC1845AMDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 4.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Sep-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC1842AMDREP SOIC D 8 2500 367.0 367.0 35.0
UC1843AMDREP SOIC D 8 2500 367.0 367.0 35.0
UC1844AMDREP SOIC D 8 2500 367.0 367.0 35.0
UC1845AMDREP SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Sep-2017
Pack Materials-Page 2
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