Mixed Signal ISP Flash MCU Family
C8051F55x/56x/57x
Rev. 1.2 9/14 Copyright © 2014 by Silicon Laboratories C8051F55x, C8051F56x, C8051F57x
Analog Peripherals
-12-Bit ADC
•Up to 200 ksps
•Up to 32 external single-ended inputs
•VREF from on-chip VREF, external pin or VDD
•Internal or external start of conversion source
•Built-in temperature sensor
-Two Comparators
•Programmable hysteresis and response time
•Configurable as interrupt or reset source
•Low current
On-Chip Debug
-On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
-Provides breakpoints, single stepping,
inspect/modify memory and registers
-Superior performance to emulation systems using
ICE-chips, target pods, and sockets
-Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
-Typical operating current: 19 mA at 50 MHz
-Typical stop mode current: 1 µA
High-Speed 8051 µC Core
-Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-Up to 50 MIPS throughput with 50 MHz clock
-Expanded interrupt handler
Memory
-2304 bytes internal data RAM (256 + 2048 XRAM)
-32 or 16 kB Flash; In-system programmable in
512-byte Sectors
Digital Peripherals
-33, 25, or 18 Port I/O; All 5 V tolerant
-CAN 2.0 Controller—no crystal required
-LIN 2.1 Controller (Master and Slave capable); no
crystal required
-Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
-Four general purpose 16-bit counter/timers
-16-bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM
functionality
Clock Sources
-Internal 24 MHz with ±0.5% accuracy for CAN and
master LIN operation
-External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
-Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
-40-pin QFN (C8051F568-9 and ‘F570-5)
-32-pin QFP/QFN (C8051 F560-7)
-24-pin QFN (C8051F550-7)
Automotive Qualified
-Temperature Range: –40 to +125 °C
-Compliant to AEC-Q100
ANALOG
PERIPHERALS
32 kB
ISP FLASH 2 kB XRAM
POR
DEBUG
CIRCUITRY
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DIGITAL I/O
24 MHz PRECISION
INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
WDT
2x Clock Multiplier
UART 0
SMBus
SPI
PCA
Timers 0-3
CAN
Crossbar
LIN
Ports 0-4
External
Memory
Interface
A
M
U
X
12-bit
200 ksps
ADC
TEMP
SENSOR
Voltage
Comparator s 0-1 VREG
VREF
C8051F55x/56x/57x
2 Rev. 1.2
C8051F55x/56x/57x
Rev. 1.2 3
Table of Contents
1. System Overview..................................................................................................... 16
2. Ordering Information............................................................................................... 20
3. Pin Definitions.......................................................................................................... 22
4. Package Specifications........................................................................................... 28
4.1. QFN-40 Package Specifications........................................................................ 28
4.2. QFP-32 Package Specifications........................................................................ 30
4.3. QFN-32 Package Specifications........................................................................ 32
4.4. QFN-24 Package Specifications........................................................................ 34
5. Electrical Characteristics........................................................................................ 36
5.1. Absolute Maximum Specifications..................................................................... 36
5.2. Electrical Characteristics................................................................................... 37
6. 12-Bit ADC (ADC0)................................................................................................... 47
6.1. Modes of Operation........................................................................................... 48
6.1.1. Starting a Conversion................................................................................ 48
6.1.2. Tracking Modes......................................................................................... 48
6.1.3. Timing ....................................................................................................... 49
6.1.4. Burst Mode................................................................................................ 50
6.2. Output Code Formatting.................................................................................... 52
6.2.1. Settling Time Requirements...................................................................... 52
6.3. Selectable Gain................................................................................................. 53
6.3.1. Calculating the Gain Value........................................................................ 53
6.3.2. Setting the Gain Value.............................................................................. 55
6.4. Programmable Window Detector....................................................................... 61
6.4.1. Window Detector In Single-Ended Mode.................................................. 63
6.5. ADC0 Analog Multiplexer .................................................................................. 65
6.6. Temperature Sensor.......................................................................................... 67
7. Voltage Reference.................................................................................................... 68
8. Comparators............................................................................................................. 70
8.1. Comparator Multiplexer..................................................................................... 76
9. Voltage Regulator (REG0)....................................................................................... 79
10. CIP-51 Microcontroller........................................................................................... 81
10.1. Performance.................................................................................................... 81
10.2. Instruction Set.................................................................................................. 83
10.2.1. Instruction and CPU Timing.................................................................... 83
10.3. CIP-51 Register Descriptions.......................................................................... 87
10.4. Serial Number Special Function Registers (SFRs) ......................................... 91
11. Memory Organization............................................................................................ 92
11.1. Program Memory............................................................................................. 92
11.1.1. MOVX Instruction and Program Memory................................................ 93
11.2. Data Memory................................................................................................... 93
11.2.1. Internal RAM........................................................................................... 93
12. Special Function Registers................................................................................... 95
12.1. SFR Paging..................................................................................................... 95
C8051F55x/56x/57x
4 Rev. 1.2
12.2. Interrupts and SFR Paging.............................................................................. 95
12.3. SFR Page Stack Example............................................................................... 97
13. Interrupts.............................................................................................................. 112
13.1. MCU Interrupt Sources and Vectors.............................................................. 112
13.1.1. Interrupt Priorities.................................................................................. 113
13.1.2. Interrupt Latency................................................................................... 113
13.2. Interrupt Register Descriptions...................................................................... 115
13.3. External Interrupts INT0 and INT1................................................................. 122
14. Flash Memory....................................................................................................... 124
14.1. Programming The Flash Memory.................................................................. 124
14.1.1. Flash Lock and Key Functions.............................................................. 124
14.1.2. Flash Erase Procedure ......................................................................... 125
14.1.3. Flash Write Procedure .......................................................................... 125
14.1.4. Flash Write Optimization....................................................................... 126
14.2. Non-volatile Data Storage ............................................................................. 127
14.3. Security Options............................................................................................ 127
14.4. Flash Write and Erase Guidelines................................................................. 129
14.4.1. VDD Maintenance and the VDD monitor ................................................ 129
14.4.2. PSWE Maintenance.............................................................................. 130
14.4.3. System Clock........................................................................................ 130
15. Power Management Modes................................................................................. 135
15.1. Idle Mode....................................................................................................... 135
15.2. Stop Mode..................................................................................................... 136
15.3. Suspend Mode .............................................................................................. 136
16. Reset Sources...................................................................................................... 138
16.1. Power-On Reset............................................................................................ 139
16.2. Power-Fail Reset/VDD Monitor ..................................................................... 139
16.3. External Reset............................................................................................... 141
16.4. Missing Clock Detector Reset ....................................................................... 141
16.5. Comparator0 Reset....................................................................................... 142
16.6. PCA Watchdog Timer Reset ......................................................................... 142
16.7. Flash Error Reset .......................................................................................... 142
16.8. Software Reset.............................................................................................. 142
17. External Data Memory Interface and On-Chip XRAM....................................... 144
17.1. Accessing XRAM........................................................................................... 144
17.1.1. 16-Bit MOVX Example.......................................................................... 144
17.1.2. 8-Bit MOVX Example............................................................................ 144
17.2. Configuring the External Memory Interface................................................... 145
17.3. Port Configuration.......................................................................................... 145
17.4. Multiplexed Mode .......................................................................................... 149
17.5. Memory Mode Selection................................................................................ 150
17.5.1. Internal XRAM Only .............................................................................. 150
17.5.2. Split Mode without Bank Select............................................................. 150
17.5.3. Split Mode with Bank Select.................................................................. 151
17.5.4. External Only......................................................................................... 151
C8051F55x/56x/57x
Rev. 1.2 5
17.6. Timing .......................................................................................................... 151
17.6.1. Multiplexed Mode.................................................................................. 153
18. Oscillators and Clock Selection......................................................................... 157
18.1. System Clock Selection................................................................................. 157
18.2. Programmable Internal Oscillator.................................................................. 159
18.2.1. Internal Oscillator Suspend Mode......................................................... 159
18.3. Clock Multiplier.............................................................................................. 162
18.4. External Oscillator Drive Circuit. .................................................................... 164
18.4.1. External Crystal Example...................................................................... 166
18.4.2. External RC Example............................................................................ 167
18.4.3. External Capacitor Example.................................................................. 167
19. Port Input/Output................................................................................................. 169
19.1. Port I/O Modes of Operation.......................................................................... 170
19.1.1. Port Pins Configured for Analog I/O...................................................... 170
19.1.2. Port Pins Configured For Digital I/O...................................................... 170
19.1.3. Interfacing Port I/O in a Multi-Voltage System...................................... 171
19.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 171
19.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 171
19.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 171
19.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 172
19.3. Priority Crossbar Decoder............................................................................. 172
19.4. Port I/O Initialization ...................................................................................... 174
19.5. Port Match..................................................................................................... 179
19.6. Special Function Registers for Accessing and Configuring Port I/O ............. 183
20. Local Interconnect Network (LIN0)..................................................................... 193
20.1. Software Interface with the LIN Controller..................................................... 194
20.2. LIN Interface Setup and Operation................................................................ 194
20.2.1. Mode Definition..................................................................................... 194
20.2.2. Baud Rate Options: Manual or Autobaud ............................................. 194
20.2.3. Baud Rate Calculations: Manual Mode................................................. 194
20.2.4. Baud Rate Calculations—Automatic Mode........................................... 196
20.3. LIN Master Mode Operation.......................................................................... 197
20.4. LIN Slave Mode Operation............................................................................ 198
20.5. Sleep Mode and Wake-Up ............................................................................ 199
20.6. Error Detection and Handling........................................................................ 199
20.7. LIN Registers................................................................................................. 200
20.7.1. LIN Direct Access SFR Registers Definitions ....................................... 200
20.7.2. LIN Indirect Access SFR Registers Definitions..................................... 202
21. Controller Area Network (CAN0) ........................................................................ 210
21.1. Bosch CAN Controller Operation................................................................... 211
21.1.1. CAN Controller Timing.......................................................................... 211
21.1.2. CAN Register Access............................................................................ 212
21.1.3. Example Timing Calculation for 1 Mbit/Sec Communication ................ 212
21.2. CAN Registers............................................................................................... 214
21.2.1. CAN Controller Protocol Registers........................................................ 214
C8051F55x/56x/57x
6 Rev. 1.2
21.2.2. Message Object Interface Registers..................................................... 214
21.2.3. Message Handler Registers.................................................................. 214
21.2.4. CAN Register Assignment .................................................................... 215
22. SMBus................................................................................................................... 218
22.1. Supporting Documents.................................................................................. 219
22.2. SMBus Configuration..................................................................................... 219
22.3. SMBus Operation.......................................................................................... 219
22.3.1. Transmitter Vs. Receiver....................................................................... 220
22.3.2. Arbitration.............................................................................................. 220
22.3.3. Clock Low Extension............................................................................. 220
22.3.4. SCL Low Timeout.................................................................................. 220
22.3.5. SCL High (SMBus Free) Timeout ......................................................... 221
22.4. Using the SMBus........................................................................................... 221
22.4.1. SMBus Configuration Register.............................................................. 221
22.4.2. SMB0CN Control Register.................................................................... 225
22.4.3. Data Register........................................................................................ 228
22.5. SMBus Transfer Modes................................................................................. 228
22.5.1. Write Sequence (Master)...................................................................... 229
22.5.2. Read Sequence (Master)...................................................................... 230
22.5.3. Write Sequence (Slave)........................................................................ 231
22.5.4. Read Sequence (Slave)........................................................................ 232
22.6. SMBus Status Decoding................................................................................ 232
23. UART0................................................................................................................... 235
23.1. Baud Rate Generator .................................................................................... 235
23.2. Data Format................................................................................................... 237
23.3. Configuration and Operation ......................................................................... 238
23.3.1. Data Transmission................................................................................ 238
23.3.2. Data Reception ..................................................................................... 238
23.3.3. Multiprocessor Communications........................................................... 240
24. Enhanced Serial Peripheral Interface (SPI0)..................................................... 246
24.1. Signal Descriptions........................................................................................ 247
24.1.1. Master Out, Slave In (MOSI)................................................................. 247
24.1.2. Master In, Slave Out (MISO)................................................................. 247
24.1.3. Serial Clock (SCK)................................................................................ 247
24.1.4. Slave Select (NSS)............................................................................... 247
24.2. SPI0 Master Mode Operation........................................................................ 248
24.3. SPI0 Slave Mode Operation.......................................................................... 250
24.4. SPI0 Interrupt Sources.................................................................................. 250
24.5. Serial Clock Phase and Polarity.................................................................... 251
24.6. SPI Special Function Registers..................................................................... 252
25. Timers................................................................................................................... 259
25.1. Timer 0 and Timer 1...................................................................................... 261
25.1.1. Mode 0: 13-bit Counter/Timer............................................................... 261
25.1.2. Mode 1: 16-bit Counter/Timer............................................................... 262
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 262
C8051F55x/56x/57x
Rev. 1.2 7
25.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 263
25.2. Timer 2 .......................................................................................................... 269
25.2.1. 16-bit Timer with Auto-Reload............................................................... 269
25.2.2. 8-bit Timers with Auto-Reload............................................................... 269
25.2.3. External Oscillator Capture Mode......................................................... 270
25.3. Timer 3 .......................................................................................................... 275
25.3.1. 16-Bit Timer with Auto-Reload.............................................................. 275
25.3.2. 8-Bit Timers with Auto-Reload .............................................................. 275
25.3.3. External Oscillator Capture Mode......................................................... 276
26. Programmable Counter Array............................................................................. 281
26.1. PCA Counter/Timer....................................................................................... 282
26.2. PCA0 Interrupt Sources................................................................................. 283
26.3. Capture/Compare Modules ........................................................................... 283
26.3.1. Edge-triggered Capture Mode............................................................... 284
26.3.2. Software Timer (Compare) Mode.......................................................... 285
26.3.3. High-Speed Output Mode ..................................................................... 286
26.3.4. Frequency Output Mode ....................................................................... 287
26.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes................. 288
26.3.6. 16-Bit Pulse Width Modulator Mode...................................................... 290
26.4. Watchdog Timer Mode.................................................................................. 291
26.4.1. Watchdog Timer Operation................................................................... 291
26.4.2. Watchdog Timer Usage ........................................................................ 292
26.5. Register Descriptions for PCA0..................................................................... 294
27. C2 Interface .......................................................................................................... 300
27.1. C2 Interface Registers................................................................................... 300
27.2. C2 Pin Sharing .............................................................................................. 303
C8051F55x/56x/57x
Rev. 1.2 8
List of Figures
Figure 1.1. C8051F568-9 and ‘F570-5 (40-pin) Block Diagram .............................. 17
Figure 1.2. C8051F560-7 (32-pin) Block Diagram ................................................... 18
Figure 1.3. C8051F550-7 (24-pin) Block Diagram ................................................... 19
Figure 3.1. QFN-40 Pinout Diagram (Top View) ..................................................... 24
Figure 3.2. QFP-32 Pinout Diagram (Top View) ...................................................... 25
Figure 3.3. QFN-32 Pinout Diagram (Top View) ..................................................... 26
Figure 3.4. QFN-24 Pinout Diagram (Top View) ..................................................... 27
Figure 4.1. QFN-40 Package Drawing .................................................................... 28
Figure 4.2. QFN-40 Landing Diagram ..................................................................... 29
Figure 4.3. QFP-32 Package Drawing ..................................................................... 30
Figure 4.4. QFP-32 Landing Diagram ..................................................................... 31
Figure 4.5. QFN-32 Package Drawing .................................................................... 32
Figure 4.6. QFN-32 Landing Diagram ..................................................................... 33
Figure 4.7. QFN-24 Package Drawing .................................................................... 34
Figure 4.8. QFN-24 Landing Diagram ..................................................................... 35
Figure 5.1. Minimum VDD Monitor Threshold vs. System Clock Frequency ........... 39
Figure 6.1. ADC0 Functional Block Diagram ........................................................... 47
Figure 6.2. ADC0 Tracking Modes .......................................................................... 49
Figure 6.3. 12-Bit ADC Tracking Mode Example ..................................................... 50
Figure 6.4. 12-Bit ADC Burst Mode Example With Repeat Count Set to 4 ............. 51
Figure 6.5. ADC0 Equivalent Input Circuit ............................................................... 53
Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 64
Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 64
Figure 6.8. ADC0 Multiplexer Block Diagram .......................................................... 65
Figure 6.9. Temperature Sensor Transfer Function ................................................ 67
Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 68
Figure 8.1. Comparator Functional Block Diagram ................................................. 70
Figure 8.2. Comparator Hysteresis Plot .................................................................. 71
Figure 8.3. Comparator Input Multiplexer Block Diagram ........................................ 76
Figure 9.1. External Capacitors for Voltage Regulator Input/Output—
Regulator Enabled ............................................................................................. 79
Figure 9.2. External Capacitors for Voltage Regulator Input/Output—Regulator Dis-
abled ............................................................................................................... 80
Figure 10.1. CIP-51 Block Diagram ......................................................................... 82
Figure 11.1. C8051F55x/56x/57x Memory Map ...................................................... 92
Figure 11.2. Flash Program Memory Map ............................................................... 93
Figure 12.1. SFR Page Stack .................................................................................. 96
Figure 12.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT ... 97
Figure 12.3. SFR Page Stack After CAN0 Interrupt Occurs .................................... 98
Figure 12.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR . 99
Figure 12.5. SFR Page Stack Upon Return From PCA Interrupt .......................... 100
Figure 12.6. SFR Page Stack Upon Return From CAN0 Interrupt ........................ 101
Figure 14.1. Flash Program Memory Map ............................................................. 127
C8051F55x/56x/57x
9 Rev. 1.2
Figure 16.1. Reset Sources ................................................................................... 138
Figure 16.2. Power-On and VDD Monitor Reset Timing ....................................... 139
Figure 17.1. Multiplexed Configuration Example ................................................... 149
Figure 17.2. EMIF Operating Modes ..................................................................... 150
Figure 17.3. Multiplexed 16-bit MOVX Timing ....................................................... 153
Figure 17.4. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 154
Figure 17.5. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 155
Figure 18.1. Oscillator Options .............................................................................. 157
Figure 18.2. Example Clock Multiplier Output ....................................................... 162
Figure 18.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 167
Figure 19.1. Port I/O Functional Block Diagram .................................................... 169
Figure 19.2. Port I/O Cell Block Diagram .............................................................. 170
Figure 19.3. Peripheral Availability on Port I/O Pins .............................................. 173
Figure 19.4. Crossbar Priority Decoder in Example Configuration ........................ 174
Figure 20.1. LIN Block Diagram ............................................................................ 193
Figure 21.1. Typical CAN Bus Configuration ......................................................... 210
Figure 21.2. CAN Controller Diagram .................................................................... 211
Figure 21.3. Four segments of a CAN Bit .............................................................. 213
Figure 22.1. SMBus Block Diagram ...................................................................... 218
Figure 22.2. Typical SMBus Configuration ............................................................ 219
Figure 22.3. SMBus Transaction ........................................................................... 220
Figure 22.4. Typical SMBus SCL Generation ........................................................ 222
Figure 22.5. Typical Master Write Sequence ........................................................ 229
Figure 22.6. Typical Master Read Sequence ........................................................ 230
Figure 22.7. Typical Slave Write Sequence .......................................................... 231
Figure 22.8. Typical Slave Read Sequence .......................................................... 232
Figure 23.1. UART0 Block Diagram ...................................................................... 235
Figure 23.2. UART0 Timing Without Parity or Extra Bit ......................................... 237
Figure 23.3. UART0 Timing With Parity ................................................................ 237
Figure 23.4. UART0 Timing With Extra Bit ............................................................ 237
Figure 23.5. Typical UART Interconnect Diagram ................................................. 238
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram ......................... 240
Figure 24.1. SPI Block Diagram ............................................................................ 246
Figure 24.2. Multiple-Master Mode Connection Diagram ...................................... 249
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
............................................................................................................. 249
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
............................................................................................................. 249
Figure 24.5. Master Mode Data/Clock Timing ....................................................... 251
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 252
Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 252
Figure 24.8. SPI Master Timing (CKPHA = 0) ....................................................... 256
Figure 24.9. SPI Master Timing (CKPHA = 1) ....................................................... 256
Figure 24.10. SPI Slave Timing (CKPHA = 0) ....................................................... 257
Figure 24.11. SPI Slave Timing (CKPHA = 1) ....................................................... 257
C8051F55x/56x/57x
Rev. 1.2 10
Figure 25.1. T0 Mode 0 Block Diagram ................................................................. 262
Figure 25.2. T0 Mode 2 Block Diagram ................................................................. 263
Figure 25.3. T0 Mode 3 Block Diagram ................................................................. 264
Figure 25.4. Timer 2 16-Bit Mode Block Diagram ................................................. 269
Figure 25.5. Timer 2 8-Bit Mode Block Diagram ................................................... 270
Figure 25.6. Timer 2 External Oscillator Capture Mode Block Diagram ................ 271
Figure 25.7. Timer 3 16-Bit Mode Block Diagram ................................................. 275
Figure 25.8. Timer 3 8-Bit Mode Block Diagram ................................................... 276
Figure 25.9. Timer 3 External Oscillator Capture Mode Block Diagram ................ 277
Figure 26.1. PCA Block Diagram ........................................................................... 281
Figure 26.2. PCA Counter/Timer Block Diagram ................................................... 282
Figure 26.3. PCA Interrupt Block Diagram ............................................................ 283
Figure 26.4. PCA Capture Mode Diagram ............................................................. 285
Figure 26.5. PCA Software Timer Mode Diagram ................................................. 286
Figure 26.6. PCA High-Speed Output Mode Diagram ........................................... 287
Figure 26.7. PCA Frequency Output Mode ........................................................... 288
Figure 26.8. PCA 8-Bit PWM Mode Diagram ........................................................ 289
Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 290
Figure 26.10. PCA 16-Bit PWM Mode ................................................................... 291
Figure 26.11. PCA Module 2 with Watchdog Timer Enabled ................................ 292
Figure 27.1. Typical C2 Pin Sharing ...................................................................... 303
C8051F55x/56x/57x
Rev. 1.2 11
List of Tables
Table 2.1. Product Selection Guide ......................................................................... 21
Table 3.1. Pin Definitions for the C8051F55x/56x/57x ............................................ 22
Table 4.1. QFN-40 Package Dimensions ................................................................ 28
Table 4.2. QFN-40 Landing Diagram Dimensions ................................................... 29
Table 4.3. QFP-32 Package Dimensions ................................................................ 30
Table 4.4. QFP-32 Landing Diagram Dimensions ................................................... 31
Table 4.5. QFN-32 Package Dimensions ................................................................ 32
Table 4.6. QFN-32 Landing Diagram Dimensions ................................................... 33
Table 4.7. QFN-24 Package Dimensions ................................................................ 34
Table 4.8. QFN-24 Landing Diagram Dimensions ................................................... 35
Table 5.1. Absolute Maximum Ratings .................................................................... 36
Table 5.2. Global Electrical Characteristics ............................................................. 37
Table 5.3. Port I/O DC Electrical Characteristics ..................................................... 40
Table 5.4. Reset Electrical Characteristics .............................................................. 41
Table 5.5. Flash Electrical Characteristics .............................................................. 41
Table 5.6. Internal High-Frequency Oscillator Electrical Characteristics ................. 42
Table 5.7. Clock Multiplier Electrical Specifications ................................................ 43
Table 5.8. Voltage Regulator Electrical Characteristics .......................................... 43
Table 5.9. ADC0 Electrical Characteristics .............................................................. 44
Table 5.10. Temperature Sensor Electrical Characteristics .................................... 45
Table 5.11. Voltage Reference Electrical Characteristics ....................................... 45
Table 5.12. Comparator 0 and Comparator 1 Electrical Characteristics ................. 46
Table 10.1. CIP-51 Instruction Set Summary .......................................................... 84
Table 12.1. Special Function Register (SFR) Memory Map for Pages 0x00 and 0x0F
106
Table 12.2. Special Function Register (SFR) Memory Map for Page 0x0C .......... 107
Table 12.3. Special Function Registers ................................................................. 108
Table 13.1. Interrupt Summary .............................................................................. 114
Table 14.1. Flash Security Summary .................................................................... 128
Table 17.1. EMIF Pinout (C8051F568-9 and ‘F570-5) .......................................... 146
Table 17.2. AC Parameters for External Memory Interface ................................... 156
Table 19.1. Port I/O Assignment for Analog Functions ......................................... 171
Table 19.2. Port I/O Assignment for Digital Functions ........................................... 172
Table 19.3. Port I/O Assignment for External Digital Event Capture Functions .... 172
Table 20.1. Baud Rate Calculation Variable Ranges ............................................ 194
Table 20.2. Manual Baud Rate Parameters Examples ......................................... 196
Table 20.3. Autobaud Parameters Examples ........................................................ 197
Table 20.4. LIN Registers* (Indirectly Addressable) .............................................. 202
Table 21.1. Background System Information ........................................................ 212
Table 21.2. Standard CAN Registers and Reset Values ....................................... 215
Table 22.1. SMBus Clock Source Selection .......................................................... 222
Table 22.2. Minimum SDA Setup and Hold Times ................................................ 223
C8051F55x/56x/57x
12 Rev. 1.2
Table 22.3. Sources for Hardware Changes to SMB0CN ..................................... 227
Table 22.4. SMBus Status Decoding ..................................................................... 233
Table 23.1. Baud Rate Generator Settings for Standard Baud Rates ................... 236
Table 24.1. SPI Slave Timing Parameters ............................................................ 258
Table 26.1. PCA Timebase Input Options ............................................................. 282
Table 26.2. PCA0CPM and PCA0PWM Bit Settings for
PCA Capture/Compare Modules ........................................................ 284
Table 26.3. Watchdog Timer Timeout Intervals1 ................................................... 293
C8051F55x/56x/57x
Rev. 1.2 13
List of Registers
SFR Definition 6.4. ADC0CF: ADC0 Configuration ...................................................... 58
SFR Definition 6.5. ADC0H: ADC0 Data Word MSB .................................................... 59
SFR Definition 6.6. ADC0L: ADC0 Data Word LSB ...................................................... 59
SFR Definition 6.7. ADC0CN: ADC0 Control ................................................................ 60
SFR Definition 6.8. ADC0TK: ADC0 Tracking Mode Select ......................................... 61
SFR Definition 6.9. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 62
SFR Definition 6.10. ADC0GTL: ADC0 Greater-Than Data Low Byte .......................... 62
SFR Definition 6.11. ADC0LTH: ADC0 Less-Than Data High Byte .............................. 63
SFR Definition 6.12. ADC0LTL: ADC0 Less-Than Data Low Byte ............................... 63
SFR Definition 6.13. ADC0MX: ADC0 Channel Select ................................................. 66
SFR Definition 7.1. REF0CN: Reference Control ......................................................... 69
SFR Definition 8.1. CPT0CN: Comparator0 Control ..................................................... 72
SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection ....................................... 73
SFR Definition 8.3. CPT1CN: Comparator1 Control ..................................................... 74
SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection ....................................... 75
SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection ........................................ 77
SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection ........................................ 78
SFR Definition 9.1. REG0CN: Regulator Control .......................................................... 80
SFR Definition 10.1. DPL: Data Pointer Low Byte ........................................................ 88
SFR Definition 10.2. DPH: Data Pointer High Byte ....................................................... 88
SFR Definition 10.3. SP: Stack Pointer ......................................................................... 89
SFR Definition 10.4. ACC: Accumulator ....................................................................... 89
SFR Definition 10.5. B: B Register ................................................................................ 89
SFR Definition 10.6. PSW: Program Status Word ........................................................ 90
SFR Definition 10.7. SNn: Serial Number n .................................................................. 91
SFR Definition 12.1. SFR0CN: SFR Page Control ..................................................... 102
SFR Definition 12.2. SFRPAGE: SFR Page ............................................................... 103
SFR Definition 12.3. SFRNEXT: SFR Next ................................................................ 104
SFR Definition 12.4. SFRLAST: SFR Last .................................................................. 105
SFR Definition 13.1. IE: Interrupt Enable .................................................................... 116
SFR Definition 13.2. IP: Interrupt Priority .................................................................... 117
SFR Definition 13.3. EIE1: Extended Interrupt Enable 1 ............................................ 118
SFR Definition 13.4. EIP1: Extended Interrupt Priority 1 ............................................ 119
SFR Definition 13.5. EIE2: Extended Interrupt Enable 2 ............................................ 120
SFR Definition 13.6. EIP2: Extended Interrupt Priority Enabled 2 .............................. 121
SFR Definition 13.7. IT01CF: INT0/INT1 Configuration .............................................. 123
SFR Definition 14.1. PSCTL: Program Store R/W Control ......................................... 131
SFR Definition 14.2. FLKEY: Flash Lock and Key ...................................................... 132
SFR Definition 14.3. FLSCL: Flash Scale ................................................................... 133
SFR Definition 14.4. CCH0CN: Cache Control ........................................................... 134
SFR Definition 14.5. ONESHOT: Flash Oneshot Period ............................................ 134
SFR Definition 15.1. PCON: Power Control ................................................................ 137
SFR Definition 16.1. VDM0CN: VDD Monitor Control ................................................ 141
C8051F55x/56x/57x
14 Rev. 1.2
SFR Definition 16.2. RSTSRC: Reset Source ............................................................ 143
SFR Definition 17.1. EMI0CN: External Memory Interface Control ............................ 147
SFR Definition 17.2. EMI0CF: External Memory Configuration .................................. 148
SFR Definition 17.3. EMI0TC: External Memory Timing Control ................................ 152
SFR Definition 18.1. CLKSEL: Clock Select ............................................................... 158
SFR Definition 18.2. OSCICN: Internal Oscillator Control .......................................... 160
SFR Definition 18.3. OSCICRS: Internal Oscillator Coarse Calibration ...................... 161
SFR Definition 18.4. OSCIFIN: Internal Oscillator Fine Calibration ............................ 161
SFR Definition 18.5. CLKMUL: Clock Multiplier .......................................................... 163
SFR Definition 18.6. OSCXCN: External Oscillator Control ........................................ 165
SFR Definition 19.1. XBR0: Port I/O Crossbar Register 0 .......................................... 176
SFR Definition 19.2. XBR1: Port I/O Crossbar Register 1 .......................................... 177
SFR Definition 19.3. XBR2: Port I/O Crossbar Register 1 .......................................... 178
SFR Definition 19.4. P0MASK: Port 0 Mask Register ................................................. 179
SFR Definition 19.5. P0MAT: Port 0 Match Register .................................................. 179
SFR Definition 19.6. P1MASK: Port 1 Mask Register ................................................. 180
SFR Definition 19.7. P1MAT: Port 1 Match Register .................................................. 180
SFR Definition 19.8. P2MASK: Port 2 Mask Register ................................................. 181
SFR Definition 19.9. P2MAT: Port 2 Match Register .................................................. 181
SFR Definition 19.10. P3MASK: Port 3 Mask Register ............................................... 182
SFR Definition 19.11. P3MAT: Port 3 Match Register ................................................ 182
SFR Definition 19.12. P0: Port 0 ................................................................................. 183
SFR Definition 19.13. P0MDIN: Port 0 Input Mode ..................................................... 184
SFR Definition 19.14. P0MDOUT: Port 0 Output Mode .............................................. 184
SFR Definition 19.15. P0SKIP: Port 0 Skip ................................................................. 185
SFR Definition 19.16. P1: Port 1 ................................................................................. 185
SFR Definition 19.17. P1MDIN: Port 1 Input Mode ..................................................... 186
SFR Definition 19.18. P1MDOUT: Port 1 Output Mode .............................................. 186
SFR Definition 19.19. P1SKIP: Port 1 Skip ................................................................. 187
SFR Definition 19.20. P2: Port 2 ................................................................................. 187
SFR Definition 19.21. P2MDIN: Port 2 Input Mode ..................................................... 188
SFR Definition 19.22. P2MDOUT: Port 2 Output Mode .............................................. 188
SFR Definition 19.23. P2SKIP: Port 2 Skip ................................................................. 189
SFR Definition 19.24. P3: Port 3 ................................................................................. 189
SFR Definition 19.25. P3MDIN: Port 3 Input Mode ..................................................... 190
SFR Definition 19.26. P3MDOUT: Port 3 Output Mode .............................................. 190
SFR Definition 19.27. P3SKIP: Port 3Skip .................................................................. 191
SFR Definition 19.28. P4: Port 4 ................................................................................. 191
SFR Definition 19.29. P4MDOUT: Port 4 Output Mode .............................................. 192
SFR Definition 20.1. LIN0ADR: LIN0 Indirect Address Register ................................. 200
SFR Definition 20.2. LIN0DAT: LIN0 Indirect Data Register ....................................... 200
SFR Definition 20.3. LIN0CF: LIN0 Control Mode Register ........................................ 201
SFR Definition 21.1. CAN0CFG: CAN Clock Configuration ........................................ 217
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration ...................................... 224
SFR Definition 22.2. SMB0CN: SMBus Control .......................................................... 226
C8051F55x/56x/57x
Rev. 1.2 15
SFR Definition 22.3. SMB0DAT: SMBus Data ............................................................ 228
SFR Definition 23.1. SCON0: Serial Port 0 Control .................................................... 241
SFR Definition 23.2. SMOD0: Serial Port 0 Control .................................................... 243
SFR Definition 23.3. SBUF0: Serial (UART0) Port Data Buffer .................................. 244
SFR Definition 23.4. SBCON0: UART0 Baud Rate Generator Control ...................... 244
SFR Definition 23.6. SBRLL0: UART0 Baud Rate Generator Reload Low Byte ........ 245
SFR Definition 23.5. SBRLH0: UART0 Baud Rate Generator Reload High Byte ....... 245
SFR Definition 24.1. SPI0CFG: SPI0 Configuration ................................................... 253
SFR Definition 24.2. SPI0CN: SPI0 Control ............................................................... 254
SFR Definition 24.3. SPI0CKR: SPI0 Clock Rate ....................................................... 255
SFR Definition 24.4. SPI0DAT: SPI0 Data ................................................................. 255
SFR Definition 25.1. CKCON: Clock Control .............................................................. 260
SFR Definition 25.2. TCON: Timer Control ................................................................. 265
SFR Definition 25.3. TMOD: Timer Mode ................................................................... 266
SFR Definition 25.4. TL0: Timer 0 Low Byte ............................................................... 267
SFR Definition 25.5. TL1: Timer 1 Low Byte ............................................................... 267
SFR Definition 25.6. TH0: Timer 0 High Byte ............................................................. 268
SFR Definition 25.7. TH1: Timer 1 High Byte ............................................................. 268
SFR Definition 25.8. TMR2CN: Timer 2 Control ......................................................... 272
SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 273
SFR Definition 25.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 273
SFR Definition 25.11. TMR2L: Timer 2 Low Byte ....................................................... 274
SFR Definition 25.12. TMR2H Timer 2 High Byte ....................................................... 274
SFR Definition 25.13. TMR3CN: Timer 3 Control ....................................................... 278
SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 279
SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 279
SFR Definition 25.16. TMR3L: Timer 3 Low Byte ....................................................... 280
SFR Definition 25.17. TMR3H Timer 3 High Byte ....................................................... 280
SFR Definition 26.1. PCA0CN: PCA Control .............................................................. 294
SFR Definition 26.2. PCA0MD: PCA Mode ................................................................ 295
SFR Definition 26.3. PCA0PWM: PCA PWM Configuration ....................................... 296
SFR Definition 26.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 297
SFR Definition 26.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 298
SFR Definition 26.6. PCA0H: PCA Counter/Timer High Byte ..................................... 298
SFR Definition 26.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 299
SFR Definition 26.8. PCA0CPHn: PCA Capture Module High Byte ........................... 299
C8051F55x/56x/57x
Rev. 1.2 16
1. System Overview
C8051F55x/56x/57x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted fea-
tures are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.
High-speed pipelined 8051-compatible microcontroller core (up to 50 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
Controller Area Network (CAN 2.0B) Controller with 32 message objects, each with its own indentifier
mask (C8051F550/1/4/5, ‘F560/1/4/5/8/9, and ‘F572/3)
LIN 2.1 peripheral (fully backwards compatible, master and slave modes) (C8 0 51 F550/2/4/6,
‘F560/2/4/6/8, and ‘F57 0 /2/ 4)
True 12-bit 200 ksps 32-channel single-ended ADC with analog multiplexer
Precision programmable 24 MHz internal oscillator that is within ±0.5% across the temperature range
and for VDD voltages greater than or equal to the on-chip voltage regulator minimum output at the low
setting. The oscillator is within +1.0% for VDD voltages below this minimum output setting.
On-chip Clock Multiplier to reach up to 50 MHz
32 kB (C8051F550-3, ‘F560-3 , ‘F568-9, and ‘F570-1) or 16 kB (C80 51F554-7, ‘F564-7, an d ‘F572-5) of
on-chip Flash memory
2304 bytes of on-chip RAM
SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Four general- pu rp o se 16 - bit tim er s
External Data Memory Interface (C8051F56 8-9 and ‘F570-5) with 64 kB address space
Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer
function
On-chip Voltage Regulator
On-chip Power-On Reset, VDD Monitor, and Temperature Sensor
On-chip Voltage Comparator
33, 25, or 18 Port I/O (5 V push-pull)
With on-chip Voltage Regulator, Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the
C8051F55x/56x/57x devices are truly stand-alone System-on-a-Chip so luti ons. T he Fl ash m emo ry can be
reprogrammed even in-circuit, providing non-volatile data storage, and a lso allowing field upgr ades of the
8051 firmware. User software has complete control of all peripherals, and may individually shut down any
or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-
out occupying package pins.
The devices are specified for 1.8 V to 5.25 V operation over the automotive temperature range (–40 to
+125 °C). The C8051F568-9 and ‘F570-5 are available in 40-pin QFN packages, the C8051F560-7
devices are available in 32-pin QFP and QFN packages, and the C8051F550-7 are available in 24-pin
QFN packages. All package options are lead-free and RoHS compliant. See Table 2.1 for ordering infor-
mation. Block diagrams are included in Figure 1.1, Figure 1.2, and Figure 1.3.
C8051F55x/56x/57x
17 Rev. 1.2
Figure 1.1. C8051F568-9 and ‘F570-5 (40-pin) Block Diagram
Digital Peripherals
UART0
Timers 0,
1, 2, 3
6 channel
PCA/WDT
LIN 2.1
Priority
Crossbar
Decoder
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Crossbar Control
Port I/O Configu ra tio n
SFR
Bus
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
SPI
Debug /
Programming
Hardware
Power On
Reset
Reset
C2CK/RST
P1.6
P1.7
Analog Peripherals
Comparator 0 +
-
12- bit
200ksps
ADC
A
M
U
X
VREF
VDD
VDD
VREF
GND
CP0, CP0A
Voltage
Reference VREF
S ystem Clock Setup
External Oscillator
XTAL1
CIP-51 8051 Con troller
Core (50 MHz)
32 or 16 kB Flash
Program Memory
256 Byte RA M
Port 0
Drivers
Port 1
Drivers
Voltage Regulator
(LDO)
GND
VREGIN
VDD
XTAL2
VIO
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 2
Drivers
Port 3
Drivers
Temp
Sensor
P0 – P3
Comparator 1 +
-
CP1, CP1A
CAN 2.0B
GNDA
VDDA
Clock M u ltiplie r
Internal Osc illator
(±0.5%)
External M e mory Inte rface
2 kB XRAM
I2C
C2D
P4.0/C2D
Port 4
Driver
C8051F55x/56x/57x
Rev. 1.2 18
Figure 1.2. C8051F560-7 (32-pin) Block Diagram
Digital Peripherals
UART0
Timers 0,
1, 2, 3
6 channel
PCA/WDT
LIN 2.1
Priority
Crossbar
Decoder
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Crossbar Control
Port I/O Config u rat io n
SFR
Bus
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
SPI
Debug /
Programm ing
Hardware
Power On
Reset
Reset
C2CK/RST
P1.6
P1.7
Analog Peripherals
Comparator 0 +
-
12-bit
200ksps
ADC
A
M
U
X
VREF
VDD
VDD
VREF
GND
CP0, CP0A
Voltage
Reference VREF
System Clock Setup
Extern al Oscillator
XTAL1
CIP-51 8051 Controller
Core (50 MHz)
32 or 16 kB Flash
Program Memory
256 Byte RA M
Port 0
Drivers
Port 1
Drivers
Voltage Regulator
(LDO)
GND
VREGIN
VDD
XTAL2
VIO
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Port 2
Drivers
Port 3
Driver
Temp
Sensor
P0 – P3
Comparator 1 +
-
CP1, CP1A
CAN 2.0B
GNDA
VDDA
Cloc k Multiplier
Intern al Os c illator
(±0.5%)
2 kB XRAM
I2C
C2D
C8051F55x/56x/57x
19 Rev. 1.2
Figure 1.3. C8051F550-7 (24-pin) Block Diagram
Digital Peripherals
UART0
Timers 0,
1, 2, 3
6 channel
PCA/WDT
LIN 2.1
Priority
Crossbar
Decoder
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Crossbar Control
Port I/O C o nfigu ration
SFR
Bus
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
SPI
Debug /
Programming
Hardware
Power On
Reset
Reset
C2CK/RST
P1.6
P1.7
Analog Peripherals
Comparator 0 +
-
12-bit
200ksps
ADC
A
M
U
X
VREF
VDD
VDD
VREF
GND
CP0, CP0A
Voltage
Reference VREF
System Clock Setup
External Oscillator
XTAL1
CIP-51 8051 Controller
Core (50 MHz)
32 or 16 kB F lash
Program Memory
256 By te RA M
Port 0
Drivers
Port 1
Drivers
Voltage Regulator
(LDO)
GND
VREGIN
VDD
XTAL2
VIO
P2.0
P2.1/C2D
Port 2
Drivers
Temp
Sensor
P0 – P2
Comparator 1 +
-
CP1, CP1A
CAN 2.0B
GNDA
Clo c k Multiplie r
Internal Oscillator
(±0.5%)
2 kB XRAM
I2C
C2D
C8051F55x/56x/57x
Rev. 1.2 20
2. Ordering Information
The following features are common to all devices in this family:
50 MHz system clock and 50 MIPS throughput (peak)
2304 bytes of RAM (256 internal bytes and 2048 XRAM bytes)
SMBus/I2C, Enhanced SPI, Enhanced UART
Four Timers
Six Programmable Counte r Array channels
Internal 24 MHz oscillator
Internal Voltage Regulator
12-bit, 200 ksps ADC
Internal Voltage Reference and Temperature Sensor
Tw o Analog Comparators
Table 2.1 shows the feature that differentiate the devices in this family.
C8051F55x/56x/57x
21 Rev. 1.2
Note: The suffix of the part number indicates the device rating and the package. All devices are RoHS compliant.
All devices in Tabl e 2.1 are also available in an automoti ve version. For the auto motive version, the -I in the
ordering part number is replaced with -A. For example, the automotive version of the C8051F550-IM is the
C8051F550-AM.
The -AM and -AQ devices receive full automotive quality production status, including AEC-Q1 00 qualifica -
tion, registration with International Material Data System (IMDS) and Part Production Approval Process
(PPAP) documentation. PPAP documentation is available at www.silabs.com with a registered and NDA
approved user account. The -AM and -AQ devices enable high volume automotive OEM applications with
their enhanced testing and processing. Please contact Silicon Labs sales for more information regarding
–AM and -AQ dev ice s for your automotive project.
Table 2.1. Product Selection Guide
Ordering Part Number
Flash Memory (kB)
CAN2.0B
LIN2.1
Digital Port I/Os
External Mem. Interface
Package
Ordering Part Number
Flash Memory (kB)
CAN2.0B
LIN2.1
Digital Port I/Os
External Mem. Interface
Package
C8051F550-IM 32
18 —QFN-24 C8051F564-IM 16
25 —QFN-32
C8051F551-IM 32
—18 —QFN-24 C8051F564-IQ 16
25 —QFP-32
C8051F552-IM 32 —
18 —QFN-24 C8051F565-IM 16
—25 —QFN-32
C8051F553-IM 32 — — 18 —QFN-24 C8051F565-IQ 16
—25 —QFP-32
C8051F554-IM 16
18 —QFN-24 C8051F566-IM 16 —
25 —QFN-32
C8051F555-IM 16
—18 —QFN-24 C8051F566-IQ 16 —
25 —QFP-32
C8051F556-IM 16 —
18 —QFN-24 C8051F567-IM 16 — — 25 —QFN-32
C8051F557-IM 16 — — 18 —QFN-24 C8051F567-IQ 16 — — 25 —QFP-32
C8051F560-IM 32
25 —QFN-32 C8051F568-IM 32
33
QFN-40
C8051F560-IQ 32
25 —QFP-32 C8051F569-IM 32
—33
QFN-40
C8051F561-IM 32
—25 —QFN-32 C8051F570-IM 32 —
33
QFN-40
C8051F561-IQ 32
—25 —QFP-32 C8051F571-IM 32 — — 33
QFN-40
C8051F562-IM 32 —
25 —QFN-32 C8051F572-IM 16
33
QFN-40
C8051F562-IQ 32 —
25 —QFP-32 C8051F573-IM 16
—33
QFN-40
C8051F563-IM 32 — — 25 —QFN-32 C8051F574-IM 16 —
33
QFN-40
C8051F563-IQ 32 — — 25 —QFP-32 C8051F575-IM 16 — — 33
QFN-40
C8051F55x/56x/57x
Rev. 1.2 22
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F55x/56x/57x
Name Pin
40-pin
packages
Pin
32-pin
packages
Pin
24-pin
packages
Type Description
VDD 4 4 3 Digital Supply Voltage. Mu st be connected.
GND 6 6 4 Digital Ground. Must be connected.
VDDA 5 5 — Analog Supply Voltage. Must be connected.
GNDA 7 7 5 Analog Ground. Must be connected.
VREGIN 3 3 2 Voltage Regulator Input
VIO 2 2 1 Port I/O Supply Voltage. Must be connected.
RST/
C2CK
10 10 8D I/O
D I/O
Device Reset. Open-drain output of internal
POR or VDD Monitor.
Clock signal for the C2 Debug Interface.
P4.0/
C2D
9 — — D I/O or A In
D I/O
Port 4.0. See SFR Definition 19.28.
Bi-directional data signal for the C2 Debug
Interface.
P3.0/
C2D
9 — D I/O or A In
D I/O
Port 3.0. See SFR Definition 19.24.
Bi-directional data signal for the C2 Debug
Interface.
P2.1/
C2D
— 7 D I/O or A In
D I/O
Port 2.1. See SFR Definition 19.20.
Bi-directional data signal for the C2 Debug
Interface.
P0.0 8 8 6 D I/O or A In Port 0.0. See SFR Definition 19.12 .
P0.1 1 1 24 D I/O or A In Port 0.1
P0.2 40 32 23 D I/O or A In Port 0.2
P0.3 39 31 22 D I/O or A In Port 0.3
P0.4 38 30 21 D I/O or A In Port 0.4
P0.5 37 29 20 D I/O or A In Port 0.5
P0.6 36 28 19 D I/O or A In Port 0.6
P0.7 35 27 18 D I/O or A In Port 0.7
C8051F55x/56x/57x
23 Rev. 1.2
P1.0 34 26 17 D I/O or A In Port 1.0. See SFR Definition 19.16.
P1.1 33 25 16 D I/O or A In Port 1.1.
P1.2 32 24 15 D I/O or A In Port 1.2.
P1.3 31 23 14 D I/O or A In Port 1.3.
P1.4 30 22 13 D I/O or A In Port 1.4.
P1.5 29 21 12 D I/O or A In Port 1.5.
P1.6 28 20 11 D I/O or A In Port 1.6.
P1.7 27 19 10 D I/O or A In Port 1.7.
P2.0 26 18 9D I/O or A In Port 2.0. See SFR Definition 19.20.
P2.1 25 17 —D I/O or A In Port 2.1.
P2.2 24 16 —D I/O or A In Port 2.2.
P2.3 23 15 —D I/O or A In Port 2.3.
P2.4 22 14 —D I/O or A In Port 2.4.
P2.5 21 13 —D I/O or A In Port 2.5.
P2.6 20 12 —D I/O or A In Port 2.6.
P2.7 19 11 —D I/O or A In Port 2.7.
P3.0 18 — — D I/O or A In Port 3.0. See SFR Definition 19.24.
P3.1 17 — — D I/O or A In Port 3.1.
P3.2 16 — — D I/O or A In Port 3.2.
P3.3 15 — — D I/O or A In Port 3.3.
P3.4 14 — — D I/O or A In Port 3.4.
P3.5 13 ——D I/O or A In Port 3.5.
P3.6 12 — — D I/O or A In Port 3.6.
P3.7 11 — — D I/O or A In Port 3.7.
Table 3.1. Pin Definitions for the C8051F55x/56x/57x (Continued)
Name Pin
40-pin
packages
Pin
32-pin
packages
Pin
24-pin
packages
Type Description
C8051F55x/56x/57x
Rev. 1.2 24
Figure 3.1. QFN-40 Pinout Diagram (Top View)
GND
C8051F568-IM
C8051F569-IM
C8051F570-IM
C8051F571-IM
C8051F572-IM
C8051F573-IM
C8051F574-IM
C8051F575-IM
(Top View) P2.2
P2.1
P2.0
P1.7
P1.6
P1.5
27
28
29
25
24
26
P1.430
P2.323
P2.422
P2.521
P3.2
P3.1
P3.0
P2.7
P2.6
14
13
12
16
17
15
11
P3.3
18
P3.4
19
P3.5
20
P3.6
P3.7
GNDA
GND
VDDA
VDD
VREGIN
VIO
4
3
2
6
7
5
P0.1 / CNVSTR 1
P0 .0 / V REF 8
P 4.0 / C 2 D 9
RST / C2CK 10
P1.0
P0.7 / CAN RX
P0.6 / CAN TX
P0.5 / UART0 RX
P0.4 / UART0 TX
P0.3 / XTAL2
37
38
39
35
34
36
P0.2 / XTAL140
P1.133
P1.232
P1.331
C8051F55x/56x/57x
25 Rev. 1.2
Figure 3.2. QFP-32 Pinout Diagram (Top View)
1
VREGIN
P1.2
P1.7
P1.4
P1.3
P1.5
GNDA
VIO
P2.0
P2.1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
P1.6
C8051F560-IQ
C8051F561-IQ
C8051F562-IQ
C8051F563-IQ
C8051F564-IQ
C8051F565-IQ
C8051F566-IQ
C8051F567-IQ
(Top View)
P0.0 / VREF
VDD
VDDA
P0.1 / CNVSTR
P2.6
P2.5
P2.4
P2.3
P2.2 P1.1
P1.0
P2.7
P0.6 / CAN TX
P0.5 / UART0 RX
P0.4 / UART0 TX
RST / C2CK
P3.0 / C2D
GND
P0.7 / CAN RX
P0.3 / XTAL2
P0.2 / XTAL1
C8051F55x/56x/57x
Rev. 1.2 26
Figure 3.3. QFN-32 Pinout Diagram (Top View)
P2.0
P1.7
P1.6
P1.5
P1.4
P1.3
21
22
23
19
18
20
P1.224
P2.117
GND
VIO
VREGIN
VDD
VDDA
GND
GNDA
5
6
7
4
3
2
P0.0 / VREF 8
P0.1 / CNVSTR 1
P1.0
P0.7 / CAN RX
P0.6 / CAN TX
P0.5 / UART0 RX
P0.4 / UART0 TX
P0.3 / XTAL2
29
30
31
27
26
28
P0.2 / XTAL132
P1.125
C8051F560-IM
C8051F561-IM
C8051F562-IM
C8051F563-IM
C8051F564-IM
C8051F565-IM
C8051F566-IM
C8051F567-IM
(Top View)
RST / C2CK
P2.7
P2.6
P2.5
P2.4
P2.3
13
14
15
11
10
12
P2.2 16
P3.0 / C2D 9
C8051F55x/56x/57x
27 Rev. 1.2
Figure 3.4. QFN-24 Pinout Diagram (Top View)
GND P1.4
P1.3
P1.2
P1.1
P1.0
P0.7/CAN0 RX
15
14
13
17
18
16
P2.1/C2D
RST/C2CK
P2.0
P1.7
P1.6
P1.5
10
11
12
8
7
9
VIO
VREGIN
VDD
GND
GNDA
P0.0/VREF
4
5
6
2
1
3
P0.6/CAN0 TX
P0.5/UART0 RX
P0.4/UART0 TX
P0.3/XTAL2
P0.2/XTAL1
P0.1/CNVSTR
22
23
24
20
19
21
C8051F550-IM
C8051F551-IM
C8051F552-IM
C8051F553-IM
C8051F554-IM
C8051F555-IM
C8051F556-IM
C8051F557-IM
(Top View)
C8051F55x/56x/57x
Rev. 1.2 28
4. Package Specifications
4.1. QFN-40 Package Specifications
Figure 4.1. QFN-40 Package Drawing
Table 4.1. QFN-40 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A0.80 0.85 0.90 E2 4.00 4.10 4.20
A1 0.00 0.05 L0.35 0.40 0.45
b0.18 0.23 0.28 L1 0.10
D6.00 BSC aaa 0.10
D2 4.00 4.10 4.20 bbb 0.10
e0.50 BSC ddd 0.05
E6.00 BSC eee 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation VJJD-5, except for
features A, D2, and E2 which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F55x/56x/57x
29 Rev. 1.2
Figure 4.2. QFN-40 Landing Diagram
Table 4.2. QFN-40 Landing Diagram Dimensions
Dimension Min Max Dimension Min Max
C1 5.80 5.90 X2 4.10 4.20
C2 5.80 5.90 Y1 0.75 0.85
e0.50 BSC Y2 4.10 4.20
X1 0.15 0.25
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimension an d Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-SM-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 4x4 array of 0.80 mm square openings on a 1.05 mm pitch should be used for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F55x/56x/57x
Rev. 1.2 30
4.2. QFP-32 Package Specifications
Figure 4.3. QFP-32 Package Drawing
Table 4.3. QFP-32 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A — — 1.60 E9.00 BSC.
A1 0.05 —0.15 E1 7.00 BSC.
A2 1.35 1.40 1.45 L0.45 0.60 0.75
b0.30 0.37 0.45 aaa 0.20
c0.09 —0.20 bbb 0.20
D9.00 BSC. ccc 0.10
D1 7.00 BSC. ddd 0.20
e0.80 BSC. θ0° 3.5° 7°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC outline MS-026, variation BBA.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F55x/56x/57x
31 Rev. 1.2
Figure 4.4. QFP-32 Landing Diagram
Table 4.4. QFP-32 Landing Diagram Dimensions
Dimension Min Max Dimension Min Max
C1 8.40 8.50 X1 0.40 0.50
C2 8.40 8.50 Y1 1.25 1.35
E0.80 BSC
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
7. A No-Clean, T y pe-3 solder paste is recommended.
8. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F55x/56x/57x
Rev. 1.2 32
4.3. QFN-32 Package Specifications
Figure 4.5. QFN-32 Package Drawing
Table 4.5. QFN-32 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A0.80 0.9 1.00 E2 3.20 3.30 3.40
A1 0.00 0.02 0.05 L0.30 0.40 0.50
b0.18 0.25 0.30 L1 0.00 —0.15
D5.00 BSC. aaa — — 0.15
D2 3.20 3.30 3.40 bbb — — 0.15
e0.50 BSC. ddd — — 0.05
E5.00 BSC. eee — — 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F55x/56x/57x
33 Rev. 1.2
Figure 4.6. QFN-32 Landing Diagram
Table 4.6. QFN-32 Landing Diagram Dimensions
Dimension Min Max Dimension Min Max
C1 4.80 4.90 X2 3.20 3.40
C2 4.80 4.90 Y1 0.75 0.85
e0.50 BSC Y2 3.20 3.40
X1 0.20 0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 3x3 array of 1.0 mm openings on a 1.20 mm pitch should be used for the center ground pad.
Card Assembly
8. A No-Clean, T y pe-3 solder paste is recommended.
9. The recommended card refl ow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F55x/56x/57x
Rev. 1.2 34
4.4. QFN-24 Package Specifications
Figure 4.7. QFN-24 Package Drawing
Table 4.7. QFN-24 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A0.70 0.75 0.80 L0.30 0.40 0.50
A1 0.00 0.02 0.05 L1 0.00 0.15
b0.18 0.25 0.30 aaa 0.15
D4.00 BSC bbb 0.10
D2 2.55 2.70 2.80 ddd 0.05
e0.50 BSC eee 0.08
E4.00 BSC Z0.24
E2 2.55 2.70 2.80 Y0.18
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted .
2. Dimensioning and Tolerancing per ANSI Y14.5M-199 4.
3. This drawing conforms to JEDEC Solid State Outline MO-22 0, variation WGGD, except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F55x/56x/57x
35 Rev. 1.2
Figure 4.8. QFN-24 Landing Diagram
Table 4.8. QFN-24 Landing Diagram Dimensions
Dimension Min Max Dimension Min Max
C1 3.90 4.00 X2 2.70 2.80
C2 3.90 4.00 Y1 0.65 0.75
E0.50 BSC Y2 2.70 2.80
X1 0.20 0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center ground
pad.
Card Assembly
8. A No-Clean, T y pe-3 solder paste is recommended.
9. The recommended card refl ow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
C8051F55x/56x/57x
Rev. 1.2 36
5. Electrical Characteristics
5.1. Absolute Maximum Specifications
Table 5.1. Absolute Maximum Ratings
Parameter Conditions Min Typ Max Units
Ambient Temperature under Bias –55 — 135 °C
Storage Temperatu re –65 — 150 °C
Voltage on VREGIN with Respect to GND –0.3 — 5.5 V
Voltage on VDD with Respect to GND –0.3 — 2.8 V
Voltage on VDDA with Respect to GND –0.3 — 2.8 V
Voltage on VIO with Respect to GND –0.3 — 5.5 V
Voltage on any Port I/O Pin or RST with Respect to
GND –0.3 — VIO + 0.3 V
Maximum Total Current through VREGIN or GND — — 500 mA
Maximum Output Curre nt Sunk by RST or any Port Pin — — 100 mA
Maximum Output Current Sourced by any Port Pin — — 100 mA
Note: Stresses outside of the range of the “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the devices at those or any other conditions
outside of those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
C8051F55x/56x/57x
37 Rev. 1.2
5.2. Electrical Characteristics
Table 5.2. Global Electrical Characteristics
–40 to +125 °C, 24 MHz system clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Supply Input Voltage (VREGIN)1.8—5.25V
Digital Supply Voltage (VDD) System Clock < 25 MHz
System Clock > 25 MHz
VRST1—2.75 V
2 — 2.75
Analog Supply Voltage (VDDA)
(Must be connected to VDD)
System Clock < 25 MHz
System Clock > 25 MHz
VRST1—2.75 V
2 — 2.75
Port I/O Supply Voltage (VIO) Normal Operation 1.82—5.25 V
Digital Supply RAM Data
Retention Voltage —1.5— V
SYSCLK (System Clock)30—50MHz
TSYSH (SYSCLK High Time) 9 — — ns
TSYSL (SYSCLK Low Time) 9 — — ns
Specified Operating
Temperature Range –40 — +125 °C
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
IDD4VDD = 2.1 V, F = 200 kHz — 85 — µA
VDD = 2.1 V, F = 1.5 MHz — 660 — µA
VDD = 2.1 V, F = 25 MHz — 9.2 11 mA
VDD = 2.1 V, F = 50 MHz — 17 21 mA
IDD4VDD = 2.6 V, F = 200 kHz — 120 — µA
VDD = 2.6 V, F = 1.5 MHz — 920 — µA
VDD = 2.6 V, F = 25 MHz — 13 21 mA
VDD = 2.6 V, F = 50 MHz — 22 33 mA
IDD Supply Sensitivity4F = 25 MHz — 68 — %/V
F = 1 MHz — 77 — %/V
Notes:
1. Given in Table 5.4 on page 41.
2. VIO should not be lower than the VDD voltage.
3. SYSCLK must be at least 32 kHz to enable debugging.
4. Guaranteed by characterization . Does not include oscillator supp ly current.
5. IDD estima tion for different frequencies.
6. Idle IDD esti mation for different frequencies.
C8051F55x/56x/57x
Rev. 1.2 38
IDD Frequency Sensitivity 4,5 VDD = 2.1 V, F < 12.5 MHz, T =
25 °C— 0.43 — mA/MHz
VDD = 2.1 V, F > 12.5 MHz, T =
25 °C— 0.33 — mA/MHz
VDD = 2.6 V, F < 12.5 MHz, T =
25 °C— 0.60 — mA/MHz
VDD = 2.6 V, F > 12.5 MHz, T =
25 °C— 0.42 — mA/MHz
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
IDD4VDD = 2.1 V, F = 200 kHz — 50 — µA
VDD = 2.1 V, F = 1.5 MHz — 410 — µA
VDD = 2.1 V, F = 25 MHz — 6.5 8.0 mA
VDD = 2.1 V, F = 50 MHz — 13 16 mA
IDD4VDD = 2.6 V, F = 200 kHz — 67 — µA
VDD = 2.6 V, F = 1.5 MHz — 530 — µA
VDD = 2.6 V, F = 25 MHz — 8.0 15 mA
VDD = 2.6 V, F = 50 MHz — 16 25 mA
IDD Supply Sensitivity4F = 25 MHz — 55 — %/V
F = 1 MHz — 58 —
IDD Frequency Sensitivity 4.6 VDD = 2.1V, F < 12.5 MHz, T = 25 °C — 0.26 —
mA/MHz
VDD = 2.1V, F > 12.5 MHz, T = 25 °C — 0.26 —
VDD = 2.6V, F < 12.5 MHz, T = 25 °C — 0.34 —
VDD = 2.6V, F > 12.5 MHz, T = 25 °C — 0.34 —
Digital Supply Current4
(Stop or Suspend Mode) Oscillator not running,
VDD Monitor Disabled µA
Temp = 25 °C—1—
Temp = 60 °C—6—
Temp= 125 °C—70—
Table 5.2. Global Electrical Characteristics (Continued)
–40 to +125 °C, 24 MHz system clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Notes:
1. Given in Tabl e 5.4 on page 41.
2. VIO should not be lower than the VDD voltage.
3. SYSCLK must be at least 32 kHz to enable debugging.
4. Guaranteed by characterization . Does not include oscillator supp ly current.
5. IDD estima tion for different frequencies.
6. Idle IDD estimation for different frequencies.
C8051F55x/56x/57x
39 Rev. 1.2
Figure 5.1. Minimum VDD Monitor Threshold vs. System Clock Frequency
Note: With system clock frequencies greater than 25 MHz, the VDD monitor level shoul d be set to the high threshold
(VDMLVL = 1b in SFR VDM0CN) to prevent undefined CPU operation. The high threshold should only be used
with an external regulator powering VDD directly. See Figure 9.2 on page 80 for the recommended power
supply connections.
C8051F55x/56x/57x
Rev. 1.2 40
Table 5.3. Port I/O DC Electrical Characteristics
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameters Conditions Min Typ Max Units
Output High Voltage IOH = –3 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
VIO – 0.4
VIO – 0.02
—
—
—
VIO – 0.7
—
—
—
V
Output Low Voltage VIO = 1.8 V:
IOL = 70 µA
IOL = 8.5 mA
VIO = 2.7 V:
IOL = 70 µA
IOL = 8.5 mA
VIO = 5.25 V:
IOL = 70 µA
IOL = 8.5 mA
—
—
—
—
—
—
—
—
—
—
—
—
50
750
45
550
40
400
mV
Input High Vo ltage VREGIN = 5.25 V 0.7 x VIO — V
Input Low Vo ltage VREGIN = 2. 7 V — — 0.3 x VIO V
Input Leakag e
Current
Weak Pullup Off
Weak Pullup On, VIO = 2.1 V,
VIN = 0 V, VDD = 1.8 V
Weak Pullup On, VIO = 2.6 V,
VIN = 0 V, VDD = 2.6 V
Weak Pullup On, VIO = 5.0 V,
VIN = 0 V, VDD = 2.6 V
—
—
—
—
—
7
17
49
±2
9
22
115
µA
C8051F55x/56x/57x
41 Rev. 1.2
Table 5.4. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
RST Output Low Voltage VIO = 5 V; IOL = 70 µA — — 40 mV
RST Input High Voltage 0.7 x VIO ——
RST Input Low Voltage — — 0.3 x VIO
RST Input Pullup Current RST = 0.0 V, VIO = 5 V — 49 115 µA
VDD RST Threshold (VRST-LOW)1.65 1.75 1.80 V
VDD RST Threshold (VRST-HIGH)2.25 2.30 2.45 V
VREGIN Ramp Time for Power On VREGIN Ramp 0–1.8 V ——1ms
Missing Clock Detector Timeout
Time from last system clock
rising edge to reset initiation
VDD = 2.1 V
VDD = 2.5 V 200
200 340
250 600
600
µs
Reset Time Delay Delay between release of
any reset source and code
execution at location 0x0000 —155175µs
Minimum RST Low Time to
Generate a System Reset 6——µs
VDD Monitor Turn-on Tim e —60100µs
VDD Monitor Supply Current —12µA
Table 5.5. Flash Electrical Characteristics
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Flash Size
C8051F550-3, ‘F560-3,
‘F568-9, and ‘F570-1 327681Bytes
C8051F554-7, ‘F564-7, and
‘F572-5 16384
Endurance 20 k 150 k — Erase/Write
Retention 125 °C 10 — — Years
Erase Cycle Time 25 MHz System Clock 28 30 45 ms
Write Cycle Time 25 MHz System Clock 79 84 125 µs
VDD Write/Erase operations VRST-HIGH2—— V
Temperature during
Programming Opera-
tions
–I Devices
–A Devices 0
–40 —
—+125
+125 °C
1. On the 32 kB Flash devices, 1024 bytes at addresses 0x7C00 to 0x7FFF are reserved.
2. See Table 5.4 for the VRST - HIGH specification.
C8051F55x/56x/57x
Rev. 1.2 42
Table 5.6. Internal High-Frequency Oscillator Electrical Characteristics
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified; Using factory-calibrated settings.
Parameter Conditions Min Typ Max Units
Oscillator Frequency IFCN = 111b;
VDD > VREGMIN1
IFCN = 111b;
VDD < VREGMIN1
24 – 0.5%
24 – 1.0%
242
242
24 + 0.5%
24 + 1.0%
MHz
Oscillator Supply Current
(from VDD)Internal Oscillator On
OSCICN[7:6] = 11b —880 1300 µA
Internal Oscillat or Suspen d
OSCICN[7:6] = 00b
ZTCEN = 1
Temp = 25 °C
Temp = 85 °C
Temp = 125 °C
—67
90
130
—
Wake-up Time From Suspend OSCICN[7:6] = 00b — 1 — µs
Power Supply Sensitivity Constant Temperature —0.11 —%/V
Temperature Sensitivity3Constant Supply
TC1
TC2
—
—5.0
–0.65 —
—ppm/°C
ppm/°C2
1. VREGMIN is the minimum output of the voltage regulator for its low setting (REG0CN: REG0MD = 0b). See
Table 5 .8 , “Voltage Regulator Electrical Characteristics,” on page 43.
2. This is the average frequency across the operating temperature range
3. Use temperature coefficients TC1 and TC2 to calculate the new internal oscillator frequency using the
following equation: f(T) = f0 x (1 + TC1 x (T - T0) + TC2 x (T - T0)2)
where f0 is the internal oscillator frequency at 25 °C and T0 is 25 °C.
C8051F55x/56x/57x
43 Rev. 1.2
Table 5.7. Clock Multiplier Electrical Specifications
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Input Frequency (Fcmin)2——MHz
Output Frequency — — 50 MHz
Power Supply Current — 0.9 1.9 mA
Table 5.8. Voltage Regulator Electrical Characteristics
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Input Voltage Range (VREGIN)1.8* — 5.25 V
Dropout Voltage (VDO)Maximum Current = 50 mA — 10 — mV/mA
Output Voltage (VDD)2.1 V operation (REG0MD = 0)
2.6 V operation (REG0MD = 1) 2.0
2.5 2.1
2.6 2.25
2.75 V
Bias Current — 1 9 µA
Dropout Indica tor Detection
Threshold With respe ct to VDD –0.21 — –0.02 V
Output Voltage Temperature
Coefficient —0.29 —mV/°C
VREG Settling Time 50 mA load with VREGIN = 2.4 V
and VDD load capacitor of 4.8 µF —450 — µs
*Note: The minimum input voltage is 1.8 V or VDD + VDO(max load), whichever is greater
C8051F55x/56x/57x
Rev. 1.2 44
Table 5.9. ADC0 Electrical Characteristics
VDDA = 1.8 to 2.75 V, –40 to +125 °C, VREF = 1.5 V (REFSL=0) unless otherwise specified.
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 12 bits
Integral Nonlinearity —±0.5 ±3 LSB
Differential Nonlinearity Guaranteed Monotonic —±0.5 ±1 LSB
Offset Error1–10 3.0 10 LSB
Full Scale Error –20 5.7 20 LSB
Offset Temperature Coefficient —7.7 —ppm/°C
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion 63 65 —dB
Total Harmonic Distortion Up to the 5th harmonic; —80 —dB
Spurious- F re e Dyn a mic Rang e —-82 —dB
Conversion Rate
SAR Conversion Clock — — 3.6 MHz
Conversion Time in SAR Clocks213 — — clocks
Track/Hold Acquisition Time3VDDA > 2.0 V
VDDA < 2.0 V 1.5
3.5 —
——
—µs
Throughput Rate4VDDA > 2.0 V — — 200 ksps
Analog Inputs
ADC Input Voltage Range5gain = 1.0 (default)
gain = n 0
0—VREF
VREF / n V
Absolute Pin Voltage with respect
to GND 0 — VIO V
Sampling Capacitance —31 —pF
Input Multiplexer Impedance — 3 — kΩ
Power Specifications
Power Supply Current
(VDDA supplied to ADC0) Operating Mode, 200 ksps —1100 1500 µA
Burst Mode (Idle) —1100 1500 µA
Power-On Time 5 — — µs
Power Supply Rejection —–60 —mV/V
Notes:
1. Represents one standard deviation from the mean. Offset and full-scale error can be removed through
calibration.
2. An additional 2 FCLK cycles are required to start and complete a conversion
3. Additional tracking time may be required depending on the output impedance conn ected to the ADC input.
See Section “6.2.1. Settling Time Requirements” on page 52.
4. An increase in tra cking time will decrease the ADC throughput.
5. See Section “6.3. Selectable Gain” on page 53 for more information about the setting the gain.
C8051F55x/56x/57x
45 Rev. 1.2
Table 5.10. Temperature Sensor Electrical Characteristics
VDDA = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Linearity —±0.1 —°C
Slope —3.33 —mV/°C
Slope Error* —88 —µV/°C
Offset Temp = 0 °C —856 —mV
Offset Error* Temp = 0 °C —±14 —mV
Power Supply Current —18 —µA
Tracking Time 12 — — µs
*Note: Represents one standard deviation from the mean.
Table 5.11. Voltage Reference Electrical Characteristics
VDDA = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Internal Reference (REFBE = 1)
Output Voltage 25 °C ambient (REFLV = 0) 1.45 1.50 1.55 V
25 °C ambient (REFLV = 1), VDD = 2.6 V 2.15 2.20 2.25
VREF Short-Circuit Current — 5 10 mA
VREF Temperature
Coefficient —38 —ppm/°C
Power Consumption Internal —30 50 µA
Load Regulation Load = 0 to 200 µA to AGND — 3 — µV/µA
VREF Turn-on Time 1 4.7 µF tantalum and 0.1 µF bypass —1.5 —ms
VREF Turn-on Time 2 0.1 µF bypass —46 —µs
Power Supply Rejection —1.2 —mV/V
External Referenc e (REF BE = 0)
Input Voltage Range 1.5 — VDDA V
Input Current Sample Rate = 200 ksps; VREF = 1.5 V — 2.1 —µA
Power Specifications
Reference Bias Generator REFBE = 1 or TEMPE = 1 —21 40 µA
C8051F55x/56x/57x
Rev. 1.2 46
Table 5.12. Comparator 0 and Comparator 1 Electrical Characteristics
VIO = 1.8 to 5.25 V, –40 to +125 °C unless otherwise noted.
Parameter Conditions Min Typ Max Units
Response Time:
Mode 0, Vcm* = 1.5 V CPn+ – CPn– = 100 mV —330 —ns
CPn+ – CPn– = –100 mV —390 —ns
Response Time:
Mode 1, Vcm* = 1.5 V CPn+ – CPn– = 100 mV —490 —ns
CPn+ – CPn– = –100 mV —610 —ns
Response Time:
Mode 2, Vcm* = 1.5 V CPn+ – CPn– = 100 mV —590 —ns
CP0+ – CP0– = –100 mV —750 —ns
Response Time:
Mode 3, Vcm* = 1.5 V CPn+ – CPn– = 100 mV —2300 —ns
CPn+ – CPn– = –100 mV —3100 —ns
Common-Mode Rejection Ratio —2.1 13 mV/V
Positive Hysteresis 1 CPnHYP1–0 = 00 -2 0 2 mV
Positive Hysteresis 2 CPnHYP1–0 = 01 2 6 10 mV
Positive Hysteresis 3 CPnHYP1–0 = 10 511 20 mV
Positive Hysteresis 4 CPnHYP1–0 = 11 13 21 40 mV
Negative Hysteresis 1 CPnHYN1–0 = 00 -2 0 2 mV
Negative Hysteresis 2 CPnHYN1–0 = 01 2510 mV
Negative Hysteresis 3 CPnHYN1–0 = 10 511 20 mV
Negative Hysteresis 4 CPnHYN1–0 = 11 13 21 40 mV
Inverting or Non-Inverting Input
Voltage Range –0.25 — VIO + 0.25 V
Input Capacitance — 8 — pF
Input Offset Voltage –10 —+10 mV
Power Supply
Power Supply Rejection —0.18 —mV/V
Power-up Time — 3 — µs
Supply Current at DC
Mode 0 —6.3 20 µA
Mode 1 —3.4 10 µA
Mode 2 —2.6 7.5 µA
Mode 3 —0.6 3µA
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
C8051F55x/56x/57x
Rev. 1.2 47
6. 12-Bit ADC (ADC0)
The ADC0 on the C8051F55x/56x/57x consists of an analog multiplexer (AMUX0) with 33, 25, or 18 total
input selections and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated
track-and-hold , pro grammable window dete ctor, programmable at tenuatio n (1:2) , and h ardware a ccumula-
tor. The ADC0 subsystem has a special Burst Mode which can automatically enable ADC0, capture and
accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. The
AMUX0, data conversion modes, and window detector are all configurable under software control via the
Special Function Registers shows in Figure 6.1. ADC0 inputs are single-ended and may be configured to
measure P0.0-P3.7, the Temperatur e Se nsor output, V DD, or GND with resp ect to GND. The voltage refer-
ence for ADC0 is selected as described in Section “6.6. Temperature Sensor” on page 67. ADC0 is
enabled when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing
conversions in Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode
conversions are taking place.
Figure 6.1. ADC0 Functional Block Diagram
ADC0CN
AD0CM0
AD0CM1
AD0LJST
AD0WINT
AD0BUSY
AD0INT
BURSTEN
AD0EN
Start
Conversion
VDD
35-to-1
AMUX0
VDD
P0.0
P0.7
P1.0
P1.7
ADC0MX
ADC0MX4
ADC0MX3
ADC0MX2
ADC0MX1
ADC0MX0
GND
Temp Sensor
ADC0TK
AD0PWR3
AD0PWR2
AD0PWR1
AD0PWR0
AD0TM1
AD0TM0
AD0TK1
AD0TK0
Burst Mode
Logic
Start
Conversion
Burst Mode
Oscillator
25 MHz Max
SYSCLK
FCLK
P2.2-P2.7, P3.0 available
on 40-pin and 32-pin
packages
P3.1-P3.7 available on 40-
pin packages
00 AD0BUSY (W)
10 CNV S T R In p ut
Timer 2 Overflow11
01 Timer 1 Overflow
12-Bit
SAR
ADC
REF
FCLK
ADC0H
32
ADC0LTH
AD0WINT
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
ADC0CF
GAINEN
AD0RPT0
AD0RPT1
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
AD0POST
AD0PRE
AD0TM1:0
Accumulator
Window
Comp are
Logic
Selectable
Gain
P2.0
P2.7
P3.0
P3.7
ADC0GNLADC0GNH ADC0GNA
C8051F55x/56x/57x
48 Rev. 1.2
6.1. Modes of Operation
In a typical system, ADC0 is configured using the following steps:
1. If a gain adjustment is required, refer to Section “6.3. Selectable Gain” on page 53.
2. Choose the start of conversion source.
3. Choose Normal Mode or Burst Mode operation.
4. If Burst Mode, choose the ADC0 Idle Power State and set the Power-up Time.
5. Choose the tracking mode. Note that Pre-Tracking Mode can only be used with Normal Mode.
6. Calculate the required settling time and set the post co nvert-start tracking time using the AD0TK bits.
7. Choose the repeat count.
8. Choose the output word justification (Right-Justified or Left-Justified).
9. Enable or disable the End of Conversion and Window Comparator Interrupts.
6.1.1. Starting a Conversion
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM1–0) in register ADC0CN. Conversions may be initiated by o ne of th e fol-
lowing:
Writing a 1 to the AD0BUSY bit of register ADC0CN
A rising edge on the CNVSTR input signal (pin P0.1)
A Timer 1 overflow (i.e., timed continuous conversions)
A Timer 2 overflow (i.e., timed continuous conversions)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand.” During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registe rs, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 overflows are used as the conversion source, Low Byte overflows are
used if Timer2 is in 8-bit mode; High byte overflows are used if Timer 2 is in 16-bit mode. See Section
“25. Timers” on page 259 for timer configuration.
Import ant Note Ab out Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.1. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.1 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.1, set to 1 Bit1 in register P0SKIP. See Section “19. Port
Input/Output” on page 169 for details on Port I/O configuration.
6.1.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accu-
rate. ADC0 has three tracking modes: Pre-Tracking, Post-T racking, and Dual-T racking. Pre-T racking Mode
provides the minimum delay between the convert start signal and end of conversion by tracking continu-
ously before the con vert s tart sign al. T his m ode requ ires software management in order to meet minimum
tracking requirements. In Post-Tracking Mode, a programmable tracking time starts after the convert start
signal and is managed by hardware. Dual-Tracking Mode maximizes tracking time by tracking before and
after the convert start signal. Figure 6.2 shows examples of the three tracking modes.
Pre-Tracking M ode is selected when AD0TM is set to 10b. Conversions are started immediately following
the convert start signal. ADC0 is tracking continuously when not performing a conversion. Software must
allow at least the minimum tracking time betwe en each end of co nversion and the next con vert st art signal.
The minimum tracking time must also be met prior to the first convert start signal after ADC0 is enabled.
C8051F55x/56x/57x
Rev. 1.2 49
Post-Tracking Mode is selected when AD0TM is set to 01b. A programmable tracking time based on
AD0TK is started immediately following the convert start signal. Conversions are started after the pro-
grammed tracking time ends. After a conversion is complete, ADC0 does not track the input. Rather, the
sampling capacitor remains disconnected from the input making the input pin high-impedance until the
next convert start signal.
Dual-Tracking Mode is selected when AD0TM is set to 11b. A programmable tracking time based on
AD0TK is started immediately following the convert start signal. Conversions are started after the pro-
grammed tracking time ends. After a conversion is complete, ADC0 tracks continuously until the next con-
version is started.
Depending on the output connected to the ADC input, additional tracking time, more than is specified in
Table 5.9, may be required after changing MUX settings. See the settling time requirements described in
Section “6.2.1. Settling Time Requirements” on page 52.
Figure 6.2. ADC0 Tracking Modes
6.1.3. Timing
ADC0 has a maximum conversion speed specified in Table 5.9. ADC0 is clocked from the ADC0 Subsys-
tem Clock (FCLK). The source of FCLK is selected based on the BURSTEN bit. When BURSTEN is
logic 0, FCLK is derived from the current system clock. When BURSTEN is logic 1, FCLK is derived from
the Burst Mode Oscillator, an independent clock source with a maximum frequency of 25 MHz.
When ADC0 is performing a conversion, it requires a clock source that is typically slower than FCLK. The
ADC0 SAR conversion clock (SAR clock) is a divided version of FCLK. The divide ratio can be configured
using the AD0SC bits in the ADC0CF register. The maximum SAR clock frequency is listed in Table 5.9.
ADC0 can be in one of th ree states at any g iven tim e: tracking, converting, or idle. Tracking time depends
on the tracking mode selected. For Pre-Tracking Mode, tracking is managed by software and ADC0 starts
conversions immediately following the convert start signal. For Post-Tracking and Dual-Tracking Modes,
the tracking time after the convert start signal is equal to the value determined by the AD0TK bits plus 2
FCLK cycles. Tracking is immediately followed by a conversion. The ADC0 conversion time is always 13
SAR clock cycles plus an additional 2 FCLK cycles to start and complete a conversion. Figure 6.3 shows
timing diagrams for a conversion in Pre-Tracking Mode and tracking plus conversion in Post-Tracking or
Dual-Tracking Mode. In this example, repeat coun t is set to one.
Convert Start
Post-Tracking
AD0TM= 01 Track Convert IdleIdle Track Convert..
Pre-Tracking
AD0TM = 10 Track Convert Track C o nv ert ...
Dual-Tracking
AD0TM = 11 Track Convert TrackTrack Track Convert..
C8051F55x/56x/57x
50 Rev. 1.2
Figure 6.3. 12-Bit ADC Tracking Mode Example
6.1.4. Burst Mode
Burst Mode is a powe r saving featur e that allows ADC0 to remain in a very low power state between co n-
versions. When Burst Mode is enabled, ADC0 wakes from a very low power state, accumulates 1, 4, 8, or
16 samples using an internal Burst Mode clock (approximately 25 MHz), then re-enters a very low power
state. Since the Burst Mode clock is independent of the system clock, ADC 0 can pe rform m ultiple conv er-
sions then ente r a very low power state within a single system clock cycle, even if the system clock is slow
(e.g., 32.768 kHz), or suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power state (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down a fter each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each conver t start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wa it the programm able Power-up Time controlled by the AD0 PWR
bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 6.4 shows an example of Burst
Mode Operation with a slow system clock and a repeat count of 4.
Import ant Note: When Bur st Mode is enabled, on ly Post- Tracking and Dual-Tracking modes can be use d.
When Burst Mode is enab led, a single convert star t will initiate a number of conversion s equal to the r epeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
Convert Sta r t
ADC0 State Track
ADC0 State Convert
Time FS1 S2 S12 S13
... F
Time FS1 S2 S12 S13
... F
Convert
FS1 S2 F
Post-Tracking or Dual-Tracking Modes (AD0TK = ‘00')
Pre-Tracking Mode
AD0INT Flag
AD0INT Flag
Key
F
Sn
Equal to one pe rio d of FCLK.
Each Sn is equal to one period of the SAR clock.
C8051F55x/56x/57x
Rev. 1.2 51
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
Note: When using Burst Mode, care must be taken to issue a convert start signal no faster than once every four
SYSCLK periods. This includes external convert start signals.
Figure 6.4. 12-Bit ADC Burst Mode Example With Repeat Count Set to 4
Track..
System Clock
Convert Start
(AD0BUSY or Timer
Overflow)
Post-Tracking
AD0TM = 01
AD0EN = 0
Powered
Down Powered
Down
T C
Power-Up
and Idle T C T C T C Power-Up
and Idle TC..
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down Powered
Down
T C
Power-Up
and Track T C T C T C Power-Up
and Track TC..
AD0PWR
Post-Tracking
AD0TM = 01
AD0EN = 1 Idle IdleT C T C T C T C T C..
Dual-Tracking
AD0TM = 11
AD0EN = 1 Track TrackT C T C T C T C T C..
T C T C
T C T C
T = Tracking
C = Converting
Convert Start
(CNVSTR)
Post-Tracking
AD0TM = 01
AD0EN = 0
Powered
Down Powered
Down
T C
Power-Up
and Idle Power-Up
and Idle TC..
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down Powered
Down
T C
Power-Up
and Track Power-Up
and Track TC..
AD0PWR
Post-Tracking
AD0TM = 01
AD0EN = 1 Idle IdleT C
Dual-Tracking
AD0TM = 11
AD0EN = 1 Track TrackT C T C
T C
T = Tracking
C = Converting
Idle..
C8051F55x/56x/57x
52 Rev. 1.2
6.2. Output Code Formatting
The registers ADC0H and ADC0L cont ain the high and low bytes of the output conversion code. When the
repeat count is set to 1, conversion codes are rep resented in 12-bit un signed integ er format an d the outp ut
conversion code is updated after each conversion. In pu ts are measured from 0 to VREF x 4095/4096. Data
can be right-justified or left-justified, depending on the setting of the AD0LJST bit (ADC0CN.2). Unused
bits in the ADC0H and ADC0L registers are set to 0. Example codes are shown below for both right-justi-
fied and left-justified data.
When the ADC0 Repe at Count is greate r than 1, the output conversion code represents the accumula ted
result of the conversions performed and is updated after the last conversion in the series is finished. Sets
of 4, 8, or 1 6 consecutive samples c an be accumulated an d represented in u nsigned integer form at. The
repeat count can be selected using the AD0RPT bits in th e ADC0CF registe r. T he va lu e mu st be r igh t- jus -
tified (AD0LJST = 0), and unused bits in the ADC0H and ADC0L registers are set to 0. The following
example shows right-justified codes for repeat counts greater than 1. Notice that accumulating 2n samples
is equivalent to left-shifting by n bit positions when all samples returned from the ADC have the same
value.
6.2.1. Settling Ti me Requirements
A minimum tracking time is required before an accurate conversion is performed. This tracking time is
determined by any series impedance, including the AMUX0 resistance, the ADC0 sampling capacitance,
and the accuracy required for the conversion.
Figure 6.5 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 6.1. When measuring the Temperature Sensor output,
use the settling time specified in Table 5.10. When measuring VDD with respect to GND, RTOTAL reduces to
RMUX. See Table 5.9 for ADC0 minimum settling time requirements as well as the mux impedance and
sampling capacitor values.
Equation 6.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB).
t is the required settling time in seconds. RTOTAL is the sum of the AMUX0 resistance and any external
source resistance. n is the ADC resolution in bits (10).
Input Voltage Right-Justified ADC0H:ADC0L
(AD0LJST = 0) L e ft-Justified ADC 0H: A D C0L
(AD0LJST = 1)
VREF x 4095/4096 0x0FFF 0xFFF0
VREF x 2048/4096 0x0800 0x8000
VREF x 2047/4096 0x07FF 0x7FF0
00x0000 0x0000
Input Voltage Repeat Count = 4 Repeat Count = 8 Repeat Count = 16
VREF x 4095/4096 0x3FFC 0x7FF8 0xFFF0
VREF x 2048/4096 0x2000 0x4000 0x8000
VREF x 2047/4096 0x1FFC 0x3FF8 0x7FF0
00x0000 0x0000 0x0000
t2n
SA
--------
RTOTALCSAMPLE
×ln=
C8051F55x/56x/57x
Rev. 1.2 53
Figure 6.5. ADC0 Equivalent Input Circuit
6.3. Selectable Gain
ADC0 on the C8051F55x/56x/57x family of devices implements a selectable gain adjustment option. By
writing a value to the gain adjust address range, the user ca n select gain values between 0 and 1.016.
For example, three analog sources to be measured have full-scale outputs of 5.0 V, 4.0 V, and 3.0 V,
respectively. Each ADC measurement would ideally use the full dynamic rang e of the ADC with an inte rna l
voltage reference of 1.5 V or 2.2 V (set to 2.2 V for this example). When selecting the first source (5.0 V
full-scale), a gain value of 0. 44 (5 V full scale x 0.44 = 2.2 V full scale) provides a full- scale sign al of 2.2 V
when the input signal is 5.0 V. Likewise, a gain value of 0.55 (4 V full scale x 0.55 = 2.2 V full scale) for the
second source and 0.73 (3 V full scale x 0.73 = 2.2 V full scale) for the third source provide full-scale ADC0
measurement s when the input signal is full-scale.
Additionally, some sensors or other input sources have small part-to-part variations that must be
accounted for to achieve accurate results. In this case, the programmable gain value could be used as a
calibration value to eliminate these part-to-part variations.
6.3.1. Calculating the Gain Value
The ADC0 selectable gain feature is controlled by 13 bits in three registers. ADC0GNH contains the 8
upper bits of the gain value and ADC0GNL contains the 4 lower bits of the gain value. The final GAINADD
bit (ADC0GNA.0) controls an optional extra 1/64 (0.016) of gain that can be added in addition to the
ADC0GNH and ADC0G NL ga in . The ADC0 GN A.0 bit is set to 1 after a power- on reset .
The equivalent gain for the ADC0GNH, ADC0GNL and ADC0GNA registers is as follows:
Equation 6.2. Equivalent Gain from the ADC0GNH and ADC0GNL Registers
Where:
GAIN is the 12-bit word of ADC0GNH[7:0] and ADC0GNL[7:4]
GAINADD is the value of the GAINADD bit (ADC0GNA.0)
gain is the equivalent gain value from 0 to 1.016
RMUX
CSAMPLE
RCInput= RMUX * C SAMPLE
M UX Select
Px.x
gain GAIN
4096
---------------
GAINADD 1
64
------
×+=
C8051F55x/56x/57x
54 Rev. 1.2
For example, if ADC0GNH = 0xFC, ADC0GNL = 0x00, and GAINADD = 1, GAIN = 0xFC0 = 4032, and the
resulting equatio n is as follow s:
The table below equates values in the ADC0GNH, ADC0GNL, and ADC0GNA registers to the equivalent
gain using this equation.
For any desired gain value, the GAIN registers can be calculated by the following:
Equation 6.3. Calculating the ADC0GNH and ADC0GNL Va lues from the Desired Gain
Where:
GAIN is the 12-bit word of ADC0GNH[7:0] and ADC0GNL[7:4]
GAINADD is the value of the GAINADD bit (ADC0GNA.0)
gain is the equivalent gain value from 0 to 1.016
When calculating the value of GAIN to load in to the ADC0GNH and ADC0GNL registers, the GAINADD bit
can be turned on or off to reach a value closer to the desired gain value.
For example, the initial example in this section requ ires a gain of 0.4 4 to convert 5 V full scale to 2.2 V full
scale. Using Equation 6.3:
If GAINADD is set to 1, this makes the equation:
The actual gain from setting GAINADD to 1 and ADC0GNH and ADC0GNL to 0x6CA is 0.4399. A similar
gain can be achieved if GAINADD is set to 0 with a different value for ADC0GNH and ADC0GNL.
ADC0GNH Value ADC0GNL Value GAINADD Value GAIN Value Equivalent Gain
0xFC (default) 0x00 (default) 1 (default) 4032 + 64 1.0 (default)
0x7C 0x00 1 1984 + 64 0.5
0xBC 0x00 1 3008 + 64 0.75
0x3C 0x00 1 960 + 64 0.25
0xFF 0xF0 0 4095 + 0 ~1.0
0xFF 0xF0 1 4096 + 64 1.016
GAIN 4032
4096
-------------
11
64
------
×
+0.984 0.016+1.0===
GAIN gain GAINADD 1
64
------
×–
4096×=
GAIN 0.44 GAINADD 1
64
------
×–
4096×=
GAIN 0.44 1 1
64
------
×–
4096×0.424 4096×1738 0x06CA====
C8051F55x/56x/57x
Rev. 1.2 55
6.3.2. Setting the Gain Value
The three programmable gain registers are accessed indirectly using the ADC0H and ADC0L registers
when the GAINEN bit (ADC0CF.0) bit is set. ADC0H acts as the address register, and ADC0L is the data
register. The programmable gain registers can only be written to and cannot be read. See Gain Register
Definition 6.1, Gain Register Definition 6.2, and Gain Register Definition 6.3 for more information.
The gain is programmed using the following steps:
1. Set the GAINEN bit (ADC0CF.0)
2. Load the ADC0H with the ADC0GNH, ADC0GNL, or ADC0GNA address.
3. Load ADC0L with the desired value for the selected gain register.
4. Reset the GAINEN bit (ADC0CF.0)
Notes:
1. An ADC conversion should not be performed while the GAINEN bit is set.
2. Even with gain enabled, the maximum input voltage must be less than VREGIN and the maximum
voltage of the signal after gain must be less than or equal to VREF.
In code, changing the value to 0.44 gain from the previous example looks like:
// in ‘C’:
ADC0CF |= 0x01; // GAINEN = 1
ADC0H = 0x04; // Load the ADC0GNH address
ADC0L = 0x6C; // Load the upper byte of 0x6CA to ADC0GNH
ADC0H = 0x07; // Load the ADC0GNL address
ADC0L = 0xA0; // Load the lower nibble of 0x6CA to ADC0GNL
ADC0H = 0x08; // Load the ADC0GNA address
ADC0L = 0x01; // Set the GAINADD bit
ADC0CF &= ~0x01; // GAINEN = 0
; in assembly
ORL ADC0CF,#01H ; GAINEN = 1
MOV ADC0H,#04H ; Load the ADC0GNH address
MOV ADC0L,#06CH ; Load the upper byte of 0x6CA to ADC0GNH
MOV ADC0H,#07H ; Load the ADC0GNL address
MOV ADC0L,#0A0H ; Load the lower nibble of 0x6CA to ADC0GNL
MOV ADC0H,#08H ; Load the ADC0GNA address
MOV ADC0L,#01H ; Set the GAINADD bit
ANL ADC0CF,#0FEH ; GAINEN = 0
C8051F55x/56x/57x
56 Rev. 1.2
Indirect Address = 0x04;
Indirect Address = 0x07;
Gain Register Definition 6.1. ADC0GNH: ADC0 Selectable Gain High Byte
Bit76543210
Name GAINH[7:0]
Type W
Reset 11111100
Bit Name Function
7:0 GAINH[7:0] ADC0 Gain High Byte.
See Section 6.3.1 for details on calculating the value for this register.
Note: This register is accessed indirectly; See Section 6.3.2 for details for writing this register.
Gain Register Definition 6.2. ADC0GNL: ADC0 Selectable Gain Low Byte
Bit76543210
Name GAINL[3:0] Reserved Reserved Reserved Reserved
Type W W W W W
Reset 00000000
Bit Name Function
7:4 GAINL[3:0] ADC0 Gain Lower 4 Bits.
See Figure 6.3.1 for details for setting this register.
This register is only accessed indirectly through the ADC0H and ADC0L register.
3:0 Reserved Must Write 0000b
Note: This register is accessed indirectly; See Section 6.3.2 for details for writing this register.
C8051F55x/56x/57x
Rev. 1.2 57
Indirect Address = 0x08;
Gain Register Definition 6.3. ADC0GNA: ADC0 Additional Selectable Gain
Bit76543210
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved GAINADD
Type WWWWWWWW
Reset 00000001
Bit Name Function
7:1 Reserved Must Write 0000000b.
0GAINADD ADC0 Additional Gain Bit.
Setting this bit add 1/64 (0.016) gain to the gain value in the ADC0GNH and
ADC0GNL registers.
Note: This register is accessed indirectly; See Section 6.3.2 for details for writing this register.
C8051F55x/56x/57x
58 Rev. 1.2
SFR Address = 0xBC; SFR Page = 0x00
SFR Definition 6.4. ADC0CF: ADC0 Configuration
Bit76543210
Name AD0SC[4:0] AD0RPT[1:0] GAINEN
Type R/W R/W R/W R/W
Reset 11111000
Bit Name Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clo c k by the following eq uatio n, wher e
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table
BURSTEN = 0: FCLK is the current system clock
BURSTEN = 1: FCLK is a maximum of 30 MHz, independent of the current system
clock..
Note: Round up the result of the calculation for AD0SC
2:1 A0RPT[1:0] ADC0 Repeat Count.
Controls the number of conver sions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A con-
vert start is required for each conversion unless Burst Mode is enabled. In Burst
Mode, a single convert start can initiate multiple self-timed conversions. Results in
both modes are a ccumulated in the ADC0H:ADC0L register. When AD0RPT1–0 are
set to a value other than '00', the AD0LJST bit in the ADC0CN register must be
set to '0' (right just ifi ed ) .
00: 1 conversi on is per fo rm ed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
0GAINEN Gain Enable Bit.
Controls the gain progr amming. Refer to Section “6.3. Selectable Gain” on page 53
for information about using this bit.
AD0SC FCLK
CLKSAR
-------------------- 1–=
C8051F55x/56x/57x
Rev. 1.2 59
SFR Address = 0xBE; SFR Page = 0x00
SFR Address = 0xBD; SFR Page = 0x00
SFR Definition 6.5. ADC0H: ADC0 Data Word MSB
Bit76543210
Name ADC0H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits.
For AD0LJST = 0 and AD0RPT as follows:
00: Bits 3–0 are the upper 4 bits of the 12-bit result. Bits 7–4 are 0000b.
01: Bits 4–0 are the upper 5 bits of the 14-bit result. Bits 7–5 are 000b.
10: Bits 5–0 are the upper 6 bits of the 15-bit result. Bits 7–6 are 00b.
11: Bits 7–0 are the upper 8 bits of the 16-bit result.
For AD0LJST = 1 (AD0RPT must be 00): Bits 7–0 are the most-significant bits of the
ADC0 12-bit result.
SFR Definition 6.6. ADC0L: ADC0 Data Word LSB
Bit76543210
Name ADC0L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0L[7:0] ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the ADC0 Accumulated Result.
For AD0LJST = 1 (AD0RPT must be '00'): Bits 7–4 are the lower 4 bits of the 12-bit
result. Bits 3–0 are 0000b.
C8051F55x/56x/57x
60 Rev. 1.2
SFR Address = 0xE8; SFR Page = 0x00; Bit-Addressable
SFR Definition 6.7. ADC0CN: ADC0 Control
Bit76543210
Name AD0EN BURSTEN AD0INT AD0BUSY AD0WINT AD0LJST AD0CM[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7AD0EN ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
6BURSTEN ADC0 Burst Mode Enable Bit.
0: Burst Mode Disabled.
1: Burst Mode Enabled.
5AD0INT ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a da ta conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
4AD0BUSY ADC0 Busy Bit. Read:
0: ADC0 conversion is not
in progress.
1: ADC0 conversion is in
progress.
Write:
0: No Effect.
1: Initiates ADC0 Conver-
sion if AD0CM[1:0] = 00b
3AD0WINT ADC0 Window Compare Interrupt Flag.
This bit must be cleared by software
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
2AD0LJST ADC0 Left Justify Select Bit.
0: Data in ADC0H:ADC0L registers is right-justified
1: Data in ADC0H:ADC0L registers is left-justified. This option should not be used
with a repeat count greater than 1 (when AD0RPT[1:0] is 01b, 10b, or 11b).
1:0 AD0CM[1:0] ADC0 Start of Conversion Mode Select.
00: ADC0 start-of-conversion source is write of 1 to AD0BUSY.
01: ADC0 start-of-conversion source is overflo w of Timer 1.
10: ADC0 start-of-conversion source is rising edge of external CNVSTR.
11: ADC0 start-of-conversion source is overflow of Timer 2.
C8051F55x/56x/57x
Rev. 1.2 61
SFR Address = 0xBA; SFR Page = 0x00
6.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limit s, and notifies the system whe n a desired co ndition is dete cted. This is especially ef fective i n
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comp arison values. The window detector flag can be programmed to in dicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Definition 6.8. ADC0TK: ADC0 Tracking Mode Select
Bit76543210
Name AD0PWR[3:0] AD0TM[1:0] AD0TK[1:0]
Type R/W R/W R/W
Reset 11111111
Bit Name Function
7:4 AD0PWR[3:0] ADC0 Burst Power-up Time.
For BURSTEN = 0: ADC0 Power state controlled by AD0EN
For BURSTEN = 1, AD0EN = 1: ADC0 remains enabled and does not enter the
very low power state
For BURSTEN = 1, AD0EN = 0: ADC0 enters the very low power state and is
enabled after each convert start signal. The Power-up time is programmed accord-
ing the following equation:
or
3:2 AD0TM[1:0] ADC0 Tracking Mode Enable Select Bits.
00: Reserved.
01: ADC0 is configured to Post-Tracking Mode.
10: ADC0 is configured to Pre-Tracking Mode.
11: ADC0 is configured to Dual Tracking Mode.
1:0 AD0TK[1:0] ADC0 Post-Trac k Time.
00: Post-Tracking time is equal to 2 SAR clock cycles + 2 FCLK cycles.
01: Post-Tracking time is equal to 4 SAR clock cycles + 2 FCLK cycles.
10: Post-Tracking time is equal to 8 SAR clock cycles + 2 FCLK cycles.
11: Post-Tracking time is equal to 16 SAR clock cycles + 2 FCLK cycles.
AD0PWR Tstartup
200ns
------------------------ 1–=
Tstartup AD0PWR 1+()200ns=
C8051F55x/56x/57x
62 Rev. 1.2
SFR Address = 0xC4; SFR Page = 0x00
SFR Address = 0xC3; SFR Page = 0x00
SFR Definition 6.9. ADC0GTH: ADC0 Greater-Than Data High Byte
Bit76543210
Name ADC0GTH[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits.
SFR Definition 6.10. ADC0GTL: ADC0 Greater-Than Data Low Byte
Bit76543210
Name ADC0GTL[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 ADC0GTL[7:0] ADC0 Greater-Than Data Word Low-Order Bits .
C8051F55x/56x/57x
Rev. 1.2 63
SFR Address = 0xC6; SFR Page = 0x00
SFR Address = 0xC5; SFR Page = 0x00
6.4.1. Window Detector In Single-Ended Mode
Figure 6.6 shows two example window comparisons for right-justified data with
ADC0LTH:ADC0LTL = 0x0200 (512d) and ADC0GTH:ADC0GTL = 0x0100 (256d). The input voltage can
range from 0 to VREF x (4095/4096) with respect to GND, and is represented by a 12-bit unsigned integer
value. The repeat count is set to one. In the left example, an AD0WINT interrupt will be generated if the
ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if 0x0100 < ADC0H:ADC0L < 0x0200). In the right example, and AD0WINT interrupt
will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and
ADC0LT registers (if ADC0H:ADC0L < 0x0100 or ADC0H:ADC0L > 0x0200). Figure 6.7 shows an exam-
ple using left-justified data with the same comparison values.
SFR Definition 6.11. ADC0LTH: ADC0 Less-Than Data High Byte
Bit76543210
Name ADC0LTH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits.
SFR Definition 6.12. ADC0LTL: ADC0 Less-Than Data Low Byte
Bit76543210
Name ADC0LTL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0LTL[7:0] ADC0 Less-Tha n Data Word Low-Order Bits.
C8051F55x/56x/57x
64 Rev. 1.2
Figure 6.6. ADC Window Compare Example: Right-Justified Data
Figure 6.7. ADC Window Compare Example: Left-Justified Data
0x0FFF
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (4095/4096)
VREF x (512/4096)
VREF x (256/4096)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0x0FFF
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/
1024)
VREF x (512/4096)
VREF x (256/4096)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0xFFF0
0x2010
0x2000
0x1FF0
0x1010
0x1000
0x0FF0
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (4095/4096)
VREF x (512/4096)
VREF x (256/4096)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0xFFF0
0x2010
0x2000
0x1FF0
0x1010
0x1000
0x0FF0
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (4095/4096)
VREF x (512/4096)
VREF x (256/4096)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
C8051F55x/56x/57x
Rev. 1.2 65
6.5. ADC0 Analog Multiplexer
ADC0 includes an analog multiplexer to enable multiple analog input sources. Any of the following may be
selected as an input: P0.0–P3.7, the on-chip temperature sensor, the core power supply (VDD), or grou nd
(GND). ADC0 is single-ended and all signals measured are with respect to GND. The ADC0 input
channels are selected using the ADC0MX register as described in SFR Definition 6.13.
Figure 6.8. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to 1
the corresponding bit in register PnSKIP. See Section “19. Port Input/Output” on page 169 for more Port
I/O configuration details.
ADC0
Temp
Sensor
AMUX
VDD
ADC0MX
ADC0MX5
ADC0MX4
ADC0MX3
ADC0MX2
ADC0MX1
ADC0MX0
P0.0
P2.2-P2.7, P3.0 available as
inputs on 40-pin and 32-pin
packages
P3.1-P3.7 available as inputs on
48-pin and 40-pin packages
GND
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
C8051F55x/56x/57x
66 Rev. 1.2
SFR Address = 0xBB; SFR Page = 0x00;
SFR Definition 6.13. ADC0MX: ADC0 Channel Select
Bit76543210
Name ADC0MX[5:0]
Type R R R/W
Reset 00111111
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care.
5:0 AMX0P[5:0] AMUX0 Positive Input Selection.
000000: P0.0
000001: P0.1
000010: P0.2
000011: P0.3
000100: P0.4
000101: P0.5
000110: P0.6
000111: P0.7
001000: P1.0
001001: P1.1
001010: P1.2
001011: P1.3
001100: P1.4
001101: P1.5
001110: P1.6
001111: P1.7
010000: P2.0
010001: P2.1
010010: P2.2 (Only available on 40-pin and 32-pin package devices)
010011: P2.3 (Only available on 40-pin and 32-pin package devices)
010100: P2.4 (Only available on 40-pin and 32-pin package devices)
010101: P2.5 (Only available on 40-pin and 32-pin package devices)
010110: P2.6 (Only available on 40-pin and 32-pin package devices)
010111: P2.7 (Only available on 40-pin and 32-pin package devices)
011000: P3.0 (Only available on 40-pin and 32-pin package devices)
011001: P3.1 (Only available on 40-pin package devices)
011010: P3.2 (Only available on 40-pin package devices)
011011: P3.3 (Only available on 40-pin package devices)
011100: P3.4 (Only available on 40-pin package devices)
011101: P3.5 (Only available on 40-pin package devices)
011110: P3.6 (Only available on 40-pin package devices)
011111: P3.7 (Only available on 40-pin package devices)
100000–101111: Reserved
110000: Temp Sensor
110001: VDD
110010–111111: GND
C8051F55x/56x/57x
Rev. 1.2 67
6.6. Temperature Sensor
An on-chip temperature sensor is included on the C8051F55x/56x/57x devices which can be directly
accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the tempera-
ture sensor, the ADC multiplexer channel should be configured to connect to the temperature sensor. The
temperature sensor transfer function is shown in Figure 6.9. The output voltage (VTEMP) is the positive
ADC input is selected by bits AD0MX[4:0] in register ADC0MX. The TEMPE bit in register REF0CN
enables/disables the temperat ure sensor, as described in SFR Definition 7.1 . Wh ile disabl ed, the tem per a-
ture sensor defaults to a high impedance state and any ADC measurements performed on the sensor will
result in meaningless dat a. Re fer to Table 5.10 for the slope and of fset parameters of the temperature sen-
sor.
Figure 6.9. Temperature Sensor Transfer Function
Temperature
Voltage
VTEMP = (Slope x TempC) + Offset
Offset (V at 0 Celsius)
Slope (V / deg C)
TempC = (VTEMP - Offset) / Slope
C8051F55x/56x/57x
Rev. 1.2 68
7. Voltage Reference
The Voltage reference multiplexer on the C8051F55x/56x/57x devices is configurable to use an externally
connected voltage reference, the on-chip reference voltage generator routed to the VREF pin, or the VDD
power supply voltage (see Figure 7.1). The REFSL bit in the Reference Control register (REF0CN, SFR
Definition 7.1) selects the reference source for the ADC. For an external source or the on-chip reference,
REFSL should be set to 0 to select the VREF pin. To use VDD as the reference source, REFSL should be
set to 1.
The BIASE bit enables the internal voltage bi as generator, which is used by the ADC, Temperature Sensor,
and internal oscillator. This bias is automatically enabled when any peripheral which requires it is enabled,
and it does not need to be enabled manually. The bias generator may be enabled manually by writing a 1
to the BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given
in Table 5.11.
The on-chip voltage reference circuit consists of a temperature stable bandgap voltage reference genera-
tor and a gain-of-two output buffer amplifier. The output voltage is selectable between 1.5 V and 2.25 V.
The on-chip volt age reference can be d riven on the VREF pin by setting the REF BE bit in register REF0CN
to a 1. The maximum load seen by the VREF pin must be less than 200 µA to GND. Bypass capacitors of
0.1 µF and 4.7 µF are recommended from the VREF pin to GND. If the on-chip reference is not used, the
REFBE bit should be cleared to 0. Electrical specifications for the on-chip voltage reference are given in
Table 5.11.
Important Note about the VREF Pin: When using either an external voltage reference or the on-chip ref-
erence circuitry, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar.
Refer to Section “19. Port Input/Output” on page 169 for the location of the VREF pin, as well as details of
how to configure the pin in analog mode and to be skipped by the crossbar. If VDD is selected as the volt-
age reference in the REF0CN register and th e ADC is enabled in the ADC0CN register, the P0.0/VREF pin
cannot operate as a general purpose I/O pin in open-drain mode. With the above settings, this pin can
operate in push-pull output mode or as an analog input.
Figure 7.1. Voltage Reference Functional Block Diagram
VREF
(to ADC)
To Analog Mux
VDD
VREF
R1
VDD External
Voltage
Reference
Circuit
GND
Temp Sensor
EN
Bias Generator To A DC, In te rn a l
Oscillators
EN
IOSCE
N
0
1
REF0CN
REFSL
TEMPE
BIASE
REFBE
REFBE
Intern al
Reference
EN
Recomm ended B ypass
Capacitors
+
4.7μF0.1μF
C8051F55x/56x/57x
69 Rev. 1.2
SFR Address = 0xD1; SFR Page = 0x00
SFR Definition 7.1. REF0CN: Reference Control
Bit76543210
Name ZTCEN REFLV REFSL TEMPE BIASE REFBE
Type RRRRR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:6 Unused Read = 00b; Write = don’t care.
5ZTCEN Zero Te mpera tu re Co ef fi cie n t Bia s Enab le Bit.
This bit must be set to 1b before entering oscillator suspend mode.
0: ZeroTC Bias Generator au tomatically enabled when required.
1: ZeroTC Bias Generator forced on.
4REFLV Voltage Reference Output Level Select.
This bit selects the output voltage level for the internal voltage reference
0: Internal voltage reference set to 1.5 V.
1: Internal voltage reference set to 2.20 V.
3REFSL Voltage Reference Select.
This bit selects the ADCs voltage reference.
0: VREF pin used as voltage reference.
1: VDD used as voltage reference. If VDD is selected as the voltage referenc e an d th e
ADC is enabled in the ADC0CN register, the P0.0/VREF pin cannot operate as a gen-
eral purpose I/O pin in open-drain mode. With the above settings, this pin can operate
in push-pull output mode or as an analog input.
2TEMPE Temperature Sensor Enable Bit.
0: Internal Tem p er at ur e Se nso r off.
1: Internal Tem p er at ur e Se nso r on.
1BIASE Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
0REFBE On-chip Reference Buffer Enable Bit.
0: On-chip Reference Buffer off.
1: On-chip Reference Buffer on. Internal voltage re ference driven on the VREF pin.
C8051F55x/56x/57x
Rev. 1.2 70
8. Comparators
The C8051F55x/56x/57x devices include two on-chip programmable voltage Comparators. A block dia-
gram of the comparators is shown in Figure 8.1, where “n” is the comparator number (0 or 1). The two
Comparators operate identically except that Comparator0 can also be used a reset source. For input
selection details, refer to SFR Definition 8.5 and SFR Definition 8.6.
Each Comp arator of fers p rogrammable re sponse time a nd hysteresis, an an alog input multip lexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system
clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “19.4. Port I/O Initialization” on page 174). Comparator0 may also be used as a
reset source (see Section “16.5. Comparator0 Reset” on page 142) .
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 8.5). The CMX0P1-CMX0P0
bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative
input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 8.6). The CMX1P1-
CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the Comparator1
negative input.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs in their associated Port configuration r egi ster, and configured to be skippe d by the
Crossbar (for details on Port configuration, see Section “19.1. Port I/O Modes of Operation” on page 170).
Figure 8.1. Comparator Functional Block Diagram
VIO
Reset
Decision
Tree
+
- Crossbar
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CPn +
CPn -
CPTnMD
CPnRIE
CPnFIE
CPnMD1
CPnMD0
CPn
CPnA
CPn
Interrupt
0
1
0
1
CPnRIF
CPnFIF
0
1
CPnEN 0
1
EA
Comparator
Input Mux
CPTnCN
CPnEN
CPnOUT
CPnRIF
CPnFIF
CPnHYP1
CPnHYP0
CPnHYN1
CPnHYN0
C8051F55x/56x/57x
71 Rev. 1.2
Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Compar ator output ( if assigne d to a Port I/O pin via the Cr ossbar ) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “19.3. Priority Crossbar Decoder” on
page 172 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comp arator elec-
trical specifications are given in Table 5.12.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Defini-
tion 8.2). Selecting a longer response time reduces the Comparator supply current. See Table 5.12 for
complete timing and supply current requirements.
Figure 8.2. Comparator Hysteresis Plot
Comparator hyste resis is software-progr ammable via its Comparator Control register CPTnCN.
The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits. As shown in
Figure 8.2, various levels of negative hysteresis can be programmed, or negative hysteresis can be dis-
abled. In a similar way, the amount of positive hysteresis is determined by the setting the CPnHYP bits.
Compara tor interrup ts can be generated on both rising-edge and falling-edge output tran sition s. (Fo r Inte r-
rupt enable and priority control, see “13. Interrupts” .) The CPnFIF flag is set to 1 upon a Comparator fall-
ing-edge, and the CPnRIF flag is set to 1 upon the Comparator rising-edge. Once set, these bits remain
set until cleared by software. The output state of the Comparator can be obtained at any time by reading
the CPnOUT bit. The Comparator is enabled by setting th e CPnEN b it to 1, and is disab led by clea ring this
bit to 0.
Positive Hysteresis Voltage
(Programmed with CPnHYP Bits)
Negative Hysteresis Voltage
(Programmed by CPnHYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CPn+
CPn- CPn
VIN+
VIN- OUT
VOH
Positive Hysteresis
Disabled Maximum
Positive Hysteresis
Negative Hysteresis
Disabled Maximum
Negative Hysteresis
OUTPUT
VOL
C8051F55x/56x/57x
Rev. 1.2 72
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed.
SFR Address = 0x9A; SFR Page = 0x00
SFR Definition 8.1. CPT0CN: Comparator0 Control
Bit76543210
Name CP0EN CP0OUT CP0RIF CP0FIF CP0HYP[1:0] CP0HYN[1:0]
Type R/W RR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CP0EN Comparator0 Enable Bit.
0: Comparator0 Disab led .
1: Comparator0 Enab led.
6CP0OUT Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
5CP0RIF Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator 0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4CP0FIF Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling- E d ge has occurr ed .
3:2 CP0HYP[1:0] Comparator0 Positive Hys teresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
C8051F55x/56x/57x
73 Rev. 1.2
SFR Address = 0x9B; SFR Page = 0x00
SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection
Bit76543210
Name CP0RIE CP0FIE CP0MD[1:0]
Type R R R/W R/W R R R/W
Reset 00000010
Bit Name Function
7:6 Unused Read = 00b, Write = Don’t Care.
5CP0RIE Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4CP0FIE Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2 Unused Read = 00b, Write = don’t care.
1:0 CP0MD[1:0] Comparator0 Mode Select.
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
C8051F55x/56x/57x
Rev. 1.2 74
SFR Address = 0x9D; SFR Page = 0x00
SFR Definition 8.3. CPT1CN: Comparator1 Control
Bit76543210
Name CP1EN CP1OUT CP1RIF CP1FIF CP1HYP[1:0] CP1HYN[1:0]
Type R/W RR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CP1EN Comparator1 Enable Bit.
0: Comparator1 Disab led .
1: Comparator1 Enab led.
6CP1OUT Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
5CP1RIF Comparator1 Rising-Edge Flag. Must be cleared by software.
0: No Comparator 1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
4CP1FIF Comparator1 Falling-Edge Flag. Must be cleared by software.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling- E d ge has occurr ed .
3:2 CP1HYP[1:0] Comparator1 Positive Hys teresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
C8051F55x/56x/57x
75 Rev. 1.2
SFR Address = 0x9E; SFR Page = 0x00
SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection
Bit76543210
Name CP1RIE CP1FIE CP1MD[1:0]
Type R R R/W R/W R R R/W
Reset 00000010
Bit Name Function
7:6 Unused Read = 00b, Write = Don’t Care.
5CP1RIE Comparator1 Rising-Edge Interrupt Enable.
0: Comparator1 Rising-edge interrupt disabled.
1: Comparator1 Rising-edge interrupt enabled.
4CP1FIE Comparator1 Falling-Edge Interrupt Enable.
0: Comparator1 Falling-edge interrupt disabled.
1: Comparator1 Falling-edge interrupt enabled.
3:2 Unused Read = 00b, Write = don’t care.
1:0 CP1MD[1:0] Comparator1 Mode Select.
These bits affect the response time and power consumption for Comparator1.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
C8051F55x/56x/57x
Rev. 1.2 76
8.1. Comparator Multiplexer
C8051F55x/56x/57x devices include an analog input multiplexer for each of the comparators to connect
Port I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR
Definition 8.5). The CMX0P3–CMX0P0 bits select the Comparator0 positive input; the CMX0N3–CMX0N0
bits select the Comparator0 negative input. Similarly, the Comparator1 inputs are selected in the CPT1MX
register using the CMX1P3-CMX1P0 bit s and CMX1N3–C MX1N0 bits . The same pins are available to both
multiplexers at the same time and can be used by both comparators simultane ously.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration r egi ster, and configured to be skippe d by the
Crossbar (for details on Port configuration, see Section “19.6. Special Function Registers for Accessing
and Configuring Port I/O” on page 183).
Figure 8.3. Comparator Input Multiplexer Block Diagram
VDD
+
-
GND
CPn +
CPn -
P0.1
P0.3
P0.5
P0.7
CPTnMX
CMXnN3
CMXnN2
CMXnN1
CMXnN0
CMXnP3
CMXnP2
CMXnP1
CMXnP0
P1.1
P1.3
P1.5
P1.7
P2.1
P2.3
P2.5
P2.7
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P2.0
P2.2
P2.4
P2.6
C8051F55x/56x/57x
77 Rev. 1.2
SFR Address = 0x9C; SFR Page = 0x00
SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection
Bit76543210
Name CMX0N[3:0] CMX0P[3:0]
Type R/W R/W
Reset 01110111
Bit Name Function
7:4 CMX0N[3:0] Comparator0 Negative Input MUX Selection.
0000: P0.1
0001: P0.3
0010: P0.5
0011: P0.7
0100: P1.1
0101: P1.3
0110: P1.5
0111: P1.7
1000: P2.1
1001: P2.3 (only available on 40-pin and 32-pin devices)
1010: P2.5 (only available on 40-pin and 32-pin devices)
1011: P2.7 (only available on 40-pin and 32-pin devices)
1100–1111: None
3:0 CMX0P[3:0] Comparator0 Positive Input MUX Selection.
0000: P0.0
0001: P0.2
0010: P0.4
0011: P0.6
0100: P1.0
0101: P1.2
0110: P1.4
0111: P1.6
1000: P2.0
1001: P2.2 (only available on 40-pin and 32-pin devices)
1010: P2.4 (only available on 40-pin and 32-pin devices)
1011: P2.6 (only available on 40-pin and 32-pin devices)
1100–1111: None
C8051F55x/56x/57x
Rev. 1.2 78
SFR Address = 0x9F; SFR Page = 0x00
SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection
Bit76543210
Name CMX1N[3:0] CMX1P[3:0]
Type R/W R/W
Reset 01110111
Bit Name Function
7:4 CMX1N[3:0] Comparator1 Negative Input MUX Selection.
0000: P0.1
0001: P0.3
0010: P0.5
0011: P0.7
0100: P1.1
0101: P1.3
0110: P1.5
0111: P1.7
1000: P2.1
1001: P2.3 (only available on 40-pin and 32-pin devices)
1010: P2.5 (only available on 40-pin and 32-pin devices)
1011: P2.7 (only available on 40-pin and 32-pin devices)
1100–1111: None
3:0 CMX1P[3:0] Comparator1 Positive Input MUX Selection.
0000: P0.0
0001: P0.2
0010: P0.4
0011: P0.6
0100: P1.0
0101: P1.2
0110: P1.4
0111: P1.6
1000: P2.0
1001: P2.2 (only available on 40-pin and 32-pin devices)
1010: P2.4 (only available on 40-pin and 32-pin devices)
1011: P2.6 (only available on 40-pin and 32-pin devices)
1100–1111: None
C8051F55x/56x/57x
Rev. 1.2 79
9. Voltage Regulator (REG0)
C8051F55x/56x/57x devices include an on-chip low dropout voltage regulator (REG0). The input to REG0
at the VREGIN pin can be as high as 5. 25 V. The output can be selected b y softwar e to 2.1 V or 2.6 V. When
enabled, the output of REG0 appears on th e VDD pin, powers the microcontroller core, and can be used to
power external devices. On reset, REG0 is enabled and can be disabled by soft ware.
The Voltage regulator can generate an interrupt (if enabled by EREG0, EIE2.0) that is triggered whenever
the VREGIN input voltage drops below the dropout threshold voltage. This d ropout interrupt has no pending
flag and the recommended procedure to use it is as follows:
1. Wait enough time to ensure the VREGIN input voltage is stable
2. Enable the dropout interrupt (EREG0, EIE2.0) and select the proper priority (PREG0, EIP2.0)
3. If triggered, inside the interrupt disable it (clear EREG0, EIE2.0), execute all procedures necessary to
protect your application (put it in a safe mode and leave the interrupt now disable d.
4. In the main application, now running in the safe mode, regularly checks the DROPOUT bit
(REG0CN.0). Once it is cleared by the regulator hardware the application can enable the interrupt
again (EREG0, EIE1.6) and return to the normal mode operation.
The input (VREGIN) and output (VDD) of the voltage regulator should both be bypassed with a large capaci-
tor (4.7 µF + 0.1 µF) to gr oun d as show n in F igure 9.1. This capacitor will e liminat e po wer s pikes and pro -
vide any immediate power required by the microcontroller. The settling time associated with the voltage
regulator is shown in Table 5.8 on page 43.
Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset
event. The output of the un-calibrated internal regulator could be below the high threshold setting of
the VDD Monitor. If this is the case and the VDD Monitor is set to the high threshold setting and if the
MCU receives a non-power on reset (POR), the MCU will remain in reset until a P OR oc cu rs (i.e .,
VDD Monitor will keep the device in reset). A POR will force the VDD Monitor to the low threshold
setting which is guaranteed to be below the un-calibr ated output of the intern al regulator . The device
will then exit reset and resume normal opera tion. It is for this reason Silicon Labs strongly
recommends that the VDD Monitor is always left in the low threshold setting (i.e. default value upon
POR).
Figure 9.1. External Capacitors for Voltage Regulator Input/Output—
Regulator Enabled
VDD
VDD
REG0
4.7 µF
4.7 µF .1 µF
.1 µF
VREGIN
C8051F55x/56x/57x
80 Rev. 1.2
If the internal voltage r egulator is not used, the VREGIN inp ut should be tied to VDD, as shown in Figure 9.2.
Figure 9.2. External Capacitors for Voltage Regulator Input/Output—Regulator Disabled
SFR Address = 0xC9; SFR Page = 0x00
SFR Definition 9.1. REG0CN: Regulator Control
Bit 7 6 5 4 3 2 1 0
Name REGDIS Reserved REG0MD DROPOUT
Type R/W R/W RR/W R R R R
Reset 0 1 0 1 0 0 0 0
Bit Name Function
7REGDIS Voltage Regulator Disable Bit.
0: Voltage Regulator Enabled
1: Voltage Regulator Disabled
6 Reserved Read = 1b; Must Write 1b.
5Unused Read = 0b; Write = Don’t Care.
4REG0MD Voltage Regulator Mode Select Bit.
0: Voltage Regulator Output is 2.1 V.
1: Voltage Regulator Output is 2.6 V.
3:1 Unused Read = 000b. Write = Don’t Care.
0DROPOUT Voltage Regulator Dropout Indicator.
0: Voltage Regulator is not in dropout.
1: Voltage Regulator is in or near dropout.
VREGIN
VDD
VDD
4.7 µF .1 µF
C8051F55x/56x/57x
Rev. 1.2 81
10. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 27), and interfaces directly with the ana-
log and digit al subsystems providin g a complete dat a acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram).
The CIP-51 includes the following fe atures:
Fully Compatible with MCS-51 Instruction Set
50 MIPS Peak Throughput with 50 MHz Clock
0 to 50 MHz Clock Frequency
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
10.1. Performance
The CIP-51 emplo ys a p ipeli ned architectu re tha t grea tly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
C8051F55x/56x/57x
82 Rev. 1.2
Figure 10.1. CIP-51 Block Diagram
With the CIP-51's maximum system clock at 50 MHz, it has a peak throughput of 50 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wir e Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “27. C2 Interface” on page 300.
The CIP-51 is supported by developm ent to ols from Silicon Labs and third p arty vend ors. Silicon Lab s pro-
vides an integrated deve lopment environmen t (IDE) including editor, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys-
tem device programming and debugging. Third party macro assemblers and C compilers are also avail-
able.
Clocks to Execute 1 2 2/3 33/4 44/5 5 8
Number of Instructions 26 50 514 7 3 1 2 1
DATA BUS
TMP1 TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE POWER CONT ROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER SRAM
D8
STACK POINTER
D8
C8051F55x/56x/57x
Rev. 1.2 83
10.2. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
10.2.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 10.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
C8051F55x/56x/57x
84 Rev. 1.2
Table 10.1. CIP-51 Instruction Set Summary
Mnemonic Description Bytes Clock
Cycles
Arithmetic Operations
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with borr ow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2
SUBB A, #data Subtract immediate from A with borr ow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrement regis te r 1 1
DEC direct Decrement direct byt e 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
Logical Operations
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 12
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #d ata OR immedia te to direct byte 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR dire ct by te to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 14.3).
C8051F55x/56x/57x
Rev. 1.2 85
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
CLR A Clear A 1 1
CPL A Complement A 1 2
RL A Ro tat e A l eft 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 14-7*
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
Table 10.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 14.3).
C8051F55x/56x/57x
86 Rev. 1.2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carr y 1 1
CPL bit Complement direct bit 2 2
ANL C, bit AND direct bit to Carry 2 2
ANL C, /bit AND complement of direct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to direct bit 2 2
JC rel Jump if Carry is set 22/(4-6)*
JNC rel Jump if Carry is not set 22/(4-6)*
JB bit, rel Jump if direct bit is set 33/(5-7)*
JNB bit, rel Jump if direct bit is not set 33/(5-7)*
JBC bit, rel Jump if direct bit is set and clear bit 33/(5-7)*
Program Branching
ACALL addr11 Absolute subroutine call 24-6*
LCALL addr16 Long subroutine call 35-7*
RET Return from subroutine 16-8*
RETI Return from interrupt 16-8*
AJMP addr11 Absolute jump 24-6*
LJMP addr16 Long jump 35-7*
SJMP rel Short jump (relative address) 24-6*
JMP @A+DPTR Jump indirect relative to DPTR 13-5*
JZ rel Jump if A equals zero 22/(4-6)*
JNZ rel Jump if A does not equal zero 22/(4-6)*
CJNE A, direct, rel Compare direct byte to A and jump if not equal 34/(6-8)*
CJNE A, #data, rel Compare immediate to A and jump if not equal 33/(6-8)*
CJNE Rn, #data, rel Compare immediate to Register and jump if not
equal 33/(5-7)*
CJNE @Ri, #data, re l Compare immediate to indirect and jump if not
equal 34/(6-8)*
DJNZ Rn, rel Decrement Register and jump if not zero 22/(4-6)*
DJNZ direct, rel Decrement direct byt e an d jum p if not zer o 33/(5-7)*
NOP No operation 1 1
Table 10.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 14.3).
C8051F55x/56x/57x
Rev. 1.2 87
10.3. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys-
tem function.
Notes on Registers, Oper ands and Addressing Modes:
Rn—Register R0–R7 of the currently selected register bank.
@Ri—Data RAM location addressed indirectly through R0 or R1.
rel—8-bit, signed (two’s complement) of fset relative to th e first byte of the follow ing instruction. Used by
SJMP and all conditional jumps.
direct—8-bit internal data location’s address. This co uld be a dir ec t-a cc ess Data RAM location (0 x00–
0x7F) or an SFR (0x80–0xFF).
#data—8-bit constant
#data16—16-bit constant
bit—Direct-accessed bit in Data RAM or SFR
addr11—11-bit destination address used by ACALL and AJMP. The destination must be within the
same 2 kB page of program memory as the first byte of the following instruction.
addr16—16-bit destin ation address used by LCALL a nd LJMP. The destination may be anywhere within
the 64 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
C8051F55x/56x/57x
88 Rev. 1.2
SFR Address = 0x82; SFR Page = All Pages
SFR Address = 0x83; SFR Page = All Pages
SFR Definition 10.1. DPL: Data Pointer Low Byte
Bit76543210
Name DPL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
SFR Definition 10.2. DPH: Data Pointer High Byte
Bit76543210
Name DPH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
C8051F55x/56x/57x
Rev. 1.2 89
SFR Address = 0x81; SFR Page = All Pages
SFR Address = 0xE0; SFR Page = All Pages; Bit-Addressable
SFR Address = 0xF0; SFR Page = All Pages; Bit-Addressable
SFR Definition 10.3. SP: Stack Pointer
Bit76543210
Name SP[7:0]
Type R/W
Reset 00000111
Bit Name Function
7:0 SP[7:0] Stack Pointer.
The S t ack Pointer holds the location of the top of the stack. The st ack pointer is incre-
mented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 10.4. ACC: Accumulator
Bit76543210
Name ACC[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ACC[7:0] Accumulator.
This register is the accumulator for arithm etic operations.
SFR Definition 10.5. B: B Register
Bit76543210
Name B[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 B[7:0] B Register.
This register serves as a second accumulator for certain arithmetic operations.
C8051F55x/56x/57x
90 Rev. 1.2
SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable
SFR Definition 10.6. PSW: Program Status Word
Bit76543210
Name CY AC F0 RS[1:0] OV F1 PARITY
Type R/W R/W R/W R/W R/W R/W R
Reset 00000000
Bit Name Function
7CY Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleare d to logic 0 by all other arithmetic operations.
6AC Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) th e high order nibble. It is cleared to logic 0 by all other arith-
metic operation s .
5F0 User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3 RS[1:0] Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2OV Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1F1 User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
0PARITY Parity Flag.
This bit is set to logic 1 if the sum of the eigh t bits in the accumulator is odd a nd cleared
if the sum is even.
C8051F55x/56x/57x
Rev. 1.2 91
10.4. Serial Number Special Function Registers (SFRs)
The C8051F55x/56x/57x devices include four SFRs, SN0 through SN3, that are pre-programmed during
production with a unique, 32-bit serial number. The serial number provides a unique identification number
for each device and ca n be read fr om the applica tion firm ware. If the serial number is not used in the appli-
cation, these four registers can be used as general purpose SFRs.
SFR Addresses: SN0 = 0xF9; SN1 = 0xFA; SN2 = 0xFB; SN3 = 0xFC; SFR Page = 0x0F;
SFR Definition 10.7. SNn: Serial Number n
Bit76543210
Name SERNUMn[7:0]
Type R/W
Reset Varies—Unique 32-bit value
Bit Name Function
7:0 SERNUMn[7:0] Serial Number Bits.
The four serial number registers form a 32-bit serial number, with SN3 as the
most significant byte and SN0 as the least significant byte.
C8051F55x/56x/57x
Rev. 1.2 92
11. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address spa ce but are accessed via dif f erent instr uction types. The memor y organization is sh own in
Figure 11.1
Figure 11.1. C8051F55x/56x/57x Memory Map
11.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F55x/56x/57x devices implement 32 kB
or 16 kB of this program memory space as in-system, r e-programmab le Flash memory, organized in a con-
tiguous block from addresses 0x0000 to 0x7FFF in 32 kB devices and addresses 0x0000 to 0x3FFF in
16 kB devices. The address 0x7BFF in 32 kB devices and 0x3FFF in 16 kB devices serves as the security
lock byte for the device. Addresses above 0x7BFF are reserved in the 32 kB devices.
PROGRAM/DATA MEMORY
(FLASH)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF Special Function
Register's
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F Bit Addressable
Lower 128 RAM
(Direct a nd Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
0x0000
0x07FF
Same 2048 bytes as
from 0x0000 to 0x07FF,
wrapped on 2048-byte
boundaries
0x8000
0xFFFF
32 kB FLAS H
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x7C00
0x7BFF
C8051F550/1/2/3
C8051F560/1/2/3/8/9
C8051F570/1
16 kB FLASH
(In-Sy s tem
Programmable in 512
Byte Sectors)
0x0000
0x3FFF XRAM
2K Bytes
(accessable using
MO VX instructio n )
C8051F554/5/6/7
C8051F564/5/6/7
C8051F572/3/4/5
C8051F55x/56x/57x
93 Rev. 1.2
Figure 11.2. Flash Program Memory Map
11.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F55x/56x/57x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but
can be re-configure d to write and erase on-chip Flash memory space. MOVC instructions are always use d
to read Flash memory, while MOVX write instructions are used to era se and write Fl ash. This Flash a ccess
feature provides a mechanism for the C8051F55x/56x/57x to update program code and use the program
memory space for non-volatile data storage. Refer to Section “14. Flash Memory” on page 124 for further
details.
11.2. Data Memory
The C8051F55x/56x/57x devices include 2304 bytes of RAM data memory. 256 bytes of this memory is
mapped into the internal RAM space of the 8051. The other 2048 bytes of this memory is on-chip “exter-
nal” memory. The data memory map is shown in Fig ur e 11.1 for reference.
11.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space . Instructions using ind irect addressing a bove 0x7F access th e
upper 128 bytes of data memory. Figure 11.1 illustrates the data memory organization of the
Lock Byte
0x0000
0x3FFF
0x3FFE
FLASH memory organized in
512-byte pages
0x3E00
Flash Mem ory Space
(16 kB Flash Device)
Lock B yte Page
Lock Byte
0x0000
0x7BFF
0x7BFE
0x7C00
0x7A00
Flash Mem ory Space
(32 kB Flash D evice)
Lock Byte Page
0x7FFF
Reserved A rea
C8051F550/1/2/3
C8051F560/1/2/3/8/9
C8051F570/1
C8051F554/5/6/7
C8051F564/5/6/7
C8051F572/3/4/5
C8051F55x/56x/57x
Rev. 1.2 94
C8051F55x/56x/57x.
11.2.1.1. General Purpose Registers
The lower 32 bytes of dat a memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in th e progr am st atus wo rd , RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 10.6). This allows
fast context switching when entering su broutin es and interrupt se rvice routine s. Indirect addr essing modes
use registers R0 and R1 as index registers.
11.2.1.2. Bit Addressable Locations
In addition to direct access to d ata memory organized as bytes, the sixtee n data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0 x20 has bit addr ess 0x00 while bit7 of the byte at 0x20 has bit addr ess
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
11.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis-
ter (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a location in the data memory not being used for data storage. The stack depth can extend up to
256 bytes.
C8051F55x/56x/57x
Rev. 1.2 95
12. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F55x/56x/57x's resources and
peripherals. The CIP- 51 controller core duplicates the SFRs found in a typical 805 1 implement ation as well
as implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F55x/56x/57x. This allows the addition of new functionality while retaining compatibility with the
MCS-51™ instruction set. Table 12.3 list s th e SFRs implemented in the C8051F55x/56x/57x device family.
The SFR regist ers are acc essed anytime the direct a ddressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing unoccupied addresses in the SFR
space will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the
data sheet, as indi cated in Table 12.3, for a detailed description of each register.
12.1. SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory
address space. The SF R memory space has 256 pages. In this way, each memory location from 0x80 to
0xFF can access up to 256 SFRs. The C8051F55x/56x/57x family of devices utilizes three SFR pages:
0x00, 0x0C, and 0x0F. SFR pages are selected using the Special Function Register Page Selection regis-
ter, SFRPAGE (see SFR Definition 11.3). The procedure for reading and wr iting an SFR is as follows:
1. Select the appropriate SFR page number using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
12.2. Interrupts and SFR Paging
When an interrupt occurs, the SFR Page Register will automatically switch to the SFR page containing the
flag bit that caused the interrupt. The automatic SFR Page switch function conveniently removes the bur-
den of switching SFR pages from the interrupt service routine. Upon execution of the RETI instruction, the
SFR page is automatically restored to the SFR Page in use prior to the interrupt. This is accomplished via
a three-byte SFR Page Stack. The top byte of the stack is SFRPAGE, the cu rrent SFR Page . The second
byte of the S FR Page Stack is SFRNEXT. The third, or bottom byte of the SFR Page Stack is SFRLAST.
Upon an interrupt, the current SFRPAGE value is pushed to the SFRNEXT byte, and the value of
SFRNEXT is pushed to SFRLAST. Hardware then loads SFRPAGE with the SFR Page containing the flag
bit associated with the interrupt. On a return from interrupt, the SFR Page Stack is popped resulting in the
value of SFRNEXT returning to the SFRPAGE register, thereby restoring the SFR page context without
software intervention. The value in SFRLAST (0x00 if there is no SFR Page value in the bottom of the
stack) of the stack is placed in SFRNEXT register. If desired, the values stored in SFRNEXT and SFR-
LAST may be modified during an interrupt, enabling the CPU to return to a different SFR Page upon exe-
cution of the RETI instruction (on interrupt exit). Modifying registers in th e SFR Page Stack does not cause
a push or pop of the stack. Only interrupt calls and returns will cause push/pop operations on the SFR
Page Stack.
On the C8051F55x/56x/57x devices, vectoring to an interrupt will switch SFRPAGE to page 0x00, except
for the CAN0 interrupt which will switch SFRPAGE to page 0x0C.
C8051F55x/56x/57x
96 Rev. 1.2
Figure 12.1. SFR Page Stack
Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using
the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFR0CN). This
function defaults to “enabled” upon reset. In this way, the autoswitching function will be enabled unless dis-
abled in software.
A summary of the SFR locations (addr ess and SFR page) are provided in Table 12.3 in the form of an SFR
memory map. Each memory location in the map has an SFR page row, denoting the page in which that
SFR resides. Certain SFR s are accessible from AL L SFR pages, and are denoted by the “(ALL PAGES)”
designation. For example, the Port I/O registers P0, P1, P2, and P3 all have the “(ALL PAGES)” designa-
tion, indicating these SFRs are accessible from all SFR pages regardless of the SFRPAGE register value.
SFRNEXT
SFRPAGE
SFRLAST
CIP-51
Interrupt
Logic
SFRPGCN Bit
C8051F55x/56x/57x
Rev. 1.2 97
12.3. SFR Page Stack Example
The following is an example that shows the operation of the SFR Page Stack during interrupts. In this
example, th e SFR Contr ol regis ter is le ft in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51
is executing in-line code that is writing values to SPI Data Register (SFR “SPI0DAT”, located at address
0xA3 on SFR Page 0x00). The device is also using the CAN peripheral (CAN0) and the Programmable
Counter Array (PCA0) perip heral to gen erate a PWM outp ut. The PCA is timing a critical contro l function i n
its interrup t service and so it s associated ISR that is set to high priority. At this point, the SFR page is set to
access the SPI0DAT SFR (SFRPAGE = 0x00). See Figure 12.2.
Figure 12.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT
0x0
(SPI0DAT) SFRPAGE
SFRLAST
SFRNEXT
SFR Page
Stack SFR's
C8051F55x/56x/57x
98 Rev. 1.2
While CIP-51 executes in-line code (writing values to SPI0DAT in this example), the CAN0 Interrupt
occurs. The CIP-51 vectors to the CAN0 ISR and pushes the current SFR Page value (SFR Page 0x00)
into SFRNEXT in the SFR Page S t ack. The SFR page need ed to access CAN’ s SFRs is then automatically
placed in the SFRPAGE register (SFR Page 0x0C). SFRPAGE is considered the “top” of the SFR Page
Stack. Software can now access the CAN0 SFRs. Software may switch to any SFR Page by writing a new
value to the SFRPAGE register at any time during the CAN0 ISR to access SFRs that are not on SFR
Page 0x0C. See Figure 12.3.
Figure 12.3. SFR Page Stack After CAN0 Interrupt Occurs
0xC
(CAN0)
0x0
(SPI0DAT)
SFRPAGE
SFRLAST
SFRNEXT
SFRPAGE
pushed to
SFRNEXT
SFR Page 0xC
Automatically
pushed on stack in
SFRPAGE on CAN0
interrupt
C8051F55x/56x/57x
Rev. 1.2 99
While in the CAN0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority
interrupt, while the CAN0 inter rupt is configure d as a low priority interrupt. Thus, the CIP-51 will now vector
to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to
access the PCA’s special function registers into the SFRPAGE register, SFR Page 0x00. The value that
was in the SFRPAGE register before the PCA interrupt (SFR Page 0x0C for CAN0) is pushed down the
stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register before the PCA interrupt (in
this case SFR Page 0x00 for SPI0DAT) is pushed down to the SFRLAST register, the “bottom” of the
stack. Note that a value stored in SFRLAST (via a previous sof twa re wr ite to the SFRL AST re gister) will b e
overwritten. See Figure 12.4.
Figure 12.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR
0x0
(PCA)
0xC
(CAN0)
0x0
(SPI0DAT)
SFRPAGE
SFRLAST
SFRNEXT
SFR Page 0x0
Automatically
pushed on stack in
SFRPAGE on PCA
interrupt
SFRPAGE
pushed to
SFRNEXT
SFRNEXT
pushed to
SFRLAST
C8051F55x/56x/57x
100 Rev. 1.2
On exit from the PCA interrupt service routin e, the CIP- 51 will retur n to the CAN0 ISR. On execution of the
RETI instruction, SFR Page 0x00 used to access the PCA registers will be automatically popped off of the
SFR Page Stack, and the co ntents of the SFRNEXT register will be moved to the SF RPAGE register. Soft-
ware in the CAN0 ISR can continue to access SFRs as it did prior to the PCA interrupt. Likewise, the con-
tents of SFRLAST are moved to the SFRNEXT register. Recall this was the SFR Page value 0x00 being
used to access SPI0DAT before the CAN0 interrupt occurred. See Figure 12.5.
Figure 12.5. SFR Page Stack Upon Return From PCA Interrupt
0xC
(CAN0)
0x0
(SPI0DAT)
SFRPAGE
SFRLAST
SFRNEXT
SFR Page 0x0
Automatically
popped off of the
stack on return from
interrupt
SFRNEXT
popped to
SFRPAGE
SFRLAST
popped to
SFRNEXT
C8051F55x/56x/57x
Rev. 1.2 101
On the execution of the RETI instruction in the CAN0 ISR, the value in SFRPAGE register is overwritten
with the contents of SFRNEXT. The CIP-51 may now access the SPI0DAT register as it did prior to the
interrupts occurring. See Figure 12.6.
Figure 12.6. SFR Page Stack Upon Return From CAN0 Interrupt
In the example above, all thre e bytes in the SFR Pa ge Stack are accessible via the SFRPAGE, SFRNEXT,
and SFRLAST special function registers. If the stack is altered while servicing an interrupt, it is possible to
return to a different SFR Page upon interrup t exit than se lected prior to the interr upt call. Dir ect access to
the SFR Page stack can be useful to enable real-time operating systems to control and manage context
switching between multiple tasks.
Push operations on the SFR Page Stack only occur on interrupt service, and pop operations only occur on
interrupt exit (execution on the RETI instruction). The automatic switching of the SFRPAGE and operation
of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic
Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFR0CN). See SFR Definition 12.1.
0x0
(SPI0DAT) SFRPAGE
SFRLAST
SFRNEXT
SFR Page 0xC
Automatically
popped off of the
stack on return from
interrupt
SFRNEXT
popped to
SFRPAGE
C8051F55x/56x/57x
102 Rev. 1.2
SFR Address = 0x84; SFR Page = 0x0F
SFR Definition 12.1. SFR0CN: SFR Page Control
Bit 7 6 5 4 3 2 1 0
Name SFRPGEN
Type RRRRRRRR/W
Reset 0 0 0 0 0 0 0 1
Bit Name Function
7:1 Unused Read = 0000000b; Write = Don’t Care
0SFRPGEN SFR Automatic Page Control Enable.
Upon interrupt, the C8051 Core will vector to the specified interrupt service routine
and automatically switch the SFR page to the corresponding peripheral or function’s
SFR page. This bit is used to control this autopaging function.
0: SFR Automatic Paging disabled. The C8051 core will not automatically change to
the appropriate SFR page (i.e., the SFR page that contains the SFRs for the periph-
eral/function that was the source of the interrupt).
1: SFR Automatic Paging enabled. Upon interrupt, the C8051 will switch the SFR
page to the page that contains the SFRs for the peripheral or function that is the
source of the interrupt.
C8051F55x/56x/57x
Rev. 1.2 103
SFR Address = 0xA7; SFR Page = All Pages
SFR Definition 12.2. SFRPAGE: SFR Page
Bit 7 6 5 4 3 2 1 0
Name SFRPAGE[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 SFRPAGE[7:0] SFR Page Bits.
Represents the SFR Page the C8051 core uses when reading or modifying
SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 core is using.
When enabled in the SFR Page Control Registe r (SFR0CN), the C8051 core will
automatically switch to the SFR Page that contains the SFRs of the correspond-
ing peripheral/function that caused the interrupt, and return to the previous SFR
page upon return from interrupt (unless SFR Stack was altered before a return-
ing from the interrupt). SFRPAGE is the top byte of the SFR Page Stack, and
push/pop events of this stack are caused by interrupts (and not by reading/writ-
ing to the SFRPAGE register)
C8051F55x/56x/57x
104 Rev. 1.2
SFR Address = 0x85; SFR Page = All Pages
SFR Definition 12.3. SFRNEXT: SFR Next
Bit 7 6 5 4 3 2 1 0
Name SFRNEXT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 SFRNEXT[7:0] SFR Page Bits.
This is the value that will go to the SFR Page register upon a return from inter-
rupt.
Write: Sets the SFR Page contained in the second byte of the SFR Stack. This
will cause the SFRPAGE SFR to have this SFR page value upon a return from
interrupt.
Read: Returns the value of the SFR page contained in the second byte of the
SFR stack.
SFR page context is retained upon interrupts/return from interrupts in a 3 byte
SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and
SFRLAST is the th ird entry. T he SFR stack bytes may be us ed alter the con text
in the SFR Page Stack, and will not cause the stack to “push” or “pop”. Only
interrupts and return from interrupts cause pushes and pops of the SFR Page
Stack.
C8051F55x/56x/57x
Rev. 1.2 105
SFR Address = 0xA7; SFR Page = All Pages
SFR Definition 12.4. SFRLAST: SFR Last
Bit 7 6 5 4 3 2 1 0
Name SFRLAST[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 SFRLAST[7:0] SFR Page Stack Bits.
This is the value that will go to the SFRNEXT register upon a return from inter-
rupt.
Write: Sets the SFR Page in the last entry of the SFR Stack. This will cause the
SFRNEXT SFR to have this SFR page value upon a return from interrupt.
Read: Returns the value of the SFR page contained in the last entry of the SFR
stack.
SFR page context is retained upon interrupts/return from interrupts in a 3 byte
SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and
SFRLAST is the th ird entry. T he SFR stack bytes may be us ed alter the con text
in the SFR Page Stack, and will not cause the stack to “push” or “pop”. Only
interrupts and return from interrupts cause pushes and pops of the SFR Page
Stack.
C8051F55x/56x/57x
106 Rev. 1.2
Table 12.1. Special Function Register (SFR) Memory Map for Pages 0x00 and 0x0F
Address
Page
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
F8 0
FSPI0CN PCA0L
SN0 PCA0H
SN1 PCA0CPL0
SN2 PCA0CPH0
SN3 PCACPL4 PCACPH4 VDM0CN
F0 0
FB
(All Pages) P0MAT
P0MDIN P0MASK
P1MDIN P1MAT
P2MDIN P1MASK
P3MDIN EIP1
EIP1 EIP2
EIP2
E8 0
FADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPL3 RSTSRC
E0 0
FACC
(All Pages) XBR0 XBR1 CCH0CN IT01CF EIE1
(All Pages) EIE2
(All Pages)
D8 0
FPCA0CN PCA0MD
PCA0PWM PCA0CPM0PCA0CPM1PCA0CPM2 PCA0CPM3PCA0CPM4PCA0CPM5
D0 0
FPSW
(All Pages) REF0CN LIN0DATA LIN0ADDR P0SKIP P1SKIP P2SKIP P3SKIP
C8 0
FTMR2CN REG0CN
LIN0CF TMR2RLL TMR2RLH TMR2L TMR2H PCA0CPL5 PCA0CPH5
C0 0
FSMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH XBR2
B8 0
FIP
(All Pages) ADC0TK ADC0MX ADC0CF ADC0L ADC0H
B0 0
FP3
(All Pages) P2MAT P2MASK
EMI0CF P4
(All Pages) FLSCL
(All Pages) FLKEY
(All Pages)
A8 0
FIE
(All Pages) SMOD0 EMI0CN
EMI0TC SBCON0 SBRLL0 SBRLH0 P3MAT
P3MDOUT P3MASK
P4MDOUT
A0 0
FP2
(All Pages) SPI0CFG
OSCICN SPI0CKR
OSCICRS SPI0DAT P0MDOUT P1MDOUT P2MDOUT SFRPAGE
(All Pages)
98 0
FSCON0 SBUF0 CPT0CN CPT0MD CPT0MX CPT1CN CPT1MD
OSCIFIN CPT1MX
OSCXCN
90 0
FP1
(All Pages) TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H CLKMUL
88 0
FTCON
(All Pages) TMOD
(All Pages) TL0
(All Pages) TL1
(All Pages) TH0
(All Pages) TH1
(All Pages) CKCON
(All Pages) PSCTL
CLKSEL
80 0
FP0
(All Pages) SP
(All Pages) DPL
(All Pages) DPH
(All Pages) SFR0CN SFRNEXT
(All Pages) SFRLAST
(All Pages) PCON
(All Pages)
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
C8051F55x/56x/57x
Rev. 1.2 107
Table 12.2. Special Function Register (SFR) Memory Map for Page 0x0C
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
F8 CAN0IF2DA2L CAN0IF2DA2H CAN0IF2DB1L CAN0IF2DB1H CAN0IF2DB2L CAN0IF2DB2H
F0 B
(All Pages) CAN0IF2A2L CAN0IF2A2H CAN0IF2DA1L CAN0IF2DA1H
E8 CAN0IF2M1L CAN0IF2M1H CAN0IF2M2L CAN0IF2M2H CAN0IF2A1L CAN0IF2A1H
E0 ACC
(All Pages) CAN0IF2CML CAN0IF2CMH EIE1
(All Pages) EIE2
(All Pages)
D8 CAN0IF1DB1L CAN0IF1DB1H CAN0IF1DB2L CAN0IF1DB2H CAN0IF2CRL CAN0IF2CRH
D0 PSW
(All Pages) CAN0IF1MCL CAN0IF1MCH CAN0IF1DA1L CAN0IF1DA1H CAN0IF1DA2L CAN0IF1DA2H
C8 CAN0IF1A1L CAN0IF1A1H CAN0IF1A2L CAN0IF1A2H CAN0IF2MCL CAN0IF2MCH
C0 CAN0CN CAN0IF1CML CAN0IF1CMH CAN0IF1M1L CAN0IF1M1H CAN0IF1M2L CAN0IF1M2H
B8 IP
(All Pages) CAN0MV1L CAN0MV1H CAN0MV2L CAN0MV2H CAN0IF1CRL CAN0IF1CRH
B0 P3
(All Pages) CAN0IP2L CAN0IP2H P4
(All Pages) FLSCL
(All Pages) FLKEY
(All Pages)
A8 IE
(All Pages) CAN0ND1L CAN0ND1H CAN0ND2L CAN0ND2H CAN0IP1L CAN0IP1H
A0 P2
(All Pages) CAN0BRPE CAN0TR1L CAN0TR1H CAN0TR2L CAN0TR2H SFRPAGE
(All Pages)
98 SCON0
(All Pages) CAN0BTL CAN0BTH CAN0IIDL CAN0IIDH CAN0TST
90 P1
(All Pages) CAN0CFG CAN0STAT CAN0ERRL CAN0ERRH
88 TCON
(All Pages) TMOD
(All Pages) TL0
(All Pages) TL1
(All Pages) TH0
(All Pages) TH1
(All Pages) CKCON
(All Pages)
80 P0
(All Pages) SP
(All Pages) DPL
(All Pages) DPH
(All Pages) SFRNEXT
(All Pages) SFRLAST
(All Pages) PCON
(All Pages)
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
C8051F55x/56x/57x
108 Rev. 1.2
Table 12.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address Description Page
ACC 0xE0 Accumulator 89
ADC0CF 0xBC ADC0 Configuration 58
ADC0CN 0xE8 ADC0 Control 60
ADC0GTH 0xC4 ADC0 Greate r- Th a n Co mpare High 62
ADC0GTL 0xC3 ADC0 Greate r- Th a n Co mpare Lo w 62
ADC0H 0xBE ADC0 High 59
ADC0L 0xBD ADC0 Low 59
ADC0LTH 0xC6 ADC0 Less-Than Compare Word High 63
ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low 63
ADC0MX 0xBB ADC0 Mux Configuration 66
ADC0TK 0xBA ADC0 Tracking Mode Select 61
B0xF0 B Register 89
CCH0CN 0xE3 Cache Control 134
CKCON 0x8E Clock Control 260
CLKMUL 0x97 Clock Multiplier 163
CLKSEL 0x8F Clock Select 158
CPT0CN 0x9A Comparator0 Control 72
CPT0MD 0x9B Comparato r0 Mode Selection 73
CPT0MX 0x9C Comparator0 MUX Selection 77
CPT1CN 0x9D Comparator1 Control 72
CPT1MD 0x9E Comparato r1 Mode Selection 73
CPT1MX 0x9F Comparator1 MUX Selection 77
DPH 0x83 Data Pointer High 88
DPL 0x82 Data Pointer Low 88
EIE1 0xE6 Extended Interrupt Enable 1 118
EIE2 0xE7 Extended Interrupt Enable 2 118
EIP1 0xF6 Extended Interrupt Priority 1 119
EIP2 0xF7 Extended Interrupt Priority 2 120
EMI0CF 0xB2 External Memory Interface Configuration 148
EMI0CN 0xAA External Memory Interface Control 147
EMI0TC 0xAA External Memory Interface Timing Control 152
FLKEY 0xB7 Flash Lock and Key 132
FLSCL 0xB6 Flash Scale 133
IE 0xA8 Interrupt Enable 116
IP 0xB8 Interrupt Priority 117
C8051F55x/56x/57x
Rev. 1.2 109
IT01CF 0xE4 INT0/INT1 Configuration 123
LIN0ADR 0xD3 LIN0 Address 200
LIN0CF 0xC9 LIN0 Configuration 200
LIN0DAT 0xD2 LIN0 Data 201
OSCICN 0xA1 Internal Oscillator Control 160
OSCICRS 0xA2 Internal Oscillator Coarse Control 161
OSCIFIN 0x9E Internal Oscillator Fine Calibration 161
OSCXCN 0x9F External Oscillator Control 165
P0 0x80 Port 0 Latch 183
P0MASK 0xF2 Port 0 Mask Conf igu ra tion 179
P0MAT 0xF1 Port 0 Match Configuration 179
P0MDIN 0xF1 Port 0 Input Mo de Con fig ur at ion 184
P0MDOUT 0xA4 Port 0 Output Mode Configuration 184
P0SKIP 0xD4 Port 0 Skip 185
P1 0x90 Port 1 Latch 185
P1MASK 0xF4 Port 1 Mask Conf igu ra tion 180
P1MAT 0xF3 Port 1 Match Configuration 180
P1MDIN 0xF2 Port 1 Input Mo de Con fig ur at ion 186
P1MDOUT 0xA5 Port 1 Output Mode Configuration 186
P1SKIP 0xD5 Port 1 Skip 187
P2 0xA0 Port 2 Latch 187
P2MASK 0xB2 Port 2 Mask Configura tio n 181
P2MAT 0xB1 Port 2 Match Configuration 181
P2MDIN 0xF3 Port 2 Input Mo de Con fig ur at ion 188
P2MDOUT 0xA6 Port 2 Output Mode Configuration 188
P2SKIP 0xD6 Port 2 Skip 189
P3 0xB0 Port 3 Latch 189
P3MASK 0xAF Port 3 Mask Configura tio n 182
P3MAT 0xAE Port 3 Match Configuration 182
P3MDIN 0xF4 Port 3 Input Mo de Con fig ur at ion 190
P3MDOUT 0xAE Port 3 Output Mode Configuration 190
P3SKIP 0xD7 Port 3 Skip 191
P4 0xB5 Port 4 Latch 191
P4MDOUT 0xAF Port 4 Output Mode Configuration 192
PCA0CN 0xD8 PCA Control 294
PCA0CPH0 0xFC PCA Capture 0 High 299
Table 12.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address Description Page
C8051F55x/56x/57x
110 Rev. 1.2
PCA0CPH1 0xEA PCA Captur e 1 Hi gh 299
PCA0CPH2 0xEC PCA Capture 2 High 299
PCA0CPH3 0xEE PCA Captur e 3 Hi gh 299
PCA0CPH4 0xFE PCA Capture 4 High 299
PCA0CPH5 0xCF PCA Capture 5 High 299
PCA0CPL0 0xFB PCA Capture 0 Low 299
PCA0CPL1 0xE9 PCA Capture 1 Low 299
PCA0CPL2 0xEB PCA Capture 2 Lo w 299
PCA0CPL3 0xED PCA Capture 3 Low 299
PCA0CPL4 0xFD PCA Capture 4 Low 299
PCA0CPL5 0xCE PCA Capture 5 Low 299
PCA0CPM0 0xDA PCA Module 0 Mode Register 297
PCA0CPM1 0xDB PCA Module 1 Mode Register 297
PCA0CPM2 0xDC PCA Module 2 Mode Register 297
PCA0CPM3 0xDD PCA Module 3 Mode Register 297
PCA0CPM4 0xDE PCA Module 4 Mode Register 297
PCA0CPM5 0xDF PCA Module 5 Mode Register 297
PCA0H 0xFA PCA Counter High 298
PCA0L 0xF9 PCA Counter Low 298
PCA0MD 0xD9 PCA Mode 295
PCA0PWM 0xD9 PCA PWM Configuration 296
PCON 0x87 Power Control 137
PSCTL 0x8F Program Store R/W Control 131
PSW 0xD0 Program Status Word 90
REF0CN 0xD1 Voltage Reference Control 69
REG0CN 0xC9 Voltage Regulator Control 80
RSTSRC 0xEF Reset Source Configuration/Status 143
SBCON0 0xAB UART0 Baud Rate Generator Control 244
SBRLH0 0xAD UART0 Baud Rate Reload High Byte 245
SBRLL0 0xAC UART0 Baud Rate Reload Low Byte 245
SBUF0 0x99 UART0 Data Buffer 244
SCON0 0x98 UART0 Control 241
SFR0CN 0x84 SFR Page Control 102
SFRLAST 0x86 SFR Stack Last Page 105
SFRNEXT 0x85 SFR Stack Next Page 104
SFRPAGE 0xA7 SFR Page Select 103
Table 12.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address Description Page
C8051F55x/56x/57x
Rev. 1.2 111
SMB0CF 0xC1 SMBus0 Configuration 224
SMB0CN 0xC0 SMBus0 Control 226
SMB0DAT 0xC2 SMBus0 Data 228
SMOD0 0xA9 UART0 Mode 243
SN0 0xF9 Serial Number 0 91
SN1 0xFA Serial Number 1 91
SN2 0xFB Serial Number 2 91
SN3 0xFC Serial Number 3 91
SP 0x81 Stack Pointer 89
SPI0CFG 0xA1 SPI0 Configuration 253
SPI0CKR 0xA2 SPI0 Clock Rate Control 255
SPI0CN 0xF8 SPI0 Control 254
SPI0DAT 0xA3 SPI0 Data 255
TCON 0x88 Timer/Counter Control 265
TH0 0x8C Timer/Counter 0 High 268
TH1 0x8D Timer/Counter 1 High 268
TL0 0x8A Timer/Counter 0 Low 267
TL1 0x8B Timer/Counter 1 Low 267
TMOD 0x89 Timer/Counter Mode 266
TMR2CN 0xC8 Timer/Counter 2 Control 272
TMR2H 0xCD Timer/Counter 2 High 274
TMR2L 0xCC Timer/Counter 2 Low 274
TMR2RLH 0xCB Timer/Counter 2 Reload High 273
TMR2RLL 0xCA Timer/Counter 2 Reload Low 273
TMR3CN 0x91 Timer/Counter 3 Control 278
TMR3H 0x95 Timer/Counter 3 High 280
TMR3L 0x94 Timer/Counter 3 Low 280
TMR3RLH 0x93 Timer/Counter 3 Reload High 279
TMR3RLL 0x92 Timer/Counter 3 Reload Low 279
VDM0CN 0xFF VDD Monitor Control 141
XBR0 0xE1 Port I/O Crossbar Control 0 176
XBR1 0xE2 Port I/O Crossbar Control 1 177
XBR2 0xC7 Port I/O Crossbar Control 2 178
Table 12.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address Description Page
C8051F55x/56x/57x
Rev. 1.2 112
13. Interrupts
The C8051F55x/56x/57x devices include an extended interrupt system supporting a total of 18 interrupt
sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and exter-
nal inputs pins varies according to the specific version of the device. Each interrupt source has one or
more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets
a valid interrupt condition, the associated interrupt-pending flag is set to logi c 1.
If interrupt s are ena bled for the sour ce, an interrupt request is gener ated when the interru pt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin executio n of an interrupt service ro utine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt requ est had not occurred. If inter rupt s are not enabled, the inter rupt-pending fla g is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regard-
less of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE, EIE1, or EIE2). However, interrupts must first be globally enabled by setting the
EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0
disables all interrupt sources regardless of the individual interrupt-enable settings.
Note: Any instruction that clears a bit to disable an interrupt should be immediately followed by an instruction that has
two or more opcode bytes. Using EA (global interrupt enable) as an example:
// in 'C':
EA = 0; // clear EA bit.
EA = 0; // this is a dummy instruction with two-byte opcode.
; in assembly:
CLR EA ; clear EA bit.
CLR EA ; this is a dummy instruction with two-byte opcode.
For example, if an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction
which clears a bit to disable an interrupt source ), and the instruction is followed by a single-cycle instruc-
tion, the interrupt may be t aken. However, a read of the enable bit will return a 0 inside the interrupt service
routine. When the bit-clear ing opcode i s followed by a multi-cycle instruction, the interrupt will not b e ta ken.
Some interrupt-pending flags ar e auto matically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the har dware a nd mu st b e clear ed by software before returning from th e
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
13.1. MCU Interrupt Sources and Vectors
The C8051F55x/56x/57x MCUs suppor t 18 interr upt sources. Software can simulate an interrup t by setting
any interrupt-pending fla g to logic 1. If interrupt s are enabl ed for the fla g, an interrupt requ est will be gene r-
ated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt
sources, associated vector addresses, priority order and control bits are summarized in Table 13.1. Refer
to the datasheet section associated with a particular on-chip peripheral for information regarding valid
interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
C8051F55x/56x/57x
113 Rev. 1.2
13.1.1. Interrupt Priorities
Each interrupt source can be in dividua lly prog ra mmed to on e o f two p riority levels: lo w or h igh. A low prio r-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IE, EIP1, or EIP2) used to
configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the
interrupt with the hig her pr ior ity is service d first. If both interrupts have the same priority level, a fixed prior-
ity order is used to arbitrate, given in Table 13.1.
13.1.2. Interrupt Latency
Interrupt response time depen ds on the state of the CPU when the interrupt occurs. Pending interru pts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to serv ice the pendin g inte rrup t. Th eref ore, the ma ximu m res ponse tim e for an int erru pt (wh en no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing a n R ETI instruction fo llow ed b y a DIV as the next instr uc tio n. In this case, t he re sp on se tim e is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interru pt with equal or higher priority, the new interrupt will not be serviced un til the
current ISR complet es , inclu ding the RET I an d followin g instr uc tio n.
C8051F55x/56x/57x
Rev. 1.2 114
Table 13.1. Interrupt Summary
Interrupt Source Interrupt
Vector Priority
Order Pending Flag
Bit addressable?
Cleared by HW?
Enable
Flag Priority
Control
Reset 0x0000 Top None N/A N/A Always
Enabled Always
Highest
External Interrupt 0
(INT0)0x0003 0IE0 (TCON.1) YYEX0 (IE.0) PX0 (IP.0)
Tim e r 0 Ov e rf l ow 0x000B 1TF0 (TCON.5) YYET0 (IE.1) PT0 (IP.1)
External Interrupt 1
(INT1)0x0013 2IE1 (TCON.3) YYEX1 (IE.2) PX1 (IP.2)
Tim e r 1 Ov e rf l ow 0x001B 3TF1 (TCON.7) YYET1 (IE.3) PT1 (IP.3)
UART0 0x0023 4RI0 (SCON0.0)
TI0 (SCON0.1) Y N ES0 (IE.4) PS0 (IP.4)
Tim e r 2 Ov e rf l ow 0x002B 5TF2H (TMR2CN.7)
TF2L (TMR2CN.6) Y N ET2 (IE.5) PT2 (IP.5)
SPI0 0x0033 6SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Y N ESPI0
(IE.6) PSPI0
(IP.6)
SMB0 0x003B 7SI (SMB0CN.0) Y N ESMB0
(EIE1.0) PSMB0
(EIP1.0)
ADC0 Window Com-
pare 0x0043 8AD0WINT
(ADC0CN.3) Y N EWADC0
(EIE1.1) PWADC0
(EIP1.1)
ADC0 Conversion
Complete 0x004B 9AD0IN T (ADC0C N.5) Y N EADC0
(EIE1.2) PADC0
(EIP1.2)
Programmable
Counter Array 0x0053 10 CF (PCA0CN.7)
CCFn (PCA0CN.n)
COVF (PCA0PWM.6)
Y N EPCA0
(EIE1.3) PPCA0
(EIP1.3)
Comparator0 0x005B 11 CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5) NNECP0
(EIE1.4) PCP0
(EIP1.4)
Comparator1 0x0063 12 CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5) NNECP1
(EIE1.5) PCP1
(EIP1.5)
Tim e r 3 Ov e rf l ow 0x006B 13 TF3H (TMR3CN.7)
TF3L (TMR3CN.6) NNET3
(EIE1.6) PT3
(EIP1.6)
LIN0 0x0073 14 LIN0INT (LINST.3) NN* ELIN0
(EIE1.7) PLIN0
(EIP1.7)
Voltage Regulator
Dropout0x007B 15 N/A N/A N/A EREG0
(EIE2.0) PREG0
(EIP2.0)
CAN0 0x0083 16 CAN0INT
(CAN0CN.7) N Y ECAN0
(EIE2.1) PCAN0
(EIP2.1)
Port Match 0x008B 17 None N/A N/A EMAT
(EIE2.2) PMAT
(EIP2.2)
*Note: The LIN0INT bit is cleared by setting RSTINT (LINCTRL.3)
C8051F55x/56x/57x
115 Rev. 1.2
13.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions fo r the peripheral and the behavior of its interrupt-pending flag(s).
C8051F55x/56x/57x
Rev. 1.2 116
SFR Address = 0xA8; Bit-Addressable; SFR Page = All Pages
SFR Definition 13.1. IE: Interrupt Enable
Bit76543210
Name EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7EA Enable All Interrupts.
Globally enables/disables all inter rupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
6ESPI0 Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit set s the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
5ET2 Enable Timer 2 Interrupt.
This bit set s the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt request s generated by the TF2L or TF2H flags.
4ES0 Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UAR T0 interrupt.
3ET1 Enable Timer 1 Interrupt.
This bit set s the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
2EX1 Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
1ET0 Enable Timer 0 Interrupt.
This bit set s the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
0EX0 Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
C8051F55x/56x/57x
117 Rev. 1.2
SFR Address = 0xB8; Bit-Addressable; SFR Page = All Pages
SFR Definition 13.2. IP: Interrupt Priority
Bit76543210
Name PSPI0 PT2 PS0 PT1 PX1 PT0 PX0
Type RR/W R/W R/W R/W R/W R/W R/W
Reset 10000000
Bit Name Function
7Unused Read = 1b, Write = Don't Care.
6PSPI0 Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
5PT2 Timer 2 Interrupt Priority Control.
This bit sets the priority of th e Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupt set to high priority level.
4PS0 UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt se t to low priority level.
1: UART0 interrupt se t to high priority level.
3PT1 Timer 1 Interrupt Priority Control.
This bit sets the priority of th e Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupt set to high priority level.
2PX1 External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
1PT0 Timer 0 Interrupt Priority Control.
This bit sets the priority of th e Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
0PX0 External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
C8051F55x/56x/57x
Rev. 1.2 118
SFR Address = 0xE6; SFR Page = All Pages
SFR Definition 13.3. EIE1: Extended Interrupt Enable 1
Bit76543210
Name ELIN0 ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 ESMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7ELIN0 Enable LIN0 Interrupt.
This bit sets the masking of the LIN0 interrupt.
0: Disable LIN0 interrupts.
1: Enable interrupt requests generated by the LIN0INT flag.
6ET3 Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupt s.
1: Enable interrupt requests generated by the TF3 L or TF3H flags.
5ECP1 Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1 RIF or CP1FIF flags.
4ECP0 Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0 RIF or CP0FIF flags.
3EPCA0 Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
2EADC0 Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
1EWADC0 Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
0ESMB0 Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
C8051F55x/56x/57x
119 Rev. 1.2
SFR Address = 0xF6; SFR Page = 0x00 and 0x0F
SFR Definition 13.4. EIP1: Extended Interrupt Priority 1
Bit76543210
Name PLIN0 PT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PSMB0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PLIN0 LIN0 Interrupt Priority Control.
This bit sets the priority of the LIN0 interrupt.
0: LIN0 interrupts set to low priority level.
1: LIN0 interrupts set to high priority level.
6PT3 Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
5PCP1 Comparator0 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interru pt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
4PCP0 Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interru pt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
3PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
2PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high prior ity level.
1PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
0PSMB0 SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 inte rrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
C8051F55x/56x/57x
Rev. 1.2 120
SFR Address = 0xE7; SFR Page = All Pages
SFR Definition 13.5. EIE2: Extended Interrupt Enable 2
Bit76543210
Name EMAT ECAN0 EREG0
Type RRRRRR/W R/W R/W
Reset 00000000
Bit Name Function
7:3 Unused Read = 00000b; Write = Don’t Care.
2EMAT Enable Port Match Interrupt.
This bit sets the masking of the Port Match interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match
1ECAN0 Enable CAN0 Interrupts.
This bit sets the masking of the CAN0 interrupt.
0: Disable all CAN0 interrupts.
1: Enable interrupt requests generated by CAN0.
0EREG0 Enable Voltage Regulator Dropout Interrupt.
This bit sets the masking of the Voltage Regulator Dropout interrupt.
0: Disable the Voltage Regulator Dropout interrupt.
1: Enable the Voltage Regulator Dropout interrupt.
C8051F55x/56x/57x
121 Rev. 1.2
SFR Address = 0xF7; SFR Page = 0x00 and 0x0F
SFR Definition 13.6. EIP2: Extended Interrupt Priority Enabled 2
Bit76543210
Name PMAT PCAN0 PREG0
Type RRRRRR/W R/W R/W
Reset 00000000
Bit Name Function
7:3 Unused Read = 00000b; Write = Don’t Care.
2PMAT Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
1PCAN0 CAN0 Interrupt Priority Control.
This bit sets the priority of the CAN0 interrupt.
0: CAN0 interrupt set to low priority level.
1: CAN0 interrupt set to high priority level.
0PREG0 Voltage Regulator Dropout Interrupt Priority Control.
This bit sets the priority of the Voltage Regulator Dropout interrupt.
0: Voltage Regulator Dropout interrupt set to low prior ity level.
1: Voltage Regulator Dropout interrupt set to high priority level.
C8051F55x/56x/57x
Rev. 1.2 122
13.3. External Interrupts INT0 and INT1
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0 Polarity) and IN1PL (INT 1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “25.1. Timer 0 and Timer 1” on page 261) select level or
edge sensitive. Th e table below lists the possible con fig urations.
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 13.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Po rt pins without d isturbin g the periph eral that was assigne d the Port pi n via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure th e Crossbar to skip the selected pin( s).
This is accomplished by setting the associated bit in register XBR0 (see Section “19.3. Priority Crossbar
Decoder” on page 172 for complete det ails on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external inter-
rupts, respectively. If an INT0 or INT1 external interrupt is configu red as edge- se nsitive , the corre spon din g
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
IT0 IN0PL INT0 Interrupt IT1 IN1PL INT1 Interrupt
1 0 Active low, edge sensitive 1 0 Active low, edge sensitive
1 1 Active high, edge sensitive 1 1 Active high, edge sensitive
0 0 Active low, level sensitive 0 0 Active low, level sensitive
0 1 Active high, level sensitive 0 1 Active high, level sensitive
C8051F55x/56x/57x
123 Rev. 1.2
SFR Address = 0xE4; SFR Page = 0x0F
SFR Definition 13.7. IT01CF: INT0/INT1 Configuration
Bit76543210
Name IN1PL IN1SL[2:0] IN0PL IN0SL[2:0]
Type R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7IN1PL INT1 Polarity.
0: INT1 input is active low.
1: INT1 input is active high.
6:4 IN1SL[2:0] INT1 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT1. Note that this pin assignment is
independent of the Crossbar; INT1 will monitor the assigned Por t pin without disturb-
ing the peripheral that has been assigned the Port pin via the Cr ossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P1.0
001: Select P1.1
010: Select P1.2
011: Select P1.3
100: Select P1.4
101: Select P1.5
110: Select P1.6
111: Select P1.7
3IN0PL INT0 Polarity.
0: INT0 input is active low.
1: INT0 input is active high.
2:0 IN0SL[2:0] INT0 Port Pin Selection Bits.
These bits select which Port pin is assigned to INT0. Note that this pin assignment is
independent of the Crossbar; INT0 will monitor the assigned Por t pin without disturb-
ing the peripheral that has been assigned the Port pin via the Cr ossbar. The Crossbar
will not assign the Port pin to a peripheral if it is configured to skip the selected pin.
000: Select P1.0
001: Select P1.1
010: Select P1.2
011: Select P1.3
100: Select P1.4
101: Select P1.5
110: Select P1.6
111: Select P1.7
C8051F55x/56x/57x
Rev. 1.2 124
14. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft-
ware using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to
logic 1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and
erase operations are automatically timed by hardware for proper execution; data polling to determine the
end of the write/erase operation is not required. Code execution is stalled during a Flash write/erase oper-
ation. Refer to Table 5.5 for comple te Flash memory electrical characteristics.
14.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial-
ized device. For details on the C2 commands to program Flash memory, see Section “27. C2 Interface” on
page 300.
To ensure the integrity of Flash contents, it is strongly recommended that the on-chip VDD Monitor be
enabled in any system that includes cod e that writes and /or erases Flash memor y from sof tware. See Sec-
tion 14.4 for more details. Before performing any Flash write or erase procedure, set the FLEWT bit in
Flash Scale register (FLSCL) to 1. Also, note that 8-bit MOVX instructions cannot be used to erase or write
to Flash memory at addresses higher than 0x00FF.
For –I (Industrial Grade) parts, parts programmed at a cold temperature below 0 °C may exhibit weakly
programmed fla sh memory bit s. If pro grammed at 0 °C or h igh er, there is no p roblem r eading Flas h a cross
the entire temperature range of -40 °C to 125 °C. This temperature restriction does not apply to –A (Auto-
motive Grade) devices.
14.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be dis abled until th e next syste m reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be per-
formed. The FLKEY register is detailed in SFR Definition 14.2.
C8051F55x/56x/57x
125 Rev. 1.2
14.1.2. Flash Erase Procedure
The Flash memory can be pr ogrammed by so ftware u sing the MOVX write instruction with the address and
data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX,
Flash write operations must be enabled by doing the following: (1) setting the PSWE Program Store Write
Enable bit (PSC TL.0) to logic 1 (this dir ects the MOVX writes to target F lash me mory) ; and (2) Writing the
Flash key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared
by software.
A write to Flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits
to logic 1 in Flash. A byte loc ation to be prog rammed should be er ased befo re a new value is written.
The Flash memory is organized in 512-byte pages. The erase operation applies to an entire page (setting
all bytes in the page to 0xFF). To erase an entire 512-byte page, perform the following step s:
1. Disable interrupts (recommended).
2. Set the FLEWT bit (register FLSCL).
3. Set the PSEE bit (register PSCTL).
4. Set the PSWE bit (register PSCTL).
5. Write the first key code to FLKEY: 0x A5.
6. Write the second key code to FLKEY: 0xF1.
7. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased.
8. Clear the PSWE and PSEE bits.
14.1.3. Flash Write Procedure
Flash bytes are programmed by software with the following sequence:
1. Disable interrupts (recommended).
2. Erase the 512-byte Flash page containing the target location, as described in Section 14.1.2.
3. Set the FLEWT bit (register FLSCL).
4. Set the PSWE bit (register PSCTL).
5. Clear the PSEE bit (register PSCTL).
6. Write the first key code to FLKEY: 0x A5.
7. Write the second key code to FLKEY: 0xF1.
8. Using the MOVX instruction, write a single data byte to the desired location within the 512-byte sector.
9. Clear the PSWE bit.
Steps 5–7 must b e re peated for each b yt e t o be wr itte n . After Flas h writes are co mp le te, PSWE should be
cleared so that MOVX instructions do not target program memory.
C8051F55x/56x/57x
Rev. 1.2 126
14.1.4. Flash Write Optimization
The Flash write procedure includes a block write option to optimize the time to perform consecutive byte
writes. When block write is enabled by setting the CHBLKW bit (CCH0CN.0), writes to two consecutive
bytes in Flash require the same a mount of time as a single byte write . This is performed by cach ing the first
byte that is written to Flash and then committing both bytes to Flash when the second byte is written. When
block writes are enabled, if the second write does not occur, the first data byte written is not actually written
to Flash. Flash bytes with block write enabled are programmed by software with the following sequence:
1. Disable interrupts (recommended).
2. Erase the 512-byte Flash page containing the target location, as described in Section 14.1.2.
3. Set the FLEWT bit (register FLSCL).
4. Set the CHBLKW bit (register CCH0CN).
5. Set the PSWE bit (register PSCTL).
6. Clear the PSEE bit (register PSCTL).
7. Write the first key code to FLKEY: 0x A5.
8. Write the second key code to FLKEY: 0xF1.
9. Using the MOVX instruction, write the first data byte to the desired location within the 512- byte sector.
10.Write the first key code to FLKEY: 0xA5.
11.Write the second key code to FLKEY: 0xF1.
12.Using the MOVX instruction, write the second data byte to the desired location within the 512-byte
sector. The location of the second byte must be the next higher address from the first data byte.
13.Clear the PSWE bit.
14.Clear the CHBLKW bit.
C8051F55x/56x/57x
127 Rev. 1.2
14.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and r ead us ing the M OVC instructi on. Note: MOVX read instru ctions always t a rget XRAM.
14.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to 1 before software can modify the Flash memory; both PSWE and PSEE must be set to 1 before soft-
ware can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (re ads, writes, or er ases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x01FF), w here n is the ones complement number represented by the Security Lock Byte. Note that the
page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked
(all bits of the Lock Byte are 1) and locked when any other Flash pages are locked (any bit of the
Lock Byte is 0). See example in Figure 14.1.
Figure 14.1. Flash Program Memory Map
Lock Byte Page
Locked Flash Pages
Access limit set
according to the
FLASH secur ity
lock byte
Lock Byte
Reserved Area
Unlocked FLASH Pages
Locked when
any other FLASH
pages are locked
Security Lock Byte: 11111101b
1s Complement: 00000010b
Flash pages locked: 3 (First two Flash pages + Lock Byte Page)
C8051F55x/56x/57x
Rev. 1.2 128
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, an d user firmwar e executin g on lo cked pages. Tab le 14.1 summar izes the F lash secu rity
features of the C8051F55x/56x/57x devices.
Table 14.1. Flash Security Summary
Action C2 Debug
Interface User Firmware executing fr om :
an unlocked page a locked page
Read, Write or Erase unlocked pages
(except page with Lock Byte) Permitted Permitted Permitted
Read, Write or Erase locked pages
(except page with Lock Byte) Not Permit ted Flash Error Reset Permitted
Read or Write page containing Lock Byte
(if no pages are locked) Permitted Permitted Permitted
Read or Write page containing Lock Byte
(if any page is locked) Not Permitted Flash Error Reset Permitted
Read contents of Lock Byte
(if no pages are locked) Permitted Permitted Permitted
Read contents of Lock Byte
(if any page is locked) Not Permitted Flash Error Reset Permitted
Erase page containing Lock Byte
(if no pages are locked) Permitted Flash Error Reset Flash Error Reset
Erase page containing Lock Byte—Unlock all
pages ( if any page is locked) C2 Device
Erase Only Flash Error Reset Flash Error Reset
Lock additional pages
(change '1's to '0's in the Lock Byte) Not Permitted Flash Error Reset Flash Error Reset
Unlock individual pages
(change '0's to '1's in the Lock Byte) Not Permitted Flash Error Reset Flash Error Reset
Read, Write or Erase Reserved Area Not Permitted Flash Error Reset Flash Error Reset
C2 Device Erase—Erases all Fla sh pages including the page containing the Lock Byte.
Flash Error Reset—Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is '1' after
reset).
- All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset).
- Locking any Flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device re se t.
C8051F55x/56x/57x
129 Rev. 1.2
14.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating ra nge of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a sys tem failure tha t is only recover-
able by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
14.4.1. VDD Maintenance and the VDD monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power sup ply to ensu re that th e supp ly voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Make cert ain that the minimum VREGIN rise time specification of 1 ms is met. If the system cannot
meet this rise time specification, then add an e xternal VDD brownout circuit to the RST pin of the device
that holds the device in reset until VDD reaches the mini mum threshold and re-assert s RST if VDD drop s
below the minimum thresho ld.
3. Enable the on -chip VDD monitor in the high setting and enable the VDD monitor as a rese t s ource as
early in code as possible. This should be the first set of instructions executed after the Reset Vector.
For C-based systems, this will involve modifying the startup code added by the C compiler. See your
compiler documentation for more details. Make certain that there are no delays in software between
enabling the VDD monitor in the high setting and enabling the VDD monitor as a reset source. Code
examples showing this can be found in “AN201: Writing to Flash from Firmware", available from the
Silicon Laboratories web site.
4. As an added precaution, explicitly enable the VDD monitor in the high setting and enable the VDD
monitor as a reset source inside the functions that write and erase Flash memory. The VDD monitor
enable instructions should be placed just after the instruction to set PSWE to a 1, but before the Flash
write or erase operation instruction.
Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset
event. The output of the un-calibrated internal regulator could be below the high threshold setting of
the VDD Monitor. If this is the case and the VDD Monitor is set to the high threshold setting and if the
MCU receives a non-power on reset (POR), the MCU will remain in reset until a P OR oc cu rs (i.e .,
VDD Monitor will keep the device in reset). A POR will force the VDD Monitor to the low threshold
setting which is guaranteed to be below the un-calibr ated output of the intern al regulator . The device
will then exit reset and resume normal opera tion. It is for this reason Silicon Labs strongly
recommends that the VDD Monitor is always left in the low threshold setting (i.e. default value upon
POR). When programming the Flash in-system, the VDD Monitor must be set to the high threshold
setting. For the highest system r eliability, the time the VDD Monitor is set to the high threshold setting
should be minimize d (e.g., settin g the VDD Monitor to the high threshold setting just before the Flash
write operation and then changing it back to the low threshold setting immediately after the Flash
write operation).
5. Make cert ain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct. "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator , for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
C8051F55x/56x/57x
Rev. 1.2 130
14.4.2. PSWE Maintenance
1. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There should be
exactly one routine in code that set s PSWE to a 1 to write Flash bytes and one routine in co de that set s
PSWE and PSEE both to a 1 to erase Flash pages.
2. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop variable ma inte na nc e ou tside the "PSWE = 1;... PS WE = 0;" area . Cod e exam ple s sh owin g
this can be found in ”AN201: Writing to Flash from Firmware" available from the Silicon Laboratories
web site.
3. Disable inte r ru pts prior to set tin g PSWE to a 1 and leave them disabled until after PSWE has been
reset to '0'. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
4. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions regarding how to explicitly locate variables in different memory
areas.
5. Add address boun ds checking to th e routines th at write or erase Flas h memor y to ensu re that a r outine
called with an illegal address does not result in modification of the Flash.
14.4.3. System Clock
1. If operating from an external crystal, be advised that crystal performance is susceptible to electrical
interference and is sensitive to layout and to changes in temperatur e. If the system is operating in an
electrically noisy environment, use the internal oscillator or use an external CMOS clock.
2. If operating from the external oscillator, switch to the internal oscillator during Flash write or erase
operations. The external oscillator can continue to run, and the CPU can switch back to the external
oscillator after the Flash op eration has completed.
Additional Flash recommendations and examp le cod e can be found in “AN201: Writing to Flash from Firm-
ware" available from the Silicon Laboratories web site.
C8051F55x/56x/57x
131 Rev. 1.2
SFR Address = 0x8F; SFR Page = 0x00
SFR Definition 14.1. PSCTL: Program Store R/W Control
Bit76543210
Name PSEE PSWE
Type RRRRRRR/W R/W
Reset 00000000
Bit Name Function
7:2 Unused Read = 000000b, Write = don’t care.
1PSEE Program Store Erase Enable.
Setting this bit (in combination with PSWE) allows an entire page of Flash program
memory to be erased. If this bit is logic 1 and Fla sh writes are enabled (PSWE is logic
1), a write to Flash memory using the MOVX instruction will erase th e en tir e page that
conta ins the location addressed by the MOVX instruction. The value of the da ta byte
written does not matter.
0: Flash program memory erasure disabled.
1: Flash prog ram memory er asure enable d.
0PSWE Program Store Write Enable.
Setting this bit allows writing a byte of data to the Flash program memory using the
MOVX write instruction. The Flash locatio n should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX write instruction targets Flash
memory.
C8051F55x/56x/57x
Rev. 1.2 132
SFR Address = 0xB7; SFR Page = All Pages
SFR Definition 14.2. FLKEY: Flash Lock and Key
Bit76543210
Name FLKEY[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FLKEY[7:0] Flash Lock and Key Register.
Write:
This register provides a lock and key function for Flash erasures and writes. Flash
writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY regis-
ter. Flash writes and erases are automatically disable d after the next write or erase is
complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase
operation is atte m pte d while th es e op er at ion s ar e disabled, the Fla sh will be per m a-
nently locked from writes or erasures until the next device reset. If an application
never writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to
FLKEY from software.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writ es /e ra se s disa ble d until th e ne xt re se t.
C8051F55x/56x/57x
133 Rev. 1.2
SFR Address = 0xB6; SFR Page = All Pages
SFR Definition 14.3. FLSCL: Flash Scale
Bit76543210
Name Reserved Reserved Reserved FLRT Reserved Reserved FLEWT Reserved
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:5 Reserved Must Write 000b.
4FLRT Flash Read Time Control.
This bit should be program med to the smallest allowed value, according to the system
clock speed.
0: SYSCLK < 25 MHz (Flash read strobe is one system clock).
1: SYSCLK > 25 MHz (Flash read strobe is two system clocks).
3:2 Reserved Must Write 00b.
1FLEWT Flash Erase Write Time Control.
This bit should be set to 1b before Writing or Erasing Flash.
0: Short Flash Erase / Write Timing.
1: Extended Flash Erase / Write Timing.
0Reserved Must Write 0b.
C8051F55x/56x/57x
Rev. 1.2 134
SFR Address = 0xE3; SFR Page = 0x0F
SFR Address = 0xBE; SFR Page = 0x0F
SFR Definition 14.4. CCH0CN: Cache Control
Bit76543210
Name Reserved Reserved CHPFEN Reserved Reserved Reserved Reserved CHBLKW
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00100000
Bit Name Function
7:6 Reserved Must Write 00b
5CHPFEN Cache Prefect Enab le Bit.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
4:1 Reserved Must Write 0000b.
0CHBLKW Block Write Enable Bit.
This bit allows block writes to Flash memory from firmware.
0: Each byte of a software Flash write is written individually.
1: Flash bytes are writte n in gr ou ps of two.
SFR Definition 14.5. ONESHOT: Flash Oneshot Period
Bit76543210
Name PERIOD[3:0]
Type RRRRR/W R/W R/W R/W
Reset 00001111
Bit Name Function
7:4 Unused Read = 0000b. Write = don’t care.
3:0 PERIOD[3:0] Oneshot Period Control Bits.
These bit s limit the inter nal Flash read strob e width as fo llows. When the Flash read
strobe is de-asserted, the Flash memory enters a low-power state for the remainder
of the system clock cycle.
FLASHRDMAX 5ns PERIOD 5ns×()+=
C8051F55x/56x/57x
Rev. 1.2 135
15. Power Management Modes
The C8051F55x/56x/57x devices have three software programmable power management modes: Idle,
Stop, and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend
mode is an enhanced power-saving mode implemented by the high-spe ed oscillator peripheral.
Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted,
all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is
stopped (analog peripherals remain in their selected states; the external oscillator is not affected). Sus-
pend mode is similar to Stop mode in that the internal oscillator and CPU are halted, but the device can
wake on events such as a Port Match or Comparator low output. Since clocks are running in Idle mode,
power consumption is dependent upon the system clock frequency and the number of peripherals left in
active mode before entering Idle. Stop mode and Suspend mode consume the least power because the
majority of the device is shut down with no clocks active. SFR Definition 15.1 describes the Power Control
Register (PCON) used to control the C8051F55x/56x/57x devices’ Stop and Idle power management
modes. Suspend mode is controlled by the SUSPEND bit in the OSCICN register (SFR Definition 18.2).
Although the C8051F55x/56x/57x has Idle, Stop, and Suspend modes available, more control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog
peripheral ca n be disabled when no t in use and placed in low power mode. Digit al peripherals, such a s tim-
ers or serial buses, draw little power when they are not in use. Turning off oscillators lowers power con-
sumption considerably, at the expense of reduced functionality.
15.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the hardware to halt the CPU and enter Idle mode as
soon as the instruction that sets the bit completes execution. All internal registers and memory maintain
their original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs
during the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode
when a future interrupt occurs. Therefore, instructions that set the IDLE bit should be followed by an
instruction that has two or more opcode bytes, for example:
// in ‘C’:
PCON |= 0x01; // set IDLE bit
PCON = PCON; // ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h ; set IDLE bit
MOV PCON, PCON ; ... followed by a 3-cycle dummy instruction
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and ther eby termi-
nate the Idle mode. This featur e protect s the system from an unintended per manent sh ut down in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software p rior to ente ring th e Idle mode if the WDT was ini tially configure d to allow this operation. This pro-
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefi-
nitely, waiting for an external stimulus to wake up th e system. Refer to Section “1 6.6. PCA W atchdog Timer
Reset” on page 142 for more information on the use and configuration of the WDT.
C8051F55x/56x/57x
136 Rev. 1.2
15.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the
instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital
peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the device performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Dete ctor should be disa bled if the CPU is to be pu t to in ST OP mode for long er than th e
MCD timeout of 100 µs.
15.3. Suspend Mode
Setting the SUSPEND bit (OSCICN.5) causes the hardware to halt the CPU and the high-frequency inter-
nal oscillator, and go into Suspend mode as soon as the instruction that sets the bit completes execution.
All internal registers and memory maintain their original data. Most digita l periphe rals are not active in Sus-
pend mode. The exception to this is the Port Match feature.
Suspend mode can be terminate d by th ree typ es of eve nts, a port mat ch (des cribed in Section “ 19.5. Port
Match” on p age 179), a Comparator low output (if enabled), or a device reset event. When Suspend mode
is terminated, the device will continue execution on the instruction following the one that set the SUSPEND
bit. If the wake event was configured to generate an interrupt, the interrupt will be serviced upon waking
the device. If Suspend mode is terminated by an internal or external reset, the CIP-51 performs a normal
reset sequence and begins program execution at add ress 0x0000.
Note: Before entering suspend mode, firmware must set the ZTCEN bit in REF0CN (SFR Definition 7.1).
C8051F55x/56x/57x
Rev. 1.2 137
SFR Address = 0x87; SFR Page = All Pages
SFR Definition 15.1. PCON: Power Control
Bit76543210
Name GF[5:0] STOP IDLE
Type R/W R/W R/W
Reset 00000000
Bit Name Function
7:2 GF[5:0] General Purpose Flags 5–0.
These are general purpose flags for use under software control.
1STOP Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
0IDLE IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
Serial Ports, and Analog Peripherals are still active.)
C8051F55x/56x/57x
Rev. 1.2 138
16. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the da ta on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled
during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device
exits the re set state.
Note: When VIO rises faster than VDD, which can happen when VREGIN and VIO are tied together, a
delay created between GPIO power (VIO) and the logic controlling GPIO (VDD) results in a
temporary unknown state at the GPIO pins. When VIO rises faster than VDD, the GPIO may enter
the following states: floating, glitch low, or glitch high. Cross coupling VIO and VDD with a 4.7 µF
capacitor mitigates the root cause of the problem by allowing VIO and VDD to rise at the same rate.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. The W atch dog Timer is enabled with the syste m clock divided by 12 as its clock source. Pro-
gram execution begins at location 0x0000.
Figure 16.1. Reset Sources
PCA
WDT
Missing
Clock
Detector
(one-
shot) (Software Reset)
System Reset
Reset
Funnel
Px.x
Px.x
EN SWRSF
System
Clock CIP-51
Microcontroller
Core
Extended Interrupt
Handler
EN
WDT
Enable
MCD
Enable
Errant
FLASH
Operation
/RST
(wired-OR)
Power On
Reset
'0'
+
-
Comparator 0
C0RSEF
VDD
+
-
Supply
Monitor
Enable
C8051F55x/56x/57x
139 Rev. 1.2
16.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time
increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 16.2. plots the
power-on and VDD monitor reset timing.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to deter mine if a po we r-up wa s the cause of reset. The co nten t of inter na l da ta mem-
ory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a
power-on reset.
Note: For devices with a date code before year 2011, work week 24 (1124), if the /RST pin is held low for
more than 1 second while power is applied to the device, and then /RST is released, a percentage
of devices may lock up and fail to execute co de. Toggling the /RST pin does not clea r th e co ndition .
The condition is cleared by cycling power. Most devices that are affected will show the lock up
behavior only within a narrow range of temperatures (a 5 to 10 °C window). Parts with a date code
of year 2011, work week 24 (1124) or later do not have any restrictions on /RST low time. The date
code of a device is a four-digit number on the bottom-most line of each device with the format
YYWW, where YY is the two-digit calendar year and WW is the two digit work week.
Figure 16.2. Power-On and VDD Monitor Reset Timing
Power-On
Reset
VDD
Monitor
Reset
/RST
t
volts
1.0
2.0
Logic HIGH
Logic LOW TPORDelay
VDD
2.45
2.25 VRST
VDD
C8051F55x/56x/57x
Rev. 1.2 140
16.2. Power-Fail Reset/VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST p in low and hold the CIP-51 in a reset sta te (see Figure 16.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal dat a
memory content s are not altered by the power-fail rese t, it is impossible to determ ine if VDD dropped below
the level requir ed for data retention. If the PORSF flag reads 1, the data may no longer be valid. The VDD
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the VDD monitor is disabled by code and a software reset is performed, the
VDD monitor will still be disabled after the reset. To protect the integrity of Flash contents, the VDD
monitor must be enabled to the higher setting (VDMLVL = 1) and selected as a reset source if soft-
ware contains routines which erase or write Flash memory. If the VDD monitor is not enabled and
set to the high level, any erase or write performe d on Flash memory will cause a Flash Error device
reset.
Important Note: If the VDD monitor is being turned on from a disabled state, it should be enabled before it
is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabi-
lized may cause a system reset. In some applications, this reset may be undesirable. If this i s not desirabl e
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the VDD monitor and configuring it as a reset source from a disabled
state is as follows:
1. Enable the V DD monitor (VDMEN bit in VDM0CN = 1).
2. If necessary, wait for the VDD monitor to stabilize (see Table 5.4 for the VDD Monitor turn-on time).
Note: This delay should be omitted if software contains routines that erase or write Flash
memory.
3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 16.2 for VDD monitor timing; note that the power-on-reset delay is not incurred after a VDD
monitor reset. See Table 5.4 for complete electrical characteristics of the VDD monitor.
Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset
event. The output of the un-calibrated internal regulator could be below the high threshold setting of
the VDD Monitor. If this is the case and the VDD Monitor is set to the high threshold setting and if the
MCU receives a non-power on reset (POR), the MCU will remain in reset until a P OR oc cu rs (i.e .,
VDD Monitor will keep the device in reset). A POR will force the VDD Monitor to the low threshold
setting which is guaranteed to be below the un-calibr ated output of the intern al regulator . The device
will then exit reset and resume normal opera tion. It is for this reason Silicon Labs strongly
recommends that the VDD Monitor is always left in the low threshold setting (i.e. default value upon
POR).
When programming the Flash in-system, the VDD Monitor must be set to the high threshold setting. For the
highest system reliability, the time the VDD Monitor is set to the high threshold setting should be minimized
(e.g., setting the VDD Monitor to the high threshold setting just before the Flash write operation and then
changing it back to the low threshold setting immediately after the Flash write operation).
Note: The VDD Monitor may trigger on fast changes in voltage on the VDD pin, regardless of whether the
voltage increased or decreased.
C8051F55x/56x/57x
141 Rev. 1.2
SFR Address = 0xFF; SFR Page = 0x00
16.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin g enera tes a reset; an e xterna l pullup a nd/or deco upling o f the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 5.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
16.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the s yst em clock . If the syst em
clock remains high or low for more than the value specified in Table 5.4, “Reset Ele c tr ical Ch ar ac te rist ics, ”
on page 41, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag
(RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to
the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin is
unaffected by this reset.
SFR Definition 16.1. VDM0CN: VDD Monitor Control
Bit 7 6 5 4 3 2 1 0
Name VDMEN VDDSTAT VDMLVL
Type R/W RR/W R R R R R
Reset Varies Varies 0 0 0 0 0 0
Bit Name Function
7VDMEN VDD Monitor Enable.
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate sys-
tem resets until it is also selected as a reset source in register RSTSRC (SFR Defi-
nition 16.2). Selecting the VDD monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the VDD Monitor and selecting it as a
reset so urce. See Table 5.4 for the minimum VDD Monitor turn-on time.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
6VDDSTAT VDD Status.
This bit indicates the current powe r supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above th e V DD monitor threshold.
5VDMLVL VDD Monitor Level Select.
0: VDD Monitor Threshold is set to VRST-LOW
1: VDD Monitor Threshold is set to VRST -HIGH. This setting is required for any sys-
tem includes code that writes to and/or erases Flash.
4:0 Unused Read = 00000b; Write = Don’t care.
C8051F55x/56x/57x
Rev. 1.2 142
16.5. Comparator0 Reset
Comparator0 can be configured as a reset sourc e by writing a 1 to the C0RSEF flag (RSTSRC.5). Com -
parator0 should b e enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from gene rating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the
reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this reset.
16.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “26.4. Watchdog Timer Mode” on
page 291; the WDT is enabled and clocked by SYSCLK/12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The state of the RST pin is unaffected by this reset.
16.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attempted above user code sp ace. This occurs when PSWE is set to 1 and a
MOVX write operation t argets an address in or above the reserved space.
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address in or above the reserved space.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address in or above the reserved sp ace.
A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“14.3. Security Options” on page 127).
A Flash read, write, or erase is attempted when the VDD Monitor is not enabled to the high threshold
and set as a reset source.
The FERROR bit (RSTSRC.6) is set following a Flash erro r reset. The sta te of the RST pin is unaf fected by
this reset.
16.8. Soft ware Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
C8051F55x/56x/57x
143 Rev. 1.2
SFR Address = 0xEF; SFR Page = 0x00
SFR Definition 16.2. RSTSRC: Reset Source
Bit76543210
Name FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF
Type R R R/W R/W RR/W R/W R
Reset 0Varies Varies Varies Varies Varies Varies Varies
Bit Name Description Write Read
7Unused Unused. Don’t care. 0
6FERROR Flash Error Reset Flag. N/A Set to 1 if Flash
read/write/erase error
caused the last reset.
5C0RSEF Comparator0 Reset Enable
and Flag. Writing a 1 enables Com-
parator0 as a reset source
(active-low).
Set to 1 if Comparator0
caused the last reset.
4SWRSF Software Reset Force and
Flag. Writing a 1 forces a sys-
tem reset. Set to 1 if last reset was
caused by a write to
SWRSF.
3WDTRSF Wa tchdog Timer Reset Flag. N/A Set to 1 if W atchdog T imer
overflow caused the last
reset.
2MCDRSF Missing Clock Detector
Enable and Flag. Writing a 1 enables the
Missing Clock Detector.
The MCD triggers a reset
if a missing clock condition
is detected.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
1PORSF Power-On/VDD Monitor
Reset Flag, and VDD monitor
Reset Enable.
Writing a 1 enables the
VDD monitor as a reset
source.
Writing 1 to this bit
before the VDD monitor
is enabled and stabilized
may cause a system
reset.
Set to 1 anytime a power-
on or VDD monitor reset
occurs.
When set to 1 all other
RSTSRC flags are inde-
terminate.
0PINRSF HW Pin Reset Fl ag . N/A Set to 1 if RST pin caused
the last reset.
Note: Do not use read-modify-write operations on this register
C8051F55x/56x/57x
Rev. 1.2 144
17. External Data Memory Interface and On-Chip XRAM
For C8051F55x/56x/57x devices, 2 kB of RAM are included on-chip and mapped into the external data
memory spa ce (XRAM). Additionally, an External Memory Interface (EMIF) is available o n the C8051F5 68-
9 and ‘F570-5 devices, wh ich can b e used to a ccess of f-chip da t a memor ies and m emory-mapp ed devices
connected to the GPIO ports. The external memory space may be accessed using the external move
instruction (MOVX) and th e dat a pointer (DPT R), or using the MOVX indirect add ressing mod e using R0 or
R1. If the MOVX instruction is used with an 8-bit a ddress operand ( such as @R1), then the high byte of the
16-bit address is provided by the External Memory Interface Control Register (EMI0CN, shown in SFR
Definition 17.1).
Note: The MOVX instruction can also be used for writin g to the Flash me mory. See Section “14. Flash Memory” on
page 124 for details. The MOVX instruction accesses XRAM by default.
17.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The sec-
ond method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
17.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
MOV DPTR, #1234h ; load DPTR with 16-bit address to read (0x1234)
MOVX A, @DPTR ; load contents of 0x1234 into accumulator A
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed th rough th e SFR regi sters DPH, which cont ain s the uppe r 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
17.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the content s of the EMI0CN SFR to determ ine the upp er 8-bit s
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV EMI0CN, #12h ; load high byte of address into EMI0CN
MOV R0, #34h ; load low byte of address into R0 (or R1)
MOVX a, @R0 ; load contents of 0x1234 into accumulator A
C8051F55x/56x/57x
145 Rev. 1.2
17.2. Configuring the External Memory Interface
Configuring the External Memory Interfac e consists of four steps:
1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is
most common), and skip the associated pins in the crossbar.
2. Configure Port latches to “p ark” the EMIF pins in a dormant state (usually by setting them to logic 1).
3. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or
off-chip only).
4. Set up timing to inte r fac e with off-chip memor y or per iph er a ls.
Each of these four steps is explained in detail in the following sections. The Port selection and Mode bits
are located in the EMI0CF register shown in SFR Definition .
17.3. Port Configuration
The External Memory Interface appears on Ports 1, 2 and 3 when it is used for off-chip memory access.
These ports ar e multi plexed so th at low-ord er address lines ar e shared with the dat a lines. When the EMIF
is used, the Crossbar should be configured to skip over the /RD control line (P1.6) and the /WR control line
(P1.7) using the P1SKIP register and also skip over the ALE control line (P1.5). For more information
about configur ing the Cr ossb ar, see Section “19.6. Special Function Registers for Accessing and Configur-
ing Port I/O” on page 183. The EMIF pinout is shown inTable 17.1 on page 146.
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches or to the Cro ssbar settin gs for th ose pins . See Sect ion “19. Port Input/Out-
put” on page 169 for more information about the Crossbar and Port operation and configuration. The Port
latches should be explicitly configured to “park” the External Memory Interface pins in a dormant
state, most commonly by setting them to a logic 1.
During the execution of the MOVX instruction, the Extern al Memory In terface will ex plicitly disa ble th e driv-
ers on all Port pins that are actin g as Inpu ts (Data[7:0] during a READ operation, for exam ple). The Ou tp ut
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,
the output modes of all EMIF pins should be configu red for push-pull mode.
C8051F55x/56x/57x
Rev. 1.2 146
Table 17.1. EMIF Pinout (C8051F568-9 and ‘F570-5)
Multiplexed Mode
Signal Name Port Pin
RD P1.6
WR P1.7
ALE P1.5
D0/A0 P3.0
D1/A1 P3.1
D2/A2 P3.2
D3/A3 P3.3
D4/A4 P3.4
D5/A5 P3.5
D6/A6 P3.6
D7/A7 P3.7
A8 P2.0
A9 P2.1
A10 P2.2
A11 P2.3
A12 P2.4
A13 P2.5
A14 P2.6
A15 P2.7
C8051F55x/56x/57x
147 Rev. 1.2
SFR Address = 0xAA; SFR Page = 0x00
SFR Definition 17.1. EMI0CN: External Memory Interface Control
Bit76543210
Name PGSEL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 PGSEL[7:0] XRAM Page Select Bits.
The XRAM Page Select Bits provide the h igh byte of the 16-bit external data memory
address when using an 8-b it MOVX command, effectively selecting a 256-byte page of
RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF
C8051F55x/56x/57x
Rev. 1.2 148
SFR Address = 0xB2; SFR Page = 0x0F
SFR Definition 17.2. EMI0CF: External Memory Configuration
Bit76543210
Name Reserved EMD[1:0] EALE[1:0]
Type R/W
Reset 00000011
Bit Name Function
7:5 Unused Read = 000b; Write = Don’t Care.
4Reserved Read = 0b; Must Write 0b.
3:2 EMD[1:0] EMIF Operating Mode Select Bits.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to
on-chip memory space
01: Split Mode without Bank Select: Accesses below the 2 kB boundary are directed
on-chip. Accesses above the 2 kB boundary are directed off-chip. 8-bit off-chip MOVX
operations use curr ent contents of the Address high port latches to resolve the upper
address byte. To access off chip space, EMI0CN must be set to a page that is not con-
tained in the on-chip address space.
10: Split Mode with Bank Select: Accesses below the 2 kB boundary are directed on-
chip. Accesses above the 2 kB boundary are directed off-chip. 8-bit off-chip MOVX
operations uses the contents of EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to
the CPU.
1:0 EALE[1:0] ALE Pulse-Width Select Bits.
These bits only have an effect when EMD2 = 0.
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
C8051F55x/56x/57x
149 Rev. 1.2
17.4. Multiplexed Mode
The External Memory Interface operates only in a Multiplexed mode. In Multiplexed mode, the Data Bus
and the lower 8-bits of th e Add ress B us sha re t he sam e Port p ins: AD[7: 0]. In th is mo de, an exter nal la tch
(74HC373 or equivalent logic gate) is used to hold the lower 8-bits of the RAM address. The external latch
is controlled by the ALE (Address Latch Enable) signal, which is driven by the External Memory Interface
logic. An example of a Multiplexed Configur ation is shown in Figure 17.1.
In Multiplexed m ode, the extern al MOVX ope ration c an be broken into two phases delineated by the state
of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are pre-
sented to AD[7:0]. During this phase, the address latch is configured such that the Q outputs reflect the
states of the ‘D’ inputs. When ALE falls, signaling the beginning of the second phase, the address latch
outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data
Bus controls the state of the AD[7:0] port at the time RD or WR is asserted.
See Section “17.6.1. Multiplexed Mode” on page 153 for more information.
Figure 17.1. Multiplexed Configuration Example
ADDRESS/DATA BUS
ADDRESS BUS
E
M
I
F
A[15:8]
AD[7:0]
/WR
/RD
ALE
64 K X 8
SRAM
OE
WE
I/O[7:0]
74HC373
G
DQ
A[15:8]
A[7:0]
CE
VDD
8(Optional)
C8051F55x/56x/57x
Rev. 1.2 150
17.5. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 17.2, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 17.2). These modes are summarized below.
More information about the different modes can be found in Section “17.6. Timing” on page 151.
Figure 17.2. EMIF Operating Modes
17.5.1. Internal XRAM Only
When bits EMI0CF[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the
device. Memory accesses to addresses beyond the populated space will wrap on 2 kB boundaries. As an
example, the addresses 0x800 and 0x1 000 both evaluate to address 0x0000 in on-chip XRAM space.
8-bit MOVX operations use the contents of EMI0CN to determine the high-b yte of the ef fe ctive address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
17.5.2. Split Mode without Bank Select
When bit EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and off-
chip space.
Effe ctive addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-
chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Addre ss Bus du rin g an off-chip acces s. Th is allo ws th e use r to manip ula te
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with “S plit Mode with Bank Select” described below . The lower 8-bit s of the Address Bus A[7:0]
are driven, dete rmined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven
during the off-chip transaction.
EMI0CF[3:2] = 00 0xFFFF
0x0000
EMI0CF[3:2] = 11 0xFFFF
0x0000
EMI0CF[3:2] = 01 0xFFFF
0x0000
EMI0CF[3:2] = 10
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
Off-Chip
Memory
(No Bank Select)
On-Chip XRAM
0xFFFF
0x0000
Off-Chip
Memory
(Bank Select)
On-Chip XRAM
Off-Chip
Memory
C8051F55x/56x/57x
151 Rev. 1.2
17.5.3. Split Mode with Bank Select
When EMI0CF[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and off-
chip space.
Effe ctive addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-
chip or of f-chip. The up per 8-bit s of th e Address Bus A[1 5:8] are determined by EMI0CN, and the lower
8-bits o f the Address Bus A[7:0] are d etermined by R0 or R1. All 16-bit s of the Add ress Bus A[15:0] are
driven in “Bank Select” mode.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and the full 16-bits of the Address Bus A[15:0] are driven during the of f-chip transaction.
17.5.4. External Only
When EMI0CF[3:2] are set to 11, all MOVX operations are directed to of f- chip spa ce. On-chip XRAM is not
visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the
internal XRAM size boundary.
8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven
(identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This
allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower
8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full
16-bits of the Address Bus A[15 :0 ] ar e dr iven du rin g the off-chip transaction.
17.6. Timing
The timing parameters of the External Memory Interface can be configured to enable connection to
devices having different setup and hold time requirements. The Address Setup time, Address Hold time,
RD and WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in
units of SYSCLK periods through EMI0TC, shown in SFR Definition 17.3, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing
parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution
time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for RD or WR pulse + 4 SYSCLKs).
For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional
SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in multiplexed
mode is 7 SYSCLK cycles (2 for /ALE + 1 for RD or WR + 4). The programmable setup and hold times
default to the maximum delay settings after a reset. Table 17.2 lists the ac parameters for the External
Memory Interface, and Figure 17.3 through Figure 17.5 show the timing diagrams for the different External
Memory Interface modes and MOVX operations.
C8051F55x/56x/57x
Rev. 1.2 152
SFR Address = 0xAA; SFR Page = 0x0F
SFR Definition 17.3. EMI0TC: External Memory Timing Control
Bit76543210
Name EAS[1:0] EWR[3:0] EAH[1:0]
Type R/W R/W R/W
Reset 11111111
Bit Name Function
7:6 EAS[1:0] EMIF Address Setup Time Bits.
00: Address setup time = 0 SYSCLK cycles.
01: Address setup time = 1 SYSCLK cycle.
10: Address setup time = 2 SYSCLK cycles.
11: Address setup time = 3 SYSCLK cycles.
5:2 EWR[3:0] EMIF WR and RD Pulse-Width Control Bits.
0000: WR and RD pulse width = 1 SYSCLK cycle.
0001: WR and RD pulse width = 2 SYSCLK cycles.
0010: WR and RD pulse width = 3 SYSCLK cycles.
0011: WR and RD pulse width = 4 SYSCLK cycles.
0100: WR and RD pulse width = 5 SYSCLK cycles.
0101: WR and RD pulse width = 6 SYSCLK cycles.
0110: WR and RD pulse width = 7 SYSCLK cycles.
0111: WR and RD pulse width = 8 SYSCLK cycles.
1000: WR and RD pulse width = 9 SYSCLK cycles.
1001: WR and RD pulse width = 10 SYSCLK cycles.
1010: WR and RD pulse width = 11 SYSCLK cycles.
1011: WR and RD pulse width = 12 SYSCLK cycles.
1100: WR and RD pulse width = 13 SYSCLK cycles.
1101: WR and RD pulse width = 14 SYSCLK cycles.
1110: WR and RD pulse width = 15 SYSCLK cycles.
1111: WR and RD pulse width = 16 SYSCLK cycles.
1:0 EAH[1:0] EMIF Address Hold Time Bits.
00: Address hold time = 0 SYSCLK cycles.
01: Address hold time = 1 SYSCLK cycle.
10: Address hold time = 2 SYSCLK cycles.
11: Address hold time = 3 SYSCLK cycles.
C8051F55x/56x/57x
153 Rev. 1.2
17.6.1. Multiplexed Mode
17.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011
Figure 17.3. Multiplexed 16-bit MOVX Timing
ADDR[15:8]
AD[7:0]
TACH
TWDH
TACW
TACS
TWDS
ALE
WR
RD
EMIF ADDRESS (8 MSBs) from DPH
EMIF WRITE DATA
EMIF ADDRESS (8 LSBs) from
DPL
TALEH TALEL
ADDR[15:8]
AD[7:0]
TACH
TACW
TACS
ALE
RD
WR
EMIF ADDRESS (8 MSBs) from DPH
EMIF ADDRESS (8 LSBs) from
DPL
TALEH TALEL TRDH
TRDS
EMIF READ DATA
Muxed 16-bit WRIT E
Muxed 16-bit READ
C8051F55x/56x/57x
Rev. 1.2 154
17.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011
Figure 17.4. Multiplexed 8-bit MOVX without Bank Select Timing
ADDR[15:8]
AD[7:0]
TACH
TWDH
TACW
TACS
TWDS
ALE
WR
RD
EMIF WRITE DATA
EMIF ADDRESS (8 LSB s) from
R0 or R1
TALEH TALEL
ADDR[15:8]
AD[7:0]
TACH
TACW
TACS
ALE
RD
WR
EMIF ADDRESS (8 LSB s) from
R0 or R1
TALEH TALEL TRDH
TRDS
EMIF READ DATA
Muxed 8-bit WRITE Without Bank Select
Muxed 8-bit READ Without Bank Select
C8051F55x/56x/57x
155 Rev. 1.2
17.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010
Figure 17.5. Multiplexed 8-bit MOVX with Bank Select Timing
ADDR[15:8]
AD[7:0]
TACH
TWDH
TACW
TACS
TWDS
ALE
WR
RD
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF WRITE DATA
EMIF ADDRESS (8 LSBs) from
R0 or R1
TALEH TALEL
ADDR[15:8]
AD[7:0]
TACH
TACW
TACS
ALE
RD
WR
EMIF ADDRESS (8 MSBs) from EMI0CN
EMIF ADDRESS (8 LSBs) from
R0 or R1
TALEH TALEL TRDH
TRDS
EMIF READ DATA
Muxed 8-bi t WRITE with Bank Select
Muxed 8-bit READ with Bank Select
C8051F55x/56x/57x
Rev. 1.2 156
Table 17.2. AC Parameters for External Memory Interface
Parameter Description Min* Max* Units
TACS Address/Control Setup Time 0 3 x TSYSCLK ns
TACW Address/Control Pulse Width 1 x TSYSCLK 16 x TSYSCLK ns
TACH Address/Control Hold Time 0 3 x TSYSCLK ns
TALEH Address Latc h Ena b le High Time 1 x TSYSCLK 4 x TSYSCLK ns
TALEL Address Latch Enab l e Low Time 1 x TSYSCLK 4 x TSYSCLK ns
TWDS Write Data Setup Time 1 x TSYSCLK 19 x TSYSCLK ns
TWDH W rite Data Hold Time 0 3 x TSYSCLK ns
TRDS Read Data Setup Time 20 ns
TRDH Read Data Hold Time 0ns
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
C8051F55x/56x/57x
Rev. 1.2 157
18. Oscillators and Clock Selection
C8051F55x/56x/57x devices include a programmable internal high-frequency oscillator, an external oscil-
lator drive circuit, and a clock multiplier. The internal oscillator can be enabled/disabled and calibrated
using the OSCICN, OSCICRS, and OSCIFIN registers, as shown in Figure 18 .1 . Th e system cl oc k ca n be
sourced by the external oscillator circuit or the internal oscillator. The clock multiplier can produce three
possible base outputs which can be scaled by a programmable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or
1/3), or 2/7: Internal Oscillator x 2, Internal Oscillator x 4, External Oscillator x 2, or External Oscilla to r x 4.
Figure 18.1. Oscillator Options
18.1. System Clock Selection
The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the exter-
nal oscillator may still clock certain periph erals (timers, PCA) when the internal oscillator is selected as the
system clock. The system clock may be switched on-the-fly between th e internal oscillator , external oscilla-
tor, and Clock Multiplier so long as the selected clock source is en abled and has settled.
The internal oscillator r equires l ittle st art-u p time and may be selected as the system clock immediately fol-
lowing the register write which enables the oscillator. The ex ternal RC and C modes also ty pically require
no startup time.
External crystals and ceramic resonators however, ty pically require a start-up time befo re they are s ettled
and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to 1 by hardware when the
external crystal or ceramic resonator is settled. In crystal mode, to avoid reading a false XTLVLD, soft-
ware should delay at least 1 ms between enabling the external oscillator and checking XTLVLD.
OSC
Programmable Internal
Clock Generator
Input
Circuit
EN
SYSCLK
n
OSCICRS OSCICN
IOSCEN
IFRDY
SUSPEND
IFCN1
IFCN0
XTAL1
XTAL2
Option 2
VDD
XTAL2
Option 1
10MΩ
Option 3
XTAL2
Option 4
XTAL2
OSCXCN
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
XFCN2
XFCN1
XFCN0
OSCIFIN CLKSEL
SEL1
SEL0
IFCN2
CLKMUL
MULEN
MULINIT
MULRDY
MULDIV2
MULDIV0
MULSEL1
MULSEL0
MULDIV1
nx4
IOSC / 2
EXOSC / 2
IOSC
EXTOSC
IOSC
EXOSC
CLOCK MULTIPLIER
CAL
C8051F55x/56x/57x
158 Rev. 1.2
SFR Address = 0x8F; SFR Page = 0x0F
SFR Definition 18.1. CLKSEL: Clock Select
Bit76543210
Name CLKSL[1:0]
Type RRRRRR R/W
Reset 00000000
Bit Name Function
7:2 Unused Read = 000000b; Wr ite = Don’t Care
1:0 CLKSL[1:0] System Clock Sourc e Sel ect Bits.
00: SYSCLK derived from the Internal Oscillator and scaled per the IFCN bits in reg-
ister OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the Clock Multiplier.
11: reserved.
C8051F55x/56x/57x
Rev. 1.2 159
18.2. Programmable Internal Oscillator
All C8051F55x/5 6x/57 x dev ices inc lude a prog ram mabl e intern al high -fre quenc y os cillator that defaults as
the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICRS and
OSCIFIN registers defined in SFR Definition 18.3 and SFR Definition 18.4. On C8051F55x/56x/57x
devices, OSCICRS and OSCIFIN are factory calibrated to obtain a 24 MHz base frequency. Note that the
system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, 8, 16, 32, 64, or
128, as defined by the IFCN bits in register OSCICN. The divide value defaults to 128 following a reset.
18.2.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
Port 0 Match Even t.
Port 1 Match Even t.
Port 2 Match Even t.
Port 3 Match Even t.
Comparator 0 enabled and output is logic 0.
When one of the oscillator awakening event s occur, the internal oscillator, CIP-51, and affe cted peripher als
resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes
execution at the instruction following the write to SUSPEND.
Note: Before entering suspend mode, firmware must set the ZTCEN bit in REF0CN (SFR Definition 7.1).
C8051F55x/56x/57x
160 Rev. 1.2
SFR Address = 0xA1; SFR Page = 0x0F
SFR Definition 18.2. OSCICN: Internal Oscillator Control
Bit 7 6 5 4 3 2 1 0
Name IOSCEN[1:0] SUSPEND IFRDY Reserved IFCN[2:0]
Type R/W R/W R/W R R R/W
Reset 1 1 0 X 0 0 0 0
Bit Name Function
7:6 IOSCEN[1:0] Internal Oscillator Enable Bits.
00: Oscillator Disabled.
01: Reserved.
10: Reserved.
11: Oscillator enabled in normal mode and disabled in suspend mode.
5SUSPEND Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The inter-
nal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
Before entering suspend mode, firmware must set the ZTCEN bit in REF0CN.
4IFRDY Internal Oscillator Frequency Ready Flag.
Note: This flag may not accurately reflect the state of the oscillator. Firmware should
not use this flag to determine if the oscillator is running.
0: Internal oscillator is not running at programmed frequency.
1: Internal oscillator is running at programmed frequency.
3Reserved Read = 0b; Must Write = 0b.
2:0 IFCN[2:0] Internal Oscillator Frequency Divider Control Bits.
000: SYSCLK derived from Internal Oscillator divided by 128.
001: SYSCLK derived from Internal Oscillator divided by 64.
010: SYSCLK derived from Internal Oscillator divided by 32.
011: SYSCLK derived from Internal Oscillator divided by 16.
100: SYSCLK derived from Internal Oscillator divided by 8.
101: SYSCLK derived from Internal Oscillator divided by 4.
110: SYSCLK derived from Internal Oscillator divided by 2.
111: SYSCLK derived from Internal Oscillator divided by 1.
C8051F55x/56x/57x
Rev. 1.2 161
SFR Address = 0xA2; SFR Page = 0x0F
SFR Address = 0x9E; SFR Page = 0x0F
SFR Definition 18.3. OSCICRS: Internal Oscillator Coarse Calibration
Bit76543210
Name OSCICRS[6:0]
Type RR/W
Reset 0Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7Unused Read = 0; Write = Don’t Care
6:0 OSCICRS[6:0] Internal Oscillator Coarse Calibration Bits.
These bits determine the internal oscillator period. When set to 0000000b, the
internal oscillator operates at its slowest setting. When set to 1111111b, the inter-
nal oscillator operates at its fastest setting. The reset value is factory calibrated
to generate an internal oscillator frequency of 24 MHz.
SFR Definition 18.4. OSCIFIN: Internal Oscillator Fine Calibration
Bit76543210
OSCIFIN[5:0]
Type R R R/W
Reset 0 0 Varies Varies Varies Varies Varies Varies
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care
5:0 OSCIFIN[5:0] Internal Oscillator Fine Calibration Bits.
These bits are fine adjustment for the internal oscillator period. The reset value is
factory calibrated to generate an internal oscillator frequency of 24 MHz.
C8051F55x/56x/57x
162 Rev. 1.2
C8051F55x/56x/57x
Rev. 1.2 162
18.3. Clock Multiplier
The Clock Multip lier genera tes an outp ut clock wh ich is 4 times th e input clock fr equency sc aled by a p ro-
grammable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or 2/7. The Clock Multiplier’s input can be
selected from the external oscillator, or the internal or external oscill ators divided by 2. This produces three
possible base outputs which can be scaled by a programmable factor: Internal Oscillator x 2, External
Oscillator x 2, or External Oscillato r x 4. See Sect ion 18.1 on page 157 for details on system clock selec -
tion.
The Clock Multiplier is configured via the CLKMUL register (SFR Definition 18.5). The procedure for con-
figuring and enabling the Clock Multiplier is as follows:
1. Reset the Multiplier by writing 0x00 to register CLKMUL.
2. Select the Multiplier input source via the MULSEL bits.
3. Select the Mult iplier ou tp ut scalin g fa cto r via th e MU LDIV bits
4. Enable the Mu ltip lier with th e MU LEN bit (CLKMUL | = 0x80 ).
5. Delay for >5 µs.
6. Initialize the Multiplier with the MU LI NIT bit (CLKMUL | = 0xC0).
7. Poll for MULRDY > 1.
Important No te: When us ing an external oscillator as the input to the Clock Multiplier, the external source
must be enabled and stable before the Multiplier is initialized. See “18.4. External Oscillator Drive Circuit”
on page 164 for details on selecting an external oscillator source.
The Clock Multiplier allows faster operation of the CIP-51 core and is intended to generate an output fre-
quency between 25 and 50 MHz. The clock multiplier can also be used with slow input clocks. However, if
the clock is below the minimum Clock Multiplier input frequency (FCMmin), the generated clock will consist
of four fast pulses followed by a long delay until the next input clock rising edge. The average freque ncy of
the output is equal to 4x the input, but the instantaneous frequency may be faster. See Figure 18.2 below
for more informa tio n.
Figure 18.2. Example Clock Multiplier Output
if FCM >= FCMmin
in
FCM
in
FCM
out
if FCM < FCMminin
FCM
out
FCM
in
C8051F55x/56x/57x
163 Rev. 1.2
SFR Address = 0x97; SFR Page = 0x0F
SFR Definition 18.5. CLKMUL: Clock Multiplier
Bit76543210
Name MULEN MULINIT MULRDY MULDIV[2:0] MULSEL[1:0]
Type R/W R/W RR/W R/W
Reset 00000000
Bit Name Function
7MULEN Clock Multiplier Enable.
0: Clock Multiplier disabled.
1: Clock Multiplier enabled.
6MULINIT Clock Multiplier Initialize.
This bit is 0 when the Clock Multip lier is enabled. Once enabled, writing a 1 to this
bit will initialize the Clock Multiplier. The MULRDY bit reads 1 when the Clock Mul-
tiplier is stabilized.
5MULRDY Clock Multiplier Ready.
0: Clock Multiplier is not ready.
1: Clock Multiplier is ready (PLL is locked).
4:2 MULDIV[2:0] Clock Multiplier Output Scaling Factor.
000: Clock Multiplier Output scaled by a factor of 1.
001: Clock Multiplier Output scaled by a factor of 1.
010: Clock Multiplier Output scaled by a factor of 1.
011: Clock Multiplier Output scaled by a factor of 2/3*.
100: Clock Multiplier Output scaled by a factor of 2/4 (1/2).
101: Clock Multiplier Output scaled by a factor of 2/5*.
110: Clock Multiplier Output scaled by a factor of 2/6 (1/3).
111: Clock Multiplier Output scaled by a factor of 2/7*.
*Note: The Clock Multiplier output duty cycle is not 50% for these settings.
1:0 MULSEL[1:0] Clock Multiplier Input Select.
These bits select the clock supp lied to th e Cloc k Mu ltip lier
MULSEL[1:0] Selected Input Clock Clock Multiplier Output
for MULDIV[2:0] = 000b
00 Internal Oscillat or Internal Oscillator x 2
01 External Oscillator External Oscillat or x 2
10 Internal Oscillat or Internal Oscillator x 4
11 External Oscillator External Oscillat or x 4
Notes:The maximum system clock is 50 MHz, and so the Clock Multiplier output should be scaled accordingly.
If Internal Oscillator x 2 or External Oscillator x 2 is selected using the MULSEL bits, MULDIV[2:0] is ignored.
C8051F55x/56x/57x
Rev. 1.2 164
18.4. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys-
tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 18.1. A
10 MΩ resistor also must be wired across the XTAL2 and XTAL1 pins for the crystal/resonator configura-
tion. In RC, capacitor, or CMOS cloc k configuration, the clock source should be wired to the XTAL2 pin as
shown in Op tion 2, 3 , o r 4 of Fi gure 18.1. Th e typ e of ex tern al os cillator mu st be sele cted in t he OS CXCN
register, and the frequency control bits (XFCN) must be selected appr opriately (see SFR Definition 18.6).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is used as XTAL2. The Port I/O Crossbar
should be configured to skip the Port pins used by the oscillator circuit; see Section “19.3. Priority Crossbar
Decoder” on page 172 for Crossbar configuration. Additionally, when using the external oscillator circuit in
crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs.
In CMOS clock mode, the associated pin should be configured as a digital input. See Section “19.4. Port
I/O Initialization” on page 174 for details on Port input mode selection.
C8051F55x/56x/57x
165 Rev. 1.2
SFR Address = 0x9F; SFR Page = 0x0F
SFR Definition 18.6. OSCXCN: External Oscillator Control
Bit76543210
Name XTLVLD XOSCMD[2:0] XFCN[2:0]
Type RR/W RR/W
Reset 00000000
Bit Name Function
7XTLVLD Crystal Oscillator Valid Flag.
(Read only when XOSCMD = 11x.)
0: Crystal Oscillator is unused or not yet stable.
1: Crystal Oscillator is running an d stable.
6:4 XOSCMD[2:0] External Oscillator Mode Select.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode.
101: Capacitor Oscillator Mode.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
3Unused Read = 0b; Write =0b
2:0 XFCN[2:0] External Oscillator Fr equency Control Bits.
Set according to the desired frequency for Crystal or RC mode.
Set according to the desired K Factor for C mode.
XFCN Crystal Mode RC Mode C Mode
000 f ≤ 32 kHz f ≤ 25 kHz K Factor = 0.87
001 32 kHz < f ≤ 84 kHz 25 kHz < f ≤ 50 kHz K Fact or = 2.6
010 84 kHz < f ≤ 225 kHz 50 kHz < f ≤ 100 kHz K Factor = 7.7
011 225 kHz < f ≤ 590 kHz 100 kHz < f ≤ 200 kHz K Factor = 22
100 590 kHz < f ≤ 1.5 MHz 200 kHz < f ≤ 400 kHz K Factor = 65
101 1.5 MHz < f ≤ 4 MHz 400 kHz < f ≤ 800 kHz K Factor = 180
110 4 MHz < f ≤ 10 MHz 800 kHz < f ≤ 1.6 MHz K Factor = 664
111 10 MHz < f ≤ 30 MHz 1.6 MHz < f ≤ 3.2 MHz K Factor = 1590
C8051F55x/56x/57x
Rev. 1.2 166
18.4.1. External Crysta l Example
If a crystal or ceramic resonator is used as an external os cillator source for the M CU, th e cir cuit sh ould be
configured as shown in Figure 18.1, Option 1. The External Oscillator Frequency Control value (XFCN)
should be chosen from the Crystal column of the table in SFR Definition 18.6 (OSCXCN register). For
example, an 11.0592 MHz crystal requires an XFCN setting of 111b and a 32.768 kHz Watch Crystal
requires an XFCN setting of 001b. After an external 32.768 kHz oscillator is stabilized, the XFCN setting
can be switched to 000 to save power. It is recommended to enable the missing clock detector before
switching the system clock to any external oscillat or sou rce .
When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time
to achieve proper bias. Introducing a delay of 1 ms between enabling the oscillator and checking the
XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the
external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. Th e rec-
ommended procedure is:
1. Force XTAL1 and XTAL2 to a high state. This involves enabling the Crossbar and writing 1 to the port
pins associated with XTAL1 and XTAL2.
2. Configure XTAL1 and XTAL2 as analog inputs using.
3. Enable the ext er na l osc illato r.
4. Wait at least 1 ms.
5. Poll for XTLVLD => 1.
6. Enable the Mis sing C loc k Dete ct or.
7. Switch the system clock to the external oscillator.
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with
the stray capacitance of the XTAL1 and XTAL2 pins.
Note: The desired load capacitance depends upon the crystal and the manufacturer. Refer to the crystal data sheet
when completing these calculations.
For example, a tuning-fork cry stal of 32.768 kHz with a recommended load capacitance of 12.5 pF should
use the configuration shown in Figur e 18.1, Option 1. The to tal val ue of the cap acitors and the stray cap ac-
itance of the XTAL pins should equal 25 pF. With a stray capa citance of 3 pF per pin, the 22 pF capacitors
yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 18.3.
C8051F55x/56x/57x
167 Rev. 1.2
Figure 18.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram
18.4.2. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in Figure 18.1, Option 2. The capacitor should be no greater than 100 pF; however for very small
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter-
mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation, according to Equation 18.1,
where f = the frequency of oscillation in MHz, C = the capacitor value in pF, and R = the pull-up resistor
value in kΩ.
Equation 18.1. RC Mode Oscillator Frequency
For example: If the frequency desired is 100 kHz, let R = 246 kΩ and C = 50 pF:
f = 1.23(103)/RC = 1.23(103)/[246 x 50] = 0.1 MHz = 100 kHz
Referring to the table in SFR Definition 18.6, the required XFCN setting is 010b.
18.4.3. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 18.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors,
the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capaci-
tor to be used and find the fr equ ency of o scillation acco rding to Equation , where f = the frequency of oscil-
lation in MHz, C = the capacito r value in pF, and VDD = the MCU power supply in Volts.
XTAL1
XTAL2
10MΩ
22pF*22pF* 32.768 kHz
* Capacitor values depend on
crystal specifications
f1.2310
3
×RC×()⁄=
C8051F55x/56x/57x
Rev. 1.2 168
Equation 18.2. C Mode Oscillator Frequency
For example: Assume VDD = 2.1 V and f = 75 kHz:
f = KF / (C x VDD)
0.075 MHz = KF / (C x 2.1)
Since the frequency of roughly 75 kHz is desired, select the K Factor from the table in SFR Definition 18.6
(OSCXCN) as KF = 7.7:
0.075 MHz = 7.7 / (C x 2.1)
C x 2.1 = 7.7 / 0.075 MHz
C = 102.6 / 2.0 pF = 51.3 pF
Therefore, the XFCN value to use in this example is 010b.
fKF()RV
DD
×()⁄=
C8051F55x/56x/57x
Rev. 1.2 169
19. Port Input/Output
Digital and analog resources are available through 33 (C8051F568-9 and ‘F570-5), 25 (C8051F550-7) or
18 (C8051F 550 -7) I/ O pins . Port p ins P0.0-P 4.0 o n the C8051F568-9 and ‘F570-5, port pins P0.0-P3.0 on
theC8051F560-7, and port pins P0.0-P2.1 on the C8051F550-7 can be defined as general-purpose I/O
(GPIO), assigned to one of the internal digital resources, or assigned to an analog function as shown in
Figure 19.3. Port pin P4.0 on the C8051F568-9 and ‘F570-5 can be used as GPIO and is shared with the
C2 Interfac e Data signal (C2D ). Similarly, por t pin P3.0 is shared with C2D on the C8051F560-7 and port
pin P2.1 on the C8051F550-7. The designer has complete control over which functions are assigned, lim-
ited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the
use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corre-
sponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 19.3 and Figure 19.4). The registers XBR0, XBR1, XBR2 are defined in SFR Definition 19.1 and
SFR Definition 19.2 and are used to select internal digital functions.
The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers
(PnMDOUT, where n = 0,1). Complete Electrical Specifications for Port I/O are given in Table 5.3 on
page 40.
Figure 19.1. Port I/O Functional Block Diagram
External
Pins
Digital
Crossbar
Priority
Decoder
SPI0
CAN0
UART0
CP0
T 0 , T 1 ,
/IN T0,
/INT1
P1.0
P1.7
P2.0
P2.7
P0.0
P0.7
Highest
Priority
Lowest
Priority
8
8
CP1
(Internal Digital Signals)
SMBus0
P3.0
P3.7
8
8
PnMDOUT,
PnDMIN Registers
XBR0, XBR1,
XBR2, PnSKIP
P1
I/O
Cells
P3
I/O
Cells
P0
I/O
Cells
P2
I/O
Cells
PCA0 7
LIN0 2
PnMASK
PnMATCH
Registers
/SYSCLK
4
Lowest
Priority
Highest
Priority
Port
Latches
P0
P1
P2
P3
P4
33
(Px.0-Px.7)
P4.0
8P4
I/O
Cell
2
2
2
4
2
2
C8051F55x/56x/57x
170 Rev. 1.2
Note: When VIO rises faster than VDD, which can happen when VREGIN and VIO are tied together, a
delay created between GPIO power (VIO) and the logic controlling GPIO (VDD) results in a
temporary unknown state at the GPIO pins. When VIO rises faster than VDD, the GPIO may enter
the following states: floating, glitch low, or glitch high. Cross coupling VIO and VDD with a 4.7 µF
capacitor mitigates the root cause of the problem by allowing VIO and VDD to rise at the same rate.
19.1. Port I/O Modes of Operation
Port pins P0.0–P4.0 use the Port I/O cell shown in Figure 19.2. Each Port I/O cell can be configured by
software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a
high impedance state with weak pull-ups enabled until the Crossbar is enabled (XBARE = 1).
19.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC inputs, external oscillator inputs, or VREF should be config-
ured for analog I/O (PnMDIN.n = 0). When a pin is configured for analog I/O, its weak pullup, digital driver,
and digital receiver are disabled . Por t pin s con fig ur e d for analog I/O will always read back a value of 0.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
19.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be configu red as digit al I/O (PnMDIN.n = 1). For digit al I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pa d to the VIO or GND supp ly r ails base d on th e outp ut
logic value of the Port pin . Open-dra in output s ha ve the high side driver disabled; therefore, the y only drive
the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high low
drivers turned off) when the output logic value is 1.
Figure 19.2. Port I/O Cell Block Diagram
GND
VIO VIO
(WEAK)
PORT
PAD
To/From Analog
Peripheral
PxMDIN.x
(1 for digital)
(0 for analog)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
XBARE
(Crossbar
Enable)
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
WEAKPUD
(Weak Pull-Up Disable)
C8051F55x/56x/57x
Rev. 1.2 171
When a digit a l I/O cell is placed in the h igh im ped an ce state, a weak pull-up transistor pulls the Port pad to
the VIO supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled
when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting
WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally pulled or driven
to a valid logic state to minimize power cons umption. Port pins configured for digital I/O always read back
the logic state of the Port pad, regard le ss of th e outp ut logic value of the Por t pin.
19.1.3. Interfacing Port I/O in a Multi-Voltage System
All Port I/O are capable of interfacing to digital logic operating at a supply voltage higher than VDD and
less than 5.25 V. Connect the VIO pin to the voltage source of the interface logic.
19.2. Assigning Port I/O Pins to Analog and Digital Functions
Port I/O pins P0.0–P3.7 can be assigned to various analog, digital, and external interrupt functions. P4.0
can be assigned to only digital functions. The Port pins assigned to analog functions should be configured
for analog I/O, and Port pins assigned to d igital or external interrupt functions should be configured for dig-
ital I/O.
19.2.1. Assigning Port I/O Pins to Analog Functions
Table 19.1 shows all available analog functions that require Port I/O assignments. Port pins selected for
these analog f unctions should have their corresponding bit in PnSKIP set to 1. This reserves the pin
for use by the analog function and does not allow it to be claimed by the Crossbar. Table 19.1 shows the
potential mapping of Port I/O to each analog function.
19.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital func-
tions and any Port pins sele cted for use as GPIO should hav e their correspo nding bit in PnSKIP set
to 1. Table 19.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
Table 19.1. Port I/O Assignment for Analog Functions
Analog Function Potentially Assignable
Port Pins SFR(s) used for
Assignment
ADC Input P0.0–P3.71ADC0MX, PnSKIP
Comparator0 or Compartor1 Input P0.0–P2.71CPT0MX, CPT1MX,
PnSKIP
Voltage Reference (VREF0)2P0.0 REF0CN, PnSKIP
External Oscillator in Crystal Mode (XTAL1) P0.2 OSCXCN, PnSKIP
External Oscillator in RC, C, or Crystal Mode (XTAL2) P0.3 OSCXCN, PnSKIP
Notes:
1. P3.1–P3.7 are available on the 40-pin packages. P2.2-P3.0 are available 40-pin and 32-pin packages.
2. If VDD is selected as the voltage reference in the REF0CN register and the ADC is enabled in the ADC0CN
register, the P0.0/VREF pin cannot operate as a general purpose I/O pin in open-drain mode. With the above
settings, this pin can operate in push-pull output mode or as an analog input.
C8051F55x/56x/57x
172 Rev. 1.2
19.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digit al I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossba r (PnSKIP
= 0). External digital event capture functions cannot be used on pins configured for analog I/O. Table 19.3
shows all available external digital event capture functions.
19.3. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 19.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource excluding UAR T0, which is always assigned to pins P0.4 and P0.5, and excluding CAN0 which is
always assigned to pins P0.6 and P0.7. If a Port pin is assigned, the Crossbar skips that pin when assign-
ing the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the
PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for
analog input, dedicated functions, or GPIO.
Because of the nature of Priority Crossbar Decoder, not all peripherals can be located on all port pins.
Figure 19.3 maps peripherals to the potential port pins on which the perip heral I/O can appear.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.1 if the
ADC is configured to use the external conversion start signal (CNVSTR), P0.3 and/or P0.2 if the external
oscillator circuit is enabled, and any selected ADC or Comp arator inp ut s. The Crossbar skip s selected pins
as if they were alread y as sign e d, and moves to the next unassigned pin.
Table 19.2. Port I/O Assignment for Digital Functions
Digital Function Poten ti all y As sig n a bl e Po rt Pins SFR(s) used for
Assignment
UART0, SPI0, SMBus,
CAN0, LIN0, CP0, CP0A,
CP1, CP1A, SYSCLK, PCA0
(CEX0-5 and ECI ), T0 or T1 .
Any Port pin available for assignment by the
Crossbar. This includes P0.0–P4.0* pins which
have their PnSKIP bit set to 0.
Note: The Crossbar will always assign UART0
pins to P0.4 and P0.5 and always assign CAN0
to P0.6 and P0.7.
XBR0, XBR1, XBR2
Any pin used for GPIO P0.0–P4.0* P0SKIP, P1SKIP,
P2SKIP, P3SKIP
*Note: P3.1–P3.7 are available on the 40-pin packages. P2.2-P3.0 are available 40-pin and 32-pin packages.
Table 19.3. Port I/O Assignment for External Digital Event Capture Functions
Digital Function Poten ti all y As sig n a bl e Po rt Pins SFR(s) used for
Assignment
External Interrupt 0 P1.0–P1.7 IT01CF
External Interrupt 1 P1.0–P1.7 IT01CF
Port Match P0.0–P3.7* P0MASK, P0MAT
P1MASK, P1MAT
P2MASK, P2MAT
P3MASK, P3MAT
*Note: P3.1–P3.7 are available on the 40-pin packages. P2.2-P3.0 are available 40-pin and 32-pin packages
C8051F55x/56x/57x
Rev. 1.2 173
Figure 19.3. Peripheral Availability on Port I/O Pins
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); and similarly when the UART, CAN or LIN are selected, the Crossbar assigns both pins
associated with the peripheral (TX and RX). UART0 pin assignments are fixed for bootloading purposes:
UART TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. CAN0 pin assignments are
fixed to P0.6 for CAN_TX and P0.7 for CAN_RX. Standard Port I/Os appear contiguously after the priori-
tized functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSS-
MD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
As an example configuration, if CAN0, SPI0 in 4 -wire mode, and PCA0 Modu les 0, 1, and 2 are enabl ed on
the crossbar with P0.1, P0.2, and P0.5 skipped, the registers should be set as follows: XBR0 = 0x06
(CAN0 and SPI0 enabled), XBR1 = 0x0C (PCA0 modules 0, 1, and 2 enabled), XBR2 = 0x40 (Crossbar
enabled), and P0SKIP = 0x26 (P 0.1, P0.2, and P0.5 sk ipped). The resulting cr ossbar wo uld look a s shown
in Figure 19.4.
Port
P4
Special
Function
Signals
VREF
CNVSTR
XTAL1
XTAL2
ALE
/RD
/WR
P IN I/O 012345670123456701234567012345670
UART_TX
UART_RX
CAN_TX
CAN_RX
SCK
MISO
MOSI
NSS
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
LIN_TX
LIN_RX
P 3.1-P 3.7, P 4.0
available on 40-pin
packages
P 2.2-P 2.7, P 3.0
available on 40-pin
and 32-pin pack ages
P3P0 P1 P2
C8051F55x/56x/57x
174 Rev. 1.2
Figure 19.4. Crossbar Priority Decoder in Example Configuration
19.4. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
2. Select the output mode (open-drain or push-pull) for all Port pins, usin g the Port Output Mode register
(PnMDOUT).
3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals.
5. Enable the Crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. Port 4 C8051F568-9 and ‘F570-5 is a
digital-only Port. Any pins to be used as Comparator or ADC inputs should be configured as an analog
inputs. When a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are
disabled. This process saves power and reduces noise on the analog input. Pins configured as digital
inputs may still be used by analog peripherals; however this practice is not recommended.
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bi ts in Pn SKIP). Port input mode is set in the PnMDIN register, where a 1 indicates a
digital inpu t, and a 0 indica tes an analog inpu t. All pins default to digit al inpu t s on reset. See SFR Definition
19.13 for the PnMDIN register details.
Port
P4
Special
Function
Signals
VREF
CNVSTR
XTAL1
XTAL2
ALE
/RD
/WR
PIN I/O 012345670123456701234567012345670
UART_TX
UART_RX
CAN_TX
CAN_RX
SCK
MISO
MOSI
NSS *NSS Is only pinned out in 4-wire SP I M ode
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
LIN_TX
LIN_RX 01100100000000000000000000000000
P 2S KIP [0:7]
P 3.1-P3.7, P 4.0
available on 40-pin
packages
P 2.2-P 2.7, P3.0
available on 40-pin
and 32-pin packages
P3P0 P1
P0SKIP[0:7] P1SKIP[0:7] P3SKIP[0:7]
P2
C8051F55x/56x/57x
Rev. 1.2 175
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings. When the WEAKPUD bit in XBR2 is 0, a weak pullup is enabled for all Port I/O config-
ured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is
turned off on an output that is driving a 0 to avoid unnecessary power dissipation.
Registers XBR0, XBR1, and XBR2 must be loaded with the appropriate values to select the digital I/O
functions required by the design. Setting the XBARE bit in XBR2 to 1 enables the Crossbar. Until the
Crossbar is enabled , the externa l pins remain as st andard Port I/O (in input mode) , regardless o f the XBRn
Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority
Decode Table; as an alternative, the Configuratio n Wizard utility of the Silicon Labs IDE software will deter-
mine the Port I/O pin-assignments based on the XBRn Register settings.
The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers
are disabled while the Crossbar is disabled.
C8051F55x/56x/57x
176 Rev. 1.2
SFR Address = 0xE1; SFR Page = 0x0F
SFR Definition 19.1. XBR0: Port I/O Crossbar Register 0
Bit76543210
Name CP1AE CP1E CP0AE CP0E SMB0E SPI0E CAN0E URT0E
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CP1AE Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 unavailable at Port pin.
1: Asynchronous CP1 routed to Port pin.
6CP1E Comparator1 Output Enable.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
5CP0AE Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
4CP0E Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
3SMB0E SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
2SPI0E SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
1CAN0E CAN I/O Output Enable .
0: CAN I/O unavailable at Port pins.
1: CAN_TX, CAN_RX routed to Port pins P0.6 and P0.7.
0URT0E UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
C8051F55x/56x/57x
Rev. 1.2 177
SFR Address = 0xE2; SFR Page = 0x0F
SFR Definition 19.2. XBR1: Port I/O Crossbar Register 1
Bit 7 6 5 4 3 2 1 0
Name T1E T0E ECIE PCA0ME[2:0] SYSCKE Reserved
Type R/W R/W R/W R/W R/W RR/W R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7T1E T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
6T0E T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
5ECIE PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
4:2 PCA0ME[2:0] PCA Module I/O Enable Bits.
000: All PCA I/O unavailable at Port pins.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins.
111: RESERVED
1SYSCKE /SYSCLK Output Enable.
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
0Reserved Always Write to 0.
C8051F55x/56x/57x
178 Rev. 1.2
SFR Address = 0xC7; SFR Page = 0x0F
SFR Definition 19.3. XBR2: Port I/O Crossbar Register 1
Bit 7 6 5 4 3 2 1 0
Name WEAKPUD XBARE Reserved LIN0E
Type R/W R/W R/W R/W R/W RR/W R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
6XBARE Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
5:1 Reserved Always Write to 00000b.
0LIN0E LIN I/O Output Enable.
0: LIN I/O unavailable at Port pin.
1: LIN_TX, LIN_RX routed to Port pins.
C8051F55x/56x/57x
Rev. 1.2 179
19.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0, P1, P2 o r P3.
A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values
of P0, P1, P2, and P3. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer
match the software controlled value. This allows Software to be notified if a certain change or pattern
occurs on P0, P1, P2, or P3 input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which of the port pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (Pn & PnMASK) does not equal
(PnMATCH & PnMASK), where n is 0, 1, 2 or 3
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
SFR Address = 0xF2; SFR Page = 0x00
SFR Address = 0xF1; SFR Page = 0x00
SFR Definition 19.4. P0MASK: Port 0 Mask Register
Bit76543210
Name P0MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0MASK[7:0] Port 0 Mask Value.
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
SFR Definition 19.5. P0MAT: Port 0 Match Register
Bit76543210
Name P0MAT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P0MAT[7:0] Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MAT which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
C8051F55x/56x/57x
180 Rev. 1.2
SFR Address = 0xF4; SFR Page = 0x00
SFR Address = 0xF3; SFR Page = 0x00
SFR Definition 19.6. P1MASK: Port 1 Mask Register
Bit76543210
Name P1MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1MASK[7:0] Port 1 Mask Value.
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
SFR Definition 19.7. P1MAT: Port 1 Match Register
Bit76543210
Name P1MAT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P1MAT[7:0] Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MAT which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
C8051F55x/56x/57x
Rev. 1.2 181
SFR Address = 0xB2; SFR Page = 0x00
SFR Address = 0xB1; SFR Page = 0x00
SFR Definition 19.8. P2MASK: Port 2 Mask Register
Bit76543210
Name P2MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P2MASK[7:0] Port 2 Mask Value.
Selects P2 pins to be compared to the corresponding bits in P2MAT.
0: P2.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P2.n pin logic value is compared to P2MAT.n.
Note: P2.2–P2.7 are available on 40-pin and 32-pin packages.
SFR Definition 19.9. P2MAT: Port 2 Match Register
Bit76543210
Name P2MAT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P2MAT[7:0] Port 2 Match Value.
Match comparison value used on Port 2 for bits in P2MAT which are set to 1.
0: P2.n pin logic value is compared with logic LOW.
1: P2.n pin logic value is compared with logic HIGH.
Note: P2.2–P2.7 are available on 40-pin and 32-pin packages.
C8051F55x/56x/57x
182 Rev. 1.2
SFR Address = 0xAF; SFR Page = 0x00
SFR Address = 0xAE; SFR Page = 0x00
SFR Definition 19.10. P3MASK: Port 3 Mask Register
Bit76543210
Name P3MASK[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P3MASK[7:0] Port 1 Mask Value.
Selects P3 pins to be compared to the corresponding bits in P3MAT.
0: P3.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P3.n pin logic value is compared to P3MAT.n.
Note: P3.0 is available on 40-pin and 32-pin packages. P3.1-P3.7 are available on 40-pin packages
SFR Definition 19.11. P3MAT: Port 3 Match Register
Bit76543210
Name P3MAT[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P3MAT[7:0] Port 3 Match Value.
Match comparison value used on Port 3 for bits in P3MAT which are set to 1.
0: P3.n pin logic value is compared with logic LOW.
1: P3.n pin logic value is compared with logic HIGH.
Note: P3.0 is available on 40-pin and 32-pin packages. P3.1-P3.7 are available on 40-pin packages
C8051F55x/56x/57x
Rev. 1.2 183
19.6. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bi t addre ssable, excep t for P4 wh ich is only byte ad dressable . When writin g to a Por t, the
value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic
levels of the Port's input pins are returned regardless of the XBRn settings (i.e., even when the pin is
assigned to another signal by the Crossbar, the Port register can always read its corresponding Port I/O
pin). The exce ption to this is the ex ecution of the read- modify-write instructions tha t target a Port Latch reg-
ister as the destination. The read-modi fy-write instructions when operating on a Port SFR are the following:
ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, C LR or SETB, when the destination is an individ-
ual bit in a Port SFR. For these instructions, the value of the latch register (not the pin) is read, modified,
and written back to the SFR.
Ports 0–3 have a cor responding PnSKIP register which allows its in dividual Port pins to be assigned to dig-
ital functions or skipped by the Crossbar . All Port pins used for analog functions, GPIO, or dedicated digital
functions such as the EMIF should have th eir PnSKIP bit set to 1.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P4, which can only be
used for digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
SFR Address = 0x80; SFR Page = All Pages; Bit-Addressable
SFR Definition 19.12. P0: Port 0
Bit76543210
Name P0[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P0[7:0] Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
C8051F55x/56x/57x
184 Rev. 1.2
SFR Address = 0xF1; SFR Page = 0x0F
SFR Address = 0xA4; SFR Page = 0x0F
SFR Definition 19.13. P0MDIN: Port 0 Input Mode
Bit76543210
Name P0MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their we ak pull-up and digital receiver
disabled. For analog mode, the pin also needs to be configured for open-drain
mode in the P0MDOUT register.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
SFR Definition 19.14. P0MDOUT: Port 0 Output Mode
Bit76543210
Name P0MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0MDOUT[7:0] Output Configurat ion Bits for P0.7–P0.0 (respectively).
These bits ar e ignored if the corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Correspon ding P0 .n Ou tp u t is push -pu l l.
C8051F55x/56x/57x
Rev. 1.2 185
SFR Address = 0xD4; SFR Page = 0x0F
SFR Address = 0x90; SFR Page = All Pages; Bit-Addressable
SFR Definition 19.15. P0SKIP: Port 0 Skip
Bit76543210
Name P0SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skippe d by the Crossbar.
SFR Definition 19.16. P1: Port 1
Bit76543210
Name P1[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P1[7:0] Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
C8051F55x/56x/57x
186 Rev. 1.2
SFR Address = 0xF2; SFR Page = 0x0F
SFR Address = 0xA5; SFR Page = 0x0F
SFR Definition 19.17. P1MDIN: Port 1 Input Mode
Bit76543210
Name P1MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively).
Port pins configured for analog mode have their we ak pull-up and digital receiver
disabled. For analog mode, the pin also needs to be configured for open-drain
mode in the P1MDOUT register.
0: Corresponding P1.n pin is configured for analog mode.
1: Corresponding P1.n pin is not configured for analog mode.
SFR Definition 19.18. P1MDOUT: Port 1 Output Mode
Bit76543210
Name P1MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1MDOUT[7:0] Output Configurat ion Bits for P1.7–P1.0 (respectively).
These bits ar e ignored if the corresponding bit in register P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Correspon ding P1 .n Ou tp u t is push -pu l l.
C8051F55x/56x/57x
Rev. 1.2 187
SFR Address = 0xD5; SFR Page = 0x0F
SFR Address = 0xA0; SFR Page = All Pages; Bit-Addressable
SFR Definition 19.19. P1SKIP: Port 1 Skip
Bit76543210
Name P1SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skippe d by the Crossbar.
SFR Definition 19.20. P2: Port 2
Bit76543210
Name P2[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P2[7:0] Port 2Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
Note: P2.2-P2.7 are available on 40-pin and 32-pin packages.
C8051F55x/56x/57x
188 Rev. 1.2
SFR Address = 0xF3; SFR Page = 0x0F
SFR Address = 0xA6; SFR Page = 0x0F
SFR Definition 19.21. P2MDIN: Port 2 Input Mode
Bit76543210
Name P2MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured for analog mode have their we ak pull-up and digital receiver
disabled. For analog mode, the pin also needs to be configured for open-drain
mode in the P2MDOUT register.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
Note: P2.2-P2.7 are available on 40-pin and 32-pin packages.
SFR Definition 19.22. P2MDOUT: Port 2 Output Mode
Bit76543210
Name P2MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P2MDOUT[7:0] Output Configurat ion Bits for P2.7–P2.0 (respectively).
These bits ar e ignored if the corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Correspon ding P2 .n Ou tp u t is push -pu l l.
Note: P2.2-P2.7 are available on 40-pin and 32-pin packages.
C8051F55x/56x/57x
Rev. 1.2 189
SFR Address = 0xD6; SFR Page = 0x0F
SFR Address = 0xB0; SFR Page = All Pages; Bit-Addressable
SFR Definition 19.23. P2SKIP: Port 2 Skip
Bit76543210
Name P2SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P2SKIP[7:0] Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skippe d by the Crossbar.
Note: P2.2-P2.7 are available on 40-pin and 32-pin packages.
SFR Definition 19.24. P3: Port 3
Bit76543210
Name P3[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P3[7:0] Port 3 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P3.n Port pin is logic
LOW.
1: P3.n Port pin is logic
HIGH.
Note: P3.0 is available on 40-pin and 32-pin packages. P3.1-P3.7 are available on 40-pin packages
C8051F55x/56x/57x
190 Rev. 1.2
SFR Address = 0xF4; SFR Page = 0x0F
SFR Address = 0xAE; SFR Page = 0x0F
SFR Definition 19.25. P3MDIN: Port 3 Input Mode
Bit76543210
Name P3MDIN[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 P3MDIN[7:0] Analog Configuration Bits for P3.7–P3.0 (respectively).
Port pins configured for analog mode have their we ak pull-up and digital receiver
disabled. For analog mode, the pin also needs to be configured for open-drain
mode in the P3MDOUT register.
0: Corresponding P3.n pin is configured for analog mode.
1: Corresponding P3.n pin is not configured for analog mode.
Note: P3.0 is available on 40-pin and 32-pin packages. P3.1-P3.7 are available on 40-pin packages
SFR Definition 19.26. P3MDOUT: Port 3 Output Mode
Bit76543210
Name P3MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P3MDOUT[7:0] Output Configurat ion Bits for P3.7–P3.0 (respectively).
These bits ar e ignored if the corresponding bit in register P3MDIN is logic 0.
0: Corresponding P3.n Output is open-drain.
1: Correspon ding P3 .n Ou tp u t is push -pu l l.
Note: P3.0 is available on 40-pin and 32-pin packages. P3.1-P3.7 are available on 40-pin packages
C8051F55x/56x/57x
Rev. 1.2 191
SFR Address = 0xD7; SFR Page = 0x0F
SFR Address = 0xB5; SFR Page = All Pages
SFR Definition 19.27. P3SKIP: Port 3Skip
Bit76543210
Name P3SKIP[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P3SKIP[7:0] Port 3 Crossbar Skip Enable Bits.
These bits select Port 3 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P3.n pin is not skipped by the Crossbar.
1: Corresponding P3.n pin is skippe d by the Crossbar.
Note: P3.0 is available on 40-pin and 32-pin packages. P3.1-P3.7 are available on 40-pin packages
SFR Definition 19.28. P4: Port 4
Bit76543210
Name P4[7:0]
Type R/W
Reset 11111111
Bit Name Description Write Read
7:0 P4[7:0] Port 4 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0: P4.n Port pin is logic
LOW.
1: P4.n Port pin is logic
HIGH.
Note: Port 4.0 is available on 40-pin packages.
C8051F55x/56x/57x
192 Rev. 1.2
SFR Address = 0xAF; SFR Page = 0x0F
SFR Definition 19.29. P4MDOUT: Port 4 Output Mode
Bit76543210
Name P4MDOUT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 P4MDOUT[7:0] Output Configurat ion Bits for P4.7–P4.0 (respectively).
0: Corresponding P4.n Output is open-drain.
1: Correspon ding P4 .n Ou tp u t is push -pu l l.
Note: Port 4.0 is available on 40-pin packages.
C8051F55x/56x/57x
Rev. 1.2 193
20. Local Interconnect Network (LIN0)
Important Note: This chapter assumes an understanding of the Local Interconnect Network (LIN) proto-
col. For more information about the LIN protocol, includ ing specifications, please refe r to the LIN consor-
tium (http://www.lin-subbus.org).
LIN is an asynchronous, serial communications interface used primarily in automotive networks. The Sili-
con Laboratories LIN controller is compliant to the 2.1 Specification, implements a complete hardware LIN
interface and includes the following features:
Selectable Maste r and Slave modes.
Automatic baud rate option in slave mode.
The internal oscillator is accurate to within 0 .5% of 24 MHz across the entire temp erature range and for
VDD voltages greater than or equal to the minimum output of the on-chip voltage regulator, so an
external oscillator is not necessary for ma st er mod e opera tio n fo r mo st systems.
Note: The minimum system clock (SYSCLK) required when using the LIN controller is 8 MHz.
Figure 20.1. LIN Block Diagram
The LIN controller has four main components:
LIN Access Registers—Provide the interface between the MCU core and the LIN controller.
LIN Data Registers—Where transmitted and received message data byte s are stored.
LIN Control Regist er s— Con tr ol th e functionality of the LI N inte rfa ce .
Control State Machine and Bit Streaming Logic—Contains the hardware that serializes messages and
controls the bus timing of the controller.
Indirectly Addressed Registers
LIN0ADR
LIN0DAT
LIN0CF
LIN Data
Registers
Control State Ma chine
8051 MCU Core
TX
RX
LIN Controller
LIN Control
Registers
C8051F55x/56x/57x
194 Rev. 1.2
20.1. Soft ware Interface with the LIN Controller
The selection of the mode ( Master or Slave) and the automatic bau d rate feature are done thoug h the LIN0
Control Mode (LIN0CF) register. The other LIN registers are accessed indirectly through the two SFRs
LIN0 Address (LIN0ADR) and LIN0 Data (LIN0DAT). The LIN0ADR register selects which LIN register is
targeted by reads/writes of the LIN0DAT register. The full list of indirectly-accessible LIN registers is given
in Table 20.4 on page 202.
20.2. LIN Interface Setup and Operation
The hardware based LIN controller allows for the implementation of both Master and Slave nodes with
minimal firmware overhead and complete control of the interface status while allowing for interrupt and
polled mode operation.
The first step to use the controller is to define the basic characteristics of the node:
Mode—Master or Slave
Baud Rate—Either defined manually or using the autobaud feature (slave mode only)
Checksum Type—Select between classic or enhanced checksum, both of which are implemented in hard-
ware.
20.2.1. Mode Definition
Following the LIN specificatio n, the cont roller implemen ts in ha rdware both the Slave an d Master ope rating
modes. The mod e is con figur ed usin g th e MO DE bit (LIN0CF.6).
20.2.2. Baud Rate Options: Manual or Autobaud
The LIN controller can be selected to have its baud rate calculated manually or automatically. A master
node must always have its ba ud rate set manually, but slave nodes can choose between a manual or auto-
matic setup. The configuration is selected using the ABAUD bit (LIN0CF.5).
Both the manual and automatic baud rate configurations require additional setup. The following sections
explain the different options available and their relation with the baud rate, along with the steps necessary
to achieve the required baud rate.
20.2.3. Baud Rate Calculations: Manual Mode
The baud rate used by the LIN controller is a function of the System Clock (SYSCLK) and the LIN timing
registers according to the following equation:
The prescaler, divider and multiplier factors are part of the LIN0DIV and LIN0MUL registers and can
assume values in the following range:
Important Note: The minimum system clock (SYSCLK) to operate the LIN controller is 8 MHz.
Use the following equations to calculate the values for the variables for the baud-rate equation:
Table 20.1. Baud Rate Calculation Variable Ranges
Factor Range
prescaler 0…3
multiplier 0…31
divider 200…511
baud_rate SYSCLK
2prescaler 1+
()
divider multiplier 1+()
××
---------------------------------------------------------------------------------------------------------------------
=
C8051F55x/56x/57x
Rev. 1.2 195
In all of these equations, the results must be rounded down to the nearest integer.
The following example shows the steps for calculating the baud rate values for a Mas ter node running at
24 MHz and communicating at 19200 bits/sec. First, calculate the multiplier:
Next, calculate the prescaler:
Finally, calculate the divider:
These values lead to the following baud ra te:
The following code programs the interface in Master mode, using the Enhanced Checksum and enables
the interface to operate at 19230 bits/sec using a 24 MHz system clock.
LIN0CF = 0x80; // Activate the interface
LIN0CF |= 0x40; // Set the node as a Master
LIN0ADR = 0x0D; // Point to the LIN0MUL register
// Initialize the register (prescaler, multiplier and bit 8 of divider)
LIN0DAT = ( 0x01 << 6 ) + ( 0x00 << 1 ) + ( ( 0x138 & 0x0100 ) >> 8 );
LIN0ADR = 0x0C; // Point to the LIN0DIV register
LIN0DAT = (unsigned char)_0x138; // Initialize LIN0DIV
LIN0ADR = 0x0B; // Point to the LIN0SIZE register
LIN0DAT |= 0x80; // Initialize the checksum as Enhanced
LIN0ADR = 0x08; // Point to LIN0CTRL register
LIN0DAT = 0x0C; // Reset any error and the interrupt
Table 20.2 includes the configuration values required for the typical system clocks and baud rates:
multiplier 20000
baud_rate
----------------------------- 1
–=
prescaler ln SYSCLK
multiplier 1+
()baud_rate 200××
------------------------------------------------------------------------------------------------ 1
ln2
-------- 1
–×=
divider SYSCLK
2prescaler 1+
()
multiplier 1+()×baud_rate×()
--------------------------------------------------------------------------------------------------------------------------------------=
multiplier 20000
19200
---------------- 1 0.0417 0
≅=–=
prescaler ln 24000000
01+
()19200 200××
----------------------------------------------------------- 1
ln2
-------- 1
–×1.644=1≅=
divider 24000000
211+
()
01+()×19200×
----------------------------------------------------------------------- 312.5 312≅==
baud_rate 24000000
211+
()
01+()×312×
---------------------------------------------------------------- 19230.77
≅=
C8051F55x/56x/57x
196 Rev. 1.2
20.2.4. Baud Rate Calculations—Automatic Mode
If the LIN controller is configured for slave mode, only the prescaler and divider need to be calculated:
The following example calculates the values of these variables for a 24 MHz system clock:
Table 20.3 presents some typical values of system clock and baud rate along with their factors.
Table 20.2. Manual Baud Rate Parameters Examples
Baud (bits/sec)
20 K 19.2 K 9.6 K 4.8 K 1 K
SYSCLK
(MHz)
Mult.
Pres.
Div.
Mult.
Pres.
Div.
Mult.
Pres.
Div.
Mult.
Pres.
Div.
Mult.
Pres.
Div.
25 0 1 312 0 1 325 1 1 325 3 1 325 19 1312
24.5 0 1 306 0 1 319 1 1 319 3 1 319 19 1306
24 0 1 300 0 1 312 1 1 312 3 1 312 19 1300
22.1184 0 1 276 0 1 288 1 1 288 3 1 288 19 1276
16 0 1 200 0 1 208 1 1 208 3 1 208 19 1200
12.25 0 0 306 0 0 319 1 0 319 3 0 319 19 0306
12 0 0 300 0 0 312 1 0 312 3 0 312 19 0300
11.0592 0 0 276 0 0 288 1 0 288 3 0 288 19 0276
8 0 0 200 0 0 208 1 0 208 3 0 208 19 0200
prescaler ln SYSCLK
4000000
-------------------------1
ln2
-------- 1
–×=
divider SYSCLK
2prescaler 1+
()
20000×
----------------------------------------------------------------------=
prescaler ln 24000000
4000000
-------------------------- 1
ln2
-------- 1
–×1.585=1≅=
divider 24000000
211+
()
20000×
--------------------------------------------- 300==
C8051F55x/56x/57x
Rev. 1.2 197
20.3. LIN Master Mode Operation
The master node is responsible for the scheduling of messages and sends the header of each frame con-
taining the SYNCH BREAK FIELD, SYNCH FIELD, and IDENTIFIER FIEL D. The step s to schedule a mes-
sage transmission or reception are listed below.
1. Load the 6- bit Id en tif ier into th e LIN0ID register.
2. Load the data length into the LIN0SIZE register. Set the value to the number of data by tes or "1111b" if
the data length should be decoded from the identifier. Also, set the checksum type, classic or
enhanced, in the same LIN0SIZE register.
3. Set the data direction by settin g the TXRX bit (LIN0CTRL.5). Set the bit to 1 to perform a master
transmit operation, or set the bit to 0 to perform a master receive operation.
4. If performing a master transmit operation, load the data bytes to tr an sm it into the data buffer (LIN0DT1
to LIN0DT8).
5. Set the STREQ bit (LIN0CTRL.0) to start the message transfer. The LIN controller will schedule the
message frame and requ est an interrupt if the message tran sfer is successfully completed or if an er ror
has occurred .
This code segment shows the procedure to schedule a message in a transmission operation:
LIN0ADR = 0x08; // Point to LIN0CTRL
LIN0DAT |= 0x20; // Select to transmit data
LIN0ADR = 0x0E; // Point to LIN0ID
LIN0DAT = 0x11; // Load the ID, in this example 0x11
LIN0ADR = 0x0B; // Point to LIN0SIZE
LIN0DAT = ( LIN0DAT & 0xF0 ) | 0x08; // Load the size with 8
LIN0ADR = 0x00; // Point to Data buffer first byte
for (i=0; i<8; i++)
{
LIN0DAT = i + 0x41; // Load the buffer with ‘A’, ‘B’, ...
LIN0ADR++; // Increment the address to the next buffer
}
LIN0ADR = 0x08; // Point to LIN0CTRL
LIN0DAT = 0x01; // Start Request
Table 20.3. Autobaud Parameters Examples
System Clock (MHz) Prescaler Divider
25 1312
24.5 1306
24 1300
22.1184 1276
16 1200
12.25 0306
12 0300
11.0592 0276
8 0 200
C8051F55x/56x/57x
198 Rev. 1.2
The application should perform the following steps when an interrupt is requested.
1. Check the DONE bit (LIN0ST.0) and the ERROR bit (LIN0ST.2).
2. If performing a master receive operation and the transfer was successful, read the received data from
the data buffer.
3. If the transfer was not successful, check the error register to determine the kind of error. Further error
handling has to be done by the application.
4. Set the RSTINT (LIN0CTRL.3) and RSTERR bits (LIN0CTRL.2) to reset the interrupt request and the
error flags.
20.4. LIN Slave Mode Operation
When the device is configured for slave mode operation, it must wait for a command from a master node.
Access from the firmware to the data buffer and ID registers of the LIN controller is only possible when a
data request is pending (DTREQ bit (LIN0ST.4) is 1) and also when the LIN bus is not active (ACTIVE bit
(LIN0ST.7) is set to 0).
The LIN controller in slave mo de detects the header of the message frame sent by the LIN master. If slave
synchronization is enabled (autobaud), the slave synchronizes its internal bit time to the master bit time.
The LIN controller configured for slave mode will generated an interrupt in one of three situations:
1. After the reception of the IDENTIFIER FIELD
2. When an erro r is de tec te d
3. When the message tr ansfer is completed.
The application should perform the following steps when an interrupt is detected:
1. Check the status of the DTREQ bit (LIN0ST.4). This bit is set when the IDENTIFIER FIELD has been
received.
2. If DTREQ (LIN0ST.4) is set, read the identifier from LIN0ID and process it. If DTREQ (LIN0ST.4) is not
set, continue to step 7.
3. Set the TXRX bit (LIN0CTRL.5) to 1 if the current frame is a transmit operation for the slave and set to
0 if the current frame is a receive oper ation for the slave.
4. Load the da ta length into LIN0SIZE.
5. For a slave transmit operation, load the data to transmit into the data buffer.
6. Set the DTACK bit (LIN0CTRL.4). Continue to step 10.
7. If DTREQ (LIN0ST.4) is not set, check the DONE bit (LIN0ST.0). The transmission was successful if the
DONE bit is set.
8. If the transmission was successful and the current frame was a receive ope ration for the sla ve, load the
received data bytes fro m th e da ta buffer.
9. If the transmission was not successful, check LIN0E RR to de te rm in e th e na tu re of the error. Further
error handling has to be done by the application.
10.Set the RSTINT (LIN0CTRL.3) and RSTERR bits (LIN0CTRL.2) to reset the interrupt request and the
error flags.
In addition to these steps, the application should be aware of the following:
1. If the current frame is a transmit operation for the slave, steps 1 through 5 must be completed during
the IN-FRAME RESPONSE SPACE. If it is not completed in time, a timeout will be detected by the
master.
2. If the current frame is a receive operation for the slave, steps 1 through 5 have to be finished until the
reception of the first byte after the IDENTIFIER FIELD. Otherwise, the internal receive buffer of the LIN
controller will be overwritten and a timeout error will be detected in the LIN controller.
C8051F55x/56x/57x
Rev. 1.2 199
3. The LIN controller doe s not directly support L IN V ersion 1.3 Extended Frames. If the applicati on detects
an unknown identifier (e.g. extended identifier), it h as to write a 1 to the ST OP bit (L IN0CTRL.7) instead
of setting the DTACK (LIN0CTRL.4) bit. At that time, steps 2 through 5 can then be skipped. In this
situation, the LIN controller stops the processing of LIN communication until the next SYNC BREAK is
received.
4. Changing the configuration of the checksum during a transaction will cause the interfac e to reset and
the transaction to be lost. To prevent this, the checksum should not be configured while a transaction is
in progress. The same applies to changes in the LIN interface mode from slave mode to master mode
and from master mode to slave mode.
20.5. Sleep Mode and Wake-Up
To reduce the system’s power consumption, the LIN Protocol Specification defines a Sleep Mode. The
message used to broadcast a Sleep Mode request must be transmitted by the LIN master application in
the same way as a normal transmit message. The LIN slave application must decode the Sleep Mode
Frame from the Iden tifier and dat a byte s. After tha t, it has to put the LIN slave node in to the Sleep Mode by
setting the SLEEP bit (LIN0CTRL.6).
If the SLEEP bit (LIN0CTRL.6) of the LIN slave application is not set and there is no bus activity for four
seconds (specif ied bus idle tim eout), the IDLTOUT bit (LIN0ST.6) is set and a n interrupt re quest is gener -
ated. After that the application may assume that the LIN bus is in Sleep Mode and set the SLEEP bit
(LIN0CTRL.6).
Sending a wake-up signa l from the master or any slave node ter minates the Sleep Mode of the LIN b us. To
send a wake-up signal, the application has to set the WUPREQ bit (LIN0CTRL.1). After successful trans-
mission of the wake-up signal, the DONE bit (LIN0ST.0) of the master node is set and an interrupt request
is generated. The LIN slave does not generate an interrupt request after successful transmission of the
wake-up signal but it generates an interrupt request if the master does not respond to the wake-up signal
within 150 milliseconds. In that case, the ERROR bit (LIN0ST.2) and TOUT bit (LIN0ERR.2) are set. The
application then has to decide whether or not to transmit another wake-up signal.
All LIN nodes that detect a wake-up signal will set the W AKEUP (LIN0ST.1) and DONE bits (LIN0ST.0) and
generate an interrupt request. After that, the application has to clear the SLEEP bit (LIN0CTRL.6) in the
LIN slave.
20.6. Error Detection and Handling
The LIN controller gen erates an inte rrup t request and stop s th e processing of the curr ent frame if it detects
an error. The application has to check the type of error by processing LIN0E RR. After that, it has to re set
the error register and th e ERROR bit (L IN0ST.2) by writing a 1 to the RSTERR bit (LIN0CTRL.2). S t arting a
new message w ith the L IN cont roller se lected a s master or send ing a Wakeup signal with th e LIN co ntrol-
ler selected as a master or slave is possible only if the ERROR bit (LIN0ST.2) is set to 0.
C8051F55x/56x/57x
200 Rev. 1.2
20.7. LIN Registers
The following Special Function Registers (SFRs) and indirect registers are available for the LIN controller.
20.7.1. LIN Direct Access SFR Registers Definitions
SFR Address = 0xD3; SFR Page = 0x00
SFR Address = 0xD2; SFR Page = 0x00
SFR Definition 20.1. LIN0ADR: LIN0 Indirect Address Register
Bit76543210
Name LIN0ADR[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 LIN0ADR[7:0] LIN Indirect Address Register Bits.
This register hold an 8- bit address used to indirectly access the LIN0 core registers.
Table 20.4 lists the LIN0 core registers and their indirect addresses. Reads and
writes to LIN0DAT will target the register indicated by the LIN0ADR bits.
SFR Definition 20.2. LIN0DAT: LIN0 Indirect Data Register
Bit76543210
Name LIN0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 LIN0DAT[7:0] LIN Indirect Data Register Bits.
When this register is read, it will read the contents of the L IN0 core r egi ster po inted
to by LIN0ADR.
When this register is written, it will write the value to the LIN0 core register pointed
to by LIN0ADR.
C8051F55x/56x/57x
Rev. 1.2 201
SFR Address = 0xC9; SFR Page = 0x0F
SFR Definition 20.3. LIN0CF: LIN0 Control Mode Register
Bit 7 6 5 4 3 2 1 0
Name LINEN MODE ABAUD
Type R/W R/W R/W R R R R R
Reset 0 1 1 0 0 0 0 0
Bit Name Function
7LINEN LIN Interface Enable Bit.
0: LIN0 is disabled.
1: LIN0 is enabled.
6MODE LIN Mode Selection Bit.
0: LIN0 operates in slave mode.
1: LIN0 operates in master mode.
5ABAUD LIN Mode Automatic Baud Rate Selection.
This bit only has an effect when the MODE bit is configured for slave mode.
0: Manual baud rate selection is enabled .
1: Automatic baud rate selection is enabled.
4:0 Unused Read = 00000b; Write = Don’t Care
C8051F55x/56x/57x
202 Rev. 1.2
20.7.2. LIN Indirect Access SFR Registers Definit ions
Table 20.4 lists the 15 indirect registers used to configured and communicate with the LIN controller.
Table 20.4. LIN Registers* (Indirectly Addressable)
Name Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LIN0DT1 0x00 DATA1[7:0]
LIN0DT2 0x01 DATA2[7:0]
LIN0DT3 0x02 DATA3[7:0]
LIN0DT4 0x03 DATA4[7:0]
LIN0DT5 0x04 DATA5[7:0]
LIN0DT6 0x05 DATA67:0]
LIN0DT7 0x06 DATA7[7:0]
LIN0DT8 0x07 DATA8[7:0]
LIN0CTRL 0x08 STOP(s) SLEEP(s) TXRX DTACK(s) RSTINT RSTERR WUPREQ STREQ(m)
LIN0ST 0x09 ACTIVE IDLTOUT ABORT(s) DTREQ(s) LININT ERROR WAKEUP DONE
LIN0ERR 0x0A SYNCH(s) PRTY(s) TOUT CHK BITERR
LIN0SIZE 0x0B ENHCHK LINSIZE[3:0]
LIN0DIV 0x0C DIVLSB[7:0]
LIN0MUL 0x0D PRESCL[1:0] LINMUL[4:0] DIV9
LIN0ID 0x0E ID5 ID4 ID3 ID2 ID1 ID0
*Note: These registers are used in both master and slave mode. The register bits marked with (m) are accessible only in
Master mode while th e regist er bits marked with (s) are accessible only in slave mode. All other registers are
accessible in both modes.
C8051F55x/56x/57x
Rev. 1.2 203
Indirect Address: LIN0DT 1 = 0x00, LIN0DT2 = 0x01 , LIN0DT3 = 0x02, LIN0DT4 = 0x03, LIN0DT5 = 0x04 ,
LIN0DT6 = 0x05, LIN0DT7 = 0x06, LIN0DT8 = 0x07
LIN Register Definition 20.4. LIN0DTn: LIN0 Data Byte n
Bit76543210
Name DATAn[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DATAn[7:0] LIN Data Byte n.
Serial Data Byte that is received or transmitted across the LIN interface.
C8051F55x/56x/57x
204 Rev. 1.2
Indirect Address = 0x08
LIN Register Definition 20.5. LIN0CTRL: LIN0 Control Register
Bit76543210
Name STOP SLEEP TXRX DTACK RSTINT RSTERR WUPREQ STREQ
Type WR/W R/W R/W W W R/W R/W
Reset 00000000
Bit Name Function
7STOP Stop Communication Processing Bit. (slave mode only)
This bit always reads as 0.
0: No effect.
1: Block the processing of LIN communications until the next SYNC BREAK signal.
6SLEEP Sleep Mode Bit. (slave mode only)
0: Wake the device after receiving a Wakeup interrupt.
1: Put the device into sleep mode after receiving a Sleep Mode frame or a bus idle
timeout.
5TXRX Transmit / Receive Selection Bit.
0: Current frame is a receive operation.
1: Current frame is a transmit operation.
4DTACK Data Acknowledge Bit. (slave mode only)
Set to 1 after handling a data request interrupt to acknowledge the transfer. The bit
will automatically be cleared to 0 by the LIN controller.
3RSTINT Reset In terrupt Bit.
This bit always reads as 0.
0: No effect.
1: Reset the LININT bit (LIN0S T.3).
2RSTERR Reset Error Bit.
This bit always reads as 0.
0: No effect.
1: Reset the error bits in LIN0ST and LIN0ERR.
1WUPREQ Wakeup Request Bit.
Set to 1 to terminate sleep mode by sending a wakeup signal . The bit will automati-
cally be cleared to 0 by the LIN controller.
0STREQ Start Request Bit. (master mode only)
1: Start a LIN transmission. This should be set only after loading the identifier, data
length and data buffer if necessary.
The bit is reset to 0 upon transmission completion or error detection.
C8051F55x/56x/57x
Rev. 1.2 205
Indirect Address = 0x09
LIN Register Definition 20.6. LIN0ST: LIN0 Status Register
Bit76543210
Name ACTIVE IDLTOUT ABORT DTREQ LININT ERROR WAKEUP DONE
Type RRRRRRRR
Reset 00000000
Bit Name Function
7ACTIVE LIN Active Indicator Bit.
0: No transmission activity detected on the LIN bus.
1: Transmission activity detected on the LIN bus.
6IDLT Bus Idle Timeout Bit. (slave mode only)
0: The bus has not been idle for four seconds.
1: No bus activity has been detected for four secon ds, but the bus is no t yet in Sleep
mode.
5ABORTAborted Transmission Bit. (slave mode only)
0: The current transmission ha s not been in terrupted or stopped. This bit is reset to 0
after receiving a SYNCH BREAK that does not interrupt a pending transmission.
1: New SYNCH BREAK detected before the end of the last transmission o r the STOP
bit (LIN0CTRL.7) has been set.
4DTREQ Data Request Bit. (slave mode only)
0: Data identifier has not been received.
1: Data identifier has been received.
3LININT Interrupt Request Bit.
0: An interrupt is not pending. This bit is cleared by setting RSTINT (LIN0CTRL.3)
1: There is a pending LIN0 interrupt.
2ERROR Communication Error Bit.
0: No error has been detected. This bit is cleared by setting RSTERR (LIN0CTRL.2)
1: An error has been detected.
1WAKEUP Wakeup Bit.
0: A wakeup signal is not bein g tra n sm i tte d an d has not be en rec eiv ed .
1: A wakeup signal is being transmitted or has been received
0DONE Transmission Complete Bit.
0: A transmission is not in progress or has not been started. This bit is cleared at th e
start of a transmission.
1: The current transmission is complete.
C8051F55x/56x/57x
206 Rev. 1.2
Indirect Address = 0x0A
LIN Register Definition 20.7. LIN0ERR: LIN0 Error Register
Bit76543210
Name SYNCH PRTY TOUT CHK BITERR
Type RRRRRRRR
Reset 00000000
Bit Name Function
7:5 Unused Read = 000b; Write = Don’t Care
4SYNCH Synchronization Error Bit (slave mode only).
0: No error with the SYNCH FIELD has been detected.
1: Edges of the SYNCH FIELD are outside of the maximum tolerance.
3PRTY Parity Error Bit (slave mode only).
0: No parity error has been detected.
1: A parity error has been detected.
2TOUT Timeout Error Bit.
0: A timeout error has not been detected.
1: A timeout error has been detected. This error is detected whenever one of the fol-
lowing conditions is met:
• The ma st er is expe ctin g data from a slav e an d th e sla ve do e s not resp o nd .
• The slave is expecting data but no data is transmitted on the bus.
• A frame is not finished within the maximum frame length.
• The application does not set the DTACK bit (LIN0CTRL.4) or STOP bit
(LIN0CTRL.7) until the end of the reception of the first byte after the identifier.
1CHK Checksum Error Bit.
0: Checksum error has not been detected.
1: Checksum error has been detected.
0BITERR Bit Transmission Error Bit.
0: No error in transmission has been detected.
1: The bit value monitored during transmission is different than the bit value sent.
C8051F55x/56x/57x
Rev. 1.2 207
Indirect Address = 0x0B
LIN Register Definition 20.8. LIN0SIZE: LIN0 Message Size Register
Bit 7 6 5 4 3 2 1 0
Name ENHCHK LINSIZE[3:0]
Type R/W R R R R/W
Reset 00000000
Bit Name Function
7ENHCHK Checksum Selection Bit.
0: Use the classic, specification 1.3 compliant checksum. Checksum covers the
data bytes.
1: Use the enhanced, specification 2.0 compliant checksum. Checksum covers data
bytes and protected identifier.
6:4 Unused Read = 000b; Write = Don’t Care
3:0 LINSIZE[3:0] Data Field Size.
0000: 0 data bytes
0001: 1 data byte
0010: 2 data bytes
0011: 3 data bytes
0100: 4 data bytes
0101: 5 data bytes
0110: 6 data bytes
0111: 7 data bytes
1000: 8 data bytes
1001-1110: RESERVED
1111: Use the ID[1:0] bits (LIN0ID[5:4]) to determine the data length.
C8051F55x/56x/57x
208 Rev. 1.2
Indirect Address = 0x0C
Indirect Address = 0x0D
LIN Register Definition 20.9. LIN0DIV: LIN0 Divider Register
Bit 7 6 5 4 3 2 1 0
Name DIVLSB[3:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 DIVLSB LIN Baud Rate Divider Least Significant Bits.
The 8 least significant bits for the b aud rate divid er. The 9th and most significant bit
is the DIV9 bit (LIN0MUL.0). The valid range for the divider is 200 to 511.
LIN Register Definition 20.10. LIN0MUL: LIN0 Multiplier Register
Bit 7 6 5 4 3 2 1 0
Name PRESCL[1:0] LINMUL[4:0] DIV9
Type R/W R/W R/W
Reset 11111111
Bit Name Function
7:6 PRESCL[1:0] LIN Baud Rate Prescaler Bits.
These bits are the bau d ra te pr escaler bits.
5:1 LINMUL[4:0] LIN Baud Rate Multiplier Bits.
These bits are the bau d rate m ultip lie r bi ts. These bits ar e not used in slave mode.
0DIV9 LIN Baud Rate Divider Most Significant Bit.
The most significant bit of the baud rate divider. The 8 least significant bits are in
LIN0DIV. The valid range for the divider is 200 to 511.
C8051F55x/56x/57x
Rev. 1.2 209
Indirect Address = 0x0E
LIN Register Definition 20.11. LIN0ID: LIN0 Identifier Register
Bit 7 6 5 4 3 2 1 0
Name ID[5:0]
Type R R R/W
Reset 00000000
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care.
5:0 ID[5:0] LIN Identifier Bits.
These bits form the data identifier.
If the LINSIZE bit s (LIN0SIZE[3:0]) are 1111b, bits ID[5:4] are used to determine the
data size and are inter preted as follows:
00: 2 bytes
01: 2 bytes
10: 4 bytes
11: 8 bytes
C8051F55x/56x/57x
Rev. 1.2 210
21. Controller Area Network (CAN0)
Important Documentation Note: The Bosch CAN Controller is integrated in the C8051F550/1/4/5, ‘F560/
1/4/5/8/9, and ‘F572/3 devices. This section of the data sheet gives a description of the CAN controller as
an overview and offers a description of how the Silicon Labs CIP-51 MCU interfaces with the on-chip
Bosch CAN controller. In order to use the CAN controller, refer to Bosch’s C_CAN User’s Manual as an
accompanying manual to the Silicon Labs’ data sheet.
The C8051F550/1/4/5, ‘F560/1/4/5/8/9, and ‘F572/3 devices feature a Control Area Network (CAN) con-
troller that enables serial co mmun ication using the CAN pr otocol. Silicon La bs CAN fa cili tates communica-
tion on a CAN network in accordance with the Bosch specification 2.0A (basic CAN) and 2.0B (full CAN).
The CAN controller consists of a CAN Core, Message RAM (separate from the CIP-51 RAM), a message
handler state machine, and control registers. Silicon Labs CAN is a protocol controller and does not pro-
vide physical layer drivers (i.e., transceivers). Figure 21.1 shows an example typical configuration on a
CAN bus.
Silicon Labs’ CAN operates at bit rates of up to 1 Mbit/second, though this can be limited by the physical
layer chosen to transmit data on the CAN bus. The CAN processor has 32 Message Objects that can be
configured to transmit or receive data. Incoming data, message objects and their identifier masks are
stored in the CAN message RAM . All protocol functions for transmission of dat a and accept a nce filtering is
performed by the CAN controller and not by the CIP-51 MCU. In this way, minimal CPU bandwidth is
needed to use CAN communication. The CIP-51 configures the CAN controller, accesses received data,
and passes data for transmission via Special Function Registers (SFRs) in the CIP-51.
Figure 21.1. Typical CAN Bus Configuration
Silicon Labs MCU
CANTX CANRX
CAN_H
CAN_L
Isolati on/Buffer (Optional)
CAN
Transceiver
Isolation/Buffer (Optional)
CAN
Transceiver
Isolation/Buffer (Optional)
CAN
Transceiver
RR
CAN Protocol Device CAN Protocol Device
C8051F55x/56x/57x
211 Rev. 1.2
21.1. Bosch CAN Controller Operation
The CAN Controller featured in the C8051F550/1/4/5, ‘F560/1/4/5/8/9, and ‘F572/3 devices is a full imple-
mentation of Bosch’s full CAN module and fully complies with CAN specification 2.0B. A block diagram of
the CAN controller is shown in Figure 21.2. The CAN Core provides shifting (CANTX and CANRX), serial/
parallel conversion of messages, and other protocol related t asks such a s tran smission of data and accep-
tance filtering. The message RAM stores 32 message objects which can be received or transmitted on a
CAN network. The CAN registers and message handler provide an interface for data transfer and notifica-
tion between the CAN controller and the CIP-51.
The function and use of the CAN Controller is detailed in the Bosch CAN User’s Guide. The User ’s Guide
should be used as a reference to configure and use the CAN controller. This data sheet describes how to
access the CAN controller.
All of the CAN controller registers are loca ted on SF R Page 0x0C. Before accessin g any of th e CAN r egis-
ters, the SFRPAGE register must be set to 0x0C.
The CAN Controller is typically initialized using the following steps:
1. Set the SFRPAGE register to the CAN registers page (p age 0x0C).
2. Set the INIT and the CCE bits to 1 in CAN0CN. See the CAN User’s Guide for bit definitions.
3. Set timing parameters in the Bit Timing Register and the BRP Extension Register.
4. Initialize each message object or set its MsgVal bit to NOT VALID.
5. Reset the INIT bit to 0.
Figure 21.2. CAN Controller Diagram
21.1.1. CAN Controller Timing
The CAN controller’s clock (fsys) is derived from the CIP-51 system clock (SYSCLK). The internal oscillator
is accurate to within 0.5% of 24 MHz across the entire temperature range and for VDD voltages greater
than or equal to the minimum output of the on-chip voltage regulator, so an external oscillator is not
required for CAN communication for most systems.
Refer to Section “4.10.4 Oscillator Tolerance Range” in the Bosch CAN User ’s Guide for further informa-
tion regarding this topic.
8051 M CU Core
TXRX
System Clock
M essage
RAM
(32 Objects)
CAN Registers
m apped to
SFR space
M essage
Handler
CAN Core
CAN Controller
CAN0CFG
C8051F55x/56x/57x
Rev. 1.2 212
The CAN controller clock must be less than or equal to 25 MHz. If the CIP-51 system clock is above
25 MHz, the divider in the CAN0CFG register must be set to divide the CAN controller clock down to an
appropri at e sp ee d.
21.1.2. CAN Register Access
The CAN controller clock divider selected in the CAN0CFG SFR affects how the CAN registers can be
accessed. If the divider is set to 1, then a CAN SFR can immediately be read after it is written. If the divider
is set to a value other than 1, then a read of a CAN SFR that has just been written must be delayed by a
certain number of cycles. This delay can be performed using a NOP or some other instruction that does
not attempt to read the register. This access limitation applies to read and read-modify-write instructions
that occur immediately af ter a write. The full li st of af fected instructions is ANL, ORL, MOV, XCH, and XRL.
For example, with the CAN0CFG divider set to 1, the CAN0CN SFR can be accessed as follows:
MOV CAN0CN, #041 ; Enable access to Bit Timing Register
MOV R7, CAN0CN ; Copy CAN0CN to R7
With the CAN0CFG divider set to /2, the same exam ple code requires an additional NOP:
MOV CAN0CN, #041 ; Enable access to Bit Timing Register
NOP ; Wait for write to complete
MOV R7, CAN0CN ; Copy CAN0CN to R7
The number of delay cycles requ ired is depend ent on the divider se tting . With a divid er of 2, the read must
wait for 1 system clock cycle. With a divider of 4, the read must wait 3 system clock cycles, and with the
divider set to 8, the read must wait 7 system clock cycles. The delay only needs to be applied when read-
ing the same register that was written. The application can write and read other CAN SFRs without any
delay.
21.1.3. Example Timing Calculation for 1 Mbit/Sec Communication
This example shows how to configure the CAN controller timing parameters for a 1 Mbit/Sec bit rate.
Table 21.1 shows timing-related system parameters needed for the calculation.
Each bit transmitted on a CAN network has 4 segments (Sync_Seg, Prop_Seg, Phase_Seg1, and
Phase_Seg2), as shown in Figure 18.3. The sum of these segments determines the CAN bit time (1/bit
rate). In this example, the desired bit rate is 1 Mbit/sec; therefore, the desired bit time is 1000 ns.
Table 21.1. Background System Information
Parameter Value Description
CIP-51 system clock (SYSCLK) 24 MHz Internal Os cillat or Ma x
CAN controller clock (fsys) 24 MHz CAN0CFG divider set to 1
CAN clock period (tsys)41.667 ns Derived from 1/fsys
CAN time quantum (tq)41.667 ns Derived from tsys x BRP1,2
CAN bus length 10 m 5 ns/m signal delay between CAN nodes
Propogation delay time3400 ns 2 x (transceiver loop delay + bus line delay)
Notes:
1. The CAN time quantum is the smallest unit of time recognized by the CAN controller. Bit timing parameters
are specified in integer multiples of the time quantum.
2. The Baud Rate Prescaler (BRP) is defined as the value of the BRP Extension Register plus 1. The BRP
extension register has a reset value of 0x0000. The BRP has a reset value of 1.
3. Based on an ISO-11898 compliant transceiver. CAN does not specify a physical layer.
C8051F55x/56x/57x
213 Rev. 1.2
Figure 21.3. Four segments of a CAN Bit
The length of the 4 bit segments must be adjusted so that their sum is as close as possible to the desired
bit time. Since each segment must be an integer multiple of the time quantum (tq), the closest achievable
bit time is 24 tq (1000.008 ns), yielding a bit rate of 0.999992 Mbit/sec. The Sync_Seg is a consta nt 1 tq.
The Prop_Seg must be greater than or equal to the propagation delay of 4 00 ns and so the choice is 10 tq
(416.67 ns).
The remaining time quanta (13 tq) in the bit time are divided between Phase_Seg1 and Phase_Seg2 as
shown in. Based on this equation, Phase_Seg1 = 6 tq and Phase_Seg2 = 7 tq.
1. If Phase_Seg1 + Phase_Seg2 is even, then Phase_Seg2 = Phase_Seg1. If the sum is odd, Phase_Seg2 =
Phase_Seg1 + 1.
2. Phase_Seg2 should be at least 2 tq.
Equation 21.1. Assigning the Phase Segments
The Synchronization Jump Wid t h (SJW) timing p aramete r is defined by. It is used for determining the value
written to th e Bit Timing Register a nd for de termin ing the r equire d oscillat or tole rance. Since we are u sing
a quartz crystal as th e system clock source, an oscillator tolerance calculation is not needed.
Equation 21.2. Synchronization Jump Width (SJW)
The value written to the Bit Timing Register can be calculated using Equation 18.3. The BRP Extension
register is left at its reset value of 0x0000.
Bit Timing Register = (TSEG2 x 0x1000) + (TSEG1 x 0x0100) + (SJWp x 0x0040) + BRPE = 0x6FC0
Equation 21.3. Calculating the Bit Timing Register Value
Prop_Seg Phase_Seg1 Phase_Seg2
CAN Bit Time (4 to 25 tq)
Sync_Seg
1tq 1 to 8 tq1 to 8 tq1 to 8 tq
1tq Sample Point
Phase_Seg1 + Phase_Seg2 = Bit_Time – (Synch_Seg + Prop_Seg)
SJW = minimum (4, Phase_Seg1)
BRPE = BRP – 1 = BRP Extension Register = 0x0000
SJWp = SJW – 1 = minimum (4, 6) – 1 = 3
TSEG1 = Prop_Seg + Phase_Seg1 - 1 = 1 0 + 6 – 1 = 15
TSEG2 = Phase_Seg2 – 1 = 6
Bit Timing Register = (TSEG2 x 0x1000) + (TSEG1 x 0x0100)
C8051F55x/56x/57x
Rev. 1.2 214
21.2. CAN Registers
CAN registers are classified as follows:
1. CAN Controller Protocol Registers: CAN control, interrupt, error control, bus status, test modes.
2. Message Object Interface Registers: Used to configure 32 Message Objects, send and receive data
to and from Message Objects. The CIP-51 MCU accesses the CAN message RAM via the Message
Object Interface Registers. Upon wr iting a messa ge object num ber to an IF1 or IF2 Co mmand Requ est
Register , the contents of the associated Interface Registers (IF1 or IF2) will be transferred to or from the
message object in CAN RAM.
3. Message Handler Registers: These read only registers are used to provide information to the CIP-51
MCU about the message object s (MSGVLD flags, Transmission Request Pending, New Data Flags)
and Interrupt s Pend ing (which Me ssa ge Objects have caused an interrupt or status interrup t con dition).
For the registers other than CAN0CFG, refer to the Bosch CAN User ’s Guide for information on the func-
tion and use of the CAN Co nt ro l Protoc o l Reg iste rs .
21.2.1. CAN Controller Protocol Registers
The CAN Control Protocol Registers are used to configure the CAN controller, process interrupts, monitor
bus status, and place the controller in test modes.
The registers are: CAN Control Register (CAN0CN), CAN Clock Configuration (CAN0CFG), CAN Status
Register (CAN0STA), CAN Test Register (CAN0TST), Error Counter Register, Bit Timing Register, and the
Baud Rate Prescaler (BRP) Extension Register.
21.2.2. Message Object Interface Registers
There are two sets of Message Object Interface Registers used to configure t he 32 Messag e Objects that
transmit and receive data to and from the CAN bus. Message objects can be configured for transmit or
receive, and are assigned arbitration message identifiers for acceptance filterin g by all CAN no de s.
Message Objects are stored in Message RAM, and are accessed and configured using the Message
Object Interface Registers.
21.2.3. Message Handler Registers
The Message Handler Registers are read only registers. The message handler registers provide interrupt,
error, transmit/receive requests, and new data information.
C8051F55x/56x/57x
215 Rev. 1.2
21.2.4. CAN Register Assignment
The st a ndard Bosch CAN r egisters ar e m app ed to SFR space as shown below and their full definition s are
available in the CAN Use r’s Guide. The name shown in the Name column matches what is provided in the
CAN User's Guide. One additional SFR which is not a standard Bosch CAN register, CAN0CFG, is pro-
vided to configure the CAN clock. All CAN registers are located on SFR Page 0x0C.
Table 21.2. Standard CAN Registers and Reset Values
CAN
Addr. Name SFR Name
(High) SFR
Addr. SFR Name
(Low) SFR
Addr. 16-bit
SFR Reset
Value
0x00 CAN Control Register — — CAN0CN 0xC0 —0x01
0x02 Status Register — — CAN0STAT 0x94 —0x00
0x04 Error Counter1CAN0ERRH 0x97 CAN0ERRL 0x96 CAN0ERR 0x0000
0x06 Bit Timing Register2CAN0BTH 0x9B CAN0BTL 0x9A CAN0BT 0x2301
0x08 Interrupt Register1CAN0IIDH 0x9D CAN0IIDL 0x9C CAN0IID 0x0000
0x0A Test Register — — CAN0TST 0x9E —0x003,4
0x0C BRP Extension Register2— — CAN0BRPE 0xA1 —0x00
0x10 IF1 Command Request CAN0IF1CRH 0xBF CAN0IF1CRL 0xBE CAN0IF1CR 0x0001
0x12 IF1 Command Mask CAN0IF1CMH 0xC3 CAN0IF1CML 0xC2 CAN0IF1CM 0x0000
0x14 IF1 Mask 1 CAN0IF1M1H 0xC5 CAN0IF1M1L 0xC4 CAN0IF1M1 0xFFFF
0x16 IF1 Mask 2 CAN0IF1M2H 0xC7 CAN0IF1M2L 0xC6 CAN0IF1M2 0xFFFF
0x18 IF1 Arbitration 1 CAN0IF1A1H 0xCB CAN0IF1A1L 0xCA CAN0IF1A1 0x0000
0x1A IF1 Arbitration 2 CAN0IF1A2H 0xCD CAN0IF1A2L 0xCC CAN0IF1A2 0x0000
0x1C IF1 Message Co nt ro l CAN0IF1MCH 0xD3 CAN0IF1MCL 0xD2 CAN0IF1MC 0x0000
0x1E IF1 Data A 1 CAN0IF1DA1H 0xD5 CAN0IF1DA1L 0xD4 CAN0IF1DA1 0x0000
0x20 IF1 Data A 2 CAN0IF1DA2H 0xD7 CAN0IF1DA2L 0xD6 CAN0IF1DA2 0x0000
0x22 IF1 Data B 1 CAN0IF1DB1H 0xDB CAN0IF1DB1L 0xDA CAN0IF1DB1 0x0000
0x24 IF1 Data B 2 CAN0IF1DB2H 0xDD CAN0IF1DB2L 0xDC CAN0IF1DB2 0x0000
0x40 IF2 Command Request CAN0IF2CRH 0xDF CAN0IF2CRL 0xDE CAN0IF2CR 0x0001
0x42 IF2 Command Mask CAN0IF2CMH 0xE3 CAN0IF2CML 0xE2 CAN0IF2CM 0x0000
0x44 IF2 Mask 1 CAN0IF2M1H 0xEB CAN0IF2M1L 0xEA CAN0IF2M1 0xFFFF
0x46 IF2 Mask 2 CAN0IF2M2H 0xED CAN0IF2M2L 0xEC CAN0IF2M2 0xFFFF
0x48 IF2 Arbitration 1 CAN0IF2A1H 0xEF CAN0IF2A1L 0xEE CAN0IF2A1 0x0000
0x4A IF2 Arbitration 2 CAN0IF2A2H 0xF3 CAN0IF2A2L 0xF2 CAN0IF2A2 0x0000
0x4C IF2 Message Co nt ro l CAN0IF2MCH 0xCF CAN0IF2MCL 0xCE CAN0IF2MC 0x0000
0x4E IF2 Data A 1 CAN0IF2DA1H 0xF7 CAN0IF2DA1L 0xF6 CAN0IF2DA1 0x0000
Notes:
1. Read-only register .
2. Write-enabled by CCE.
3. The reset value of CAN0TST could also be r0000000b, where r signifies the value of the CAN RX pin.
4. Write-enabled by Test.
C8051F55x/56x/57x
Rev. 1.2 216
0x50 IF2 Data A 2 CAN0IF2DA2H 0xFB CAN0IF2DA2L 0xFA CAN0IF2DA2 0x0000
0x52 IF2 Data B 1 CAN0IF2DB1H 0xFD CAN0IF2DB1L 0xFC CAN0IF2DB1 0x0000
0x54 IF2 Data B 2 CAN0IF2DB2H 0xFF CAN0IF2DB2L 0xFE CAN0IF2DB2 0x0000
0x80 Transmission Request 11CAN0TR1H 0xA3 CAN0TR1L 0xA2 CAN0TR1 0x0000
0x82 Transmission Request 21CAN0TR2H 0xA5 CAN0TR2L 0xA4 CAN0TR2 0x0000
0x90 New Data 11 CAN0ND1H 0xAB CAN0ND1L 0xAA CAN0ND1 0x0000
0x92 New Data 21 CAN0ND2H 0xAD CAN0ND2L 0xAC CAN0ND2 0x0000
0xA0 Interrupt Pending 11CAN0IP1H 0xAF CAN0IP1L 0xAE CAN0IP1 0x0000
0xA2 Interrupt Pending 2 1CAN0IP2H 0xB3 CAN0IP2L 0xB2 CAN0IP2 0x0000
0xB0 Message Valid 11CAN0MV1H 0xBB CAN0MV1L 0xBA CAN0MV1 0x0000
0xB2 Message Valid 21CAN0MV2H 0xBD CAN0MV2L 0xBC CAN0MV2 0x0000
Table 21.2. Standard CAN Registers and Reset Values
CAN
Addr. N ame SFR Name
(High) SFR
Addr. SFR Name
(Low) SFR
Addr. 16-bit
SFR Reset
Value
Notes:
1. Read-only register .
2. Write-enabled by CCE.
3. The reset value of CAN0TST could also be r0000000b, where r signifies the value of the CAN RX pin.
4. Write-enabled by Test.
C8051F55x/56x/57x
217 Rev. 1.2
SFR Address = 0x92; SFR Page = 0x0C
SFR Definition 21.1. CAN0CFG: CAN Clock Configuration
Bit76543210
Name Unused Unused Unused Unused Unused Unused SYSDIV[1:0]
Type RRRRRR R/W
Reset 00000000
Bit Name Function
7:2 Unused Read = 000000b; W rite = Don’t Care.
1:0 SYSDIV[1:0] CAN System Clock Divider Bits.
The CAN controller clock is derived from the CIP-51 system clock. The CAN control-
ler clock must be less than or equal to 25 MHz.
00: CAN controller clock = System Clock/1.
01: CAN controller clock = System Clock/2.
10: CAN controller clock = System Clock/4.
11: CAN controller clock = System Clock/8.
C8051F55x/56x/57x
Rev. 1.2 218
22. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, dependin g on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface m ay opera te as a ma ster an d/or sla ve, and may function on a bus with multip le ma s-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. A block diagram of the SMBus peripheral and
the associated SFRs is shown in Figure 22.1.
Figure 22.1. SMBus Block Diagram
Data Path
Control
SMBUS CONTROL LOGIC
C
R
O
S
S
B
A
R
SCL
FILTER
N
SDA
Control
SCL
Control
Interrupt
Request
Port I/O
SMB0CN
S
T
A
A
C
K
R
Q
A
R
B
L
O
S
T
A
C
K
S
I
T
X
M
O
D
E
M
A
S
T
E
R
S
T
O
01
00
10
11
T0 Overflow
T1 Overflow
TMR2H Overflo w
TMR2L Overflow
SMB0CF
E
N
S
M
B
I
N
H
B
U
S
Y
E
X
T
H
O
L
D
S
M
B
T
O
E
S
M
B
F
T
E
S
M
B
C
S
1
S
M
B
C
S
0
01234567 SMB0DAT SDA
FILTER
N
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
IRQ Generation
C8051F55x/56x/57x
219 Rev. 1.2
22.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor.
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
22.2. SMBus Configuration
Figure 22.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; di f feren t devices on th e bus may oper ate at di fferent voltage levels. The bi-d ire c-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on th e bus is limited o nly by th e re quirem ent that the r ise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
Figure 22.2. Typical SMBus Configuration
22.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. It is n ot necessary to specify one device
as the Master in a system; any device who transmits a START and a slave address becomes the master
for the duration of th at transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see
Figure 22.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
The direction bi t (R/W) occupies the least-significan t bit position of the address byte. The d irection bit is set
to logic 1 to indicate a "READ" operation and cleare d to logic 0 to indicate a "WRITE" operation.
VIO = 5 V
Master
Device Slave
Device 1 Slave
Device 2
VIO = 3 V VIO = 5 V VIO = 3 V
SDA
SCL
C8051F55x/56x/57x
Rev. 1.2 220
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer , the master
generates a STOP condition to terminate the transaction and free the bus. Figure 22.3 illustrates a typical
SMBus transaction.
Figure 22.3. SMBus Transaction
22.3.1. Transmitter Vs. Receiver
On the SMBus communications interface, a device is the “transmitter” when it is sending an address or
data byte to another device on the bu s. A de vice is a “receive r” when an addr ess or dat a byte is bein g sent
to it from another device on the bus. The transmitte r controls the SDA line during the address or data byte.
After each byte of address or data information is sent by the transmitter, the receiver sends an ACK or
NACK bit during the ACK phase of the transfer, during which tim e th e re ce iver contr ols th e SDA line.
22.3.2. Arbitration
A master may st art a transfer on ly if the bus is free. The b us is free af ter a ST OP con dition or af ter the SCL
and SDA lines remain high for a specified time (see Section “22.3.5. SCL High (SMBus Free) Timeout” on
page 221). In the event that two or more devices attempt to begin a transfer at the same time, an arbitra-
tion scheme is employed to force one master to give up the bus. The master devices continue transmitting
until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be
pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning
master continues its transmission withou t interruption; the losing ma ster becomes a slave and receives the
rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and
no data is lost.
22.3.3. Clock Low Extension
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line
LOW to extend the clock low period, effectively decreasing the serial clock frequency.
22.3.4. SCL Low Timeout
If the SCL line is held low b y a slave device on the bus, n o further commun ication is possible . Furthermore,
the master ca nnot for ce the SCL lin e high t o correc t the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
When the S MBTOE bit in SM B0 CF is se t, Timer 3 is used to de te ct SCL low time ou ts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
SLA6
SDA SLA5-0 R/W D7 D6-0
SCL
Slave Address + R/W Data ByteSTART ACK NACK STOP
C8051F55x/56x/57x
221 Rev. 1.2
overflow after 25 ms (and SMBTOE set), the T i mer 3 interrupt service routine ca n be used to reset ( disable
and re-enable) the SMBus in the event of an SCL low timeout.
22.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this tim eout. Note that a clock source is requ ired for free ti meout detection, ev en in a slave- only
implementation.
22.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
SMBus interrupts are generated for each data byte or slave address that is transferred. The point at which
the interrupt is generated depends on whether the hardware is acting as a data transmitter or receiver.
When a transmitter (i.e. sending addr ess/d at a , r eceiving an ACK), this interrupt is g ene rate d after the ACK
cycle so that software may read the received ACK value; when receiving data (i.e. receiving address/data,
sending an ACK), this interrupt is generated before the ACK cycle so that software may define the outgo-
ing ACK value. See Section 22.5 for more details on transmission sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 22.4.2;
Table 22.4 pro vides a quick SMB0CN decoding reference.
22.4.1. SMBus Configuration Re gi st er
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current tra ns fe r) .
C8051F55x/56x/57x
Rev. 1.2 222
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as de fined in Equation 22.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “25. Timers” on page 259.
Equation 22.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 22.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 22.2.
Equation 22.2. Typical SMBus Bit Rate
Figure 22.4 shows the typical SCL generation described by Equation 22.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 22.1.
Figure 22.4. Typical SMBus SCL Generation
Table 22.1. SMBus Clock Source Selection
SMBCS1 SMBCS0 SMBus Clock Source
0 0 Timer 0 Overflow
0 1 Timer 1 Overflow
1 0 Timer 2 High Byte Overflow
1 1 Timer 2 Low Byte Overflow
THighMin TLowMin 1
fClockSourceOverflow
-------------------------------------------------
==
BitRate fClockSourceOverflow
3
-------------------------------------------------
=
SCL
Timer Source
Overflows
SCL High Ti meoutT
Low
T
High
C8051F55x/56x/57x
223 Rev. 1.2
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL tran sitions from low-to- high.
The minimum SDA hold time de fines the absolute mini mum time that the cur rent SDA value remains stabl e
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 22.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “22.3.4. SCL Low Timeout” on page 220). The S MBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The T imer 3 interrupt service routin e
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free T imeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 22.4).
Table 22.2. Minimum SDA Setup and Hold Times
EXTHOLD Minimum SDA Setup Time Minimum SDA Hold Time
0 Tlow – 4 system clocks
or
1 system clock + s/w delay*
3 system clocks
111 system clocks 12 system clocks
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
C8051F55x/56x/57x
Rev. 1.2 224
SFR Address = 0xC1; SFR Page = 0x00
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration
Bit76543210
Name ENSMB INH BUSY EXTHOLD SMBTOE SMBFTE SMBCS[1:0]
Type R/W R/W RR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7ENSMB SMBus Enable.
This bit enables the SMBus interface when set to 1. When enabled, the interface
constantly monitors the SDA and SCL pins.
6INH SMBus Slave Inhibit.
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave
events occur. This effectively rem oves the SMBus slave from the bus. Master Mode
interrupts are not affected.
5BUSY SMBus Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to
logic 0 when a STOP or free -timeout is sensed.
4EXTHOLD SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to Table 22.2.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
3SMBTOE SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout de tection. If set to logic 1, the SMBus forces
Timer 3 to reload while SCL is high an d allows Timer 3 to count when SCL goes low.
If T imer 3 is configured to Split Mode, only the High Byte of the timer is held in reload
while SCL is high. Timer 3 should be programmed to ge nerate interrupts at 25 ms,
and the Timer 3 interrupt ser vice r outine should reset SMBus communication.
2SMBFTE SMBus Free T imeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain
high for more than 10 SMBus clock source periods.
1:0 SMBCS[1:0] SMBus Clock Source Selection.
These two bit s select th e SMBus clock sour ce, which is used to generate the SMBus
bit rate. The selected device should be configured according to Equation 22.1.
00: Timer 0 Overflow
01: Timer 1 Overflow
10:Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
C8051F55x/56x/57x
225 Rev. 1.2
22.4.2. SMB0CN Control Regi st er
SMB0CN is used to control the interface and to provide status information (see SFR Definition 22.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER indicates whether a device is the master or slave during the current
transfer. TXMODE indicates whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to gene ra te START and STOP conditions when operating as a mas-
ter. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when
the bus be comes fr ee (STA is not c leared b y hardwa re after the START is generated). Writing a 1 to STO
while in Master Mode will cause the interface to generate a STOP and end the current transfer after the
next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be
generated.
As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit
indicates the value received during th e last ACK cycle . ACKRQ is set each time a byte is received, indicat-
ing that an outgo ing ACK value is nee ded. When ACKRQ is set, sof tware should wr ite the desired ou tgoing
value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit
before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit;
however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further
slave events will be ignored until the next START is detected.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condi-
tion. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginn ing and end of each tran sfer, after each byte frame, or
when an arbitration is lost; see Table 22.3 for more details.
Import ant Note About t he SI Bit : The SMBus interface is st alled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
C8051F55x/56x/57x
Rev. 1.2 226
SFR Address = 0xC0; Bit-Addressable; SFR Page =0x00
SFR Definition 22.2. SMB0CN: SMBus Control
Bit76543210
Name MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI
Type R R R/W R/W R R R/W R/W
Reset 00000000
Bit Name Description Read Write
7MASTER SMBus Master/Slave
Indicator. This read-on ly bit
indicates when the SMBus is
operating as a master.
0: SMBus operating in
slave mode.
1: SMBus operating in
master mode.
N/A
6TXMODE SMBus Transmit Mode
Indicator. This read-on ly bit
indicates when the SMBus is
operating as a transmitter.
0: SMBus in Receiver
Mode.
1: SMBus in Transmitter
Mode.
N/A
5STASMBus Start Flag. 0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4STO SMBus Stop Flag. 0: No Stop condition
detected.
1: Stop condition detected
(if in Slave Mode) or pend-
ing (if in Master Mode).
0: No STOP condition is
transmitted.
1: When configured as a
Master, causes a STOP
condition to be transmit-
ted afte r the next ACK
cycle.
Cleared by Hardware.
3ACKRQ SMBus Acknowledge
Request. 0: No Ack requested
1: ACK requested N/A
2ARBLOST SMBus Arbitration Lost
Indicator. 0: No arbitration error.
1: Arbitration Lost N/A
1ACK SMBus Acknowledge. 0: NACK received.
1: ACK received. 0: Send NACK
1: Send ACK
0SI SMBus Interrupt Flag.
This bit is set by hardware
under the conditions listed in
Table 15.3. SI must be cleared
by software. While SI is set,
SCL is held low and the
SMBus is stalled.
0: No interrupt pending
1: Interrupt Pending 0: Clear interrupt, and initi-
ate next state machine
event.
1: Force interrupt.
C8051F55x/56x/57x
227 Rev. 1.2
Table 22.3. Sources for Hardware Changes to SMB0CN
Bit Set by Hardware When: Cleared by Hardware When:
MASTER A START is generated. A STOP is generated.
Arbitration is lost.
TXMODE START is generated.
SMB0DAT is written before the start of an
SMBus frame.
A START is detected.
Arbitration is lost.
SMB0DAT is not written before the
start of an SMBus frame.
STA A START followed by an address byte is
received. Must be cleared by software.
STO A STOP is detected while addressed as a
slave.
Arbitration is lost due to a detected STOP.
A pending STOP is generated.
ACKRQ A byte has been received and an ACK
response value is needed. After each ACK cycle.
ARBLOST A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
SDA is sensed low while transmitting a 1
(excluding ACK bits).
Each time SI is cleared.
ACK The incoming ACK value is low
(ACKNOWLEDGE). The incoming ACK value is high
(NOT ACKNOWLEDGE).
SI A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
Must be cleared by software.
C8051F55x/56x/57x
Rev. 1.2 228
22.4.3. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Sof tware may safely rea d or write to the da ta register when the SI flag is set. Software should not
attempt to ac cess the SMB0DAT register when the SM Bus is enable d and the SI flag is cleared to logic 0,
as the interface may be in th e process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte pre sent on the bu s. In th e even t of lost a rbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
SFR Address = 0xC2; SMB0DAT = 0x00
22.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mod e any time a START is generate d, and rem ains i n
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. As a receiver, the interrupt for an ACK occurs before the ACK. As a transmitter,
interrupts occur after the ACK.
SFR Definition 22.3. SMB0DAT: SMBus Data
Bit76543210
Name SMB0DAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SMB0DAT[7:0] SMBus Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus
serial interface or a byte th at has just been received on the SMBu s serial interface.
The CPU can read fr om or write to this re gister whenever the SI serial interru pt flag
(SMB0CN.0) is set to logic 1. The serial data in the register remains stable as long
as the SI flag is set. When the SI flag is not set, the system may be in the process
of shifting data in/out and the CPU should not attempt to access this register.
C8051F55x/56x/57x
229 Rev. 1.2
22.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. Th e master in this transfer will be
a transmitter during the ad dress byt e, and a tra nsmitte r during all data bytes. The SMBus interfac e gener -
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface
will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 22.5 shows a typical master write sequence. Two transmit data bytes are shown, though any num-
ber of bytes may be transmitted. Notice that all of the ‘data byte transferred’ interrupts occur after the ACK
cycle in this mode.
Figure 22.5. Typical Master Write Sequence
A AAS W PDa ta B y te Da ta By teSLA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Received by SMBus
Interface
Transm itted by
SM Bus Interface
Interrupts
C8051F55x/56x/57x
Rev. 1.2 230
22.5.2. Read Sequence (Master)
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then
received from the slav e on SDA while th e SMBus outp ut s the seria l clock. The slave transmit s one o r more
bytes of serial data. An interrupt is generated after each received byte.
Software must write the ACK bit at that time to ACK or NACK the received byte. Writing a 1 to the ACK bit
generates an ACK; writing a 0 generate s a NACK. Sof tware should wr ite a 0 to the ACK bit for the last dat a
transfer, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and a
STOP is generated. The interface will switch to Master Transmitter Mode if SMB0DAT is written while an
active Master Receiver. Figure 22.6 shows a typical master read sequence. Two received data bytes are
shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts
occur before the ACK cycle in this mode.
Figure 22.6. Typical Master Read Sequence
Da ta By teDa ta By te A NAS R PSLA
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
R eceived by SMBus
Interface
Transmitted by
SMBu s In te rfa c e
Interrupts
C8051F55x/56x/57x
231 Rev. 1.2
22.5.3. Write Sequence (Slave)
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc-
tion bit (WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated
and the ACKRQ bit is set. The sof tware mu st respond to the received slave addre ss with an ACK, or ignore
the received slave address with a NACK.
If the received slave address is ignored, slave interrupts will be inhibited until the next START is detected.
If the received slave address is acknowledged, zero or more data bytes are received. Software must write
the ACK bit at that time to ACK or NACK the received byte.
The interface exits Slave Receiver Mode af ter receiving a ST OP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 22.7 shows a typical slave
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice
that the ‘data byte tran sferred’ interrupts occur before the ACK in this mode.
Figure 22.7. Typical Slave Write Sequence
PWSLASDa ta By teDa ta By te A AA
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
R eceived by S M Bus
Interface
Transm itted by
SMB u s In terfa c e
Interrupts
C8051F55x/56x/57x
Rev. 1.2 232
22.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the inter face enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. The interrupt will
occur after the ACK cycle.
If the received slave address is ignored, slave interrupts will be inhibited until the next START is detected.
If the received slave address is acknowledged, zero or more data bytes are transmitted. If the received
slave address is acknowledged, data should be written to SMB0DAT to be transmitted. The interface
enters Slave T ran smitter Mode, and transmit s one or more bytes of data. Af ter each byte is transmitted , the
master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT shou ld be written with the
next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared
(Note: an error condition may be generated if SMB0DAT is written following a received NACK while in
Slave Transmitter Mode). The in terface exits Slave T ran smitter Mode after receiving a STOP. Note that the
interface will switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter inter-
rupt. Figure 22.8 shows a typical slave read sequence. Two transmitted data bytes are shown, though any
number of bytes may be transmitted. Notice that all of the ‘data byte transferred’ interrupts occur after the
ACK cycle in this mode.
Figure 22.8. Typical Slave Read Sequence
22.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the tables, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown
response options are only the typical responses; application-specific procedures are allowed as long as
they conform to the SMBus specification. Highlighted responses are allowed by hardware but do not con-
form to the SMBus specification.
PRSLASDa ta By teDa ta By te A NA
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
R eceived by S M Bus
Interface
Transm itted by
SMB u s In terfa c e
Interrupts
C8051F55x/56x/57x
233 Rev. 1.2
Table 22.4. SMBus Status Decoding
Mode
Values Read Current SMbus State Typical Response Options Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
Master Transmitter
1110 00XA master START was gener-
ated. Load slave address + R/W into
SMB0DAT. 0 0 X 1100
1100 000A master dat a or addre ss byte
was transmitted; NACK
received.
Set STA to restart transfer. 1 0 X 1110
Abort transfer. 0 1 X —
001A master dat a or ad dress byte
was transmitted; ACK
received.
Load next data byte into SMB0-
DAT. 0 0 X 1100
End transfer with STOP. 0 1 X —
End transfer with STOP and start
another transfer. 1 1 X —
Send repeated START. 1 0 X 1110
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
0 0 X 1000
Master Receiver
1000 10XA master data byte was
received; ACK requ ested. Acknowledge received byte;
Read SMB0DAT. 0 0 1 1000
Send NACK to indicate last byte ,
and send STOP. 0 1 0 —
Send NACK to indicate last byte ,
and send STOP followed by
START.
1 1 0 1110
Send ACK followed by repeated
START.1 0 1 1110
Send NACK to indicate last byte ,
and send repeated START. 1 0 0 1110
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
0 0 1 1100
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
0 0 0 1100
C8051F55x/56x/57x
Rev. 1.2 234
Slave Transmitter
0100 000A slave byte was transmitted;
NACK received. No action required (expecting
STOP condition). 0 0 X 0001
001A slave byte was transmitted;
ACK received. Load SMB0DAT with next data
byte to transmit. 0 0 X 0100
01XA Slave byte was transmitted;
error detected. No action required (expecting
Master to end transfer). 0 0 X 0001
0101 0XXAn illegal STOP or bus error
was detected while a Slave
Transmission was in progress.
Clear STO. 0 0 X —
Slave Receiver
0010 10XA slave address + R/W was
received; ACK requ ested. If Write, Acknowledge re ce ive d
address 0 0 1 0000
If Read, Load SMB0DAT with
data byte; ACK re ceived addr ess 0 0 1 0100
NACK received addres s. 0 0 0 —
11XLost arbitra tio n as m ast er ;
slave address + R/W received;
ACK requested.
If Write, Acknowledge received
address 0 0 1 0000
If Read, Load SMB0DAT with
data byte; ACK re ceived addr ess 0 0 1 0100
NACK received addres s. 0 0 0 —
Reschedule failed transfer;
NACK received addres s. 1 0 0 1110
0001 00XA STO P was detected whil e
addresse d as a Slav e Trans-
mitter or Slave Receiver.
Clear STO. 0 0 X —
11XLost arbitration while attempt-
ing a STOP. No action required (transfer
complete/aborted). 0 0 0 —
0000 10XA slave byte was received;
ACK requested. Acknowledge received byte;
Read SMB0DAT. 0 0 1 0000
NACK received byte. 0 0 0 —
Bus Error Condition
0010 01XLost arbitration while attempt-
ing a repeated START. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0001 01XLost arbitratio n du e to a
detected STOP. Abort failed transfer. 0 0 X —
Reschedule failed transfer. 1 0 X 1110
0000 11XLost arbitration while transmit-
ting a data byte as master. Abort failed transfer. 0 0 0 —
Reschedule failed transfer. 1 0 0 1110
Table 22.4. SMBus Status Decoding (Continued)
Mode
Values Read Current SMbus State Typical Response Options Values to
Write
Next Status
Vector Expected
Status
Vector
ACKRQ
ARBLOST
ACK
STA
STO
ACK
C8051F55x/56x/57x
Rev. 1.2 235
23. UART0
UART0 is an asynch ronou s, full dup lex serial port offering a variety of data formatting options. A dedicate d
baud rate generator with a 16-bit timer and selectable prescaler is included, which can generate a wide
range of baud rates (details in Section “23.1. Baud Rate Generator” on page 235). A received data FIFO
allows UART 0 to receive up to thre e data bytes before data is lost and an overflow occurs.
UART0 has six associated SFRs. Three are used for the Baud Rate Generator (SBCON0, SBRLH0, and
SBRLL0), two are used for data formatting, control, and status functions (SCON0, SMOD0), and one is
used to send an d receive data (SBUF0). The single SBUF0 lo cation provides acces s to both the transmit
holding register and the receive FIFO. Writes to SBUF0 always access the Transmit register. Reads of
SBUF0 always access the first byte of the Receive FIFO; it is not possible to read data from the
Transmit Holding Register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardwa re when the CPU vectors to th e interr upt service routine. They must be cleared manually
by software, allowing software to dete rmine the cause of the UAR T0 interrupt ( transmit complete or rece ive
complete). If additional bytes are available in the Receive FIFO, th e RI0 bit cannot be cleared by software.
Figure 23.1. UART0 Block Diagram
23.1. Baud Rate Generator
The UART0 baud rate is generated by a dedicated 16-bit timer which runs from the controller ’s core clock
(SYSCLK) and ha s prescaler options of 1, 4, 12 , or 4 8. The timer a nd pr escaler option s combined allow for
a wide selection of baud rates over many clock frequencies.
The baud rate generator is configured using three registers: SBCON0, SBRLH0, and SBRLL0. The
UART0 Baud Rate Generator Control Register (SBCON0, SFR Definition 23.4) enables or disables the
baud rate generator and selects the prescaler value for the timer. The baud rate generator must be
enabled for UART0 to function. Registers SBRLH0 and SBRLL0 contain a 16-bit reload value for the dedi-
cated 16-bit timer. The internal timer counts up from the reload value on every clock tick. On timer over-
flows (0xFFFF to 0x0000), the timer is reloaded. The baud rate for UART0 is defined in Equation 23.1,
where “BRG Clock” is the baud rate generator’s selected clock source. For reliable UART operation, it is
recommended that the UART baud rate is not configured for baud rates faster than SYSCLK/16.
SBUF0
TX Holding
Register
RX FIFO
(3 Deep)
TX
Logic
RX
Logic
Write to SBUF0
Read of SBUF0
TX0
RX0
SMOD0
MCE0
S0PT1
S0PT0
PE0
S0DL1
S0DL0
XBE0
SBL0
Data Forma tting
SCON0
OVR0
PERR0
THRE0
REN0
TBX0
RBX0
TI0
RI0
Contro l / Status
UART0
Interrupt
Timer (16-bit) Pre-Scaler
(1, 4, 12 , 48)
SYSCLK
SBRLH0 SBRLL0 Overflow
SBCON0
SB0RUN
SB0PS1
SB0PS0
EN
Baud Rate Generator
C8051F55x/56x/57x
236 Rev. 1.2
Equation 23.1. UART0 Baud Rate
A quick reference for typical baud rates and clock frequencies is given in Table 23.1.
Table 23.1. Baud Rate Generator Settings for Standard Baud Rates
Target Baud
Rate (bps) Actual Baud
Rate (bps) Baud Rate
Error Oscillator
Divide
Factor
SB0PS[1:0]
(Prescaler Bits) Reload Value in
SBRLH0:SBRLL0
SYSCLK = 48
230400 230769 0.16% 208 11 0xFF98
115200 115385 0.16% 416 11 0xFF30
57600 57554 0.08% 834 11 0xFE5F
28800 28812 0.04% 1666 11 0xFCBF
14400 14397 0.02% 3334 11 0xF97D
9600 9600 0.00% 5000 11 0xF63C
2400 2400 0.00% 20000 11 0xD8F0
1200 1200 0.00% 40000 11 0xB1E0
SYSCLK = 24
230400 230769 0.16% 104 11 0xFFCC
115200 115385 0.16% 208 11 0xFF98
57600 57692 0.16% 416 11 0xFF30
28800 28777 0.08% 834 11 0xFE5F
14400 14406 0.04% 1666 11 0xFCBF
9600 9600 0.00% 2500 11 0xFB1E
2400 2400 0.00% 10000 11 0xEC78
1200 1200 0.00% 20000 11 0xD8F0
SYSCLK = 12
230400 230769 0.16% 52 11 0xFFE6
115200 115385 0.16% 104 11 0xFFCC
57600 57692 0.16% 208 11 0xFF98
28800 28846 0.16% 416 11 0xFF30
14400 14388 0.08% 834 11 0xFE5F
9600 9600 0.00% 1250 11 0xFD8F
2400 2400 0.00% 5000 11 0xF63C
1200 1200 0.00% 10000 11 0xEC78
Baud Rate SYSCLK
65536 (SBRLH0:SBRLL0)
–()
------------------------------------------------------------------------------ x1
2
---x1
Prescaler
-------------------------=
C8051F55x/56x/57x
Rev. 1.2 237
23.2. Data Format
UART0 has a number of available options for data formatting. Data transfers begin with a start bit (logic
low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two
stop bits (logic high). The data length is variable between 5 and 8 bits. A parity bit can be appended to the
data, and automatically generated and detected by hardware for even, odd, mark, or space parity. The stop
bit length is selectable between 1 and 2 bit times, and a multi-processor communication mode is available
for implementing networked UART buses. All of the data formatting options can be configured using the
SMOD0 register, shown in SFR Definition 23.2. Figure 23.2 shows the timing for a UART0 transaction
without parity or an extra bit enabled. Figure 23.3 shows the timing for a UART0 transaction with parity
enabled (PE0 = 1). Figure 23.4 is an example of a UART0 transaction when the extra bit is enabled
(XBE0 = 1). Note that the extra bit feature is not available when parity is enabled, and the second stop bit
is only an option for data lengths of 6, 7, or 8 bits.
Figure 23.2. UART0 Timing Without Parity or Extra Bit
Figure 23.3. UART0 Timing With Parity
Figure 23.4. UART0 Timing With Extra Bit
D1
D0DN-2 DN-1
START
BIT
MARK STOP
BIT 1
BIT TIMES
SPACE
N bits; N = 5, 6, 7, or 8
STOP
BIT 2
Optional
(6,7,8 bit
Data)
D1
D0DN-2 DN-1 PARITY
START
BIT
MARK STOP
BIT 1
BIT TIMES
SPACE
N bits; N = 5, 6, 7, or 8
STOP
BIT 2
Optional
(6,7,8 bit
Data)
D1
D0DN-2 DN-1 EXTRA
START
BIT
MARK STOP
BIT 1
BIT TIMES
SPACE
N bits; N = 5, 6, 7, or 8
STOP
BIT 2
Optional
(6,7,8 bit
Data)
C8051F55x/56x/57x
238 Rev. 1.2
23.3. Configuration and Operation
UART0 provides standard asynchronous, full duplex communication. It can operate in a point-to-point
serial communications applica tion, or as a node o n a multi-processor serial inte rface. To operate in a point-
to-point application, where there are only two devices on the seri al bus, the MCE0 bit in SMOD 0 should be
cleared to 0. For operation as part of a multi-processor communications bus, the MCE0 and XBE0 bits
should both be set to 1. In both types of applications, data is transmitted from the microcontroller on the
TX0 pin, and received on the RX0 pin. The TX0 and RX0 pins are configured using the crossbar and the
Port I/O registers, as detailed in Section “19. Port Input/Output” on page 169.
In typical UART communications, The transmit (TX) output of one device is connected to the receive (RX)
input of the other device, either directly or through a bus transce ive r, as shown in Figur e 23.5 .
Figure 23.5. Typical UART Interconnect Diagram
23.3.1. Data Transmission
Data transmission is doub le-buffered and begins when software writes a data byte to the SBU F0 register.
Writing to SBUF0 places data in the Transmit Holding Register, and the Transmit Holding Register Empty
flag (THRE0) will be cleared to 0. If the UART’s shift register is empty (i.e., no transmission in progress),
the data will be placed in the Transmit Holding Register until the current transmission is complete. The TI0
Transmit Interrupt Flag (SCON0.1) will be set at the end of any transmission (the beginning of the stop-bit
time). If enabled, an interrupt will occur when TI0 is set.
Note: THRE0 can have a momentary glitch high when the UART Transmit Holding Register is not empty.
The glitch will occur some time after SBUF0 was written with the previous byte and does not occur if
THRE0 is checked in the instruction(s) immedia tel y following the write to SBUF0. When firmware
writes SBUF0 and SBUF0 is not empty, TX0 will be stuck low until the next device reset. Firmware
should use or poll on TI0 rather than THRE0 for asynchronous UART writes that may have a
random delay in between tran sactions.
If the extra bit function is enabled (XBE0 = 1) and the parity function is disabled (PE0 = ‘0’), the value of the
TBX0 (SCON0.3) bit will be sent in the extra bit position. When the parity function is enabled (PE0 = 1),
hardware will generate the parity bit according to the selected parity type (selected with S0PT[1:0]), and
append it to the data field. Note: whe n parity is enable d, the ex tra bi t fun ct ion is not av aila ble .
23.3.2. Data Reception
Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the
stop bit is received, the data byte will be stored in the receive FIFO if the following conditions are met: the
receive FIFO (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. In the event that the
receive FIFO is full, the incoming byte will be lost, and a Receive FIFO Overrun Error will be generated
(OVR0 in register SCON0 will be set to logic 1). If the stop bit(s) were logic 0, the incoming data will not be
stored in the receive FIFO. If the reception conditions are met, the data is stored in th e receive FIF O, and
OR
USB C8051Fxxx
CP2102
USB-to-UART
Bridge
TX
RX
C8051Fxxx
RX
TX
MCU RX
TX
PC
USB Port
C8051F55x/56x/57x
Rev. 1.2 239
the RI0 flag will be set. Note: when MCE0 = 1, RI0 will only be set if the extra bit was equal to 1. Data can
be read from the receive FIFO by reading the SBUF0 register. The SBUF0 register represents the oldest
byte in the FIFO. After SBUF0 is read, the next byte in the FIFO is immediately loaded into SBUF0, and
space is made available in the FIFO for another incoming byte. If enabled, an interrupt will occur when RI0
is set. RI0 can only be cleared to ‘0’ by software when there is no more information in the FIFO. The rec-
ommended procedure to empty the FIFO contents is as follows:
1. Clear RI0 to 0.
2. Read SBUF0.
3. Check RI0, and repeat at step 1 if RI0 is set to 1.
If the extra bit function is enabled (XBE0 = 1) and the pa rity function is disabled (PE0 = 0), the extra bit for
the oldest byte in the FIFO can be read from the RBX0 bit (SCON0.2). If the extra bit function is not
enabled, the value of the stop bit for the oldest FIFO byte will be presented in RBX0. When the parity func-
tion is enabled (PE0 = 1), hardware will check the received parity bit against the selected parity type
(selected with S0PT[1:0]) when receiving data. If a byte with p arity error is rece ived, the PERR0 flag will be
set to 1. This flag must be cleared by software. Note: when parity is enabled, the extra bit function is not
available.
Note: The UAR T Receive FIFO pointer can be corrupted if the UART receives a byte and firmware reads
a byte from the FIFO at the same time. When this occurs, firmware will lose the received byte and
the FIFO receive overrun flag (OVR0) will also be set to 1. Systems using the UART Receive FIFO
should ensure tha t th e FIFO isn’t accesse d by har dware and firmwar e at th e sa me ti me . In ot he r
words, firmware should ensure to read the FIFO before the next byte is received.
C8051F55x/56x/57x
240 Rev. 1.2
23.3.3. Multiprocessor Communications
UART0 supports multiproces sor communication between a master processor and one o r more slave pro-
cessors by special use of the extra data bit. When a master processor wants to transmit to one or more
slaves, it first sends an address byte to se lect the target(s). An address byte differs from a data byte in that
its extra bit is logic 1; in a data byte, the extra bit is always set to logic 0.
Setting the MCE0 bit (SMOD0.7) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the extra bit is logic 1 (RBX0 = 1) signifying an
address byte has been received. In the UART interrupt handler, software will compare the received
address with the slave's own assigned address. If the addresses match, the slave will clear its MCE0 bit to
enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their
MCE0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring
the data. Once the entire message is received, the addres sed slave resets its MCE0 bit to ignore all trans-
missions until it receives the next address byte.
Multiple addresses ca n be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram
Master
Device Slave
Device
TXRX RX TX
Slave
Device
RX TX
Slave
Device
RX TX
V+
C8051F55x/56x/57x
Rev. 1.2 241
SFR Definition 23.1. SCON0: Serial Port 0 Control
Bit76543210
Name OVR0 PERR0 THRE0 REN0 TBX0 RBX0 TI0 RI0
Type R/W R/W RR/W R/W R/W R/W R/W
Reset 00100000
C8051F55x/56x/57x
242 Rev. 1.2
SFR Address = 0x98; Bit-Addressable; SFR Page = 0x00
Bit Name Function
7OVR0 Receive FIFO Overrun Flag.
0: Receive FIFO Overrun has no t occurred
1: Receive FIFO Overrun has occurred; A received character has been discarded due
to a full FIFO.
6PERR0 Parity Error Flag.
When parity is enabled, this bit indicates that a parity error has occurred. It is set to 1
when the parity of the oldest byte in the FIFO does not match the selected Parity Type.
0: Parity error has not occurred
1: Parity error has occurred.
This bit must be cleared by software.
5THRE0 Transmit Holding Register Empty Flag.
THRE0 can have a moment ary glitch high when the UAR T T ransmit Holding Register is
not empty. The glitch will occur some time after SBUF0 was written with the previous
byte and does not occur if THRE0 is checked in the instruction(s) immedia tely following
the write to SBUF0. When firmware writes SBUF0 and SBUF0 is not empty , TX0 will be
stuck low until the next device reset. Firmware should use or poll on TI0 rather than
THRE0 for asynchronous UART writes that may have a random delay in between
transactions.
0: Transmit Holding Register not Empty—do not write to SBUF0.
1: Transmit Holding Register Empty—it is safe to write to SBUF0.
4REN0 Receive Enable.
This bit enables/disables the UART receiver. When disabled, bytes can still be read
from the receive FIFO.
0: UART1 reception disabled.
1: UART1 reception ena bled.
3TBX0 Extra Transmission Bit.
The logic level of this bit will be assigned to the extra transmission bit when XBE0 is set
to 1. This bit is not used when Parity is enabled.
2RBX0 Extra Receive Bit.
RBX0 is assigned the value of the extra bit when XBE1 is set to 1. If XBE1 is cleared to
0, RBX1 will be assigned the logic level of the first stop bit. This bit is not valid when
Parity is enabled.
1TI0 Transmit Interrupt Flag.
Set to a 1 by hardware after data has been transmitted, at the beginning of the ST OP
bit. When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to
the UART0 interrupt service routine. This bi t must be cleared manually by software.
0RI0 Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software. Note that RI0 will remain set to ‘1’ as long as there is
data still in the UART FIFO. After the last byte has been shifted from the FIFO to
SBUF0, RI0 can be cleared.
C8051F55x/56x/57x
Rev. 1.2 243
SFR Address = 0xA9; SFR Page = 0x00
SFR Definition 23.2. SMOD0: Serial Port 0 Control
Bit76543210
Name MCE0 S0PT[1:0] PE0 S0DL[1:0] XBE0 SBL0
Type R/W R/W RR/W R/W R/W R/W R/W
Reset 00001100
Bit Name Function
7MCE0 Multiprocessor Communication Enable.
0: RI0 will be activated if stop bit(s) are 1.
1: RI0 will be activated if stop bit(s) and extra bit are 1. Extra bit must be enabled using
XBE0.
6:5 S0PT[1:0] Parity Type Select Bits.
00: Odd Parity
01: Even Parity
10: Mark Parity
11: Space Parity.
4PE0 Parity Enable.
This bit enables hardware parity generation and checking. The parity type is selected
by bits S0PT[1:0] when parity is enabled.
0: Hardware parity is disabled.
1: Hardware parity is enabled.
3:2 S0DL[1:0] Data Length.
00: 5-bit data
01: 6-bit data
10: 7-bit data
11: 8-bit data
1XBE0 Extra Bit Enable.
When enabled, the value of TBX0 will be appended to the data field
0: Extra Bit is disabled.
1: Extra Bit is enabled.
0SBL0 Stop Bit Length.
0: Short—stop bit is active for one bit time
1: Long—stop bit is active for two bit times (dat a length = 6, 7, or 8 bits), or 1.5 bit times
(data length = 5 bits).
C8051F55x/56x/57x
244 Rev. 1.2
SFR Address = 0x99; SFR Page = 0x00
SFR Address = 0xAB; SFR Page = 0x0F
SFR Definition 23.3. SBUF0: Serial (UART0) Port Data Buffer
Bit76543210
Name SBUF0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register and a receive latch register .
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
SFR Definition 23.4. SBCON0: UART0 Baud Rate Generator Control
Bit76543210
Name Reserved SB0RUN Reserved Reserved Reserved Reserved SB0PS[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7Reserved Read = 0b; Must Write 0b;
6SB0RUN Baud Rate Generator Enable.
0: Baud Rate Generator disabled. UART0 will not function.
1: Baud Rate Generator enabled.
5:2 Reserved Read = 0000b; Must Write = 0000b;
1:0 SB0PS[1:0] Baud Rate Prescaler Select.
00: Prescaler = 12.
01: Prescaler = 4.
10: Prescaler = 48.
11: Prescaler = 1.
C8051F55x/56x/57x
Rev. 1.2 245
SFR Address = 0xAD; SFR Page = 0x0F
SFR Address = 0xAC; SFR Page = 0x0F
SFR Definition 23.5. SBRLH0: UART0 Baud Rate Generator Reload High Byte
Bit76543210
Name SBRLH0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SBRLH0[7:0] High Byte of Reload Value for UART0 Baud Rate Generator.
This value is loaded into the high byte of the UART0 baud rate generator when the
counter overflows from 0xFFFF to 0x0000.
SFR Definition 23.6. SBRLL0: UART0 Baud Rate Generator Reload Low Byte
Bit76543210
Name SBRLL0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 SBRLL0[7:0] Low Byte of Reload Value for UART0 Baud Rate Generator.
This value is loaded into the low byte of the UART0 baud rate generator when the
counter overflows from 0xFFFF to 0x0000.
C8051F55x/56x/57x
Rev. 1.2 246
24. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and support s mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) sig na l ca n be co nfigured as an in pu t
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be conf igured as a ch ip-select ou tput in master mode, or disable d for 3-wire ope ration. Addi tional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
Figure 24.1. SPI Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write
SPI0DAT
Receive Data Buffer
SPI0DAT
01234567
Shift Register
SPI CONTROL LOGIC
SPI0CKR
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPI0CFG SPI0CN
Pin Interface
Control
Pin
Control
Logic
C
R
O
S
S
B
A
R
Port I/O
Read
SPI0DAT
SPI IRQ
Tx Data
Rx Data
SCK
MOSI
MISO
NSS
Transmit Data Buffer
Clock Divide
Logic
SYSCLK
CKPHA
CKPOL
SLVSEL
NSSMD1
NSSMD0
SPIBSY
MSTEN
NSSIN
SRMT
RXBMT
SPIF
WCOL
MODF
RXOVRN
TXBMT
SPIEN
C8051F55x/56x/57x
247 Rev. 1.2
24.1. Signal Descriptions
The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.
24.1.1. Master Out, Slave In (MOSI)
The master-out, slave-in (MOSI) signal is an output from a master device and an input t o slav e device s. It
is used to serially trans fer data from the ma ster to th e slave. This signal is an output when SPI0 is operat-
ing as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit
first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire
mode.
24.1.2. Master In, Slave Out (MISO)
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device.
It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operat-
ing as a master and an output when SPI0 is operating as a slave. Data is transfer red most-significant bit
first. The MISO pin is placed in a high-impeda nce sta te when the SPI m odule is disa bled and wh en the SPI
operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is
always driven by the MSB of the shift register.
24.1.3. Serial Clock (SCK)
The serial cl ock (SCK) signal is an outp ut from the ma ster device and an input to slave devices. It is used
to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 gen-
erates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is
not selected (NSS = 1) in 4-wire slave mode.
24.1.4. Slave Select (NSS)
The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0
bits in the SPI0CN register. There are three possible modes that can be selected with these bits :
1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is
disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select
signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-
point communication between a maste r and one slave.
2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is
enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a
master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple
master devices can be used on the same SPI bus.
3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 oper ates in 4-wire mode, and NSS is enabled as an
output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration
should only be used when operating SPI0 as a master device.
See Figure 24.2, Figure 24.3, and Figure 24.4 for typical connection diagrams of the various operational
modes. Note that the setting of NSSMD bits affect s the pinou t of the dev ice. When in 3-wire ma ster or
3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will
be mapped to a pin on the device. See Section “19. Port Input/Output” on page 169 for general purpose
port I/O and crossbar information.
C8051F55x/56x/57x
Rev. 1.2 248
24.2. SPI0 Master Mode Operation
A SPI master device initiates all data tran sfer s o n a SPI bu s. SPI0 is p lac ed in m ast er m ode by se ttin g the
Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when
in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer
is moved to the shift registe r, and a data transfer begins. The SPI0 master immediately shifts out the data
serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic
1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag
is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device
simultaneously transfers the conten t s of its sh if t register to the SPI master on the MISO line in a full-dup lex
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three dif ferent mode s: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSS-
MD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is
used to disable th e master SPI0 when anothe r master is accessing the b us. When NSS is pulled low in this
mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a
Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumst ances. In multi-master systems, devices will
typically default to being sla ve devices while th ey are not a cting as the system ma ster device. In multi-ma s-
ter mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 24.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-m aster mod e is active wh en NSSMD1 (S PI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, an d is not mapped to an external por t pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 24.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using gene ral-p urpose I/O p ins. Figur e 24.4 shows a connection diagra m for a master device i n
4-wire master mode and two slave devices.
C8051F55x/56x/57x
249 Rev. 1.2
Figure 24.2. Multiple-Master Mode Connection Diagram
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
Master
Device 2
Master
Device 1
MOSI
MISO
SCK
MISO
MOSI
SCK
NSS
GPIO NSS
GPIO
Slave
Device
Master
Device
MOSI
MISO
SCK
MISO
MOSI
SCK
Slave
Device
Master
Device
MOSI
MISO
SCK
MISO
MOSI
SCK
NSS NSS
GPIO
Slave
Device
MOSI
MISO
SCK
NSS
C8051F55x/56x/57x
Rev. 1.2 250
24.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are
shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig-
nal. A bit coun ter in the SPI0 logic cou nts SCK edges. When 8 bits have been sh ifted through the shift reg-
ister, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the
receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the
master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-
buffe red, and are placed in the transmit bu f fer first. If the shif t registe r is empty, the contents of th e transmit
buffer will immediately be transferred into the shift register. When the shift register already contains data,
the SPI will load the shift register with the transmit buffer ’s contents after the last SCK edge of the next (or
current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire
slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0,
and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS sig-
nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 24.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not
used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of
uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the
bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter
that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
enabling SPI0 with the SPIEN bit. Figure 24.3 shows a connection diagram between a slave device in 3-
wire slave mod e and a ma ster device.
24.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to
logic 1:
All of the following bits must be cleared by software.
1. The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can
occur in all SPI0 modes.
2. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when
the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to
SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0
modes.
3. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for
multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN
bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
4. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when config ured as a slave, and a
transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new
byte is not transferred to the receive buffer, allowing the previously received dat a byte to be read. The
data byte which caused the overrun is lost.
C8051F55x/56x/57x
251 Rev. 1.2
24.5. Serial Clock Phase and Polarity
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave dev ices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationship s for master mode are shown in Figure 24.5. For slave mode, the clock and
data relationships are shown in Fi gure 24.6 and Figure 24.7. CKPHA must be set to 0 on both the master
and slave SPI when communicating between two of the following devices: C8051F04x, C8051F06x,
C8051F12x, C8051F31 x, C805 1F32x, and C8051F33x.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 24.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfe r rate (bit s/sec) is one-half the system clock frequency or 12.5 MHz,
whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for
full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-
wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master
issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)
must be less than 1/10 the system clock frequency. In the special case where the master only wants to
transmit data to the slave and doe s not n eed to receive data from the slave (i.e. half-duplex operation), the
SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.
This is provided that the master issues SCK, NSS, and the seri al inpu t d at a synchr onously with the slave’s
system clock.
Figure 24.5. Master Mode Data/Clock Timing
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO/MOSI
NSS (Must Remain High
in Multi-Master Mode)
C8051F55x/56x/57x
Rev. 1.2 252
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0)
Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1)
24.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO
NSS (4-Wire Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MISO
NSS (4-Wir e Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0MOSI
C8051F55x/56x/57x
253 Rev. 1.2
SFR Address = 0xA1; SFR Page = 0x00
SFR Definition 24.1. SPI0CFG: SPI0 Configuration
Bit 7 6 5 4 3 2 1 0
Name SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT
Type RR/W R/W R/W R R R R
Reset 0 0 0 0 0 1 1 1
Bit Name Function
7SPIBSY SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6MSTEN Master Mode Enable.
0: Disable mast er mo de . Op er ate in slave mode.
1: Enable master mode. Operate as a master.
5CKPHA SPI0 Clock Phase.
0: Data centered on first edge of SCK period.*
1: Data centered on second edge of SCK period.*
4CKPOL SPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3SLVSEL Slave Selected Flag.
This bit is set to logic 1 whenever th e NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
2NSSIN NSS Instantaneous Pin Input.
This bit mimics the instantane ous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
1SRMT Shif t Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferre d to
the shift re gister from the transmit buf fer or by a transition on SCK. SRMT = 1 when
in Master Mode.
0RXBMT Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 24.1 for timing parameters.
C8051F55x/56x/57x
Rev. 1.2 254
SFR Address = 0xF8; Bit-Addressable; SFR Page = 0x00
SFR Definition 24.2. SPI0CN: SPI0 Control
Bit 7 6 5 4 3 2 1 0
Name SPIF WCOL MODF RXOVRN NSSMD[1:0] TXBMT SPIEN
Type R/W R/W R/W R/W R/W RR/W
Reset 0 0 0 0 0 1 1 0
Bit Name Function
7SPIF SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are
enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service rou-
tine. This bit is not automatically cleared by hardware. It must be cleare d by soft-
ware.
6WCOL Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a
write to the SPI0 dat a register was attempted while a data transfe r was in progress.
It must be cleared by software.
5MODF Mode Fault Flag.
This bit is set to logic 1 by ha rdware (and generates a SPI0 interrupt) when a mas -
ter mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01).
This bit is not automatically cleared by hardware. It must be cleared by software.
4RXOVRN Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the
receive buffer still holds unread data from a previous transfer and the last bit of the
current transfer is shifted into the SPI0 shift register. This bit is not automatically
cleared by hardware. It must be cleared by software.
3:2 NSSMD[1:0] Slave Select Mode.
Selects be tween the following NSS operation modes:
(See Section 24.2 and Section 24.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
1TXBMT Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
0SPIEN SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
C8051F55x/56x/57x
255 Rev. 1.2
SFR Address = 0xA2; SFR Page = 0x00
SFR Address = 0xA3; SFR Page = 0x00
SFR Definition 24.3. SPI0CKR: SPI0 Clock Rate
Bit 7 6 5 4 3 2 1 0
Name SCR[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 SCR[7:0] SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
SFR Definition 24.4. SPI0DAT: SPI0 Data
Bit 7 6 5 4 3 2 1 0
Name SPI0DAT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 SPI0DAT[7:0] SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
fSCK SYSCLK
2xSPI0CKR[7:0] 1+()
----------------------------------------------------------------=
fSCK 2000000
2x41+()
------------------------------=
fSCK 200 kHz=
C8051F55x/56x/57x
Rev. 1.2 256
Figure 24.8. SPI Master Timing (CKPHA = 0)
Figure 24.9. SPI Master Timing (CKPHA = 1)
SCK*
T
MCKH
T
MCKL
MOSI
T
MIS
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
MIH
SCK*
T
MCKH
T
MCKL
MISO
T
MIH
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
MIS
C8051F55x/56x/57x
257 Rev. 1.2
Figure 24.10. SPI Slave Timing (CKPHA = 0)
Figure 24.11. SPI Slave Timing (CKPHA = 1)
SCK*
T
SE
NSS
T
CKH
T
CKL
MOSI
T
SIS
T
SIH
MISO
T
SD
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SEZ
T
SDZ
SCK*
T
SE
NSS
T
CKH
T
CKL
MOSI
T
SIS
T
SIH
MISO
T
SD
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SLH
T
SEZ
T
SDZ
C8051F55x/56x/57x
Rev. 1.2 258
Table 24.1. SPI Slave Timing Parameters
Parameter Description Min Max Units
Master Mode Timing* (See Figure 24.8 and Figure 24.9)
TMCKH SCK High Time 1 x TSYSCLK —ns
TMCKL SCK Low Time 1 x TSYSCLK —ns
TMIS MISO Valid to SCK Shift Edge 1 x TSYSCLK + 20 —ns
TMIH SCK Shift Edge to MISO Change 0 — ns
Slave Mode Timing* (See Figure 24.10 and Figure 24.11)
TSE NSS Falling to First SCK Edge 2 x TSYSCLK —ns
TSD Last SCK Edge to NSS Rising 2 x TSYSCLK —ns
TSEZ NSS Falling to MISO Valid — 4 x TSYSCLK ns
TSDZ NSS Rising to MISO High-Z — 4 x TSYSCLK ns
TCKH SCK High Time 5 x TSYSCLK —ns
TCKL SCK Low Time 5 x TSYSCLK —ns
TSIS MOSI Valid to SCK Sample Edge 2 x TSYSCLK —ns
TSIH SCK Sample Edge to MOSI Change 2 x TSYSCLK —ns
TSOH SCK Shift Edge to MISO Change — 4 x TSYSCLK ns
TSLH Last SCK Edge to MISO Change
(CKPHA = 1 ONLY) 6 x TSYSCLK 8 x TSYSCLK ns
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
C8051F55x/56x/57x
Rev. 1.2 259
25. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload.
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 25.1 for pre-scaled clock selection).Timer 0/1
may then be configured to use this pre-scaled clock signal or the system clock.
Tim er 2 an d Timer 3 may be clocked by the sys tem clock, the system cloc k divided by 12, or the external
oscillator clock source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incr emented on each hi gh-to-low transition at the selected input pin (T0 o r T1). Event s with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
Timer 0 and Timer 1 Modes Timer 2 Modes Timer 3 Modes
13-bit counter/ tim er 16-bit timer with auto-reload 16-bit timer with auto-reload
16-bit counter/ tim er
8-bit counter/timer with
auto-reload Two 8-bit time rs with auto-reload Two 8-bit timers with auto-reload
Two 8-bit counte r/timers (Timer 0
only)
C8051F55x/56x/57x
260 Rev. 1.2
SFR Address = 0x8E; SFR Page = All Pages
SFR Definition 25.1. CKCON: Clock Control
Bit76543210
Name T3MH T3ML T2MH T2ML T1M T0M SCA[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7T3MH Timer 3 High Byte Clock Select.
Selects the clock supplied to the Timer 3 high by te (split 8-bit timer mode on ly) .
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
6T3ML Timer 3 Low Byte Clock Select.
Selects the clock supplied to T imer 3. Selects the clock supplied to the lower 8-bit timer
in split 8-bit timer mode.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
5T2MH Timer 2 High Byte Clock Select.
Selects the clock supplied to the Timer 2 high by te (split 8-bit timer mode on ly) .
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
4T2ML Timer 2 Low Byte Clock Select.
Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,
this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
3T1 Timer 1 Clock Select.
Selects the clock sour ce supplied to Timer 1. Ignored when C/T1 is set to 1.
0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].
1: Timer 1 uses the system clock.
2T0 Timer 0 Clock Select.
Selects the clock sour ce supplied to Timer 0. Ignored when C/T0 is set to 1.
0: Counter/Timer 0 uses the clock defined by the prescale bi ts SCA[1:0].
1: Counter/Timer 0 uses the system clock.
1:0 SCA[1:0] Timer 0/1 Prescale Bit s.
These bits control the Timer 0/1 Clock Prescaler:
00: System clock divided by 12
01: System clock divided by 4
10: System clock divided by 48
11: External clock divided by 8 (synchronized with the system clock)
C8051F55x/56x/57x
Rev. 1.2 261
25.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1)
and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and
Time r 1 as well as indica te status. Timer 0 interrupts can be enabled by se tting the ET0 bit in the IE regis-
ter (Section “13.2. Interrupt Register Descriptions” on page 115); Timer 1 interrupts can be enabled by set-
ting the ET1 bit in the IE register (Section “13.2. Interrupt Register Descriptions” on page 115). Both
counter/timers operate in on e of four primary modes selected by setting the Mode Select bits T1M1–T0M0
in the Counter/Timer Mode register (TMOD). Each timer can be configured independently. Each operating
mode is described below.
25.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration
and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same
manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4–TL0.0. The three upper bits of TL0 (TL0.7–TL0.5) are indeterminate and should be masked out or
ignored when reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to
0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are
enabled.
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
“19.3. Priority Crossbar Decoder” on page 172 for information on selecting and configuring external I/O
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the so urce sele cted by the Clock
Scale bits in CKCON (see SFR Definition 25.1).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 13.7). Setting GATE0 to 1
allows the timer to be controlled by the external input signal INT0 (see Section “13.2. Interrupt Register
Descriptions” on page 115), facilitating pulse width measurements.
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit reg ister for Timer 1 in the same manner as described ab ove for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 13.7).
TR0 GATE0 INT0 Counter/Timer
0 X X Disabled
1 0 X Enabled
1 1 0 Disabled
1 1 1 Enabled
Note: X = Don't Care
C8051F55x/56x/57x
262 Rev. 1.2
Figure 25.1. T0 Mode 0 Block Diagram
25.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures T ime r 0 and T imer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all
ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If
Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is
not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal INT0
is active as defined by bit IN0PL in register IT01CF (see Section “13.3. External Interrupts INT0 and INT1”
on page 122 for details on the external input signals INT0 and INT1).
TCLK TL0
(5 b its) TH0
(8 bits )
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TR0
0
1
0
1
SYSCLK
Pre-scaled Clock
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
GATE0
/INT0
T0
Crossbar
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
IN0PL XOR
C8051F55x/56x/57x
Rev. 1.2 263
Figure 25.2. T0 Mode 2 Block Diagram
25.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The
counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0,
GATE0 and TF0. TL0 can use either th e system clock or an external input signal as its timebase. The TH0
register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled
using the Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls
the Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However,
the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC
conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode set-
tings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1,
configure it for Mode 3.
TCLK
TMOD
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
TL0
(8 b its)
Reload
TH0
(8 b its)
0
1
0
1
SYSCLK
Pre-scaled Clock
IT01CF
I
N
1
S
L
1
I
N
1
S
L
0
I
N
1
S
L
2
I
N
1
P
L
I
N
0
P
L
I
N
0
S
L
2
I
N
0
S
L
1
I
N
0
S
L
0
TR0
GATE0
IN0PL XOR
/INT0
T0
Crossbar
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F55x/56x/57x
264 Rev. 1.2
Figure 25.3. T0 Mode 3 Block Diagram
TL0
(8 bits)
TMOD
0
1
TCON
TF0
TR0
TR1
TF1
IE1
IT1
IE0
IT0
Interrupt
Interrupt
0
1
SYSCLK
Pre-scaled Clock TR1 TH0
(8 bits)
T
1
M
1
T
1
M
0
C
/
T
1
G
A
T
E
1
G
A
T
E
0
C
/
T
0
T
0
M
1
T
0
M
0
TR0
GATE0
IN0PL
XOR
/INT0
T0
Crossbar
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F55x/56x/57x
Rev. 1.2 265
SFR Address = 0x88; Bit-Addressable; SFR Page = All Pages
SFR Definition 25.2. TCON: Timer Control
Bit76543210
Name TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7TF1 Timer 1 Overflow Flag.
Set to 1 by hardware whe n Timer 1 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
6TR1 Timer 1 Run Control.
Timer 1 is enabled by setting this bit to 1.
5TF0 Timer 0 Overflow Flag.
Set to 1 by hardware whe n Timer 0 overflows. This flag can be cleared by software
but is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
4TR0 Timer 0 Run Control.
Timer 0 is enabled by setting this bit to 1.
3IE1 External Interru p t 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by softwa re but is automatically cle ared when the CPU vectors to the
External Interrupt 1 service routine in edge-triggered mode.
2IT1 Interrupt 1 Type Select.
This bit selects whether the configured INT1 interrupt will be edge or level sensitive.
INT1 is configured active low or high by the IN1PL bit in the IT01CF register (see
SFR Definition 13.7).
0: INT1 is level triggered.
1: INT1 is edge triggered.
1IE0 External Interru p t 0.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It
can be cleared by softwa re but is automatically cle ared when the CPU vectors to the
External Interrupt 0 service routine in edge-triggered mode.
0IT0 Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive.
INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR
Definition 13.7).
0: INT0 is level triggered.
1: INT0 is edge triggered.
C8051F55x/56x/57x
266 Rev. 1.2
SFR Address = 0x89; SFR Page = All Pages
SFR Definition 25.3. TMOD: Timer Mode
Bit76543210
Name GATE1 C/T1 T1M[1:0] GATE0 C/T0 T0M[1:0]
Type R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7GATE1 Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by b it IN1PL in
register IT01CF (see SFR Definition 13.7).
6C/T1 Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
5:4 T1M[1:0] Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
3GATE0 Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by b it IN0PL in
register IT01CF (see SFR Definition 13.7).
2C/T0 Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
1:0 T0M[1:0] Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Two 8-bit Counte r/ Timers
C8051F55x/56x/57x
Rev. 1.2 267
SFR Address = 0x8A; SFR Page = All Pages
SFR Address = 0x8B; SFR Page = All Pages
SFR Definition 25.4. TL0: Timer 0 Low Byte
Bit76543210
Name TL0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL0[7:0] Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 25.5. TL1: Timer 1 Low Byte
Bit76543210
Name TL1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TL1[7:0] Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
C8051F55x/56x/57x
268 Rev. 1.2
SFR Address = 0x8C; SFR Page = All Pages
SFR Address = 0x8D; SFR Page = All Pages
SFR Definition 25.6. TH0: Timer 0 High Byte
Bit76543210
Name TH0[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH0[7:0] Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 25.7. TH1: Timer 1 High Byte
Bit76543210
Name TH1[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TH1[7:0] Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
C8051F55x/56x/57x
Rev. 1.2 269
25.2. Timer 2
T imer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-r eload mode or (split) 8-bit auto-reload mo de. The T2SPLIT bit (TMR2CN.3) defines
the T imer 2 operation mode.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external preci-
sion oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
25.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 25.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow fro m 0xFF to 0x00.
Figure 25.4. Timer 2 16-Bit Mode Block Diagram
25.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figur e 25.5. TMR2RLL holds the reloa d va lue for TMR2 L; TMR2RLH
holds the reload value fo r TMR2 H. The TR 2 bit in TMR2CN handl es the run cont rol for TMR2H. T MR2 L is
always runni ng when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
External Clock / 8
SYSCLK / 12
SYSCLK
TMR2L TMR2H
TMR2RLL TMR2RLH Reload
TCLK
0
1
TR2
TMR2CN
T2SPLIT
TF2CEN
TF2L
TF2H
T2XCLK
TR2
0
1
T2XCLK
Interrupt
TF2LEN
To ADC,
SMBus
To SMBus
TL2
Overflow
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F55x/56x/57x
270 Rev. 1.2
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflo ws. If Timer 2 interrupts are enab led and TF2LEN (TMR2CN.5) is set, an interr upt is g ener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
Figure 25.5. Timer 2 8-Bit Mode Block Diagram
25.2.3. External Oscillator Capture Mode
Capture Mode allows the external oscillator to be measured against the system clock. Timer 2 can be
clocked from the system clock, or the system clock divided by 12, depending on the T2ML (CKCON.4),
and T2XCLK bits. When a capture event is generated, the contents of Timer 2 (TMR2H:TMR2L) are
loaded into the Timer 2 reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set. A capture event
is generated by the falling edge of the clock source being measured, which is the external oscillator / 8. By
recording the difference between two successive timer capture values, the external oscillator frequency
can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster than the
capture clock to achieve an accurate reading. Timer 2 should be in 16-bit auto-reload mode when using
Capture Mod e.
For example, if T2ML = 1b and TF2CEN = 1b, Timer 2 will clock every SYSCLK and capture every external
clock divided by 8. If the SYSCLK is 24 MHz and the difference between two successive captures is 5984,
then the external clock frequency is as follows:
24 MHz/(5984/8) = 0.032086 MHz or 32.086 kHz
T2MH T2XCLK TMR2H Clock Source T2ML T2XCLK TMR2L Clock Source
0 0 SYSCLK/12 0 0 SYSCLK/12
0 1 External Clock/8 0 1 External Clock/8
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1TR2
External Clock / 8
SYSCLK / 12 0
1
T2XCLK
1
0
TMR2H
TMR2RLH Reload
Reload
TCLK TMR2L
TMR2RLL
Interrupt
TMR2CN
T2SPLIT
TF2CEN
TF2LEN
TF2L
TF2H
T2XCLK
TR2
To ADC,
SMBus
To SMBus
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F55x/56x/57x
Rev. 1.2 271
This mode allows software to determine the external oscillator frequency when an RC network or cap acitor
is used to generate the clock source.
Figure 25.6. Timer 2 External Oscillator Capture Mode Block Diagram
External Clo c k / 8
SYSCLK / 12
SYSCLK
0
1
0
1
T2XCLK
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR2L TMR2H
TCLK
TR2
TMR2RLL TMR2RLH
Capture
External Clock / 8
TMR2CN
T2SPLIT
TF2CEN
TF2L
TF2H
T2XCLK
TR2
TF2LEN
TF2CEN Interrupt
C8051F55x/56x/57x
272 Rev. 1.2
SFR Address = 0xC8; Bit-Addressable; SFR Page = 0x00
SFR Definition 25.8. TMR2CN: Timer 2 Control
Bit76543210
Name TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK
Type R/W R/W R/W R/W R/W R/W RR/W
Reset 00000000
Bit Name Function
7TF2H Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byt e ove r flows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2
interrupt service routine. This bit is not automatically cleared by hardware.
6TF2L Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared b y hardware.
5TF2LEN Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
4TF2CEN Timer 2 Capture Mode Enable.
0: Timer 2 Capture Mode is disabled.
1: Timer 2 Capture Mode is enabled.
3T2SPLIT Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
0: Timer 2 operates in 16-bit auto-reload mode.
1: Timer 2 operates as two 8-bit auto-reload timers.
2TR2 Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode .
1Unused Read = 0b; Write = Don’t Care
0T2XCLK Timer 2 External Clock Select.
This bit select s the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this
bit selects the external oscillator clock source for both timer bytes. However, the
Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be used to
select between the external clock and the system clock for either timer.
0: Timer 2 clock is the system clock divided by 12.
1: Timer 2 clock is the external clock divided by 8 (synchronized with SYSCLK).
C8051F55x/56x/57x
Rev. 1.2 273
SFR Address = 0xCA; SFR Page = 0x00
SFR Address = 0xCB; SFR Page = 0x00
SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte
Bit76543210
Name TMR2RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 25.10. TMR2RLH: Timer 2 Reload Register High Byte
Bit76543210
Name TMR2RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
C8051F55x/56x/57x
274 Rev. 1.2
SFR Address = 0xCC; SFR Page = 0x00
SFR Address = 0xCD; SFR Page = 0x00
SFR Definition 25.11. TMR2L: Timer 2 Low Byte
Bit76543210
Name TMR2L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2L[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-
bit mode, TMR2L contains the 8-bit low byte timer value.
SFR Definition 25.12. TMR2H Timer 2 High Byte
Bit76543210
Name TMR2H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR2H[7:0] Timer 2 High Byte.
In 16-bit mode, the TMR2H register con tains the hig h by te of the 16-bit Timer 2. In 8-
bit mode, TMR2H contains the 8-bit high byte timer value.
C8051F55x/56x/57x
Rev. 1.2 275
25.3. Timer 3
T imer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-r eload mode or (split) 8-bit auto-reload mo de. The T3SPLIT bit (TMR3CN.3) defines
the T imer 3 operation mode.
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 3 (and/or the PCA) is clocked by an external preci-
sion oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
25.3.1. 16-Bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3
reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 25.7,
and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If T imer 3 interrupts are ena bled, an interru pt
will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled and the TF3LEN
bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L) overflow from
0xFF to 0x00 .
Figure 25.7. Timer 3 16-Bit Mode Block Diagram
25.3.2. 8-Bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figur e 25.8. TMR3RLL holds the reloa d va lue for TMR3 L; TMR3RLH
holds the reload value fo r TMR3 H. The TR 3 bit in TMR3CN handl es the run cont rol for TMR3H. T MR3 L is
always runni ng when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or
the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:
External Clock / 8
SYSCLK / 12
SYSCLK
TMR3L TMR3H
TMR3RLL TMR3RLH Reload
TCLK
0
1
TR3
TMR3CN
T3SPLIT
TF3CEN
TF3L
TF3H
T3XCLK
TR3
0
1
T3XCLK
Interrupt
TF3LEN
To ADC,
SMBus
To SMBus
TL3
Overflow
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F55x/56x/57x
276 Rev. 1.2
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x0 0. When Timer 3 interrupts are enabled, an in terrupt is g enerated e ach time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
Figure 25.8. Timer 3 8-Bit Mode Block Diagram
25.3.3. External Oscillator Capture Mode
Capture Mode allows the external oscillator to be measured against the system clock. Timer 3 can be
clocked from the system clock, or the system clock divided by 12, depending on the T3ML (CKCON.6),
and T3XCLK bits. When a capture event is generated, the contents of Timer 3 (TMR3H:TMR3L) are
loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL) and the TF3H flag is set. A capture event
is generated by the falling edge of the clock source being measured, which is the external oscillator/8. By
recording the difference between two successive timer capture values, the external oscillator frequency
can be determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the
capture clock to achieve an accurate reading. Timer 3 should be in 16-bit auto-reload mode when using
Capture Mod e.
If the SYSCLK is 24 MHz and the difference between two successive captures is 5861, then the external
clock frequency is as follows:
24 MHz/(5861/8) = 0.032754 MHz or 32.754 kHz
This mode allows software to determine the external oscillator frequency when an RC network or cap acitor
is used to generate the clock source.
T3MH T3XCLK TMR3H Clock Source T3ML T3XCLK TMR3L Clock Source
0 0 SYSCLK/12 0 0 SYSCLK/12
0 1 External Clock/8 0 1 External Clock/8
1 X SYSCLK 1 X SYSCLK
SYSCLK
TCLK
0
1TR3
External Clock / 8
SYSCLK / 12 0
1
T3XCLK
1
0
TMR3H
TMR3RLH Reload
Reload
TCLK TMR3L
TMR3RLL
Interrupt
TMR3CN
T3SPLIT
TF3CEN
TF3LEN
TF3L
TF3H
T3XCLK
TR3
To ADC,
SMBus
To SMBus
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
C8051F55x/56x/57x
Rev. 1.2 277
Figure 25.9. Timer 3 External Oscillator Capture Mode Block Diagram
External Clo c k / 8
SYSCLK / 12
SYSCLK
0
1
0
1
T3XCLK
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M
TMR3L TMR3H
TCLK
TR3
TMR3RLL TMR3RLH
Capture
External Clock / 8
TMR3CN
T3SPLIT
TF3CEN
TF3L
TF3H
T3XCLK
TR3
TF3LEN
TF3CEN Interrupt
C8051F55x/56x/57x
278 Rev. 1.2
SFR Address = 0x91;SFR Page = 0x00
SFR Definition 25.13. TMR3CN: Timer 3 Control
Bit76543210
Name TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK
Type R/W R/W R/W R/W R/W R/W RR/W
Reset 00000000
Bit Name Function
7TF3H Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byt e ove r flows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000. When the
Timer 3 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3
interrupt service routine. This bit is not automatically cleared by hardware.
6TF3L Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. TF3L will
be set when the low byte overflows regardless of the Timer 3 mode. This bit is not
automatically cleared b y hardware.
5TF3LEN Timer 3 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 3 Low Byte interrupts. If Timer 3 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 3 overflows.
4TF3CEN Timer 3 Capture Mode Enable.
0: Timer 3 Capture Mode is disabled.
1: Timer 3 Capture Mode is enabled.
3T3SPLIT Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
2TR3 Timer 3 Run Control.
Timer 3 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR3H only; TMR3L is always enabled in split mode .
1Unused Read = 0b; Write = Don’t Care
0T3XCLK Timer 3 External Clock Select.
This bit select s the external clock source for Timer 3. If Timer 3 is in 8-bit mode, this
bit selects the external oscillator clock source for both timer bytes. However, the
Timer 3 Clock Select bits (T3MH and T3ML in register CKCON) may still be used to
select between the external clock and the system clock for either timer.
0: Timer 3 clock is the system clock divided by 12.
1: Timer 3 clock is the external clock divided by 8 (synchronized with SYSCLK).
C8051F55x/56x/57x
Rev. 1.2 279
SFR Address = 0x92; SFR Page = 0x00
SFR Address = 0x93; SFR Page = 0x00
SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte
Bit76543210
Name TMR3RLL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte
Bit76543210
Name TMR3RLH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
C8051F55x/56x/57x
280 Rev. 1.2
SFR Address = 0x94; SFR Page = 0x00
SFR Address = 0x95; SFR Page = 0x00
SFR Definition 25.16. TMR3L: Timer 3 Low Byte
Bit76543210
Name TMR3L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3L[7:0] Timer 3 Low Byte.
In 16-bit mode, the TMR3L register contains the low byte of the 16-bit Timer 3. In 8-
bit mode, TMR3L contains the 8-bit low byte timer value.
SFR Definition 25.17. TMR3H Timer 3 High Byte
Bit76543210
Name TMR3H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 TMR3H[7:0] Timer 3 High Byte.
In 16-bit mode, the TMR3H register con tains the hig h by te of the 16-bit Timer 3. In 8-
bit mode, TMR3H contains the 8-bit high byte timer value.
C8051F55x/56x/57x
Rev. 1.2 281
26. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer
and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between six sources: system clock, system clock divide d by four,
system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflows, or an
external clock signal on the ECI input pin. Each capture/compare module may be configured to operate
independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Fre-
quency Output, 8 to 11-Bit PWM, or 16-Bit PWM (each mode is described in Section
“26.3. Capture/Compare Modules” on page 283). The external oscillator clock option is ideal for real-time
clock (RTC) functionality, allowing the PCA to be clocked by a precision external oscillator while the inter-
nal oscillator drives the system clock. The PCA is configured and controlled through the system controller's
Special Function Registers. The PCA block diagram is shown in Figure 26.1
Import ant Note: The PCA Module 5 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 26.4 fo r de tails.
Figure 26.1. PCA Block Diagram
Capture/Compare
Module 1
Capture/Compare
Module 0 Capture/Compare
Module 2
CEX1
ECI
Crossbar
CEX2
CEX0
Port I/O
16-Bit Counter/Timer
PCA
CLOCK
MUX
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 4
Capture/Compare
Module 3 Capture/Compare
Module 5 / WDT
CEX4
CEX5
CEX3
C8051F55x/56x/57x
282 Rev. 1.2
26.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register .
Reading the PCA0L Regist er first guaran tees an a ccurate r eading of the entire 16 -bit PCA0 cou nter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS[2:0] bits in the PCA0MD reg-
ister select the timebase for the counter/timer as shown in Table 26.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware. Clearing the CIDL bit in the PCA0MD register allows the PCA to continu e norma l oper ation while th e
CPU is in Idle mode.
Figure 26.2. PCA Counter/Timer Block Diagram
Table 26.1. PCA Timebase Input Options
CPS2 CPS1 CPS0 Timebase
000System clock divided by 12.
001System clock divided by 4.
010Ti me r 0 overflow.
011High-to-low transitions on ECI (max rate = system clock divided
by 4).
100System clock.
101External oscillator source divided by 8.*
1 1 x Reserved.
*Note: External oscillator source divided by 8 is synchronized with the system clock.
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
IDLE
0
1PCA0H PCA0L
Snapshot
Register
To SFR Bus
Overflow To PCA Interrupt System
CF
PCA0L
read
To PCA Modules
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
000
001
010
011
100
101
SYSCLK
External Clock/8
C
C
F
3
C
C
F
5
C
C
F
4
C8051F55x/56x/57x
Rev. 1.2 283
26.2. PCA0 Interrupt Sources
Figure 26.3 shows a diagram of the PCA interrupt tree. There are five independent event flags that can be
used to generate a PCA0 inter rupt. T hey are a s follows: the m ain PCA coun te r overflow flag ( CF), which is
set upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on
an overflow fr om the 8th, 9t h, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA
channel (CCF0, CCF1, CCF2, CCF3, CCF4, and CCF5) , which are set accor ding to the ope ration mod e of
that module. These event flags are always set when the trigger condition occurs. Each of these flags can
be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF
for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupt s must be globally en abled before any
individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by set-
ting the EA bit and the EPCA0 bit to logic 1.
Figure 26.3. PCA Interrupt Block Diagram
26.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Soft ware Timer, High Speed Output, Frequency Output, 8 to 11-Bit Pulse Width Modulator, or 16-
Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the
CIP-51 system controller. These registers are used to exchange data with a module and configure the
module's mode of operation. Table 26.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM
registers used to select the PCA capture/compare module’s operating mode. All modules set to use 8, 9,
10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
0
1
PCA Module 0
(CCF0)
PCA Module 1
(CCF1)
ECCF1
0
1
ECCF0
0
1
PCA Module 2
(CCF2)
ECCF2
PCA Counter/Timer 16-
bit Overflow 0
1
Interrupt
Priority
Decoder
EPCA0
0
1
EA
0
1
PCA0CPMn
(for n = 0 to 2)
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
PCA0PWM
A
R
S
E
L
C
O
V
F
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
PCA Counter/Timer 8, 9,
10 or 11-bit Ov er f low
0
1
Set 8, 9, 10, or 11 bit Operation
PCA Module 3
(CCF3)
PCA Module 4
(CCF4)
PCA Module 5
(CCF5)
C
C
F
3
C
C
F
5
C
C
F
4
ECCF3
ECCF4
ECCF5
0
1
0
1
0
1
C8051F55x/56x/57x
284 Rev. 1.2
26.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA
counter/timer and load it in to the corr esponding mo dule 's 16-bit captur e/comp ar e register (P CA0CPLn an d
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn re giste r ar e u sed to select th e type of tran si-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not autom atically cleared by h ardware wh en the CPU ve ctors to the interr upt ser-
vice routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the
state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or fall-
ing-edge caused the capture.
Table 26.2. PCA0CPM and PCA0PWM Bit Settings for
PCA Capture/Compare Modules
Operational Mode PCA0CPMn PCA0PWM
Bit Number 765432107654–2 1–0
Capture triggered by positive edge on CEXn X X 1 0 0 0 0 A 0 X B XXX XX
Capture triggered by negative edge on CEXn X X 0 1 0 0 0 A 0 X B XXX XX
Capture triggered by any tran sition on CEXn X X 1 1 0 0 0 A 0 X B XXX XX
Software Timer X C 0 0 1 0 0 A 0 X B XXX XX
High Speed Output X C 0 0 1 1 0 A 0 X B XXX XX
Frequency Output X C 0 0 0 1 1 A 0 X B XXX XX
8-Bit Pulse Width Modulator (7) 0 C 0 0 E 0 1 A 0 X B XXX 00
9-Bit Pulse Width Modulator (7) 0 C 0 0 E 0 1 A D X B XXX 01
10-Bit Pulse Width Modulator (7) 0 C 0 0 E 0 1 A D X B XXX 10
11-Bit Pulse Width Modulator (7) 0 C 0 0 E 0 1 A D X B XXX 11
16-Bit Pulse Width Modulator 1 C 0 0 E 0 1 A 0 X B XXX XX
Notes:
1. X = Don’t Care (no functional difference for individu al module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high spee d and frequency output mo des, the
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
5. D = Selects whether the Capture/Compare regist er (0) or the Auto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn .
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8, 9, 10 or 11-bi t PWM mode use the same cycle length sett ing.
C8051F55x/56x/57x
Rev. 1.2 285
Figure 26.4. PCA Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
26.3.2. Software Timer (Compare) Mode
In Sof twa re Timer mode, the PCA counte r/timer value is co mpared to the module's 16-bit ca pture/ co mpare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not autom atically cleared by h ardware wh en the CPU ve ctors to the interr upt ser-
vice routine, and must be cleared b y sof twa re. Settin g the ECOMn and MATn bits in the PCA0CPMn reg is-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
PCA0L
PCA0CPLn
PCA
Timebase
CEXn
CrossbarPort I/O
PCA0H
Capture
PCA0CPHn
0
1
0
1
(to CCFn)
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
x000xx
C
C
F
3
C
C
F
5
C
C
F
4
C8051F55x/56x/57x
286 Rev. 1.2
Figure 26.5. PCA Software Timer Mode Diagram
26.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically cleared by hard ware when the CPU ve ctors to the interr upt serv ice rout ine, and m ust be clear ed
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next
match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
00 00
0
1
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
C
C
F
0
C
C
F
2
C
C
F
1
C8051F55x/56x/57x
Rev. 1.2 287
Figure 26.6. PCA High-Speed Output Mode Diagram
26.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out-
put is toggled. The frequency of the square wave is then defined by Equation 26.1.
Equation 26.1. Square Wave Frequency Output
Where FPCA is the frequency of the clock selected by the CPS[2:0] bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the mat ched value in PCA0CP Ln.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn reg-
ister. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CC Fn
flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for
the channel are equal.
Match
16-bit Comparator
PCA0H
PCA0CPHn
Enable
PCA0L
PCA
Timebase
PCA0CPLn
0
1
00 0x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
CEXn Crossbar Port I/O
Toggle 0
1
TOGn
PCA0CN
C
FC
RC
C
F
0
C
C
F
2
C
C
F
1
PCA Interrupt
C
C
F
3
C
C
F
5
C
C
F
4
FCEXn FPCA
2PCA0CPHn×
-------------------------------------------
=
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
C8051F55x/56x/57x
288 Rev. 1.2
Figure 26.7. PCA Frequency Output Mode
26.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes
Each module can be u sed indepe nde ntly to gener ate a pulse width modulated (PWM) output on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer, and
the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit PWM
mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-bit
PWM modes. It is important to note that all channels con figured for 8/9/10/11-bit PWM mode will use
the same cycle leng th. It is not p ossible to configure on e channel for 8- bit PWM mode and anothe r for 11-
bit mode (for exam p l e) . Ho wev er, other PCA channels ca n b e co nfig u re d to P in Ca ptu r e, Hig h -Speed Out-
put, Softwar e Timer, Frequency Output, or 16-bit PWM mode independently.
26.3.5.1. 8-bit Pulse Width Modulator Mode
The duty cycle of th e PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap-
ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on th e CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 26.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stor ed in the modu le’s capture/compar e
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (r ising edge) occurs. The COVF flag in PCA0PWM can be used to dete ct the overflow
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 26.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 26.2. 8-Bit PWM Duty Cycle
Using Equation 26.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
8-bit
Comparator
PCA0L
Enable
PCA Timebase
match
PCA0CPHn8-bit AdderPCA0CPLn
Adder
Enable
CEXn Crossbar Port I/O
Toggle 0
1
TOGn
000 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
Duty Cycle 256 PCA0CPHn
–()
256
-------------------------------------------------------=
C8051F55x/56x/57x
Rev. 1.2 289
Figure 26.8. PCA 8-Bit PWM Mode Diagram
26.3.5.2. 9/10/11-bit Pulse Widt h Modulator Mode
The duty cycle of the PWM output signa l in 9/10/11-bit PWM mode should be varied by writing to an “Auto-
Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the output on CEXn is asserted high. When th e counter over flo w s fr om
the Nth bit, CEXn is asserted low (see Figure 26.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by the CLSEL bits in register PCA0PWM.
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn regis-
ter, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the
MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising edge)
occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur
every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit PWM
Mode is given in Equation 26.2, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 26.3. 9, 10, and 11-Bit PWM Duty Cycle
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
8-bit
Comparator
PCA0L
PCA0CPLn
PCA0CPHn
CEXn Crossbar Port I/O
Enable
Overflow
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
PCA0PWM
A
R
S
E
L
C
O
V
F
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
x000
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
COVF
Duty Cycle 2NPCA0CPn
–()
2N
------------------------------------------------=
C8051F55x/56x/57x
290 Rev. 1.2
Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
26.3.6. 16- Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other
(8/9/10/11-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the out-
put on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. To output a vary-
ing duty cycle, new value writes should be synchronized with PCA CCFn match interrupts. 16-Bit PWM
Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a vary-
ing duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the
capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set each
time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the
overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by Equation 26.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Equation 26.4. 16-Bit PWM Duty Cycle
Using Equation 26.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
N-bit Comparator
PCA0H:L
(Capture/Compare)
PCA0CPH:Ln
(right-justified)
(Auto-Reload)
PCA0CPH:Ln
(right-justified)
CEXn Crossbar Port I/O
Enable
Overflow of N
th
Bit
PCA Timebase
00x0 x
Q
Q
SET
CLR
S
R
match
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
0
PCA0PWM
A
R
S
E
L
C
O
V
F
C
L
S
E
L
0
C
L
S
E
L
1
E
C
O
V
x
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset R/W when
ARSEL = 1
R/W when
ARSEL = 0 Set “N” bits:
01 = 9 bits
10 = 10 bits
11 = 11 bits
Duty Cycle 65536 PCA0CPn
–()
65536
---------------------------------------------------------=
C8051F55x/56x/57x
Rev. 1.2 291
Figure 26.10. PCA 16-Bit PWM Mode
26.4. Watchdog Timer Mode
A programmable wa tchdog timer (WDT) function is avail able thr ough the PCA M odu le 5. The WDT is used
to generate a reset if the time between writes to th e WDT up da te r eg ister ( PCA0 C PH5) exceed a spe cified
limit. The WDT can be configured and en abled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 5 operates as a watchdog timer (WDT). The Mod-
ule 5 high byte is compared to the PCA counter high byte; the Module 5 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled. The WDT will generate a reset
shortly after code begins execution. To avoid this reset, the WDT should be explicitly disabled (and option-
ally re-configured and re-enabled if it is used in the system).
26.4.1. Watchdog Timer Operation
While the WDT is enabled:
PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS[2:0]) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 5 is forced into software timer mode.
Writes to the Module 5 mode register (PCA0CPM5) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control bit (CR) will read zero if the WDT is enabled but
user software has not enabled the PCA counter. If a match occurs between PCA0CPH5 and PCA0H while
the WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a
write of any value to PCA0 CPH5. Upon a PCA0CPH5 write, PCA0 H plus the offset held in PCA0CPL5 is
loaded into PCA0CPH5 (See Figure 26.11).
PCA0CPLnPCA0CPHn
Enable
PCA Timebase
00x0 x
PCA0CPMn
P
W
M
1
6
n
E
C
O
M
n
E
C
C
F
n
T
O
G
n
P
W
M
n
C
A
P
P
n
C
A
P
N
n
M
A
T
n
1
16-bit Compara tor CEXn Crossbar Port I/O
Overflow
Q
Q
SET
CLR
S
R
match
PCA0H PCA0L
ENB
ENB
0
1
Write to
PCA0CPLn
Write to
PCA0CPHn
Reset
C8051F55x/56x/57x
292 Rev. 1.2
Figure 26.11. PCA Module 2 with Watchdog Timer Enabled
Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16- bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 26.5, where PCA0L is the value of the PCA0L register
at the time of the update.
Equation 26.5. Watchdog Timer Offset in PCA Clocks
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and
PCA0H. Software may force a WDT reset by writing a 1 to the CCF5 flag (PCA0CN.5) while the WDT is
enabled.
26.4.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
Disable the WDT by writing a 0 to the WDTE bit.
Select the desired PCA clock sour ce (with the CPS[2:0] bits) .
Load PCA0CPL5 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended wh ile the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to 1.
Reset the WDT timer by writing to PCA0CPH5.
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 26.5, this results in a WDT
timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 26.3 lists some example tim-
eout intervals for typical system clocks.
PCA0H
Enable
PCA0L Overflow
Reset
PCA0CPL5 8-bit Adde r
PCA0CPH5
Adder
Enable
PCA0MD
C
I
D
L
W
D
T
E
E
C
F
C
P
S
1
C
P
S
0
W
D
L
C
K
C
P
S
2
Match
Write to
PCA0CPH2
8-bit
Comparator
Offset 256 xPCA0CPL5()256 PCA0L–()+=
C8051F55x/56x/57x
Rev. 1.2 293
Table 26.3. Watchdog Timer Timeout Intervals1
System Clock (Hz) PCA0CPL5 Timeout Interval (ms)
24,000,000 255 32.8
24,000,000 128 16.5
24,000,000 32 4.2
3,000,000 255 262.1
3,000,000 128 132.1
3,000,000 32 33.8
187,5002255 4194
187,5002128 2114
187,500232 541
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by
128.
C8051F55x/56x/57x
294 Rev. 1.2
26.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function reg i sters related to the operation of the PCA.
SFR Address = 0xD8; Bit-Addressable; SFR Page = 0x00
SFR Definition 26.1. PCA0CN: PCA Control
Bit76543210
Name CF CR CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CF PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overf low (CF) interrupt is enabled, setting this bit causes the
CPU to vector to th e PCA inte rrupt service r outin e. This b it is not au toma tically clear ed
by hardware and must be cleared by sof tware.
6CR PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5CCF5 PCA Module 5 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF5 interr upt
is enabled, setting th is bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not autom atically cleared by hardware an d must be cleared by sof tware.
4CCF4 PCA Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF4 interr upt
is enabled, setting th is bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not autom atically cleared by hardware an d must be cleared by sof tware.
3CCF3 PCA Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF3 interr upt
is enabled, setting th is bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not autom atically cleared by hardware an d must be cleared by sof tware.
2CCF2 PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interr upt
is enabled, setting th is bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not autom atically cleared by hardware an d must be cleared by sof tware.
1CCF1 PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interr upt
is enabled, setting th is bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not autom atically cleared by hardware an d must be cleared by sof tware.
0CCF0 PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interr upt
is enabled, setting th is bit causes the CPU to vector to the PCA interrupt service rou-
tine. This bit is not autom atically cleared by hardware an d must be cleared by sof tware.
C8051F55x/56x/57x
Rev. 1.2 295
SFR Address = 0xD9; SFR Page = 0x00
SFR Definition 26.2. PCA0MD: PCA Mode
Bit76543210
Name CIDL WDTE WDLCK CPS[2:0] ECF
Type R/W R/W R/W RR/W R/W R/W R/W
Reset 01000000
Bit Name Function
7CIDL PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
6WDTE Watchdog Timer Enable
If this bit is set, PCA Module 5 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 5 enabled as Watchdog Timer.
5WDLCK Watchdog Timer Lock
This bit locks/unlocks the Watchdog T im er Enable. When WDLCK is set, the W atch dog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4Unused Read = 0b, Write = Don't care.
3:1 CPS[2:0] PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 over flow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
11x: Reserved
0ECF PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Coun ter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
C8051F55x/56x/57x
296 Rev. 1.2
SFR Address = 0xD9; SFR Page = 0x0F
SFR Definition 26.3. PCA0PWM: PCA PWM Configuration
Bit76543210
Name ARSEL ECOV COVF CLSEL[1:0]
Type R/W R/W R/W RRR R/W
Reset 00000000
Bit Name Function
7ARSEL Auto-Reload Register Select.
This bit selects whether to read and write the normal PCA capture/compare registers
(PCA0CPn), or the Auto-Reload registers at the same SFR addresses. This function
is used to define the reload value for 9, 10, a nd 11-bit PWM modes. In all other
modes, the Aut o- Re l oa d re gis ters have no function .
0: Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn.
1: Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn.
6ECOV Cycle Overflow Interrupt Enable .
This bit sets the masking of the Cycle Overflow Flag (COVF) interrupt.
0: COVF will not generate PCA interrupts.
1: A PCA interrupt will be generated when COVF is set.
5COVF Cycle Overflow Flag.
This bit indicates an overflow of the 8th, 9th , 10th, or 11th bit of the main PCA counter
(PCA0). The specific bit used for th is flag depends on the setting of the Cycle Length
Select bits. The bit can be set by hardware or software, but must be cleared by soft-
ware.
0: No overflow has occurred since the last time this bit was cleared.
1: An overflow has occurred since the last time this bit was cleared.
4:2 Unused Read = 000b; Write = Don’t care.
1:0 CLSEL[1:0] Cycle Length Select.
When 16-bit PWM mode is not selected, these bits select the length of the PWM
cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM which
are not using 16-bit PWM mode. The se bit s are ignored for individual channels config-
ured to16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
C8051F55x/56x/57x
Rev. 1.2 297
SFR Addresses: PCA0CPM0 = 0xDA, PCA0CPM1 = 0xDB, PCA0CPM2 = 0xDC; PCA0CPM3 = 0xDD,
PCA0CPM4 = 0xDE, PCA0CPM5 = 0xDF, SFR Page (all registers) = 0x00
SFR Definition 26.4. PCA0CPMn: PCA Capture/Compare Mode
Bit76543210
Name PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7PWM16n 16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 11-bit PWM selected.
1: 16-bit PWM selected.
6ECOMn Comparator Function Enable.
This bit enables the comparator function for PCA module n when set to 1.
5CAPPn Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
4CAPNn Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
3MATn Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a m odule's capture/comp are register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2TOGn Toggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's captu re/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
ates in Frequency Output Mode.
1PWMn Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if
PWM16n is cleared; 16-bit mo de is used if PWM16n is set to logic 1. If the TOGn bit is
also set, the module operate s in Frequency Output Mode.
0ECCFn Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM5 register cannot be modified, and module 5 acts as the
watchdog timer . To change the contents of the PCA0CPM5 register or the function of module 5, the Watchdog
Timer must be disabled.
C8051F55x/56x/57x
298 Rev. 1.2
SFR Address = 0xF9; SFR Page = 0x00
SFR Address = 0xFA; SFR Page = 0x00
SFR Definition 26.5. PCA0L: PCA Counter/Timer Low Byte
Bit76543210
Name PCA0[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[7:0] PCA Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
Note: When the WDTE bit is set to 1, the PCA0L register cannot be modified by software. To change the contents of
the PCA0L register, the Watchdog Timer must first be disabled.
SFR Definition 26.6. PCA0H: PCA Counter/Timer High Byte
Bit76543210
Name PCA0[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0[15:8] PCA Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16 -bit PCA Counter/Timer.
Reads of this register will read the contents of a “snapshot” register , whose contents
are updated only when the contents of PCA0L are read (see Section 26.1).
Note: When the WDTE bit is set to 1, the PCA0H register cannot be modified by software. To change the contents of
the PCA0H register, the Watchdog Timer must first be disabled.
C8051F55x/56x/57x
Rev. 1.2 299
SFR Addresses: PCA0CPL0 = 0xFB, PCA0CPL1 = 0xE9, PCA0CPL2 = 0xEB, PCA0CPL3 = 0xED,
PCA0CPL4 = 0xFD, PCA0CPL5 = 0xCE; SFR Page (all registers) = 0x00
SFR Addresses: PCA0CPH0 = 0xFC, PCA0CPH1 = 0xEA, PCA0CPH2 = 0xEC, PCA0CPH3 = 0xEE,
PCA0CPH4 = 0xFE, PCA0CPH5 = 0xCF; SFR Page (all registers) = 0x00
SFR Definition 26.7. PCA0CPLn: PCA Capture Module Low Byte
Bit76543210
Name PCA0CPn[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[7:0] PCA Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit ca pture module n.
This register address also allows access to the low byte of the corr esponding
PCA channel’s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit
in register PCA0PWM controls which register is accessed.
Note: A write to this regi ster will clear the module’s E CO Mn bi t to a 0.
SFR Definition 26.8. PCA0CPHn: PCA Capture Module High Byte
Bit76543210
Name PCA0CPn[15:8]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:0 PCA0CPn[15:8] PCA Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
This register address also a llows access to the high byte of the corresponding
PCA channel’ s auto-reload value for 9, 10, or 11-bit PWM mode. The ARSEL bit in
register PCA0PWM controls which register is accessed.
Note: A write to this register will set the module’s ECOMn bit to a 1.
C8051F55x/56x/57x
Rev. 1.2 300
27. C2 Interface
C8051F55x/56x/57x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash
programming and in-system debugging with the production part installed in the end application. The C2
interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information
between the device and a host system. See the C2 Interface Specification for details on the C2 protocol.
27.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming through the C2 inter-
face. All C2 registers are accessed throug h the C2 interface as descr ibed in th e C2 Interface Specification.
C2 Register Definition 27.1. C2ADD: C2 Address
Bit76543210
Name C2ADD[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 C2ADD[7:0] C2 Address.
The C2ADD register is accessed via the C2 interface to select the target Data register
for C2 Data Read and Data Write commands.
Address Description
0x00 Selects the Device ID register for Data Read instructions
0x01 Selects the Revision ID register for Data Read instructions
0x02 Selects the C2 Flash Programming Control register for Data
Read/Write instructions
0xB4 Selects the C2 Flash Programming Data register for Data
Read/Write instructions
C8051F55x/56x/57x
301 Rev. 1.2
C2 Address = 0xFD; SFR Address = 0xFD; SFR Page = 0xF
C2 Address = 0xFE; SFR Address = 0xFE; SFR Page = 0xF
C2 Register Definition 27.2. DEVICEID: C2 Device ID
Bit76543210
Name DEVICEID[7:0]
Type R/W
Reset 00010100
Bit Name Function
7:0 DEVICEID[7:0] Device ID.
This read-only register returns the 8-bit device ID: 0x22 (C8051F55x/5 6x/57x).
C2 Register Definition 27.3. REVID: C2 Revision ID
Bit76543210
Name REVID[7:0]
Type R/W
Reset Varies Varies Varies Varies Varies Varies Varies Varies
Bit Name Function
7:0 REVID[7:0] Revision ID.
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A.
C8051F55x/56x/57x
Rev. 1.2 302
C2 Address: 0x02
C2 Address: 0xB4
C2 Register Definition 27.4. FPCTL: C2 Flash Programming Control
Bit76543210
Name FPCTL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPCTL[7:0] Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2
Flash programming, the followin g codes must be written in order: 0x02, 0x01. Note
that once C2 Flash programming is enabled, a system reset must be issued to
resume normal operation.
C2 Register Definition 27.5. FPDAT: C2 Flash Programming Data
Bit76543210
Name FPDAT[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 FPDAT[7:0] C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses . Valid command s ar e lis te d be low.
Code Command
0x06 Flash Block Read
0x07 Flash Block Write
0x08 Flash Page Erase
0x03 Device Erase
C8051F55x/56x/57x
303 Rev. 1.2
27.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming may be performed. This is possible because C2 communication is typically performed
when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this
halted state, the C2 interface can safely ‘borrow’ the C2CK (RST) and C2D pins. In most applications,
external resistors are required to isolate C2 interface traffic from the user application. A typical isolation
configuration is shown in Figure 27.1.
Figure 27.1. Typical C2 Pin Sharing
The configuration in Figure 27.1 assumes the following:
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
Additional resistors may be necessary depending on the spe cific application.
C2D
C2CK
RST (a)
Input (b)
Output (c)
C2 Interface Master
C8051Fxxx
C8051F55x/56x/57x
Rev. 1.2 304
DOCUMENT CHANGE LIST
Revision 0.5 to Revision 1.0
Updated “2. Ordering Information” to include -A (Automo tive ) de vices an d au to m ot i ve qu a lifica tion
information.
Updated Figure 4.8 on page 35.
Updated supply cur re n t relate d sp ec ifica tio ns throughout “5. Electrical Characteristics” .
Updated SFR Definition 7.1 to change VREF high setting to 2.20 V from 2.25 V.
Updated Figure 8.1 to indicate that Comp arators are powered from VIO and not VDDA.
Updated the Gain Ta ble in “6.3.1. Calculating the Gain Value” to fix the ADC0GNH Value in the last
row.
Updated Table 10.1 with correct timing for all branch instructions, MOVC, and CPL A.
Updated “14.2. Non-volatile Data Storage” to clarify behavior of 8-bit MOVX instructions and when
writing/erasing Flash.
Updated SFR Definition 14.3 (FLSCL) to include FLEWT bit definition. This bit must be set before
writing or erasing Flash. Also updated Table 5.5 to reflect new Flash Write and Erase timing.
Updated “16.7. Flash Error Reset” with an additional cause of a Flash Error reset.
Updated “19.1.3. Inter facing Port I/O in a Multi-Voltage System” to remove note regarding interfacing to
voltages above VIO.
Updated “22. SMBus” to remove all hardware ACK features, including SMB0ADM and SMB0ADR
SFRs.
Updated SFR Definition 23.1 (SCON0) to correct SFR Page to 0x00 from All Pages.
All items from the C8051F55x-F56x-57x Errata dated November 5th, 2009 are incorporated into this data sheet.
Revision 1.0 to Revision 1.1
Updated “1. Syst em Overview” with a voltage range specification for the internal oscillator.
Updated Table 5.6, “Internal Hig h-Frequency Oscillator Electrica l Characteristics,” on p age 42 with new
conditions for the internal oscillator accuracy. The internal oscillator accuracy is dependent on the
operating voltage range.
Updated “5. Elec tric al Charact eristics” to remove the internal oscillator curve across temperature
diagram.
Updated Figure 6.4 on Page 51 with new timing diagram when using CNVSTR pin.
Updated SFR Definition 7.1 (REF0CN) with oscillator suspend requirement for ZTCEN.
Fixed incorrect cross references in “8. Comparators” .
Updated SFR Definition 9.1 (REG0CN) with a new definition for Bit 6. The bit 6 reset value is 1b and
must be written to 1b.
Update “15.3. Suspend Mode” with note regarding ZTCEN.
Added Port 2 Event and Port 3 Events to wake-up sources in “18.2.1. Internal Oscillator Suspend
Mode”
Updated “20. Local Interconnect Network (LIN0)” with a voltage range specification for the internal
oscillator.
Updated LIN Register Definitions 20.9 and 20.10 with correct reset values.
Updated “21. Controller Area Network (CAN0)” with a voltage range specification for the internal
oscillator.
Updated C2 Register Definitions 27.2 and 27.3 with correct C2 and SFR Addresses.
C8051F55x/56x/57x
305 Rev. 1.2
Revision 1.1 to Revision 1.2
Updated the note in “Power-Fail Reset/VDD Monitor” on page 140 to use a larger fo nt.
Added the note regarding the voltage regulator and VDD monitor in the high setting from “Power-Fail
Reset/VDD Monitor” on page 140 to “Voltage Regulator (REG0)” on page 79 and “VDD Maintenance
and the VDD monitor” on page 129.
Updated the steps in “VDD Maintenance and the VDD monitor” on page 129 to mention using the VDD
monitor in the high setting during flash write/erase operations.
Updated the SUSPEND bit description in OSCICN (SFR Definition 18.2) to mention that firmware must
set the ZTCEN bit in REF0CN (SFR Defin ition 7.1) before entering suspend.
Added a note to the IFRDY flag in the OSCICN register (SFR Definition 18.2) that the flag may not
accurately reflect the state of the oscillator.
Added VREGIN Ramp Time for Power On spec to Table 5.4, “Reset Electrical Characteristics,” on
page 41.
Updated “VDD Maintenance and the VDD monitor” on page 129 to refer to VREGIN ramp time instead of
VDD ramp time.
Added a note regarding programming at cold temperatures on –I devices to “Programming The Flash
Memory” on page 124 and added Temperature during Programming Operations specification to
Table 5.5, “Flash Electrical Characteristics,” on page 41.
Added a note regarding P0.0/VREF when VDD is used as the reference to Table 19.1, “Port I/O
Assignment for Analog Functions,” on page 171 and to the description of the REFSL bit in REF0CN
(SFR Definition 7.1).
Added a note regarding a potential unknown state on GPIO during power up if VIO ramps significantly
before VDD to “Port Input/Output” on page 169 and “Reset Sources” on page 138.
Added steps to set the FLEWT bit in the FLSCL register (SFR Definition 14.3) in the flash write/erase
procedures in “Flash Erase Pro cedur e” on p a ge 125, “Flash Write Procedure” on page 125, and “Flash
Write Optimization” on page 126.
Added a note regarding fast changes on VDD causing the VDD Monitor to trigger to “Power-Fail
Reset/VDD Monitor” on page 140.
Added notes regarding UART TX and RX behavior in “Data Transmission” on page 238, “Data
Reception” on page 238, and the THRE0 description in the SCON0 register (SFR Definition 23.1).
Added a note regarding an issue with /RST low time on some older devices to “16.1. Power-On Reset” .
C8051F55x/56x/57x
Rev. 1.2 306
NOTES:
Disclaimer
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using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
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IMR C8051F560-IMR C8051F561-IMR C8051F561-IQR C8051F562-IMR C8051F562-IQR C8051F563-IMR
C8051F563-IQR C8051F564-IMR C8051F564-IQR C8051F565-IMR C8051F565-IQR C8051F566-IMR C8051F566-
IQR C8051F567-IMR C8051F567-IQR C8051F568-IMR C8051F569-IMR C8051F570-IMR C8051F571-IMR
C8051F572-IMR C8051F573-IMR C8051F574-IMR C8051F575-IMR
