Low Cost, High Speed
Differential Amplifier
AD8132
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved.
FEATURES
High speed
350 MHz, −3 dB bandwidth
1200 V/μs slew rate
Resistor set gain
Internal common-mode feedback
Improved gain and phase balance: −68 dB @ 10 MHz
Separate input to set the common-mode output voltage
Low distortion: −99 dBc SFDR @ 5 MHz, 800 Ω load
Low power: 10.7 mA @ 5 V
Power supply range: +2.7 V to ±5.5 V
Fully AEC-Q100 qualified (AD8132W)
APPLICATIONS
Low power differential ADC drivers
Differential gain and differential filtering
Video line drivers
Differential in/out level shifting
Single-ended input to differential output drivers
Active transformers
Automotive driver assistance
Automotive infotainment
GENERAL DESCRIPTION
The AD8132 is a low cost differential or single-ended input to
differential output amplifier with resistor set gain. The AD8132
is a major advancement over op amps for driving differential input
ADCs or for driving signals over long lines. The AD8132 has a
unique internal feedback feature that provides output gain and
phase matching balanced to −68 dB at 10 MHz, suppressing
harmonics and reducing radiated EMI.
Manufactured using the next-generation of Analog Devices, Inc.,
XFCB bipolar process, the AD8132 has a −3 dB bandwidth of
350 MHz and delivers a differential signal with −99 dBc SFDR
at 5 MHz, despite its low cost. The AD8132 eliminates the need for
a transformer with high performance ADCs, preserving the low
frequency and dc information. The common-mode level of the
differential output is adjustable by applying a voltage on the
VOCM pin, easily level shifting the input signals for driving single-
supply ADCs. Fast overload recovery preserves sampling accuracy.
CONNECTION DIAGRAM
–IN
1
V
OCM 2
V+
3
+OUT
4
+IN
8
NC
7
V–
6
–OUT
5
NC = NO CONNECT
AD8132
01035-001
Figure 1.
The AD8132 is also used as a differential driver for the trans-
mission of high speed signals over low cost twisted pair or coaxial
cables. The feedback network can be adjusted to boost the high
frequency components of the signal. The AD8132 is used for either
analog or digital video signals or for other high speed data trans-
mission. The AD8132 is capable of driving either a Category 3
or Category 5 twisted pair or coaxial cable with minimal line
attenuation. The AD8132 has considerable cost and performance
improvements over discrete line driver solutions.
Differential signal processing reduces the effects of ground noise
that plagues ground-referenced systems. The AD8132 can be used
for differential signal processing (gain and filtering) throughout a
signal chain, easily simplifying the conversion between differential
and single-ended components.
The AD8132W is the automotive grade version, qualified for
125°C operation per the AEC-Q100. See the Automotive
Products section for more details.
The AD8132 is available in both 8-lead SOIC and 8-lead MSOP
packages for operation over the extended industrial temperature
range of −40°C to +125°C.
FREQUENCY (MHz)
6
1
GAIN (dB)
3
0
–3
–6
–9
–12
10 100 1k
V
S
= ±5V
G = +1
V
O, dm
= 2V p-p
R
L, dm
= 499Ω
01035-002
Figure 2. Large Signal Frequency Response
AD8132
Rev. I | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ........................................................................... 3
Specifications ..................................................................................... 4
±DIN to ±OUT Specifications ...................................................... 4
VOCM to ±OUT Specifications ..................................................... 5
±DIN to ±OUT Specifications ...................................................... 6
VOCM to ±OUT Specifications ..................................................... 7
±DIN to ±OUT Specifications ...................................................... 8
VOCM to ±OUT Specifications ..................................................... 8
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
Maximum Power Dissipation ..................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Test Circuits ..................................................................................... 20
Operational Description ................................................................ 21
Definition of Terms .................................................................... 21
Basic Circuit Operation ............................................................. 21
Theory of Operation ...................................................................... 22
General Usage of the AD8132 .................................................. 22
Differential Amplifier Without Resistors (High Input
Impedance Inverting Amplifier) .............................................. 22
Other β2 = 1 Circuits ................................................................. 23
Varying β2 ................................................................................... 23
β1 = 0............................................................................................ 23
Estimating the Output Noise Voltage ...................................... 23
Calculating Input Impedance of the Application Circuit ..... 24
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 24
Setting the Output Common-Mode Voltage .......................... 24
Driving a Capacitive Load ......................................................... 24
Open-Loop Gain and Phase ..................................................... 24
Layout, Grounding, and Bypassing .............................................. 25
Circuits ......................................................................................... 25
Applications Information .............................................................. 26
Analog-to-Digital Driver .......................................................... 26
Balanced Cable Driver ............................................................... 26
Transmit Equalizer ..................................................................... 27
Low-Pass Differential Filter ...................................................... 27
High Common-Mode Output Impedance Amplifier ........... 28
Full-Wave Rectifier .................................................................... 29
Automotive Products ................................................................. 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
AD8132
Rev. I | Page 3 of 32
REVISION HISTORY
9/09—Rev. H to Rev. I
Changes to Figure 64 Caption ...................................................... 21
5/09—Rev. G to Rev. H
Changes to Features Section, Applications Section, and General
Description Section .......................................................................... 1
Changes to Table 1 ........................................................................... 4
Changes to Table 2 ........................................................................... 5
Changes to Table 3 ........................................................................... 6
Changes to Table 4 ........................................................................... 7
Added Automotive Products Section .......................................... 29
Changes to Ordering Guide .......................................................... 30
1/09—Rev. F to Rev. G
Changes to Figure 77 ..................................................................... 26
Updated Outline Dimensions ....................................................... 29
11/06—Rev. E to Rev. F
Updated Format ................................................................. Universal
Changes to Table 1 ........................................................................... 3
Changes to Table 4 ........................................................................... 6
Changes to Table 5 ........................................................................... 7
Changes to Ordering Guide .......................................................... 29
11/05—Rev. D to Rev. E
Changes to Table 7, Thermal Resistance Section, Maximum
Power Dissipation Section, and Figure 3 ...................................... 8
Changes to Ordering Guide .......................................................... 29
12/04—Rev. C to Rev. D
Changes to General Description .................................................... 1
Changes to Specifications ............................................................... 2
Changes to Absolute Maximum Ratings....................................... 8
Updated Outline Dimensions ....................................................... 29
Changes to Ordering Guide .......................................................... 29
2/03—Rev. B to Rev. C
Changes to Specifications ............................................................... 2
Addition to Estimating the Output Noise Voltage Section ...... 15
Updated Outline Dimensions ....................................................... 21
1/02—Rev. A to Rev. B
Edits to Transmitter Equalizer Section ....................................... 18
AD8132
Rev. I | Page 4 of 32
SPECIFICATIONS
±DIN TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = ±5 V, VOCM = 0 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth VOUT = 2 V p-p 300 350 MHz
AD8132W only, TMIN to TMAX 280 MHz
V
OUT = 2 V p-p, G = +2 190 MHz
−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 360 MHz
V
OUT = 0.2 V p-p, G = +2 160 MHz
Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 90 MHz
V
OUT = 0.2 V p-p, G = +2 50 MHz
Slew Rate VOUT = 2 V p-p 1000 1200 V/μs
AD8132W only, TMIN to TMAX 950 V/μs
Settling Time 0.1%, VOUT = 2 V p-p 15 ns
Overdrive Recovery Time VIN = 5 V to 0 V step, G = +2 5 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω −96 dBc
V
OUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −83 dBc
V
OUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −73 dBc
Third Harmonic VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω −102 dBc
V
OUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −98 dBc
V
OUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −67 dBc
IMD 20 MHz, RL, dm = 800 Ω −76 dBc
IP3 20 MHz, RL, dm = 800 Ω 40 dBm
Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 8 nV/√Hz
Input Current Noise f = 0.1 MHz to 100 MHz 1.8 pA/√Hz
Differential Gain Error NTSC, G = +2, RL, dm = 150 Ω 0.01 %
Differential Phase Error NTSC, G = +2, RL, dm = 150 Ω 0.10 Degrees
INPUT CHARACTERISTICS
Offset Voltage (RTI) VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 0 V ±1.0 ±3.5 mV
AD8132W only, TMIN to TMAX ±6 mV
T
MIN to TMAX variation 10 μV/°C
Input Bias Current TA = 25°C 3 7 μA
AD8132W only, TMIN to TMAX 8 μA
Input Resistance Differential 12 MΩ
Common mode 3.5 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage −4.7 to +3.0 V
CMRR ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±1 V; resistors matched to 0.01% −70 −60 dB
AD8132W only, TMIN to TMAX −60 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ΔVOUT; single-ended output −3.6 to +3.6 V
Output Current +70 mA
Output Balance Error ΔVOUT, cm/ΔVOUT, dm; ΔVOUT, dm = 1 V −70 dB
AD8132
Rev. I | Page 5 of 32
VOCM TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = ±5 V, VOCM = 0 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth ΔVOCM = 600 mV p-p 210 MHz
Slew Rate ΔVOCM = −1 V to +1 V 400 V/μs
Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 12 nV/√Hz
DC PERFORMANCE
Input Voltage Range ±3.6 V
Input Resistance 50 kΩ
Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 0 V ±1.5 ±7 mV
AD8132W only, TMIN to TMAX ±9 mV
Input Bias Current 0.5 μA
VOCM CMRR ΔVOUT, dm/ΔVOCM; ΔVOCM = ±1 V; resistors matched to 0.01% −68 dB
Gain ΔVOUT, cm/ΔVOCM; ΔVOCM = ±1 V 0.985 1 1.015 V/V
AD8132W only, TMIN to TMAX 0.985 1.015 V/V
POWER SUPPLY
Operating Range ±1.35 ±5.5 V
Quiescent Current VDIN+ = VDIN− = VOCM = 0 V 11 12 13 mA
AD8132W only, TMIN to TMAX 9 14.5 mA
T
MIN to TMAX variation 16 μA/°C
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS; ΔVS = ±1 V −70 −60 dB
AD8132W only, TMIN to TMAX −60 dB
OPERATING TEMPERATURE RANGE −40 +125 °C
AD8132
Rev. I | Page 6 of 32
±DIN TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth VOUT = 2 V p-p 250 300 MHz
AD8132W only, TMIN to TMAX 240 MHz
V
OUT = 2 V p-p, G = +2 180 MHz
−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 360 MHz
V
OUT = 0.2 V p-p, G = +2 155 MHz
Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 65 MHz
V
OUT = 0.2 V p-p, G = +2 50 MHz
Slew Rate VOUT = 2 V p-p 800 1000 V/μs
AD8132W only, TMIN to TMAX 750 V/μs
Settling Time 0.1%, VOUT = 2 V p-p 20 ns
Overdrive Recovery Time VIN = 2.5 V to 0 V step, G = +2 5 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω −97 dBc
V
OUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −100 dBc
V
OUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −74 dBc
Third Harmonic VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω −100 dBc
V
OUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −99 dBc
V
OUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −67 dBc
IMD 20 MHz, RL, dm = 800 Ω −76 dBc
IP3 20 MHz, RL, dm = 800 Ω 40 dBm
Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 8 nV/√Hz
Input Current Noise f = 0.1 MHz to 100 MHz 1.8 pA/√Hz
Differential Gain Error NTSC, G = +2, RL, dm = 150 Ω 0.025 %
Differential Phase Error NTSC, G = +2, RL, dm = 150 Ω 0.15 Degrees
INPUT CHARACTERISTICS
Offset Voltage (RTI) VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 2.5 V ±1.0 ±3.5 mV
AD8132W only, TMIN to TMAX ±6 mV
T
MIN to TMAX variation 6 μV/°C
Input Bias Current TA = 25°C 3 7 μA
8 μA
Input Resistance Differential AD8132W only, TMIN to TMAX 10 MΩ
Common-mode 3 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage 0.3 to 3.0 V
CMRR ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±1 V; resistors matched to 0.01% −70 −60 dB
AD8132W only, TMIN to TMAX −60 dB
OUTPUT CHARACTERISTICS AD8132W only, TMIN to TMAX
Output Voltage Swing Maximum ΔVOUT; single-ended output 1.0 to 4.0 V
Output Current 50 mA
Output Balance Error ΔVOUT, cm/ΔVOUT, dm; ΔVOUT, dm = 1 V −68 dB
AD8132
Rev. I | Page 7 of 32
VOCM TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 4.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth ΔVOCM = 600 mV p-p 210 MHz
Slew Rate ΔVOCM = 1.5 V to 3.5 V 340 V/μs
Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 12 nV/√Hz
DC PERFORMANCE
Input Voltage Range 1.0 to 3.7 V
Input Resistance 30 kΩ
Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 2.5 V ±5 ±11 mV
AD8132W only, TMIN to TMAX ±13 mV
Input Bias Current 0.5 μA
VOCM CMRR ΔVOUT, dm/ΔVOCM; ΔVOCM = 2.5 V ±1 V; resistors matched to 0.01% −66 dB
Gain ΔVOUT, cm/ΔVOCM; ΔVOCM = 2.5 V ±1 V 0.985 1 1.015 V/V
AD8132W only, TMIN to TMAX 0.985 1.015 V/V
POWER SUPPLY
Operating Range 2.7 11 V
Quiescent Current VDIN+ = VDIN− = VOCM = 2.5 V 9.4 10.7 12 mA
AD8132W only, TMIN to TMAX 6 13 mA
T
MIN to TMAX variation 10 μA/°C
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS; ΔVS = ±1 V −70 −60 dB
AD8132W only, TMIN to TMAX −60 dB
OPERATING TEMPERATURE RANGE −40 +125 °C
AD8132
Rev. I | Page 8 of 32
±DIN TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = 3 V, VOCM = 1.5 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 5.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth VOUT = 1 V p-p 350 MHz
V
OUT = 1 V p-p, G = +2 165 MHz
−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 350 MHz
V
OUT = 0.2 V p-p, G = +2 150 MHz
Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 45 MHz
V
OUT = 0.2 V p-p, G = +2 50 MHz
NOISE/HARMONIC PERFORMANCE
Second Harmonic VOUT = 1 V p-p, 1 MHz, RL, dm = 800 Ω −100 dBc
V
OUT = 1 V p-p, 5 MHz, RL, dm = 800 Ω −94 dBc
V
OUT = 1 V p-p, 20 MHz, RL, dm = 800 Ω −77 dBc
Third Harmonic VOUT = 1 V p-p, 1 MHz, RL, dm = 800 Ω −90 dBc
V
OUT = 1 V p-p, 5 MHz, RL, dm = 800 Ω −85 dBc
V
OUT = 1 V p-p, 20 MHz, RL, dm = 800 Ω −66 dBc
INPUT CHARACTERISTICS
Offset Voltage (RTI) VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 1.5 V ±10 mV
Input Bias Current 3 μA
Input Common-Mode Voltage 0.3 to 1.0 V
CMRR ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±0.5 V; resistors matched to 0.01% −60 dB
VOCM TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = 3 V, VOCM = 1.5 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 6.
Parameter Conditions Min Typ Max Unit
DC PERFORMANCE
Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 1.5 V ±7 mV
Gain ΔVOUT, cm/ΔVOCM; ΔVOCM = ±0.5 V 1 V/V
POWER SUPPLY
Operating Range 2.7 11 V
Quiescent Current VDIN+ = VDIN− = VOCM = 0 V 7.25 mA
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS; ΔVS = ±0.5 V −70 dB
OPERATING TEMPERATURE RANGE −40 +125 °C
AD8132
Rev. I | Page 9 of 32
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
Supply Voltage ±5.5 V
VOCM ±VS
Internal Power Dissipation 250 mW
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of the differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. Consider rms voltages and
currents when dealing with ac signals.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces through holes, ground,
and power planes reduces the θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(θJA = 121°C/W) and 8-lead MSOP (θJA = 142°C/W) packages
on a JEDEC standard 4-layer board. θJA values are approximations.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIP
A
TION (W)
1.75
1.50
1.00
1.25
0.50
0.25
0.75
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
SOIC
MSOP
01035-082
Table 8.
Package Type θJA Unit
8-Lead SOIC, 4-Layer 121 °C/W
8-Lead MSOP, 4-Layer 142 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8132 packages
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit can change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the AD8132. Exceeding a junction temperature of 150°C for
an extended period can result in changes in the silicon devices,
potentially causing failure.
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
AD8132
Rev. I | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN 1
VOCM 2
V+ 3
+OU
T
4
+IN8
NC
7
V–
6
–OUT5
NC = NO CONNECT
AD8132
01035-004
Figure 4. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Negative Input.
2 VOCM Voltage applied to this pin sets the common-mode output voltage with a ratio of 1:1. For example, 1 V dc on
VOCM sets the dc bias level on +OUT and −OUT to 1 V.
3 V+ Positive Supply Voltage.
4 +OUT Positive Output. Note that the voltage at −DIN is inverted at +OUT (see Figure 64).
5 −OUT Negative Output. Note that the voltage at +DIN is inverted at −OUT (see Figure 64).
6 V− Negative Supply Voltage.
7 NC No Connect.
8 +IN Positive Input.
AD8132
Rev. I | Page 11 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
GAIN (dB)
2
1
1
0
–1
–2
–3
–4
–5
10 100 1k
G = +1
VO, dm = 0.2V p-p
RL, dm = 499Ω
VS = +3V VS = +5V
VS = ±5V
01035-006
Figure 5. Small Signal Frequency Response (See Figure 56)
FREQUENCY (MHz)
GAIN (dB)
1 10 100 1k
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
G = +1
VO, dm = 0.2V p-p
RL, dm = 499Ω
VS = +3V
VS = +5V
VS = ±5V
01035-007
Figure 6. 0.1 dB Flatness vs. Frequency; CF = 0 pF (See Figure 56)
FREQUENCY (MHz)
GAIN (dB)
1 10 100 1k
G = +1
V
O, dm
= 0.2V p-p
R
L, dm
= 499Ω
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
V
S
= +3V V
S
= +5V
V
S
= ±5V
01035-008
Figure 7. 0.1 dB Flatness vs. Frequency; CF = 0.5 pF (See Figure 56)
FREQUENCY (MHz)
GAIN (dB)
1 10 100 1k
2
1
0
–1
–2
–3
–4
–5
3
G = +1
VO, dm = 2V p-p FOR VS = ±5V, +5V
VO, dm = 1V p-p FOR VS = +3V
RL, dm = 499Ω
VS = +3V
VS = +5V
VS = ±5V
01035-009
Figure 8. Large Signal Frequency Response; CF = 0 pF (See Figure 56)
FREQUENCY (MHz)
GAIN (dB)
110100
2
1
0
–1
–2
–3
–4
–5
1k
G = +1
VO, dm = 2V p-p FOR VS = ±5V, +5V
VO, dm = 1V p-p FOR VS = +3V
RL, dm = 499Ω
VS = +3V
VS = +5V
VS = ±5V
01035-010
Figure 9. Large Signal Frequency Response; CF = 0.5 pF (See Figure 56)
FREQUENCY (MHz)
GAIN (dB)
110100
2
1
0
–1
–2
–3
–4
–5
3
1k
V
S
= ±5V
G = +1
V
O, dm
= 2V p-p
R
L, dm
= 499Ω
–40°C
+85°C
+25°C
01035-011
Figure 10. Large Signal Frequency Response at Various Temperatures
(See Figure 56)
AD8132
Rev. I | Page 12 of 32
FREQUENCY (MHz)
GAIN (dB)
110100
2
1
0
–1
–2
–3
–4
–5
3
1k
V
S
= ±5V
G = +1
V
O, dm
= 2V p-p
R
L, dm
= 499Ω
R
F
= 499Ω
R
F
= 348Ω
R
F
= 249Ω
01035-012
Figure 11. Large Signal Frequency Response vs. RF (See Figure 56)
FREQUENCY (MHz)
IMPEDANCE (Ω)
100
1
10
1
0.1
10 100
V
S
= +5V
V
S
= ±5V
01035-013
Figure 12. Closed-Loop Single-Ended ZOUT vs. Frequency; G = +1 (See Figure 56)
FREQUENCY (MHz)
GAIN (dB)
7
1
6
5
4
3
2
1
10 100 1k
G = +2
VO, dm = 0.2V p-p
RL, dm = 200Ω
VS = +3V
VS = ±5V, +5V
01035-015
Figure 13. Small Signal Frequency Response (See Figure 57)
FREQUENCY (MHz)
GAIN (dB)
1 10 100 1k
VS = +3V, +5V, ±5V
G = +2
VO, dm = 0.2V p-p
RL, dm = 200Ω
6.1
6.0
5.9
5.8
5.7
5.6
5.5
01035-016
Figure 14. 0.1 dB Flatness vs. Frequency (See Figure 57)
FREQUENCY (MHz)
GAIN (dB)
110100
7
6
5
4
3
2
1
1k
VS = +5V, ±5V
VS = +3V
G = +2
VO, dm = 2V p-p FOR
V
S = ±5V, +5V
VO, dm = 1V p-p FOR
V
S = +3V
RL, dm = 200Ω
01035-017
Figure 15. Large Signal Frequency Response (See Figure 57)
FREQUENCY (MHz)
GAIN (dB)
1 10 100 1k
7
6
5
4
3
2
1
VS = ±5V
G = +2
VO, dm = 0.2V p-p
RL, dm = 200Ω
RF = 1.0kΩ
RF = 499Ω
RF = 1.5kΩ
01035-018
Figure 16. Small Signal Frequency Response vs. RF (See Figure 57)
AD8132
Rev. I | Page 13 of 32
FREQUENCY (MHz)
GAIN (dB)
110100
25
20
15
10
5
0
–5
1k
VS = ±5V
VO, dm = 2V p-p
RL, dm = 200Ω
RG = 499Ω
–10
–15
01035-020
G = +10, RF = 4.99kΩ
G = +5, RF = 2.49kΩ
G = +2, RF = 1kΩ
G = +1, RF = 499Ω
Figure 17. Large Signal Frequency Response for Various Gains
(See Figure 58)
FREQUENCY (MHz)
RTI BALANCE ERROR (dB)
1 10 100 1k
–
25
–30
–35
–40
–45
–50
–55
V
S
= ±5V
ΔV
O, dm
= 2V p-p
ΔV
O, cm
/ΔV
O, dm
–60
–65
G = 1
G = 2
–70
–75
01035-022
Figure 18. RTI Output Balance Error vs. Frequency (See Figure 59)
FREQUENCY (MHz)
DISTORTION (dBc)
0 506070
–
40
–50
–60
–70
–80
–90
–100
20 30 4010
–110
RL, dm = 800Ω
VO, dm = 1V p-p
HD3 (VS = 3V)
HD2 (VS = 3V)
HD2 (VS = 5V)
HD3 (VS = 5V)
01035-024
Figure 19. Harmonic Distortion vs. Frequency, G = +1 (See Figure 62)
FREQUENCY (MHz)
DISTORTION (dBc)
050
–40
–50
–60
–70
–80
–90
–100
20 30 4010
–110
6070
RL, dm = 800Ω
VO, dm = 2V p-p
HD3 (VS = +5V)
HD2 (VS = ±5V)
HD2 (VS = +5V)
HD3 (VS = ±5V)
–
30
01035-025
Figure 20. Harmonic Distortion vs. Frequency, G = 1 (See Figure 62)
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
DISTORTION (dBc)
0.25 1.50 1.75
–
40
–50
–60
–70
–80
–90
–100
0.75 1.00 1.250.50
–110
V
S
= 3V
R
L, dm
= 800ΩHD3 (f = 20MHz)
HD2 (f = 20MHz)
HD2 (f = 5MHz)
HD3 (f = 5MHz)
01035-026
Figure 21. Harmonic Distortion vs.
Differential Output Voltage, G = 1 (See Figure 62)
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
DISTORTION (dBc)
0
–
40
–50
–60
–70
–80
–90
–100
2341
–110
V
S
= 5V
R
L, dm
= 800Ω
HD3 (f = 20MHz)
HD2 (f = 20MHz)
HD2 (f = 5MHz)
HD3 (f = 5MHz)
01035-027
Figure 22. Harmonic Distortion vs.
Differential Output Voltage, G = +1 (See Figure 62)
AD8132
Rev. I | Page 14 of 32
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
DISTORTION (dBc)
0
–
40
–50
–60
–70
–80
–90
–100
2341
–110
VS = ±5V
RL, dm = 800ΩHD3 (f = 20MHz)
HD2 (f = 20MHz)
HD2 (f = 5MHz)
HD3 (f = 5MHz)
56
01035-028
Figure 23. Harmonic Distortion vs.
Differential Output Voltage, G = +1 (See Figure 62)
RLOAD (Ω)
DISTORTION (dBc)
200 700 800
–
50
–60
–70
–80
–90
–100
400 500 600300
–110
VS = 3V
VO, dm = 1V p-p
900 1000
HD3 (f = 20MHz)
HD2 (f = 20MHz)
HD2 (f = 5MHz)
HD3 (f = 5MHz)
01035-029
Figure 24. Harmonic Distortion vs. RLOAD, G = +1 (See Figure 62)
R
LOAD
(Ω)
DISTORTION (dBc)
200 700 800
–
50
–60
–70
–80
–90
–100
400 500 600300
–110
V
S
= 5V
V
O, dm
= 2V p-p
900 1000
HD3 (f = 20MHz)
HD2 (f = 20MHz)
HD2 (f = 5MHz)
HD3 (f = 5MHz)
01035-030
Figure 25. Harmonic Distortion vs. RLOAD, G = +1 (See Figure 62)
R
LOAD
(Ω)
DISTORTION (dBc)
200 700 800
–
50
–60
–70
–80
–90
–100
400 500 600300
–110
V
S
= ±5V
V
O, dm
= 2V p-p
HD3 (f = 20MHz)
HD2 (f = 20MHz)
HD2 (f = 5MHz)
HD3 (f = 5MHz)
900 1000
01035-031
Figure 26. Harmonic Distortion vs. RLOAD, G = +1 (See Figure 62)
FREQUENCY (MHz)
DISTORTION (dBc)
40 50
–50
–60
–70
–80
–90
–100
10 20 300
–110
HD3 (V
S
= 3V)
60 70
R
L, dm
= 800Ω
V
O, dm
= 1V p-p
–
40
HD3 (V
S
= 5V)
HD2 (V
S
= 5V)
HD2 (V
S
= 3V)
01035-033
Figure 27. Harmonic Distortion vs. Frequency, G = +2 (See Figure 63)
FREQUENCY (MHz)
DISTORTION (dBc)
40 50
–50
–60
–70
–80
–90
–100
10 20 300
HD3 (V
S
= ±5V)
60 70
R
L, dm
= 800Ω
V
O, dm
= 4V p-p
–40
HD3 (V
S
= +5V)
HD2 (V
S
= +5V)
80
–30
–
20
HD2 (V
S
= ±5V)
01035-034
Figure 28. Harmonic Distortion vs. Frequency, G = +2 (See Figure 63)
AD8132
Rev. I | Page 15 of 32
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
DISTORTION (dBc)
2
–50
–60
–70
–80
–90
–100
103
V
S
= 5V
R
L, dm
= 800Ω
–
40
HD3 (f = 20MHz)
4
–110
–120
HD2 (f = 20MHz)
HD2 (f = 5MHz)
HD3 (f = 5MHz)
01035-035
Figure 29. Harmonic Distortion vs.
Differential Output Voltage, G = +2 (See Figure 63)
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
DISTORTION (dBc)
2
–50
–60
–70
–80
–90
–100
103
V
S
= 5V
R
L, dm
= 800Ω
–
40
HD3 (f = 20MHz)
4
–110
HD2 (f = 20MHz)
HD2 (f = 5MHz)
HD3 (f = 5MHz)
56
01035-036
Figure 30. Harmonic Distortion vs.
Differential Output Voltage, G = +2 (See Figure 63)
R
LOAD
(Ω)
DISTORTION (dBc)
400
–
50
–60
–70
–80
–90
–100
300200 500
HD3 (f = 20MHz)
600
–110
HD2 (f = 20MHz)
HD2 (f = 5MHz)
HD3 (f = 5MHz)
700 800
V
S
= 5V
V
O, dm
= 2V p-p
900 1000
01035-037
Figure 31. Harmonic Distortion vs. RLOAD, G = +2 (See Figure 63)
R
LOAD
(Ω)
DISTORTION (dBc)
400
–
50
–60
–70
–80
–90
–100
300200 500
HD3 (f = 20MHz)
600
–110
HD2 (f = 20MHz)
HD2 (f = 5MHz)
HD3 (f = 5MHz)
700 800
V
S
= ±5V
V
O, dm
= 2V p-p
900 1000
01035-038
Figure 32. Harmonic Distortion vs. RLOAD, G = +2 (See Figure 63)
FREQUENCY (MHz)
POUT (dBm [Re: 50Ω])
10
19.5
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
20.0 20.5
fC = 20MHz
VS = ±5V
RL, dm = 800Ω
01035-039
Figure 33. Intermodulation Distortion, G = +1
FREQUENCY (MHz)
45
15
010 70
20 30 40 50 60
40
35
30
25
20
VS = ±5V, +5V
RL, dm = 800Ω
INTERCEPT (dBm [Re: 50Ω])
01035-040
Figure 34. Third-Order Intercept vs. Frequency, G = +1
AD8132
Rev. I | Page 16 of 32
V
S
= ±5V, +5V, +3V
40mV 5ns
01035-041
Figure 35. Small Signal Transient Response, G = +1
300mV 5ns
V
S
= 3V
V
O, dm
= 1.5V p-p
C
F
= 0pF
C
F
= 0.5pF
0
1035-042
Figure 36. Large Signal Transient Response, G = +1
400mV 5ns
V
S
= 5V
V
O, dm
= 2V p-p
C
F
= 0pF
C
F
= 0.5pF
0
1035-043
Figure 37. Large Signal Transient Response, G = +1
V
S
= ±5V
V
O, dm
= 2V p-p
400mV 5ns
C
F
= 0pF
C
F
= 0.5pF
01035-044
Figure 38. Large Signal Transient Response, G = +1
1V 5ns
V
–OUT
V
+OUT
V
+DIN
V
O, dm
01035-045
Figure 39. Large Signal Transient Response, G = +1
40mV 5ns
V
S
= ±5V, +5V, +3V
01035-046
Figure 40. Small Signal Transient Response, G = +2
AD8132
Rev. I | Page 17 of 32
300mV 5ns
V
S
= 3V
01035-047
Figure 41. Large Signal Transient Response, G = +2
400mV 5ns
V
S
= +5V, ±5V
01035-048
Figure 42. Large Signal Transient Response, G = +2
1V 5ns
V
S
= ±5V
V
O, dm
V
–OUT
V
+OUT
V
+DIN
01035-049
Figure 43. Large Signal Transient Response, G = +2
2mV 5ns
V
S
= ±5V
G = +1
V
O, dm
= 2V p-p
R
L, dm
= 499Ω
5ns/DIV
0.1%/DIV
0 5 10 15 20 25 30 35 40
01035-050
Figure 44. 0.1% Settling Time
5ns
C
L
= 5pF
C
L
= 0pF
C
L
= 20pF
400mV
01035-052
Figure 45. Large Signal Transient Response
for Various Capacitor Loads (See Figure 60)
FREQUENCY (MHz)
PSRR (dB)
0.1 1 10 100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1k
ΔV
O, dm
ΔV
S
+PSRR
–PSRR
+PSRR (V
S
= ±5V, +5V)
–PSRR (V
S
= ±5V)
01035-053
Figure 46. PSRR vs. Frequency
AD8132
Rev. I | Page 18 of 32
FREQUENCY (MHz)
CMRR (dB)
1 10 100 1000
–70
–80
–50
–60
–30
–40
–
20
ΔV
O, dm
ΔV
IN, cm
ΔV
O, cm
ΔV
IN, cm
V
S
= ±5V
V
IN, cm
= 2V p-p
01035-055
Figure 47. CMRR vs. Frequency (See Figure 61)
FREQUENCY (MHz)
V
OCM
GAIN (dB)
1 10 100 1000
–9
–12
–3
–6
0
ΔV
O, cm
ΔV
OCM
ΔV
OCM
= 600mV p-p
ΔV
OCM
= 2V p-p
3
6
–15
V
S
= ±5V
01035-056
Figure 48. VOCM Gain Response
V
S
= ±5V
V
OCM
= –1V TO +1V
400mV 5ns
V
O, cm
01035-057
Figure 49. VOCM Transient Response
FREQUENCY (MHz)
V
OCM
CMRR (dB)
1 10 100 1000
–70
–80
–50
–60
–30
–40
–20
ΔV
OCM
= 2V p-p
ΔV
OCM
= 600mV p-p
ΔV
O, dm
ΔV
OCM
–
10
01035-058
Figure 50. VOCM CMRR vs. Frequency
FREQUENCY (Hz)
INPUT VOLTAGE NOISE (nV/
√
Hz)
1k
10
100
10
1
100 1k 10k 100k 1M 10M 100M
01035-059
8nV/√Hz
Figure 51. Input Voltage Noise vs. Frequency
FREQUENCY (Hz)
1k
10
100
10
1
100 1k 10k 100k 1M 10M 100M
INPUT CURRENT NOISE (pA/
√
Hz)
01035-060
1.8pA/√Hz
Figure 52. Input Current Noise vs. Frequency
AD8132
Rev. I | Page 19 of 32
5ns
V
O, dm
(0.5V/DIV)
V
IN, sm
(1V/DIV)
V
S
= 5V
V
IN
= 2.5V STEP
G = +2
R
F
= 1kΩ
R
L, dm
= 200Ω
01035-061
Figure 53. Overdrive Recovery
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
15
13
5
–50 –30 90
–1010305070
11
9
7
V
S
= ±5V
V
S
= +5V
01035-062
Figure 54. Supply Current vs. Temperature
TEMPERATURE (°C)
DIFFERENTI
A
L OUTPUT OFFSET (mV)
0
–0.5
–2.5
–40 –20 100
020406080
–1.0
–1.5
–2.0
V
S
= ±5V
V
S
= +5V
01035-063
Figure 55. Differential Output Offset Voltage vs. Temperature
AD8132
Rev. I | Page 20 of 32
TEST CIRCUITS
0.1µF
348Ω
348Ω
49.9Ω
24.9Ω
348Ω
348Ω
499Ω
C
F
C
F
01035-005
Figure 56. Basic Test Circuit, G = +1
0.1µF
499Ω
499Ω
49.9Ω
24.9Ω
1000Ω
1000Ω
200Ω
01035-014
Figure 57. Basic Test Circuit, G = +2
0.1µF
499Ω
499Ω
49.9Ω
24.9Ω
R
F
200Ω
R
F
01035-019
Figure 58. Test Circuit for Various Gains
0.1µF
49.9Ω
24.9Ω
R
F
R
F
R
G
R
G
R
L
R
L
G = +1: R
F
= R
G
= 348Ω, R
L
= 249Ω (R
L, dm
= 498Ω)
G = +2: R
F
= 1000Ω, R
G
= 499Ω, R
L
= 100Ω(R
L, dm
= 200Ω)
01035-021
Figure 59. Test Circuit for Output Balance
0.1µF
348Ω
348Ω
49.9Ω
24.9Ω
348Ω
348Ω
453Ω
24.9Ω
24.9Ω
C
L
01035-051
Figure 60. Test Circuit for Capacitor Load Drive
348Ω
348Ω
49.9Ω
348Ω
348Ω
249Ω
249Ω
V
O, dm
V
O, cm
NOTES
RESISTORS MATCHED TO 0.01%.
01035-054
Figure 61. CMRR Test Circuit
0.1µF
348Ω
348Ω
49.9Ω
24.9Ω
348Ω
348Ω
300Ω
300Ω
2:1 TRANSFORMER
LPF HPF
Z
IN
= 50Ω
01035-023
Figure 62. Harmonic Distortion Test Circuit, G = +1, RL, dm = 800 Ω
0.1µF
499Ω
499Ω
49.9Ω
24.9Ω
1000
Ω
1000Ω
300Ω
300Ω
2:1 TRANSFORMER
LPF HPF
Z
IN
= 50Ω
01035-032
Figure 63. Harmonic Distortion Test Circuit, G = +2, RL, dm = 800 Ω
AD8132
Rev. I | Page 21 of 32
OPERATIONAL DESCRIPTION
DEFINITION OF TERMS
Differential Voltage
It is the difference between two node voltages. For example, the
output differential voltage (or equivalently output differential
mode voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Common-Mode Voltage
It is the average of two node voltages. The output common-
mode voltage is defined as
VOUT, cm = (V+OUT + V−OUT)/2
AD8132
C
F
+IN
–IN
R
F
C
F
R
F
R
G
R
G
+D
IN
V
OCM
–D
IN
R
L, dm
+OUT
V
OUT, dm
–OUT
0
1035-064
Figure 64. Circuit Definitions
BASIC CIRCUIT OPERATION
One of the more useful and easy to understand ways to use the
AD8132 is to provide two equal ratio feedback networks. To
match the effect of parasitics, comprise these networks of two
equal value feedback resistors (RF) and two equal value gain
resistors (RG). This circuit is shown in Figure 64.
Like a conventional op amp, the AD8132 has two differential
inputs that can be driven with both differential mode input
voltage (VIN, dm) and common-mode input voltage (VIN, cm).
There is another input to consider (VOCM) on the AD8132 that
is not present on conventional op amps. VOCM is completely
separate from the previous inputs.
There are two complementary outputs whose response can be
defined by a differential mode output (VOUT, dm) and a common-
mode output (VOUT, cm).
Table 10 shows the gain from any type of input to either type
of output.
Table 10. Differential and Common-Mode Gains
Input VOUT, dm V
OUT, cm
VIN, dm R
F/RG 0 (by design)
VIN, cm 0 0 (by design)
VOCM 0 1 (by design)
As listed in Table 10, the differential output (VOUT, dm) is equal to
the differential input voltage (VIN, dm) times RF/RG. In this case, it
does not matter if both differential inputs are driven, or only one
output is driven and the other is tied to a reference voltage, such
as ground. As seen from the two zero entries in the VOUT, dm column,
neither of the common-mode inputs has any effect on this gain.
The gain from VIN, dm to VOUT, cm is 0, and first-order, does not
depend on the ratio matching of the feedback networks. The
common-mode feedback loop within the AD8132 provides a
corrective action to keep this gain term minimized. The term
balance error describes the degree that this gain term differs
from 0.
The gain from VIN, cm to VOUT, dm directly depends on the matching
of the feedback networks. The analogous term for this transfer
function (used in conventional op amps) is common-mode
rejection ratio (CMRR). Therefore, if it has a high CMRR, the
feedback ratios must be well matched.
The gain from VIN, cm to VOUT, cm is ideally 0 and is first-order
independent of the feedback ratio matching. As in the case of
VIN, dm to VOUT, cm, the common-mode feedback loop keeps this
term minimized.
The gain from VOCM to VOUT, dm is ideally 0 when the feedback ratios
are matched only. The amount of differential output signal that is
created by varying VOCM is related to the degree of mismatch in the
feedback networks.
VOCM controls the output common-mode voltage VOUT, cm with a
unity-gain transfer function. With equal ratio feedback networks
(as previously assumed), its effect on each output is the same,
that is the gain from VOCM to VOUT, dm is 0. If not driven, the
output common-mode voltage is set with an internal voltage
divider to a level that is nominally midsupply. It is recommended
that a 0.1 μF bypass capacitor be connected to VOCM.
When unequal feedback ratios are used, the two gains associated
with VOUT, dm become nonzero. This significantly complicates the
mathematical analysis along with any intuitive understanding of
how the part operates.
AD8132
Rev. I | Page 22 of 32
THEORY OF OPERATION
The AD8132 differs from conventional op amps by the external
presence of an additional input and output. The additional
input, VOCM, controls the output common-mode voltage. The
additional output is the analog complement of the single output
of a conventional op amp. For its operation, the AD8132 uses two
feedback loops as compared to the single loop of conventional
op amps. Although this provides significant freedom to create
various novel circuits, basic op amp theory can still be used to
analyze the operation.
One of the feedback loops controls the output common-mode
voltage, VOUT, cm. Its input is VOCM (Pin 2) and the output is the
common mode, or average voltage, of the two differential outputs
(+OUT and −OUT). The gain of this circuit is internally set to
unity. When the AD8132 is operating in its linear region, this
establishes one of the operational constraints: VOUT, cm = VOCM.
The second feedback loop controls the differential operation.
Similar to an op amp, the gain and gain shaping of the transfer
function can be controlled by adding passive feedback networks.
However, only one feedback network is required to close the
loop and fully constrain the operation, but depending on the
function desired, two feedback networks can be used. This is
possible because there are two outputs that are each inverted
with respect to the differential inputs.
GENERAL USAGE OF THE AD8132
Several assumptions are made here for a first-order analysis; they
are the typical assumptions used for the analysis of op amps.
• The input bias currents are sufficiently small so they can be
neglected.
• The output impedances are arbitrarily low.
• The open-loop gain is arbitrarily large and drives the
amplifier to a state where the input differential voltage is
effectively 0.
• Offset voltages are assumed to be 0.
Though it is possible to operate the AD8132 with a purely
differential input, many of its applications call for a circuit
that has a single-ended input with a differential output.
For a single-ended-to-differential circuit, the RG of the input that
is not driven is tied to a reference voltage or to ground. Additional
conditions are discussed in the following sections. In addition,
the voltage at VOCM, and therefore VOUT, cm, is assumed to be ground.
Figure 67 shows a generalized schematic of such a circuit using an
AD8132 with two feedback paths.
For each feedback network, a feedback factor can be defined as
the fraction of the output signal that is fed back to the opposite
sign input. These terms are
β1 = RG1/(RG1 + RF1)
β2 = RG2/(RG2 + RF2)
The feedback factor, β1, is for the side that is driven, and the
feedback factor, β2, is for the side that is tied to a reference
voltage (ground). Note that each feedback factor can vary
anywhere between 0 and 1.
A single-ended-to-differential gain equation can be derived
(this is true for all values of β1 and β2) from
(
)
()
β2β1
β1
G+
−
=12
This expression is not very intuitive, but some further examples
can provide better understanding of its implications. One
observation that can be made immediately is that a tolerance
error in β1 does not have the same effect on gain as the same
tolerance error in β2.
DIFFERENTIAL AMPLIFIER WITHOUT RESISTORS
(HIGH INPUT IMPEDANCE INVERTING AMPLIFIER)
The simplest closed-loop circuit that can be made does not
require any resistors and is shown in Figure 70. In this circuit,
β1 is equal to 0, and β2 is equal to 1. The gain is equal to 2.
A more intuitive method to figure the gain is by simple inspection.
+OUT is connected to −IN, whose voltage is equal to the voltage at
+IN under equilibrium conditions. Therefore, +VOUT is equal to
VIN, and there is unity gain in this path. Because −OUT has to
swing in the opposite direction from +OUT due to the common-
mode constraint, its effect doubles the output signal and
produces a gain of 2.
One useful function that this circuit provides is a high input
impedance inverter. If +OUT is ignored, there is a unity-gain,
high input impedance amplifier formed from +IN to −OUT.
Most traditional op amp inverters have relatively low input
impedances, unless they are buffered with another amplifier.
VOCM is assumed to be at midsupply. Because there is still the
constraint that +VOUT must equal VIN, changing the VOCM voltage
does not change +VOUT (equal to VIN). Therefore, the effect of
changing VOCM must show up at −OUT.
For example, if VOCM is raised by 1 V, then −VOUT must increase
by 2 V. This makes VOUT, cm also increase by 1 V because it is defined
as the average of the two differential output voltages. This means
that the gain from VOCM to the differential output is 2.
AD8132
Rev. I | Page 23 of 32
OTHER β2 = 1 CIRCUITS
The preceding simple configuration with β2 = 1 and its gain of 2
is the highest gain circuit that can be made under this condition.
Because β1 was equal to 0, only higher β1 values are possible.
The circuits with higher values of β1 have gains lower than 2.
However, circuits with β1 equal to 1 are not practical because
they have no effective input and result in a gain of 0.
To increase β1 from 0, it is necessary to add two resistors in a feed-
back network. A generalized circuit that has β1 with a value higher
than 0 is shown in Figure 69. A couple of different convenient
gains that can be created are a gain of 1, when β1 is equal to 1/3,
and a gain of 0.5, when β1 equals 0.6.
With β2 equal to 1 in these circuits, VOCM serves as the refer-
ence voltage that measures the input voltage and the individual
output voltages. In general, when VOCM is varied in circuits with
unmatched feedback networks, a differential output signal is
generated that is proportional to the applied VOCM voltage.
VARYING β2
Though the β2 = 1 circuit sets β2 to 1, another class of simple
circuits can be made that sets β2 equal to 0. This means that
there is no feedback from +OUT to −IN. This class of circuits
is very similar to a conventional inverting op amp. However,
the AD8132 circuits have an additional output and common-
mode input that can be analyzed separately (see Figure 71).
With −IN connected to ground, +IN becomes a virtual ground
in the sense that the term is used for conventional op amps. Both
inputs must maintain the same voltage for equilibrium operation;
therefore, if one is set to ground, the other is driven to ground.
The input impedance can also be seen to be equal to RG, just as
in a conventional op amp.
In this case, however, the positive input and negative output are
used for the feedback network. Because a conventional op amp
does not have a negative output, only its inverting input can be
used for the feedback network. The AD8132 is symmetrical,
therefore, the feedback network on either side can be used to
produce the same results.
Because +IN is a summing junction, by an analogy to conven-
tional op amps, the gain from VIN to −OUT is −RF/RG. This holds
true regardless of the voltage on VOCM, and because +OUT
moves the same amount in the opposite direction from −OUT,
the overall gain is −2(RF/RG).
VOCM still governs VOUT, cm; therefore, +OUT must be the only
output that moves when VOCM is varied. Because VOUT, cm is the
average of the two outputs, +OUT must move twice as far, and in
the same direction as VOCM, to create the proper VOUT, cm. Therefore,
the gain from VOCM to +OUT must be 2.
With β2 equal to 0 in these circuits, the gain can theoretically be
set to any value from close to 0 to infinity, just as it can with a
conventional op amp in the inverting mode. However, practical
real-world limitations and parasitics limit the range of acceptable
gain to more modest values.
β1 = 0
There is yet another class of circuits where there is no feedback
from −OUT to +IN. This is the case where β1 = 0. The differential
amplifier without a resistor described in the Differential Amplifier
Without Resistors (High Input Impedance Inverting Amplifier)
section meets this condition, but it was presented only with the
condition that β2 = 1. Recall that this circuit had a gain equal to 2.
If β2 decreases in this circuit from unity, a smaller part of +VOUT
is fed back to −IN and the gain increases (see Figure 68). This
circuit is very similar to a noninverting op amp configuration,
except for the presence of the additional complementary output.
Therefore, the overall gain is twice that of a noninverting op
amp or 2 × (1 + RF2/RG2) or 2 × (1/β2).
Once again, varying VOCM does not affect both outputs in the
same way; therefore, in addition to varying VOUT, cm with unity
gain, there is also an effect on VOUT, dm by changing VOCM.
ESTIMATING THE OUTPUT NOISE VOLTAGE
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input-referred terms, at +IN and −IN, by the
circuit noise gain. The noise gain is defined as
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+=
G
F
NR
R
G1
To compute the total output-referred noise for the circuit of
Figure 64, consideration must be given to the contribution of
resistors, RF and RG. See Table 11 for estimated output noise
voltage densities at various closed-loop gains.
Table 11. Recommended Resistor Values and Noise
Performance for Specific Gains
Gain RG (Ω) RF (Ω)
Bandwidth
−3 dB (MHz)
Output
Noise
AD8132
Only
(nV/√Hz)
Output
Noise
AD8132
+ RG, RF
(nV/√Hz)
1 499 499 360 16 17
2 499 1.0 k 160 24.1 26.1
5 499 2.49 k 65 48.4 53.3
10 499 4.99 k 20 88.9 98.6
AD8132
Rev. I | Page 24 of 32
When using the AD8132 in gain configurations where β1 ≠ β2,
differential output noise appears due to input-referred voltage
noise in the VOCM circuitry according to the following formula:
In cases where more accurate control of the output common-mode
level is required, it is a best practice that an external source or
resistor divider (with RSOURCE < 10 kΩ) be used. The output
common-mode offset values in the Specifications section assume
the VOCM input is driven by a low impedance voltage source.
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡
+
−
=β2β1
β2β1
VV NOCMOND 2
DRIVING A CAPACITIVE LOAD
where:
VOND is the output differential noise.
VNOCM is the input-referred voltage noise on VOCM.
A purely capacitive load can react with the pin and bond wire
inductance of the AD8132, resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to place a
small capacitor across each of the feedback resistors. The added
capacitance must be small to avoid destabilizing the amplifier. An
alternative technique is to place a small resistor in series with
the amplifier outputs, as shown in Figure 60.
CALCULATING INPUT IMPEDANCE OF THE
APPLICATION CIRCUIT
The effective input impedance of a circuit, such as that in Figure 64,
at +DIN and −DIN, depends on whether the amplifier is being
driven by a single-ended or differential signal source. For balanced
differential input signals, the input impedance (RIN, dm) between
the inputs (+DIN and −DIN) is simply
OPEN-LOOP GAIN AND PHASE
Open-loop gain and phase plots are shown in Figure 65 and
Figure 66.
RIN, dm = 2 × RG
–20
–10
0
10
20
30
40
50
60
0.1 1 10 100 1000
FREQUENCY (MHz)
OPEN-LOOP GAIN (dB)
R
L, dm
= 2kΩ
01035-083
In the case of a single-ended input signal (for example, if −DIN
is grounded and the input signal is applied to +DIN), the input
impedance becomes
()
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎝
⎛
+
×
−
=
F
G
F
G
dmIN,
RR
R
R
R
2
1
The circuit input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor, RG. Figure 65. Open-Loop Gain vs. Frequency
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
–200
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
20
40
0.1 1 10 100 1000
FREQUENCY (MHz)
OPEN-LOOP PHASE (Degrees)
R
L, dm
= 2kΩ
01035-084
The AD8132 is optimized for level-shifting, ground-referenced
input signals. For a single-ended input, this implies that the voltage
at −DIN in Figure 64 is 0 V when the negative power supply
voltage (at V−) of the amplifier is also set to 0 V.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the AD8132 is internally biased at a voltage
approximately equal to the midsupply point (average value of the
voltage on V+ and V−). Relying on this internal bias results in an
output common-mode voltage that is within approximately
100 mV of the expected value.
Figure 66. Open-Loop Phase vs. Frequency
AD8132
Rev. I | Page 25 of 32
LAYOUT, GROUNDING, AND BYPASSING
As a high speed part, the AD8132 is sensitive to the printed
circuit board (PCB) environment in which it operates. Realizing
its superior specifications requires attention to various details of
good high speed PCB design.
The first requirement is a good solid ground plane that covers as
much of the board area around the AD8132 as possible. The only
exception to this is that the two input pins (Pin 1 and Pin 8) are
kept a few millimeters from the ground plane and that ground
be removed from inner layers and the opposite side of the board
under the input pins. This minimizes the stray capacitance on
these nodes and helps preserve the gain flatness vs. the frequency.
Bypass the power supply pins as close as possible to the device
to the nearby ground plane and use good high frequency ceramic
chip capacitors. Do this bypassing with a capacitance value
of 0.01 μF to 0.1 μF for each supply. Farther away, provide low
frequency bypassing with 10 μF tantalum capacitors from each
supply to ground.
Keep the signal routing short and direct to avoid parasitic effects.
Wherever there are complementary signals, a symmetrical
layout with matched lengths must be provided to the extent
possible to maximize the balance performance. When running
differential signals over a long distance, place the traces on
the PCB close together or twist together any differential wiring
to minimize the area of the loop that is formed. This reduces
the radiated energy and makes the circuit less susceptible to
interference.
CIRCUITS
RF1
+
RF2
RG1
RG2
01035-065
Figure 67. Typical Four-Resistor Feedback Circuit
+
R
F2
R
G2
V
IN
01035-066
Figure 68. Typical Circuit with β1 = 0
R
F1
+
R
G1
01035-067
Figure 69. Typical Circuit with β2 = 1
+
V
IN
01035-068
Figure 70. G = +2 Circuit with β1 = 0, Without Resistors
R
F1
+
R
G1
V
IN
01035-069
Figure 71. Typical Circuit with β2 = 0
AD8132
Rev. I | Page 26 of 32
APPLICATIONS INFORMATION
ANALOG-TO-DIGITAL DRIVER
Many of the newer high speed ADCs are single supply and have
differential inputs. Thus, the driver for these devices is able to
convert from a single-ended signal to a differential signal and
provide output common-mode level shifting in addition to
having low distortion and noise. The AD8132 conveniently
performs these functions when driving the AD9203, a 10-bit,
40 MSPS ADC.
In Figure 73, a 1 V p-p signal drives the input of an AD8132
configured for unity gain. Both the AD8132 and the AD9203 are
powered from a single 3 V supply. A voltage divider biases VOCM
at midsupply and in turn drives VOUT, cm to half of the supply
voltage. This is within the common-mode range of the AD9203.
Between the ADC and the driver is a 1-pole, differential filter that
helps to filter some of the noise and assists the switched-capacitor
inputs of the ADC. Each of the ADC inputs is driven by a 0.5 V p-p
signal that ranges from 1.25 V dc to 1.75 V dc. Figure 72 is an
FFT plot of the performance of the circuit when running at a
clock rate of 40 MSPS and an input frequency of 2.5 MHz.
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0
2ND
3RD 4TH
5TH
7TH
8TH
9TH
6TH
f
S
= 40MHz
f
IN
= 2.5MHz
INPUT FREQUENCY (MHz)
OUTPUT (dBc)
FUND
01035-071
Figure 72. FTT Response for AD8132 Driving AD9203
BALANCED CABLE DRIVER
When driving a twisted pair cable, it is desirable to drive only
a pure differential signal onto the line. If the signal is purely
differential (that is, fully balanced), and the transmission line is
twisted and balanced, there is minimum radiation of any signal.
The complementary electrical fields are confined mostly to
the space between the two twisted conductors and does not
significantly radiate out from the cable. The current in the cable
creates magnetic fields that radiate to some degree. However, the
amount of radiation is mitigated by the twists, because for
each twist, the two adjacent twists have an opposite polarity
magnetic field. If the twist pitch is tight enough, these small
magnetic field loops contain most of the magnetic flux, and
the magnetic farfield strength is negligible.
3
V
0.1µF 10µF
+
3V
348Ω
0.1µF
348Ω
49.9Ω
348Ω
24.9Ω
10kΩ
10kΩ
1V p-p
348Ω
60.4Ω
60.4Ω
20pF
20pF
AINN
AINP
AVDD DRVDD
AVSS DRVSS
AD9203
DIGITAL
OUTPUTS
3V
0.1µF 0.1µF
AD8132
8
2
1
3
5
6
4
25
26
28
27 1
2
01035-070
Figure 73. AD8132 Driving AD9203, a 10-Bit, 40 MSPS ADC
AD8132
Rev. I | Page 27 of 32
499Ω
523Ω
1kΩ
1kΩ
10µF
+
+5
V
AD8132
0.1µF
49.9Ω
50Ω
S
OURCE
0.1µF
+0.1µF
10µF
–5V
49.9Ω
49.9Ω
TWISTED
PAIR
100Ω
1
2
3
4
7
5
AD830
+0.1µF
10µF
–5V
10µF
+
+5V
0.1µF
V
OUT
01035-072
Figure 74. Balanced Line Driver and Receiver Using AD8132 and AD830
Any imbalance in the differential drive signal appears as a
common-mode signal on the cable. This is the equivalent of
a single wire that is driven with the common-mode signal. In
this case, the wire acts as an antenna and radiates. Therefore, to
minimize radiation when driving differential twisted pair cables,
make sure the differential drive signal is well balanced.
The common-mode feedback loop in the AD8132 helps to
minimize the amount of common-mode voltage at the output
and can, therefore, be used to create a well-balanced differential
line driver. Figure 74 shows an application that uses an AD8132
as a balanced line driver and an AD830 as a differential receiver
configured for unity gain. This circuit was operated with 10 meters
of Category 5 cable.
TRANSMIT EQUALIZER
Any length of transmission line attenuates the signals it carries.
This effect is worse at higher frequencies than at lower frequencies.
One way to compensate for this is to provide an equalizer circuit
that boosts the higher frequencies in the transmitter circuit, so
that at the receive end of the cable, the attenuation effects are
diminished.
By lowering the impedance of the RG component of the feedback
network at a higher frequency, the gain can be increased at a
high frequency. Figure 75 shows the gain of a two-line driver
that has its RG resistors shunted by 10 pF capacitors. The effect
of this is shown in the frequency response plot of Figure 76.
249Ω
49.9Ω
10pF 499Ω
10pF
249Ω
24.9Ω
V
IN
49.9Ω
499Ω
49.9Ω
100ΩV
OUT
01035-073
Figure 75. Frequency Boost Circuit
11000
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
V
OUT
/
V
IN
(dB)
10 100
FREQUENCY (MHz)
01035-074
Figure 76. Frequency Response for Transmit Boost Circuit
LOW-PASS DIFFERENTIAL FILTER
Similar to an op amp, various types of active filters can be
created with the AD8132. These can have single-ended inputs
and differential outputs that can provide an antialias function
when driving a differential ADC.
33pF
2.15k
Ω
953Ω
953Ω
33pF
2.15kΩ
100pF
100pF
2kΩ
2kΩ
24.9Ω
49.9Ω
549Ω
549Ω
200pF
200pF
V
IN
V
OUT
01035-075
Figure 77. 1 MHz, 3-Pole Differential Output,
Low-Pass, Multiple Feedback Filter
Figure 77 is a schematic of a low-pass, multiple feedback filter.
The active section contains two poles, and an additional pole
is added at the output. The filter was designed to have a −3 dB
frequency of 1 MHz.
AD8132
Rev. I | Page 28 of 32
The actual −3 dB frequency was measured to be 1.12 MHz, as
shown in Figure 78.
FREQUENCY (Hz)
10
10k
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
100k 1M 10M 100M
V
OUT
/
V
IN
(dB)
01035-076
Figure 78. Frequency Response of 1 MHz Low-Pass Filter
HIGH COMMON-MODE OUTPUT IMPEDANCE
AMPLIFIER
Changing the connection to VOCM (Pin 2) can change the common-
mode from low impedance to high impedance. If VOCM is actively
set to a particular voltage, the AD8132 tries to force VOUT, cm to
the same voltage with a relatively low output impedance. All the
previous analysis assumed that this output impedance is arbitrarily
low enough to drive the load condition in the circuit.
However, some applications benefit from high common-mode
output impedance. This is accomplished with the circuit shown
in Figure 79.
R
G
348Ω
R
F
348Ω
R
F
348Ω
R
G
348Ω
10Ω
10Ω
1kΩ
1kΩ
49.9Ω
49.9Ω
0
1035-077
Figure 79. High Common-Mode, Output Impedance, Differential Amplifier
VOCM is driven by a resistor divider that measures the output
common-mode voltage. Thus, the common-mode output voltage
takes on the value that is set by the driven circuit. In this case,
it comes from the center point of the termination at the receive
end of a 10 meter length of Category 5 twisted pair cable.
If the receive end common-mode voltage is set to ground, it is
well defined at the receive end. Any common-mode signal that
is picked up over the cable length due to noise appears at the
transmit end and must be absorbed by the transmitter. Thus, it is
important that the transmitter have adequate common-mode
output range to absorb the full amplitude of the common-mode
signal coupled onto the cable and therefore prevent clipping.
Another way to look at this is that the circuit performs what is
sometimes called a transformer action. One main difference is
that the AD8132 passes dc while transformers do not.
A transformer can also be easily configured to have either a high or
low common-mode output impedance. If the transformers center
tap is connected to a solid voltage reference, it sets the common-
mode voltage on the secondary side of the transformer. In this case,
if one of the differential outputs is grounded, the other output has
half of the differential output signal. This keeps the common-mode
voltage at ground, where it is required to be due to the center tap
connection. This is analogous to the AD8132 operating with a low
output impedance common mode (see Figure 80).
V
DIFF
V
OCM
01035-078
Figure 80. Transformer with Low Output Impedance Secondary Set at VOCM
If the center tap of the secondary of a transformer is allowed to
float as shown in Figure 81 (or if there is no center tap), the
transformer has high common-mode output impedance. This
means that the common mode of the secondary is determined
by what it is connected to and not by anything to do with the
transformer itself.
V
DIFF
NC
01035-079
Figure 81. Transformer with High Output Impedance Secondary
If one of the differential ends of the transformer is grounded,
the other end swings with the full output voltage. This means
that the common mode of the output voltage is one-half of the
differential output voltage. However, this shows that the common
mode is not forced via low impedance to a given voltage. The
common-mode output voltage can be easily changed to any voltage
through its other output terminals.
The AD8132 can exhibit the same performance when one of
the outputs in Figure 79 is grounded. The other output swings
at the full differential output voltage. The common-mode signal
is measured by the voltage divider across the outputs and input
to VOCM. This, then, drives VOUT, cm to the same level. At higher
frequencies, it is important to minimize the capacitance on
the VOCM node; otherwise, phase shifts can compromise the
performance. The voltage divider resistances can also be lowered
for better frequency response.
AD8132
Rev. I | Page 29 of 32
FULL-WAVE RECTIFIER If there is not enough forward bias (VOUT, cm too low), the lower
sharp cusps of the full-wave rectified output waveform are rounded
off. In addition, as the frequency increases, there tends to be some
rounding of the lower cusps. The forward bias can be increased
to yield sharper cusps at higher frequencies.
The balanced outputs of the AD8132, along with a couple of
Schottky diodes, can create a very high speed, full-wave rectifier.
Such circuits are useful for measuring ac voltages and other
computational tasks.
There is not a reliable, entirely quantifiable, means to measure
the performance of a full-wave rectifier. Because the ideal
waveform has periodic sharp discontinuities, it has (mostly
even) harmonics that have no upper bound on the frequency.
However, for a practical circuit, as the frequency increases, the
higher harmonics become attenuated and the sharp cusps that
are present at low frequencies become significantly rounded.
Figure 82 shows the configuration of such a circuit. Each of the
AD8132 outputs drives the anode of an HP2835 Schottky diode.
These Schottky diodes were chosen for their high speed operation.
At lower frequencies (approximately lower than 10 MHz), a silicon
signal diode, such as a 1N4148, can be used. The cathodes of the
two diodes are connected together, and this output node is
connected to ground by a 100 Ω resistor.
R
G1
348Ω
R
F1
348Ω
R
F2
348Ω
R
G2
348Ω
+5
V
–5V
R
L
100Ω
R
T2
24.9Ω
R
T1
49.9Ω
V
IN
HP2835
V
OUT
+5V
CR1
10kΩ
01035-080
When running the circuit at a frequency up to 300 MHz, though it
stays functional, the major harmonic that remains in the output
is the second. This looks like a sine wave at 600 MHz. Figure 83 is
an oscilloscope plot of the output when driven by a 100 MHz,
2.5 V p-p input.
Sometimes a second harmonic generator is useful for creating a
clock to oversample a DAC by a factor of two. If the output of
this circuit is run through a low-pass filter, it can be used as a
second harmonic generator.
Figure 82. Full-Wave Rectifier
100mV 2ns
1V
01035-081
Operate the diodes such that they are slightly forward-biased
when the differential output voltage is zero. For the Schottky
diodes, this is approximately 400 mV. The forward biasing is
conveniently adjusted by CR1, which, in this circuit, raises and
lowers VOUT, cm without creating a differential output voltage.
One advantage of this circuit is that the feedback loop is never
momentarily opened while the diodes reverse their polarity within
the loop. This scheme is sometimes used for full-wave rectifiers
that use conventional op amps. These conventional circuits do
not work well at frequencies above approximately 1 MHz. Figure 83. Full-Wave Rectifier Response with 100 MHz Input
AUTOMOTIVE PRODUCTS
The AD8132W is qualified per the AEC-Q100 for use in
automotive applications. Custom variants of this product may
be available to meet stringent automotive performance and
quality requirements.
AD8132
Rev. I | Page 30 of 32
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 84. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
091709-A
6°
0°
0.70
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.13
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 85. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding Ordering Quantity
AD8132AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8132AR-REEL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 2,500
AD8132AR-REEL7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1,000
AD8132ARZ1 −40°C to +125°C 8-Lead SOIC_N R-8
AD8132ARZ-RL1 −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 2,500
AD8132ARZ-R71 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1,000
AD8132ARM −40°C to +125°C 8-Lead MSOP RM-8 HMA
AD8132ARM-REEL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 HMA 3,000
AD8132ARM-REEL7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 HMA 1,000
AD8132ARMZ1 −40°C to +125°C 8-Lead MSOP RM-8 HMA#
AD8132ARMZ-REEL1 −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 HMA# 3,000
AD8132ARMZ-REEL71 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 HMA# 1,000
AD8132WARMZ-R71, 2 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 H14 1,000
1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.
2 Automotive qualified product.
AD8132
Rev. I | Page 31 of 32
NOTES
AD8132
Rev. I | Page 32 of 32
NOTES
©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01035–0–9/09(I)
