MR25H256
256Kb Serial SPI MRAM
FEATURES
• Nowritedelays
• Unlimitedwriteendurance
• Dataretentiongreaterthan20years
• Automaticdataprotectiononpowerloss
• Blockwriteprotection
• Fast,simpleSPIinterfacewithupto40MHzclockrate
• 2.7to3.6Voltpowersupplyrange
• Lowcurrentsleepmode
• Industrialtemperatures
• Availablein8-pinDFNor8-pinDFNSmallFlagRoHS-compliant
packages.
• DirectreplacementforserialEEPROM,Flash,FeRAM
INTRODUCTION
TheMR25H256isa262,144-bitmagnetoresistiverandomaccess
memory(MRAM)deviceorganizedas32,768wordsof8bits.The
MR25H256oersserialEEPROMandserialFlashcompatibleread/writetimingwithnowritedelaysand
unlimitedread/writeendurance.
Unlikeotherserialmemories,bothreadsandwritescanoccurrandomlyinmemorywithnodelaybetween
writes.TheMR25H256istheidealmemorysolutionforapplicationsthatmuststoreandretrievedataand
programsquicklyusingasmallnumberofI/Opins.
TheMR25H256isavailableineithera5mmx6mm8-pinDFNpackageora5mmx6mm8-pinDFN
SmallFlagpackage.BotharecompatiblewithserialEEPROM,Flash,andFeRAMproducts.
TheMR25H256provideshighlyreliabledatastorageoverawiderangeoftemperatures.Theproductis
oeredwithindustrial(-40°to+85°C)andAEC-Q100Grade1(-40°Cto+125°C)operatingtemperature
rangeoptions.
MR25H256Rev.7,11/2011
1
RoHS
CONTENTS
1.DEVICEPINASSIGNMENT.........................................................................3
2.SPICOMMUNICATIONSPROTOCOL......................................................4
3.ELECTRICALSPECIFICATIONS.................................................................10
4.TIMINGSPECIFICATIONS.......................................................................... 14
5.ORDERINGINFORMATION.......................................................................16
6.MECHANICALDRAWING..........................................................................17
7.REVISIONHISTORY......................................................................................18
HowtoReachUs..........................................................................................18
EverspinTechnologies©2011
Overview
TheMR25H256isaserialMRAMwithmemoryarraylogicallyorganizedas32Kx8usingthefourpininterface
ofchipselect(CS),serialinput(SI),serialoutput(SO)andserialclock(SCK)oftheserialperipheralinterface
(SPI)bus.SerialMRAMimplementsasubsetofcommandscommontotoday’sSPIEEPROMandFlashcom-
ponentsallowingMRAMtoreplacethesecomponentsinthesamesocketandinteroperateonasharedSPI
bus.SerialMRAMoerssuperiorwritespeed,unlimitedendurance,lowstandby&operatingpower,and
morereliabledataretentioncomparedtoavailableserialmemoryalternatives.
32KB
MRAM ARRAY
Instruction Decode
Clock Generator
Control Logic
Write Protect
WP
CS
HOLD
SCK
SI
Instruction Register
Address Register
Counter
SO
Data I/O Register
Nonvolatile Status
Register
15 8
4
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
MR25H256
MR25H256Rev.7,11/2011
2
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System Conguration
SingleormultipledevicescanbeconnectedtothebusasshowinFigure1.2.PinsSCK,SOandSIarecom-
monamongdevices.EachdevicerequiresCSandHOLDpinstobedrivenseperately.
MOSI
MISO
MOSI = Master Out Slave In
MISO = Master In Slave Out
SCK
SCKSISO SCKSISO
HOLD
CS
HOLD
CS
2
2
1
1
HOLD HOLDCS CS
SPI
Micro Controller
EVERSPIN SPI MRAM 1 EVERSPIN SPI MRAM 2
Figure 1.2 System Conguration
Signal Name Pin I/O Function Description
CS 1 Input ChipSelect AnactivelowchipselectfortheserialMRAM.Whenchipselectishigh,the
memoryispowereddowntominimizestandbypower,inputsareignored
andtheserialoutputpinisHi-Z.Multipleserialmemoriescanshareacom-
monsetofdatapinsbyusingauniquechipselectforeachmemory.
SO 2 Output SerialOutput ThedataoutputpinisdrivenduringareadoperationandremainsHi-Zat
allothertimes.SOisHi-ZwhenHOLDislow.Datatransitionsonthedata
outputoccuronthefallingedgeofSCK.
WP 3 Input WriteProtect AlowonthewriteprotectinputpreventswriteoperationstotheStatus
Register.
VSS 4 Supply Ground Powersupplygroundpin.
SI 5 Input SerialInput Alldataisinputtothedevicethroughthispin.Thispinissampledonthe
risingedgeofSCKandignoredatothertimes.SIcanbetiedtoSOtocreate
asinglebidirectionaldatabusifdesired.
SCK 6 Input SerialClock SynchronizestheoperationoftheMRAM.Theclockcanoperateupto40
MHztoshiftcommands,address,anddataintothememory.Inputsare
capturedontherisingedgeofclock.DataoutputsfromtheMRAMoccur
onthefallingedgeofclock.TheserialMRAMsupportsbothSPIMode0
(CPOL=0,CPHA=0)andMode3(CPOL=1,CPHA=1).InMode0,theclockis
normallylow.InMode3,theclockisnormallyhigh.Memoryoperationis
staticsotheclockcanbestoppedatanytime.
HOLD 7 Input Hold AlowontheHoldpininterruptsamemoryoperationforanothertask.
WhenHOLDislow,thecurrentoperationissuspended.Thedevicewill
ignoretransitionsontheCSandSCKwhenHOLDislow.Alltransitionsof
HOLDmustoccurwhileCSislow.
VDD 8 Supply PowerSupply Powersupplyvoltagefrom+2.7to+3.6volts.
CS
SO
WP
V
V
HOLD
SCK
SI
1
2
3
4
8
7
6
5
SS
DD
Table 1.1 Pin Functions
Figure 1.3 Pin Diagrams (Top View)
8-Pin DFN or 8-Pin DFN Small Flag Packages
DEVICE PIN ASSIGNMENT MR25H256
MR25H256Rev.7,11/2011
3
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2. SPI COMMUNICATIONS PROTOCOL
MR25H256
Instruction Description Binary Code Hex Code Address Bytes Data Bytes
WRENWriteEnable 0000011006h0 0
WRDIWriteDisable0000010004h0 0
RDSR ReadStatusRegister 00000101 05h0 1
WRSR WriteStatusRegister 00000001 01h0 1
READReadDataBytes 0000001103h2 1to∞
WRITE WriteDataBytes 00000010 02h2 1to∞
SLEEP EnterSleepMode 10111001 B9h0 0
WAKE ExitSleepMode 10101011 ABh0 0
Table 2.1 Command Codes
4MR25H256Rev.7,11/2011
EverspinTechnologies©2011
Status Register and Block Write Protection
Thestatusregisterconsistsofthe8bitslistedintable2.2.StatusregisterbitsBP0andBP1denethemem-
oryblockarraysthatareprotectedasdescribedintable2.3.TheStatusRegisterWriteDisablebit(SRWD)
isusedinconjunctionwithbit1(WEL)andtheWriteProtectionpin(WP)asshownintable2.4toenable
writestostatusregisterbits.ThefastwritingspeedofMR25H256doesnotrequirewritestatusbits.The
stateofbits6,5,4,and0canbeusermodiedanddonotaectmemoryoperation.Allbitsinthestatus
registerarepre-setfromthefactorytothe“0”state.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SRWD Don’tCare Don’tCare Don’tCare BP1 BP0 WEL Don’tCare
Table 2.2 Status Register Bit Assignments
MR25H256canbeoperatedineitherSPIMode0(CPOL=0,CPHA=0)orSPIMode3(CPOL=1,CPHA=1).
Forbothmodes,inputsarecapturedontherisingedgeoftheclockanddataoutputsoccuronthefalling
edgeoftheclock.Whennotconveyingdata,SCKremainslowforMode0;whileinMode3,SCKishigh.The
memorydeterminesthemodeofoperation(Mode0orMode3)baseduponthestateoftheSCKwhenCS
falls.
AllmemorytransactionsstartwhenCSisbroughtlowtothememory.Therstbyteisacommandcode.De-
pendinguponthecommand,subsequentbytesofaddressareinput.Dataiseitherinputoroutput.There
isonlyonecommandperformedperCSactiveperiod.CSmustgoinactivebeforeanothercommandcan
beaccepted.Toensureproperpartoperationaccordingtospecications,itisnecessarytoterminateeach
accessbyraisingCSattheendofabyte(amultipleof8clockcyclesfromCSdropping)toavoidpartialor
abortedaccesses.
SPI COMMUNICATIONS PROTOCOL MR25H256
5MR25H256Rev.7,11/2011
EverspinTechnologies©2011
WEL SRWD WP Protected Blocks Unprotected Blocks Status
Register
0XXProtected Protected Protected
1 0 XProtected Writable Writable
1 1 Low Protected Writable Protected
1 1 High Protected Writable Writable
Table 2.4 Memory Protection Modes
Status Register Memory Contents
BP1 BP0 Protected Area Unprotected Area
0 0 None AllMemory
0 1 UpperQuarter LowerThree-Quarters
1 0 UpperHalf LowerHalf
1 1 All None
Table 2.3 Block Memory Write Protection
Read Status Register (RDSR)
TheReadStatusRegister(RDSR)commandallowstheStatusRegistertoberead.TheStatusRegistercan
bereadatanytimetocheckthestatusofwriteenablelatchbit,statusregisterwriteprotectbit,andblock
writeprotectbits.ForMR25H256,thewriteinprogressbit(bit0)isnotwrittenbythememorybecause
thereisnowritedelay.TheRDSRcommandisenteredbydrivingCSlow,sendingthecommandcode,and
thendrivingCShigh.
Figure 2.1 RDSR
SCK
SI
SO
CS
Status Register Out
High Impedance High Z
Mode 3
Mode 0
10 2 3 4 5 6 7 0 1 2 3 4 5 6 7
00000101
MSB
MSB
76543210
WhenWELisresetto0,writestoallblocksandthestatusregisterareprotected.WhenWELissetto1,
BP0andBP1determinewhichmemoryblocksareprotected.WhileSRWDisresetto0andWELissetto1,
statusregisterbitsBP0andBP1canbemodied.OnceSRWDissetto1,WPmustbehightomodifySRWD,
BP0andBP1.
SCK
SI
SO
CS
Instruction (04h)
High Impedance
Mode 3
Mode 0
Mode 3
Mode 0
10 234567
00000100
6MR25H256Rev.7,11/2011
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SPI COMMUNICATIONS PROTOCOL MR25H256
Write Status Register (WRSR)
TheWriteStatusRegister(WRSR)commandallowsnewvaluestobewrittentotheStatusRegister.The
WRSRcommandisnotexecutedunlesstheWriteEnableLatch(WEL)hasbeensetto1byexecutinga
WRENcommandwhilepinWPandbitSRWDcorrespondtovaluesthatmakethestatusregisterwritable
asseenintable2.4.StatusRegisterbitsarenon-volatilewiththeexceptionoftheWELwhichisresetto0
uponpowercycling.
Write Enable (WREN)
TheWriteEnable(WREN)commandsetstheWriteEnableLatch(WEL)bitinthestatusregisterto1.The
WELbitmustbesetpriortowritinginthestatusregisterorthememory.TheWRENcommandisentered
bydrivingCSlow,sendingthecommandcode,andthendrivingCShigh.
SCK
SI
SO
CS
Instruction (06h)
High Impedance
Mode 3
Mode 0
Mode 3
Mode 0
10 234567
00000110
Write Disable (WRDI)
TheWriteDisable(WRDI)commandresetstheWELbitinthestatusregisterto0.Thispreventswritesto
statusregisterormemory.TheWRDIcommandisenteredbydrivingCSlow,sendingthecommandcode,
andthendrivingCShigh.
TheWELbitisresetto0onpower-uporcompletionofWRDI.
Figure 2.3 WRDI
Figure 2.2 WREN
7MR25H256Rev.7,11/2011
EverspinTechnologies©2011
SPI COMMUNICATIONS PROTOCOL MR25H256
Figure 2.4 WRSR
SCK
SI
SO
CS
Status Register In
High Impedance
Mode 3
Mode 0
Instruction (01h)
0000000176543210
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TheWRSRcommandisenteredbydrivingCSlow,sendingthecommandcodeandstatusregisterwrite
databyte,andthendrivingCShigh.
Read Data Bytes (READ)
TheReadDataBytes(READ)commandallowsdatabytestobereadstartingatanaddressspeciedbythe
16-bitaddress.Onlyaddressbits0-14aredecodedbythememory.Thedatabytesarereadoutsequen-
tiallyfrommemoryuntilthereadoperationisterminatedbybringingCShighTheentirememorycanbe
readinasinglecommand.Theaddresscounterwillrolloverto0000hwhentheaddressreachesthetopof
memory.
TheREADcommandisenteredbydrivingCSlowandsendingthecommandcode.Thememorydrivesthe
readdatabytesontheSOpin.Readscontinueaslongasthememoryisclocked.Thecommandistermi-
natedbybringCShigh.
Figure 2.5 READ
SCK
SI
SO
CS
16-Bit Address
High Impedance
Instruction (03h)
Data Out 1 Data Out 2
00000011X 3
765432107
210
MSB
MSB
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
14 13
SPI COMMUNICATIONS PROTOCOL MR25H256
8MR25H256Rev.7,11/2011
EverspinTechnologies©2011
Write Data Bytes (WRITE)
TheWriteDataBytes(WRITE)commandallowsdatabytestobewrittenstartingatanaddressspeciedby
the16-bitaddress.Onlyaddressbits0-14aredecodedbythememory.Thedatabytesarewrittensequen-
tiallyinmemoryuntilthewriteoperationisterminatedbybringingCShigh.Theentirememorycanbe
writteninasinglecommand.Theaddresscounterwillrolloverto0000hwhentheaddressreachesthetop
ofmemory.
UnlikeEEPROMorFlashMemory,MRAMcanwritedatabytescontinuouslyatitsmaximumratedclock
speedwithoutwritedelaysordatapolling.BacktobackWRITEcommandstoanyrandomlocationinmem-
orycanbeexecutedwithoutwritedelay.MRAMisarandomaccessmemoryratherthanapage,sector,or
blockorganizedmemorymakingitidealforbothprogramanddatastorage.
TheWRITEcommandisenteredbydrivingCSlow,sendingthecommandcode,andthensequentialwrite
databytes.Writescontinueaslongasthememoryisclocked.ThecommandisterminatedbybringingCS
high.
Figure 2.6 WRITE
SCK
SI
SO
CS
16-Bit Address
High Impedance
Instruction (02h)
00000010X 321076543210
MSB MSB
012345678910 20 21 22 23 24 25 26 27 28 29 30 31
14 13
SCK
SI
SO
CS
Data Byte 3
High Impedance
Data Byte NData Byte 2
34 210 76543210
MSB
76543210765
MSB
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Mode 3
Mode 0
SPI COMMUNICATIONS PROTOCOL MR25H256
9MR25H256Rev.7,11/2011
EverspinTechnologies©2011
Enter Sleep Mode (SLEEP)
TheEnterSleepMode(SLEEP)commandturnsoallMRAMpowerregulatorsinordertoreducetheoverall
chipstandbypowerto3μAtypical.TheSLEEPcommandisenteredbydrivingCSlow,sendingthecom-
mandcode,andthendrivingCShigh.Thestandbycurrentisachievedaftertime,tDP
.Ifpowerisremoved
whenthepartisinsleepmode,uponpowerrestoration,thepartentersnormalstandby.Theonlyvalid
commandfollowingSLEEPmodeentryisaWAKEcommand.
Exit Sleep Mode (WAKE)
TheExitSleepMode(WAKE)commandturnsoninternalMRAMpowerregulatorstoallownormaloperation.
TheWAKEcommandisenteredbydrivingCSlow,sendingthecommandcode,andthendrivingCShigh.
ThememoryreturnstostandbymodeaftertRDP
.TheCSpinmustremainhighuntilthetRDPperiodisover.
Figure 2.7 SLEEP
Figure 2.8 WAKE
SCK
SI
SO
CS
Standby CurrentActive Current
Mode 3
Mode 0
Sleep Mode Current
Instruction (B9h)
10111001
01234567
DP
t
SCK
SI
SO
CS
Sleep Mode Current
Mode 3
Mode 0
Standby Current
Instruction (ABh)
10101 011
01234567
RDP
t
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Thisdevicecontainscircuitrytoprotecttheinputsagainstdamagecausedbyhighstaticvoltagesor
electricelds;however,itisadvisedthatnormalprecautionsbetakentoavoidapplicationofanyvoltage
greaterthanmaximumratedvoltagestothesehigh-impedance(Hi-Z)circuits.
Thedevicealsocontainsprotectionagainstexternalmagneticelds.Precautionsshouldbetakentoavoid
applicationofanymagneticeldmoreintensethantheeldintensityspeciedinthemaximumratings.
10
Parameter Symbol Value Unit
Supplyvoltage2VDD -0.5to4.0 V
Voltageonanypin2VIN -0.5toVDD+0.5 V
Outputcurrentperpin IOUT ±20 mA
Packagepowerdissipation3PD0.600 W
Temperatureunderbias
MR25H256C(Industrial) TBIAS -45to95 °C
Temperatureunderbias
MR25H256M(AEC-Q100Grade1) TBIAS -45to135 °C
StorageTemperature Tstg -55to150 °C
Leadtemperatureduringsolder(3minutemax) TLead 260 °C
Maximummagneticeldduringwrite Hmax_write 12,000 A/m
Maximummagneticeldduringreadorstandby Hmax_read 12,000 A/m
1Permanentdevicedamagemayoccurifabsolutemaximumratingsareexceeded.Functionalopera-
tionshouldberestrictedtorecommendedoperatingconditions.Exposuretoexcessivevoltagesor
magneticeldscouldaectdevicereliability.
2AllvoltagesarereferencedtoVSS.TheDCvalueofVINmustnotexceedactualappliedVDDbymore
than0.5V.TheACvalueofVINmustnotexceedappliedVDDbymorethan2Vfor10nswithIINlimited
tolessthan20mA.
3 Powerdissipationcapabilitydependsonpackagecharacteristicsanduseenvironment.
Table 3.1 Absolute Maximum Ratings1
MR25H256
MR25H256Rev.7,11/2011
EverspinTechnologies©2011
11
Parameter Symbol Min Typical Max Unit
Powersupplyvoltage VDD 2.7 3.6 V
Powersupplyvoltage(AEC-Q100
Grade1) VDD 3.0 3.6 V
Inputhighvoltage VIH 2.2 - VDD+0.3 V
Inputlowvoltage VIL -0.5 - 0.8 V
Temperatureunderbias
MR25H256C(Industrial) TA-40 - 85 °C
Temperatureunderbias
MR25H256M(AEC-Q100Grade1)1TA-40 - 125 °C
1AEC-Q100Grade1temperatureprofileassumes10percentdutycycleatmaximumtemperature(2years
outof20-yearlife.)
Table 3.2 Operating Conditions
MR25H256
ELECTRICAL SPECIFICATIONS
EverspinTechnologies©2011 MR25H256Rev.7,11/2011
Parameter Symbol Min Typical Max Unit
Inputleakagecurrent ILI - - ±1 μA
Outputleakagecurrent ILO - - ±1 μA
Outputlowvoltage
(IOL=+4mA)
(IOL=+100μA)
VOL --0.4
VSS+0.2v
V
Outputhighvoltage
(IOH=-4mA)
(IOH=-100μA)
VOH 2.4
VDD-0.2
- - V
Table 3.3 DC Characteristics
Table 3.4 Power Supply Characteristics
Parameter Symbol Typical Max Unit
ActiveReadCurrent(@1MHz) IDDR 2.5 3 mA
ActiveReadCurrent(@40MHz) IDDR 6 10 mA
ActiveWriteCurrent(@1MHz) IDDW 8 13 mA
ActiveWriteCurrent(@40MHz) IDDW 23 27 mA
StandbyCurrent(CSHigh)1ISB 90 115 μA
StandbySleepModeCurrent(CSHigh) IZZ 7 30 μA
1ISBcurrentisspeciedwithCShighandtheSPIbusinactive.
12
MR25H256
4. TIMING SPECIFICATIONS
Table 4.1 Capacitance1
Parameter Symbol Typical Max Unit
Controlinputcapacitance CIn - 6 pF
Input/Outputcapacitance CI/O - 8 pF
1 ƒ=1.0MHz,dV=3.0V,TA=25°C,periodicallysampledratherthan100%tested.
Table 4.2 AC Measurement Conditions
Figure 4.1 Output Load for Impedance Parameter Measurements
Figure 4.2 Output Load for all Other Parameter Measurements
Parameter Value Unit
Logicinputtimingmeasurementreferencelevel 1.5 V
Logicoutputtimingmeasurementreferencelevel 1.5 V
Logicinputpulselevels 0or3.0 V
Inputrise/falltime 2 ns
Outputloadforlowandhighimpedanceparameters SeeFigure4.1
Outputloadforallothertimingparameters SeeFigure4.2
V
Output
L= 1.5 V
RL= 50 Ω
ZD= 50 Ω
Output
435 Ω
590 Ω
30 pF
3.3 V
EverspinTechnologies©2011 MR25H256Rev.7,11/2011
13
MR25H256
TIMING SPECIFICATIONS
EverspinTechnologies©2011 MR25H256Rev.7,11/2011
Power-Up Timing
TheMR25H256isnotaccessibleforastart-uptime,tPU=400μsafterpowerup.Usersmustwaitthistime
fromthetimewhenVDD(min)isreacheduntiltherstCSlowtoallowinternalvoltagereferencestobecome
stable.TheCSsignalshouldbepulleduptoVDDsothatthesignaltracksthepowersupplyduringpower-up
sequence.
Parameter Symbol Min Typical Max Unit
WriteInhibitVoltage VWI 2.2 - 2.7 V
StartupTime tPU - - 400 μs
Table 4.3 Power-Up
VDD
VDD
V
(max)
VDD(min)
WI
tPU
Time
Normal Operation
Chip Selection not allowed
Reset state
of the
device
Figure 4.3 Power-Up Timing
MR25H256
TIMING SPECIFICATIONS
Parameter Symbol Min Typical Max Unit
SCKClockFrequency fSCK 0 - 40 MHz
InputRiseTime tRI - - 50 ns
InputFallTimetRF - - 50 ns
SCKHighTime tWH 11 - - ns
SCKLowTime tWL 11 - - ns
SynchronousDataTiming(Seegure4.4)
CSHighTime tCS 40 - - ns
CSSetupTimetCSS 10 - - ns
CSHoldTimetCSH 10 - - ns
DataInSetupTimetSU 5 - - ns
DataInHoldTime tH 5 - - ns
OutputValid(IndustrialTemp,VDD2.7v
Min.) tV 0 - 10 ns
OutputValid(IndustrialTemp,VDD3.0v
min.) tV09ns
OutputValid(AEC-Q100Grade1,VDD3.0v
min.) tV0 10 ns
OutputHoldTime tHO 0 - - ns
HOLDTiming(Seegure4.5)
HOLDSetupTime tHD 10 - - ns
HOLDHoldTime tCD 10 - - ns
HOLDtoOutputLowImpedance tLZ - - 20 ns
HOLDtoOutputHighImpedance tHZ - - 20 ns
OtherTimingSpecications
WPSetupToCSLow tWPS 5 - - ns
WPHoldFromCSHigh tWPH 5 - - ns
SleepModeEntryTime tDP 3 - - μs
SleepModeExitTime tRDP 400 - - μs
OutputDisableTime tDIS 12 - - ns
1CL=30pF
Table 4.4 AC Timing Parameters1
Synchronous Data Timing
14EverspinTechnologies©2011 MR25H256Rev.7,11/2011
MR25H256
TIMING SPECIFICATIONS
15EverspinTechnologies©2011 MR25H256Rev.7,11/2011
Figure 4.5 HOLD Timing
SCK
SO
CS
HOLD
HD
t
HZ
t
HD
t
CD
tCD
t
LZ
t
Figure 4.4 Synchronous Data Timing
SCK
SI
SO
CS
High Impedance
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
CSS
t
SU
tH
t
V
t
WH
tWL
t
CSH
t
CS
t
HO
tDIS
t
MR25H256Rev.7,11/201116
MR25H256
5. ORDERING INFORMATION
Figure 5.1 Part Numbering System
Package Options
DC 8 Pin DFN on Tray
DCR
DF
DFR
8 Pin DFN on Tape and Reel
8 pin DFN Small Flag on Tray
8 pin DFN Small Flag on Tape and Reel
Temperature Range
C-40 to +85 °C ambient (Industrial)
M-40 +125 °C ambient (AEC-Q100 Grade 1)
Memory Density
256 256Kb
Interface
25H High Speed Serial SPI Family
Product Type
MR Magnetoresistive RAM
MR 25H 256 C DC
Part Number Description Temperature
MR25H256CDC 3V256KbSerialMRAM8-DFNIndustrial -40to+85C
MR25H256CDCR 3V256KbSerialMRAM8-DFNIndustrialT&R -40to+85C
MR25H256MDC13V256KbSerialMRAM8-DFNAEC-Q100Grade1 -40to+125C
MR25H256MDCR13V256KbSerialMRAM8-DFNAEC-Q100Grade1T&R -40to+125C
MR25H256CDF 3V256KbSerialMRAM8-DFNSmallFlagIndustrial -40to+85C
MR25H256CDFR 3V256KbSerialMRAM8-DFNSmallFlagIndustrialT&R -40to+85C
MR25H256MDF13V256KbSerialMRAM8-DFNSmallFlagAEC-Q100
Grade1 -40to+125C
MR25H256MDFR13V256KbSerialMRAM8-DFNSmallFlagAEC-Q100
Grade1T&R -40to+125C
1PreliminaryProducts:TheseproductsareclassiedasPreliminaryuntilthecompletionofallqualicationtests.Thespeci-
cationsinthisdatasheetareintendedtobenalbutaresubjecttochange.PleasechecktheEverspinwebsitewww.
everspin.comforthelatestinformationonproductstatus.
Table 5.1 Available Parts
EverspinTechnologies©2011
NOTE:
1. Alldimensionsareinmm.Anglesindegrees.
2. Coplanarityappliestotheexposedpadaswellastheterminals.Coplanarityshallbe
within0.08mm.
3. Warpageshallnotexceed0.10mm.
4. RefertoJEDECMO-229
6. MECHANICAL DRAWINGS
MR25H256Rev.7,11/201117
Figure 6.1 DFN Package
MR25H256
EverspinTechnologies©2011
ExposedmetalPad.Donot
connectanythingexceptVSS
Dimension A B C D E F G H I J K L M N
Max.
Min.
5.10
4.90
6.10
5.90
1.00
0.90
1.27
BSC
0.45
0.35
0.05
0.00
0.35
Ref.
0.70
0.50
4.20
4.00
4.20
4.00
0.261
0.195 C0.35 R0.20 0.05
0.00
A
D
B
C
G
K
N
H
DAP Size
4.4 x 4.4
L
M
E
F1
4
58
J
I
Detail A
Detail A
Pin 1 Index
NOTE:
1. Alldimensionsareinmm.Anglesindegrees.
2. Coplanarityappliestotheexposedpadaswellastheterminals.Coplanarityshallbe
within0.08mm.
3. Warpageshallnotexceed0.10mm.
4. RefertoJEDECMO-229
6. MECHANICAL DRAWINGS
MR25H256Rev.7,11/201118
Figure 6.2 DFN Small Flag Package
MR25H256
EverspinTechnologies©2011
ExposedmetalPad.Donotcon-
nectanythingexceptVSS
Dimension A B C D E F G H I J K L M N
Max
Min
5.10
4.90
6.10
5.90
0.90
0.80 1.27BSC 0.45
0.35
0.05
0.00
1.60
1.20
0.70
0.50
2.10
1.90
2.10
1.90
.210
.196 C0.45 R0.20 0.05
0.00
A
D
B
C
G
KN
H
L
M
E
F1
4
5
J
I
Detail A
Detail A
Pin 1 Index
0.10 C2X
0.10 C2X
8
MR25H256
MR25H256Rev.7,11/2011
19
Revision Date Description of Change
1 Jan15,2010 PreliminaryInformationRelease
2 Apr8,2010 CorrectedREADandWRITEaddressingfrom24-bitto15-bit.Removedcommercialoption.
3 Mar3,2011 ClariedlanguageonstatusregisterWELbit.Removedautomotiveoptiontoseperatedata-
sheet.
4 May14,2011
Datasheetreleasedtoproduction.Correctedvarioustypos.Clariedblockandstatusregis-
terprotectiondescription.SpeciedmaximumPowerSupplyCharacteristicsforproduction
parts.
5 Aug11,2011 RevisedPowerSupplySpecicationTable3.4
6 Sept1,2011 AddedAECQ100Grade1orderingoption.RevisedTable3.1,Table3.2,Table4.4Note2,
Figure5.1andTable5.1.
7November18,
2011
CorrectedVOLinTable3.3toreadVOLMax=VSS+0.2v.OperatingConditionsPowerSupply
VoltageforAEC-Q100Grade1revisedto3.0-3.6v.Table4.4:OutputValidtVspecications
revisedtoincludeVDDrangesforIndustrialandAEC-Q100Grade1options.CorrectedSI
waveforminFigure2.8.NewSmallFlagDFNpackageoptionaddedtoPage1Featuresand
availablepartsTable5.1.DFNSmallFlagdrawinganddimensionstableaddedasFigure6.2.
Figure6.1,DFNPackage,cleanedupwithbetterqualitydrawinganddimensiontable.
7. REVISION HISTORY
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©Everspin Technologies, Inc. 2011
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