PRODUCT PART NUMBER DESCRIPTION APPLICATION FEATURES 256 x 16 bit Electrically Erasable Programmable Rom BR9040/F FV/RFEVRFVMW The BR9$040-W series are serial EEPROMs that can be connected directly to a serial port and can be erased and written electrically. Writing and reading is perfomed in word units, using four types of operation commands. Communication occurs through CS, SK, DI, and DO pins, WC pin control is used to initiate a write disabled state, enabling these EEPROMs to be used as one-time ROMs. During General Purpose 256words x 16 bit organization 4kbit serial EEPROM * Single power supply "Serial data [/O "Self-timed programming cycle with auto-erase Low supply current . Active (5V); 2mA (max.) : Standby (5V);_ 3uA (max.) (CMOS INPUT) "Noise filter on the SK pin Write protection when the supply is low "Space Saving DIP8/SOP8/SSOP8/MSOP8pin Packages High reliability CMOS process 100,000 erase/write cycles endurance "Provide 10 years of data retention "Easy connection to serial port "FFFFh stored in all address on shipped ABSOLUTE MAXIMUM RATINGS(Ta=25C) Parameter Symbol Rating Unit Supply Voltage VCC -0.3~7.0 Vv DIP8 80003 1) ee ; SOP8 450(342) Power dissipation Pd SSOPBB 30003) mw - MSOP8 310(%4) Storage Temperature Tstg 65~125 Cc Operating Temperature Topr 40~85 c Terminal Voitage - 0. 3~Vect0O. 3 Vv 1 Degradation is done at 8.0mW/C for operation above Ta=25C %<2 Degradation is done at 4.5mW/C for operation above Ta=25C %3 Degradation is done at 3.0mW/C for operation above Ta=25C 4 Degradation is done at 3.1mW/*C for operation above Ta=25C RECOMMENDED OPERATING CONDITION Parameter Symbol Rating Unit 2. 7~5. S(WRITE) Supply Voltage VoC 2. 7~5. S(READ) Vv Input Voltage Vin Oo ~ VCCOELECTRICAL CHARACTERISTICS Unless otherwise specified(Ta= 40~85C, VCC=2. 7~5, 5V) Limit . Test Parameter Symbol Min. Typ. Max Unit Condition Circuit 0.3x 1 _ _ . Input Low Voltage VIL1 VOC Vv DI Pin 0.7x . ' 1 _ _ . Input High Voltage VIH1 VCC Vv Di Pin Input Low Voltage 2 VIL2 - - 0.2x v_ | CS, SK, WG Pin p ie vec . . 0.8x =o Input High Voltage 2 ViH2 - - V CS, SK, WC Pin vcc Output Low Voltage VOL 0 - 0.4 Vv IOL=2.1mA Fig.4 . CC- . Output High Voltage VOH 04 - Vcc Vv IOH=-0.4mA Fig -5 Input Leakage Current ILI -1 - 1 HA | VIN-OV~VCC Fig.-8 Output Leakage Current | ILO -{ - 1 uA | VOUT=0V~VCC,CS =VCC Fig-7 Icci _ _ 2 mA | fSK=2MHz,tE/W=10ms (WRITE) | Fig.-8 Operating Current Icc2 _ _ 1 mA_ | fSK=2MHz (READ) Fig.-8 CS,SKDLWG=VCC Standby Currant ISB 3 HA DO.R/B=OPEN Fig.-9 Clock Frequency fSK _ _ 2 MHzUnless otherwise specified (Ta=40~85C, VCC=2. 7~3. 3V) Limit \ Test Parameter Symbo! Min, Typ. Max. Unit Condition Circuit Input Low Voltage 1 VILI - - van Vv DI Pin Input High Voitage 1 VIH1 ving _ _ V DI Pin 0.2x a OU Input Low Voltage 2 VIL2 _ - V CS, SK, WC Pin Voc . 0.8x =x Input High Voltage 2 VIH2 _ - V CS, SK, WC Pin vcc Output Low Voltage VOL 0 _- 0.4 Vv IOL=100uA Fig.-4 . vcc- . Output High Voltage VOH 04 - VCC Vv IOH=-100uA Fig.-5 Input Leakage Current ILI -1 _ 1 HA | VIN=O0~VCC Fig.-6 Output Leakage Current ILO -1 1 LA VOUT=0~VCC,CS=VCC Fig.-7 Ic1 - - 1.5 mA | fSK =2MHz,tE/ W=10ms (WRITE) | Fig.-8 Operating Current Icc2 - - 0.5 mA | fSK =2MHz (READ) Fig.-8 CS,SK,DLWC=VCC Standby Current ISB 2 HA DO.R/B=OPEN Fig.-9 Clack Frequency fSK _- - 2 MHz OThis product is not designed for protection against radioactive rays.DIMENSION 6.5 + 0.3 Sel 3240.2 3.4403 Fig.1-1 Outline Dimensions DIP&(BR9040-W)6.2+0.3_ 1.5+0.1 Fig.t-2 Outline Dimensions SOP8(BR9040F-W)oO oO He No yy a = |.0.3Min. mh, on IF 0.1 8 COP ayn db oO|o +|| HI +) I} iio Ls | 1 4 Cl ferre +1) = IOS f/ 0.52)|| |0.65 0.22 + 0.1 Fig.1-3 Outline Dimensions SSOPB&(BR9040RFV-W)6.4+0.3 3. oO 8 8 aL. 1 4 panne + 0.2 ro bh | 0. || 0.3Min. Lo] 0.1 ae 1.1540.1 (0.52)|| Fig.t-4 Outline Dimensions SSOPBS&(BR9040FV-W) 0.22 + 0.1 0.65 +Ww _ 8 5 oO Ay !pgng +) 2 +H} + Oo A oO; @ [O o pi eeee =F 0.475) |, 0.145 *8:83 oO = oO? | S lle THEY 0.00 +8-95/5 0.080 | 6 A cranes Fig.1-5 Outline Dimensions MSOP&(BR9I040RFVM-W)> RB < DETECT _ INSTRUCTION DECODE SUPPLY CS } CONTROL AND CLOCK VOLTAGE GENERATION HIGH _ WRITE | VOLTAGE Wo SK > DISABLE 7| GENERATOR | +>) ADDRESS _{ appress 1 DI INSTRUCTION BUFFER L-Bbit) pecorDER [2H REGISTER 4,096bit EEPROM Ls} DATA aN R/W i REGISTER (i ) AMPS (mE) po < Fig.-2 Block DiagramPIN CONFIGURATIONS VCC R/B WC GND WC GND DO ODI Tard ar) ee 1 O LJILIL IT) LJILICLItTI cs SK DI DO R/B VCC CS SK BRS040W:DIP8 TERMINAL FUNCTION BR9O40FVW:SSOP8 BR9OO40F-W:SOP8 Fig3 Pin Configurations VCC R/B WC GND a Oo LIL cS SK ODI DO BRSO40RFVMW:MSOP8 BRSO40RFVW:SSOP8 Terminal IN/OUT Function VCGG - Power Supply GND Ground (0V) cs INPUT Chip Select Input sk INPUT Serial Data Clock Input DI INPUT Serial Data Input (Op code, address) DO OUTPUT Serial Data Output WG INPUT Write Control Input R/ B OUTPUT READY / BUSY Status OutputOTEST CIRCUIT Voc Voc GND DO TOL VOL Set Output Pin to Low Fig-4 Output Low voltage test circuit voc / vec GND R/B.DO VIN-OV~VCC 1 IOH VOH Set Output Pin to High Fig.-5 Output High voltage test circuit ILI VCG ; Vcc CS,SK,DEWC GND Fig.-6 Input leakage current test circuitTEST CIRCUIT vcc vce voc iLO cs DO GND | voormver Fig~7 Output leakage current test circuit vcc icc SK Clock SK vec READ/WRITE COMMAND Input DI R/BDO OPEN vil jCS_anD Fig.-8 Operating Current test circuit vcc cc oe ISB vec SK voc WC | DI R/B,DO OPEN cs GND Fig.-9 Standby current test circuitINSTRUCTION CODE Instruction Start Bit . Op Code Address Data DO D1 - B14 D15 READ 1010 1000 AO Al A2 A3 A4 A5 AG A? (READ DATA) DO D1 - Di4 DIS WRITE 1010 0100 AO Al A2 A3 A4 Ad A6 A7 (WRITE DATA) Write Enable(WEN) 1010 0011 * * * * oF OK OK Write Disable(WDS) 1010 0000 koe Ok Ok ok ok Ok Address and data must be transferred from LSB. * Means either VIH or VIL OSYNCHRONOUS DATA INPUT OUTPUT TIMING cs tPD > PD <> tOH | 6 _X ! > we f \ Fig~10 Synchronous data input output timing Olnput Data is clocked into the DI pin on the rising edge of the clock SK. Ooutput | data is clocked out on the falling edge of the SK clock. OThe WC pin does not have any affect on the READ, WEN and WDS operations. OBetween instructions, CS must be brought High for greater than the minimum of tCS. If CS is maintained Low, the next instruction isnt detected.AG OPERATION CHARACTERISTICS (Ta=40~85C, VCC=2. 7~5. 5V) Parameter . Symbol Min. Typ. Max. Unit Chip Select Setup Time | tCSS 100 - - ns Chip Select Hold Time tCSH 100 _ - ns Data In Setup Time | . tDIS 100 | - | | ns Data In Hold Time tDIH 100 _ _ ns Delay to Output High tPD1 _ - 150 ns Delay to Output Low , tPDO _. - 150 ns Self-Timed Program Cycle tE/W - - 10 ms Minimum Chip Select High Time tcs 250 - _- ns Data Output Disable Time (From CS) tOH ') - 150 ns Clock High Time twH | 230 | | | ns Clock Low Time tWL 230 _ _ ns Write Control Setup Time twos 0 _ - ns Write Control Hold Time | tWCH 0 7 _ ns Clock High to Output READY /BUSY Status tSV - | 150 | nsTIMING CHART 1, WRITE Enable/Disable _ oH L . /| ENABLE =11 os 4 \ DISABLE = 0 0 | L Fig.-11 WRITE Enable and Disable Cycle Timing OWhen power is first applied, the device has been held in a reset status, with respect to the write enable, in the same way the write disable (WDS) instruction is executed. Before the write instruction is executed, the device must be received the write enable (WEN) instruction. Once the device is done, the device remains programmable until the write disable (WDS) instruction is executed or the supply is removed from the device. Olt is unnecessary to add the clock after 16th clock. If the device is recieved the clock, the device ignores the clock. OAs both of the enable and disable instructions don't depend on the status of the WC pin, the state of WC isn't cared during the instruction. OThe instruction is recognized after the rising edge of 8th clock for the address following 8clocks for the opcode, but the specified address isn't cared during the instructions.2. READ INSTRUCTION | H iH SK | | | | Fd | | I le] | | | 16 | | be | | L H cs \ u H DI HT s\ofs\ofs\ 0 0 0 [rok XasYas Yar) OL ven Kv Hi-Z a - tL DO Do 3) W i tOH RB oH . Read Data(n) Read Data(n+1) L Nf STANDBY a oS a Fig.-12 READ Cycle Timing OOn the falling edge of 16th clock, the data stored in the specified address (n) is clocked out of the DO pin. __. The output DO is toggled after the internal propagation tPDO or tPD1 on the falling edge of SK. During tPDO or tPD1, the data is the previous data or unstable, and to take in the data, tPD is needed. (Refer to Fig-10 Synchronous data input output timing.) OThe data stored in the next address is clocked out of the device on the falling edge of 32nd clock. The data stored in the upper address every 16 clocks is output sequentially by the continual SK input. Also the read operation is reset by CS High.3. WRITE INSTRUCTION H "LULA L i H cs - 7 7 I L : . YW V TY H ) DI HH 1 0 1 0 6@ 1 0 0 / 0) \ (as a6 KA? X DO} D5 " Hi-Z 4 HiZ BO y iv N 4 tSV pit ste Ww RB H {+ i Vy veel > <8 A pit tWCH we I . es TT Fig.-13 WRITE Cycle Timing During the write instruction, CS must be brought Low. However once the write operation started, CS may be either High or Low. But in the case of connecting the WC pin to the CS pin, CS. and WC must be brought Low during programming cycle. (if the WC pin is brought High during the write cycle, the write operation is halted. In that case, the data of the specified address is not guaranteed. It is necessary to rewrite it.) OAfter the R/B pin changed Busy to Ready, once CS is brought High, then Cs keep Low, which means the status of being able to accept an instruction. The device can take in the input from SK and DI, but in the case of keeping CS Low without being brought High once, the input is canceled until being CS High once. OAt the rising edge of 32nd clock, the R/B pin will be driven Low after the specified time delay(tSV). ODuring programming, R/B is tied to Low by the device (On the rising edge of SK taken in the last data (D15), internal timer starts and automatically finished after the data of memory cell is written spending tE/W. SK could be either High or Low at the time. OAfter r input write instruction, also the DO 10 pin will be able to show the status of s of R/B, in the case that CS is falling from High to Low while SK is tied to Low. {Refer to READY/BUSY STATUS in the next page.)READY/BUSY STATUS (on the R/B pin, the DO pin) The DO pin outputs the READY/BUSY status of the internal part, which shows whether the device is ready to receive the next instruction or not. (High or Low) _ After the write instruction is completed, if CS is brought from high to Jow while SK is Low, the DO pin outputs the internal status.(The R/ B pin may be no connection.) When written to the memory cell, R/B status is output after tSV spent from the rising edge of 32th clock on SK. R/B =Low : under writing After spending tE/W operating the internal timer, the device automatically finishes writing. During tE/W, the memory array is accessed and any instruction is not received. R/B =High : ready Auto programming has been completed. The device is ready to receive the next Instruction. SO sk \ CLOCK | \ [ ms MMMM \ wor Fig.-14 READY/BUSY Status Output timing About the direct connection between the DI and DO pins The device can be used with the DI pin connected to the DO pin directly. But when the READY/BUSY status is output, be careful about the bus conflict on the port of the controller.@MATTENTION TO USE 1. Power ON/OFF The CS is brought High during power-up and power-down. "This device is in active state while CS is Low. "The extraordinary function or data collapse may occur in that condition because of noise etc., if power-up and power-down is done with CS brought Low. In order to prevent above errors from happening, keep CS High during power-up and power-down. (Good example) CS is brought High during power-up and power-down, Please take more than 10ms between power-up and power-off, or the internal circuit is not always reset. (Bad example )CS is brought Low during power-up and power-down. The CS pin is always Low in this case, the noise may force the device to make malfunction or inadvertent write. __ * It sometimes occurs in the case that the CS pin is Hi-Z. voc frm mm nnn nnn ann n cece nnn nnnnnnnnnannas vee Qo GND nnn nnn nn mn mmm nn em mm mm mm me mmm ee ea me Vcc a _ I I I I I I I I GND 4 Good 2. NOISE REJECTION 21 SK NOISE If SK line has a fot of noise for rising time of SK, the device may recognize the noise as a clock and then clock will be shifted, 2-2 WC NOISE If WC line has noise during write cycle(tE/W), there may be a chance to deny the programming. , 2-3 VCC NOISE ft recommended that capacitor is put between VCC and GND to prevent these case, since it is possible to occur malfunction by the effect of noise or surge on power line.<3. INSTRUCTION MODE CANCEL 31. READ instruction It is possible to be canceled for any timing. { ! ' cs _ \ if i ' ( t i i} | | SK 32clocks | ! | DI | | startet | opcove | aporess | 1 l \ 4bit 4bit Sbit 16bit | ' 1 on ! ot y-- DO << bo DATA (D5 7 WC How to cancel : CS is brought High. 3-2. Write instruction cs ! a { \ 1 1 i 1 SK \ | 32elocks | 1 ; 1 T * F DI | start ert | oPcopE ADDRESS | DO | DATA ' pis | ' T ! bit Abit Bbit 1Bbit =~ R/B ' 7 i i " i =| oO -- 4 _ ! ' 1 1 1 1 o ' ' ! ! ! I I I vv A ' ! ! ! ! J a 4 x t I ft 1 t I I E t F | I a ( ! ke ~ How to cancel a : CSis brought High to cancel the instruction, and WC may be either High or Low. b : Incase that WC is brought High for a moment, or CS ts brought High, the write instruction is canceled, the data of the specified address is not changed. c : When WC is brought High, or the device is powered down (But the latter way is not recommended), the instruction is canceled but the specified data is not guaranteed. Send the instruction again. d=: When GS is brought High during R/ B High, the device is reset and ready to receive a next instruction. NOTE : The document may be strategic technical data subject to COCGOM regulations.