LM4937 Audio Sub-System with OCL Stereo Headphone Output and RF Suppression General Description Key Specifications The LM4937 is an integrated audio sub-system designed for mono voice, stereo music cell phones connecting to base band processors with mono differential analog voice paths. Operating on a 3.3V supply, it combines a mono speaker amplifier delivering 520mW into an 8 load, a stereo headphone amplifier delivering 36mW per channel into a 32 load, and a mono earpiece amplifier delivering 55mW into a 32 load. It integrates the audio amplifiers, volume control, mixer, and power management control all into a single package. In addition, the LM4937 routes and mixes the single-ended stereo and differential mono inputs into multiple distinct output modes. The LM4937 features an I2S serial interface for full range audio and an I2C or SPI compatible interface for control. The full range music path features an SNR of 85dB with a 192kHz playback. Boomer audio power amplifiers are designed specifically to provide high quality output power with a minimal amount of external components. POUT, BTL, 8, 3.3V, 1% 520mW (typ) POUT H/P, 32, 3.3V, 1% 36mW (typ) POUT Mono Earpiece, 32, 1% 55mW (typ) Shutdown current 0.6A (typ) SNR (DAC + Amplifier) 85dB (typ) Features 18-bit stereo DAC Multiple distinct output modes Mono speaker amplifier Stereo headphone amplifier Mono earpiece amplifier Differential mono analog input Independent loudspeaker, headphone and mono earpiece volume controls I2C/SPI (selectable) compatible interface Ultra low shutdown current Click and Pop Suppression circuit Applications Cell Phones PDAs Boomer(R) is a registered trademark of National Semiconductor Corporation. (c) 2007 National Semiconductor Corporation 202020 www.national.com LM4937 Audio Sub-System with OCL Stereo Headphone Output and RF Suppression November 1, 2007 LM4937 Block Diagram 20202001 FIGURE 1. Audio Sub-System Block Diagram with OCL HP Outputs (HP outputs may also be configured as cap-coupled) www.national.com 2 LM4937 Connection Diagrams 36 - Bump Micro SMD 36 - Bump Micro SMD Top Marking Drawing 20202058 20202002 Top View (Bump Side Down) Order Number LM4937TL See NS Package Number TLA36LVA Top View XY -- 2 Digit Date Code TT -- Die Traceability G -- Boomer Family I1 -- LM4937TL 36 - Bump Micro SMD 36 - Bump Micro SMD Top Marking Drawing 20202058 20202031 Top View (Bump Side Down) Order Number LM4937RL See NS Package Number RLA36LVA Top View XY -- 2 Digit Date Code TT -- Die Traceability G -- Boomer Family J3 -- LM4937RL 3 www.national.com LM4937 Pin Descriptions Pin Pin Name Digital/ Analog I/O, Power Description A1 DGND D P DIGITAL GND A2 MCLK D I MASTER CLOCK A3 I2S_WS D I/O I2S WORD SELECT A4 SDA/SDI D I/O I2C SDA OR SPI SDI A5 DVDD D P DIGITAL SUPPLY VOLTAGE A6 VDD_IO D P I/O SUPPLY VOLTAGE B1 PLL_VDD D P PLL SUPPLY VOLTAGE B2 I2S_SDATA D I I2S SERIAL DATA INPUT B3 I2S_CLK D I/O I2S CLOCK SIGNAL B4 GPIO D O TEST PIN (MUST BE LEFT FLOATING) B5 I2C_VDD D P I2C SUPPLY VOLTAGE B6 SDL/SCK D I I2C_SCL OR SPI_SCK C1 PLL_GND D P PLL GND C2 PLL_OUT D O PLL FILTER OUTPUT C3 PLL_IN D I PLL FILTER INPUT C4 ADDR/ENB D I I2C ADDRESS OR SPI ENB DEPENDING ON MODE C5 BYPASS A I HALF-SUPPLY BYPASS C6 AVDD A P ANALOG SUPPLY VOLTAGE D1 AGND A P ANALOG GND D2 AGND A P D3 NC D4 MODE D I D5 RHP A O RIGHT HEADPHONE OUTPUT D6 CHP A O HEADPHONE CENTER PIN OUTPUT (1/2 VDD or GND) E1 DIFF_ A I ANALOG NEGATIVE DIFFERENTIAL INPUT E2 LIN A I ANALOG LEFT CHANNEL INPUT E3 RIN A I ANALOG RIGHT CHANNEL INPUT LEFT HEADPHONE OUTPUT ANALOG GND NO CONNECT SELECTS BETWEEN I2C OR SPI CONTROL E4 NC E5 LHP A O E6 AGND A P ANALOG GND F1 DIFF+ A I ANALOG POSITIVE DIFFERENTIAL INPUT F2 EP_ A O MONO EARPIECE- F3 EP+ A O MONO EARPIECE+ F4 LS- A O LOUDSPEAKER OUT- F5 AVDD A P ANALOG SUPPLY VOLTAGE F6 LS+ A O LOUD SPEAKER OUT+ www.national.com NO CONNECT 4 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage Digital Supply Voltage Storage Temperature Input Voltage Power Dissipation (Note 3) ESD Susceptibility (Note 4) ESD Susceptibility (Note 5) Junction Temperature Thermal Resistance 100C/W Operating Ratings Temperature Range 6.0V 6.0V -65C to +150C -0.3V to VDD +0.3V Internally Limited 2000V 200V 150C TMIN TA TMAX Supply Voltage -40C TA +85C 2.7V AVDD 5.5V 2.7V DVDD 4.0V 1.7V I2CVDD 4.0V 1.7V VDD_IO 4.0V Audio Amplifier Electrical Characteristics AVDD = 3.0V, DVDD = 3.0V (Notes 1, 2) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4937 Typical Limits (Note 6) (Notes 7, 8) IDD Supply Current VIN = 0, No Load All Amps On + DAC, OCL (Note 11) 14 19 mA (max) Headphone Mode Only, OCL 4.6 6.25 mA (max) 7 11.5 mA (max) 3.7 3.3 5 mA (max) mA Mono Loudspeaker Mode Only (Note 11) Mono Earpiece Speaker Mode Only D_6 = 0 (register 01h) D_6 = 1 DAC Off, All Amps On (OCL) (Note 11) ISD Shutdown Current PO Output Power VFS DAC Full Scale DAC Output 10 15.5 mA (max) 0.6 2 A (max) Speaker; THD = 1%; f = 1kHz, 8 BTL 420 370 mW (min) Headphone; THD = 1%; f = 1kHz, 32 SE 27 24 mW (min) 45 40 mW (min) Earpiece; THD = 1%; f = 1kHz, 32 BTL Speaker; PO = 200mW; f = 1kHz, 8 BTL THD+N Total Harmonic Distortion Headphone; PO = 10mW; f = 1kHz, 32 SE Earpiece; PO = 20mW; f = 1kHz, 32 BTL VOS Offset Voltage O Output Noise PSRR Power Supply Rejection Ratio Units (Limits) 2.4 Vpp 0.04 % 0.01 % 0.04 % Speaker 10 55 mV (max) Earpiece 8 50 mV (max) Headphone (OCL) 8 40 mV (max) A = weighted; 0dB gain; See Table 1 f = 217Hz; Vripple = 200mVP-P CB = 2.2F; See Table 2 Table 1 Table 2 Xtalk Crosstalk Headphone; PO= 10mW f = 1kHz; OCL -60 dB TWU Wake-Up Time CB = 2.2F, CD6 = 0 35 ms (max) CB = 2.2F, CD6 = 1 85 ms (max) f = 217Hz, VRMS = 200mVpp 56 dB CMRR Common-Mode Rejection Ratio 5 www.national.com LM4937 JA (TLA36 and RLA36) See AN-1279 Absolute Maximum Ratings (Notes 1, 2) LM4937 Audio Amplifier Electrical Characteristics AVDD = 5.0V, DVDD = 3.3V (Notes 1, 2) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4937 Typical (Note 6) IDD Supply Current 17.5 mA (max) Headphone Mode Only (OCL) 5.8 mA (max) Mono Loudspeaker Mode Only (Note 11) 11.6 mA (max) 5 mA (max) 12.9 mA (max) 1.6 A (max) 1.25 mW (min) Headphone; THD = 1%; f = 1kHz, 32 SE 80 mW (min) Earpiece; THD = 1%; f = 1kHz, 32 BTL 175 mW (min) 2.4 Vpp 0.03 % 0.01 % 0.04 % DAC Off, All Amps On (OCL) (Note 11) Shutdown Current Speaker; THD = 1%; f = 1kHz, 8 BTL PO Output Power VFS DAC Full Scale DAC Output Speaker; PO = 500mW; f = 1kHz, 8 BTL THD+N Total Harmonic Distortion Headphone; PO = 30mW; f = 1kHz, 32 SE Earpiece; PO = 40mW; f = 1kHz, 32 BTL; CD4 = 0 VOS O Offset Voltage Output Noise PSRR Power Supply Rejection Ratio Speaker 10 mV Earpiece 8 mV HP (OCL) 8 mV A = weighted; 0dB gain; See Table 1 f = 217Hz; Vripple = 200mVP-P CB = 2.2F; See Table 3 Xtalk Crosstalk TWU Wake-Up Time www.national.com Units (Limits) VIN = 0, No Load All Amps On + DAC, OCL (Note 11) Mono Earpiece Mode Only (Note 11) ISD Limits (Notes 7, 8) Table 1 Table 3 Headphone; PO= 15mW f = 1kHz; OCL -56 dB CB = 2.2F, CD6 = 0 45 ms CB = 2.2F, CD6 = 1 130 ms 6 (Notes 1, 2) The following specifications apply for 3.0V AVDD 5.0V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4937 Typical (Note 6) Stereo Analog Inputs PreAmp Gain Setting Range minimum gain setting -6 maximum gain setting 15 PGR Differential Mono Analog Input PreAmp Gain Setting Range VCR ACH-CH AMUTE Output Volume Control for Loudspeaker, Headphone Output, or Earpiece Output minimum gain setting -12 maximum gain setting 9 minimum gain setting -56 maximum gain setting +5 Stereo Channel to Channel Gain Mismatch Mute Attenuation -7 dB (min) -5 dB (max) 15.5 dB (max) 14.5 dB (min) -13 dB (min) -11 dB (max) 9.5 dB (max) 8.5 dB (min) -59 dB (min) -53 dB (max) 4.5 dB (min) 5.5 dB (max) 0.3 dB Vin = 1Vrms, Gain = 0dB with load Headphone RINPUT Limits (Notes 7, 8) Units (Limits) <-90 DIFF+, DIFF-, LIN and RIN Input Impedance 23 Digital Section Electrical Characteristics dB (min) 18 k (min) 28 k (max) (Notes 1, 2) The following specifications apply for 3.0V AVDD 5.0V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4937 Typical (Note 6) DISD Digital Shutdown Current Limits (Notes 7, 8) Units (Limits) Mode 0, DVDD = 3.0V A No MCLK 0.01 5.3 6.5 mA (max) 4.8 6 mA (max) DIDD Digital Power Supply Current fMCLK = 12MHz, DVDD = 3.0V ALL MODES EXCEPT 0 PLLIDD PLL Quiescent Current fMCLK = 12MHz, DVDD = 3.0V Audio DAC (Typical numbers are with 6.144MHz audio clock and 48kHz sampling frequency RDAC Audio DAC Ripple 20Hz - 20kHz through headphone output PBDAC Audio DAC Passband width -3dB point SBADAC Audio DAC Stop band Attenuation Above 24kHz Audio DAC Dynamic Range DC - 20kHz, -60dBFS; AES17 Standard See Table 4 SNR SNRDAC DRDAC +/-0.1 dB 22.6 kHz 76 dB Table 4 dB Audio DAC-AMP Signal to Noise Ratio A-Weighted, Signal = VO at 0dBFS, f = 1kHz Noise = digital zero, A-weighted, See Table Table 4 4 dB Internal DAC SNR A-weighted (Note 10) dB 95 PLL fIN Input Frequency on MCLK pin 12 7 10 26 MHz www.national.com LM4937 Volume Control Electrical Characteristics LM4937 Symbol Parameter Conditions LM4937 Typical (Note 6) Limits (Notes 7, 8) Units (Limits) SPI/I2C (1.7V I2CVDD 2.2V) fSPI Maximum SPI Frequency 1000 kHz (max) tSPISETD SPI Data Setup Time 250 ns (max) tSPISETENB SPI ENB Setup Time 250 ns (max) tSPIHOLDD SPI Data Hold Time 250 ns (max) tSPIHOLDENB SPI ENB Hold Time 250 ns (max) tSPICL SPI Clock Low Time 500 ns (max) tSPICH SPI Clock High Time 500 ns (max) fCLKI2C I2C_CLK Frequency 400 kHz (max) tI2CHOLD I2C_DATA Hold Time 250 ns (max) tI2CSET I2C_DATA Setup Time 250 ns (max) 0.7 x I2CVDD V (min) VIH I2C/SPI Input High Voltage VIL I2C/SPI Input Low Voltage I2CV DD 0 0.25 x I2CVDD V (max) SPI/I2C (2.2V I2CVDD 4.0V) fSPI Maximum SPI Frequency 4000 kHz (max) tSPISETD SPI Data Setup Time 100 ns (max) tSPISETENB SPI ENB Setup Time 100 ns (max) tSPIHOLDD SPI Data Hold Time 100 ns (max) tSPIHOLENB SPI ENB Hold Time 100 ns (max) tSPICL SPI Clock Low Time 125 ns (max) tSPICH SPI Clock High Time 125 ns (max) fCLKI2C I2C_CLK 400 kHz (max) tI2CHOLD I2C_DATA Hold Time 100 ns (max) tI2CSET I2C_DATA Frequency Setup Time 100 ns (max) V (min) VIH I2C/SPI Input High Voltage I2CVDD 0.7 x I2CVDD VIL I2C/SPI Input Low Voltage- 0 0.3 x I2CVDD V (ax) 1536 3072 6144 12288 kHz (ax) kHz (max) 50 40 60 % % I2S (1.7V VDD_IO 2.7V) I2S_CLK Frequency fCLKI2S I2S_RES = 1 I2S_RES = 0 I2S_WS Duty Cycle VIH Digital Input High Voltage 0.75 x VDD_IO V (min) VIL Digital Input Low Voltage 0.25 x VDD_IO V (max) I2S (2.7V VDD_IO 4.0V) I2S_CLK Frequency I2S_RES = 0 1536 3072 6144 12288 kHz (max) kHz (max) I2S_WS Duty Cycle I2S_RES = 1 50 40 60 % % fCLKI2S www.national.com 8 Parameter Conditions LM4937 Typical (Note 6) Limits (Notes 7, 8) Units (Limits) VIH Digital Input High Voltage 0.7 x VDD_IO V (min) VIL Digital Input Low Voltage 0.3x VDD_IO V (max) Note 1: All voltages are measured with respect to the GND pin unless otherwise specified. Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,JA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4937 typical application with VDD = 3.3V, RL = 8 stereo operation, the total power dissipation is TBDW. JA = TBDC/W. Note 4: Human body model: 100pF discharged through a 1.5k resistor. Note 5: Machine model: 220pF - 240pF discharged through all pins. Note 6: Typicals are measured at 25C and represent the parametric norm. Note 7: Limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 9: Shutdown current is measured in a normal room environment. Note 10: Internal DAC only with DAC modes 00 and 01. Note 11: Enabling mono bit (D_6 in Output Control Register 01h) will save 400A (typ) from specified current. 9 www.national.com LM4937 Symbol LM4937 TABLE 1. Output Noise Output Noise AVDD = 5.0V and AVDD = 3.0V. All gains set to 0dB. Units in V. A - weighted MODE EP LS HP OCL Units 1 22 22 8 V 2 22 22 8 V 3 22 22 8 V 4 68 88 46 V 5 38 48 24 V 6 29 34 18 V 7 38 48 24 V TABLE 2. PSRR AVDD = 3.0V PSRR AVDD = 3.0V, f = 217Hz; Vripple = 200mVp-p; CB = 2.2F. MODE EP(Typ) LS (Typ) LS (Limit) HP (Typ) HP (Limit) Units 1 69 76 2 69 76 3 69 76 72 dB 4 63 62 55 dB 5 69 68 61 dB 6 69 70 64 dB 7 69 68 61 dB 72 67 dB 72 68 dB TABLE 3. PSRR AVDD = 5.0V PSRR AVDD = 5.0V. All gains set to 0dB. f = 217Hz; Vripple = 200mVp-p; CB = 2.2F MODE EP (Typ) LS (Typ) HP (Typ) Units 1 68 72 71 dB 2 68 72 71 dB 3 68 72 71 dB 4 68 66 69 dB 5 68 69 70 dB 6 69 72 71 dB 7 68 69 70 dB TABLE 4. Dynamic Range and SNR Dynamic Range and SNR. 3.0V AVDD 5.0V. All programmable gain set to 0dB. Units in dB. www.national.com DR (Typ) SNR (Typ) Units LS 95 85 dB HP 95 85 dB EP 97 85 dB 10 The LM4937 is controlled via either a two wire I2C compatible interface or three wire SPI interface, selectable with the MODE pin. This interface is used to configure the operating mode, interfaces, data converters, mixers and amplifiers. The LM4937 is controlled by writing 8 bit data into a series of write-only registers, the device is always a slave for both type of interfaces. THREE WIRE, SPI INTERFACE (MODE = 1) Three Wire Mode Write Bus Transaction 20202059 Three Wire Mode Write Bus Timing 20202060 FIGURE 2. Three Wire Mode Write Bus When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is clocked in on the rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are used to select an address within the device, the lower 8 bits (7:0) contain the updated data for this register. TWO WIRE I2C COMPATIBLE INTERFACE (MODE = 0) Two Wire Mode Write Bus Transaction 202020j6 11 www.national.com LM4937 System Control LM4937 Two Wire Mode Write Bus Timing 20202062 FIGURE 3. Two Wire Mode Write Bus When the part is configured as an I2C device then the LM4937 will respond to one of two addresses, according to the ADDR input. If ADDR is low then the address portion of the I2C transaction should be set to write to 0010000. When ADDR is high then the address input should be set to write to 1110000. TABLE 5. Chip Address A7 A6 A5 A4 A3 A2 A1 A0 Chip Address 0 EC EC 1 0 0 0 0 ADR = 0 0 0 0 1 0 0 0 0 ADR = 1 0 1 1 1 0 0 0 0 EC -- Externally configured by ADR pin www.national.com 12 www.national.com Output Control Mono Volume Control 0 Loud Speaker Volume Control RESERVED Headphone Left Volume Control Headphone Right Volume Control Analog R & L Input Gain Control Analog Mono & DAC 0 Input Gain Control Clock Configu ration PLL M Divider PLL N Divider PLL N_MOD Divider and Dither Level PLL_P Divider DAC Setup Interface COMPENSATION _C OEFF0_LSB COMPENSATION _C OEFF0_MSB COMPENSATION _C OEFF1_LSB COMPENSATION _C OEFF1_MSB COMPENSATION _C OEFF2_LSB 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h COMP2_7 COMP1_15 COMP1_7 COMP0_15 COMP0_7 0 0 0 VCO_FAST PLL_N_7 0 R_DIV_3 0 0 0 0 0 0 0 Mode Control 00h D7 Register Address COMP2_6 COMP1_14 COMP1_6 COMP0_14 COMP0_6 0 CUST_COMP 0 PLL_DITH_LEV_1 PLL_N_6 PLL_M_6 R_DIV_2 DIG_R_ GAIN_1 0 0 0 0 0 0 D_6 CD_6 D6 COMP2_5 COMP1_13 COMP1_5 COMP0_13 COMP0_5 0 DITHER_ALW_ON 0 PLL_DITH_LEV_0 PLL_N_5 PLL_M_5 R_DIV_1 DIG_R_ GAIN_0 ANA_R_ GAIN_2 0 0 0 0 0 0 0 D5 COMP2_4 COMP1_12 COMP1_4 COMP0_12 COMP0_4 0 DITHER_OFF 0 PLL_N_MOD_4 PLL_N_4 PLL_M_4 R_DIV_0 DIG_L_ GAIN_1 ANA_R_ GAIN_1 HP_R_VOL_4 HP_L_VOL_4 0 LS_VOL_4 EP_VOL_4 0 OCL D4 TABLE 6. Control Registers PLL_N_2 PLL_M_2 AUDIO _CLK_SEL MONO_IN_ GAIN_2 ANA_L_ GAIN_2 HP_R_VOL_2 HP_L_VOL_2 0 LS_VOL_2 EP_VOL_2 HP_L_ OUTPUT CD_2 D2 COMP2_3 COMP1_11 COMP1_3 COMP0_11 COMP0_3 I2C_FAST MUTE_R PLL_P_3 COMP2_2 COMP1_10 COMP1_2 COMP0_10 COMP0_2 I2S_MODE MUTE_L PLL_P_2 PLL_N_MOD_3 PLL_N_MOD_2 PLL_N_3 PLL_M_3 PLL_ ENABLE DIG_L_ GAIN_0 ANA_R_ GAIN_0 HP_R_VOL_3 HP_L_VOL_3 0 LS_VOL_3 EP_VOL_3 HP_R_ OUTPUT CD_3 D3 PLL_N_0 PLL_M_0 FAST_ CLOCK MONO_IN_ GAIN_0 ANA_L _GAIN_0 HP_R_VOL_0 HP_L_VOL_0 0 LS_VOL_0 EP_VOL_0 MONO_ OUTPUT CD_0 D0 PLL_P_0 COMP2_1 COMP1_9 COMP1_1 COMP0_9 COMP0_1 I2S_RESOL COMP2_0 COMP1_8 COMP1_0 COMP0_8 COMP0_0 I2S_M/S DAC_MODE_1 DAC_MODE_0 PLL_P_1 PLL_N_MOD_ PLL_N_MOD_0 1 PLL_N_1 PLL_M_1 PLL_INPUT MONO_IN_ GAIN_1 ANA_L _GAIN_1 HP_R_VOL_1 HP_L_VOL_1 0 LS_VOL_1 EP_VOL_1 LS_ OUTPUT CD_1 D1 LM4937 13 www.national.com 14 COMPENSATION _C OEFF2_MSB TEST_ REGISTER 15h 16h COMP2_14 D6 RESERVED RESERVED COMP2_15 D7 Note: All registers default to 0 on initial power-up. Register Address RESERVED COMP2_13 D5 RESERVED COMP2_12 D4 RESERVED COMP2_11 D3 RESERVED COMP2_10 D2 RESERVED COMP2_9 D1 RESERVED COMP2_8 D0 LM4937 LM4937 System Controls TABLE 7. Loudspeaker, Earpiece, HP Left or Right Volume Control EP_VOL_4, LS_VOL_4, HP_L_VOL_4, HP_R_VOL_4 EP_VOL_3, LS_VOL_3, HP_L_VOL_3, HP_R_VOL_3 EP_VOL_2, LS_VOL_2, HP_L_VOL_2, HP_R_VOL_2 EP_VOL_1, LS_VOL_1, HP_L_VOL_1, HP_R_VOL_1 EP_VOL_0, LS_VOL_0, HP_L_VOL_0, HP_R_VOL_0 Gain (dB) 0 0 0 0 0 <-90 (MUTE) 0 0 0 0 1 -56 0 0 0 1 0 -52 0 0 0 1 1 -48 0 0 1 0 0 -45 0 0 1 0 1 -42 0 0 1 1 0 -39 0 0 1 1 1 -36 0 1 0 0 0 -33 0 1 0 0 1 -30 0 1 0 1 0 -28 0 1 0 1 1 -26 0 1 1 0 0 -24 0 1 1 0 1 -22 0 1 1 1 0 -20 0 1 1 1 1 -18 1 0 0 0 0 -16 1 0 0 0 1 -14 1 0 0 1 0 -12 1 0 0 1 1 -10 1 0 1 0 0 -8 1 0 1 0 1 -6 1 0 1 1 0 -4 1 0 1 1 1 -3 1 1 0 0 0 -2 1 1 0 0 1 -1 1 1 0 1 0 0 1 1 0 1 1 +1 1 1 1 0 0 +2 1 1 1 0 1 +3 1 1 1 1 0 +4 1 1 1 1 1 +5 15 www.national.com LM4937 TABLE 8. Mixer Code Control Mode CD3 CD2 CD1 CD0 Mono Earpiece Loudspeaker Headphone L Headphone R 0 0 0 0 0 SD SD SD SD 1 1 0 0 1 M M M M 2 1 0 1 0 AL+AR AL+AR AL AR 3 1 0 1 1 M+AL+AR M+AL+AR M+AL M+AR 4 1 1 0 0 DL+DR DL+DR DL DR 5 1 1 0 1 DL+DR+ AL+AR DL+AL AL+AR DL+AL DR+AR 6 1 1 1 0 M+DL+AL+ DR+AR M+DL+AL+ DR+AR M+DL+AL M+DR+AR 7 1 1 1 1 M+DL+DR M+DL+DR M+DL M+DR SD -- Shutdown M -- Mono Differential Input AL -- Analog Left Channel AR -- Analog Right Channel DL -- I2S DAC Left Channel DR -- I2S DAC Right Channel MUTE -- Mute Note: Power-On Default Mode is Mode 0 www.national.com 16 LS_OUTPUT = 1 Loudspeaker LS_OUTPUT = 0 Output On Output Off HP_L_OUTPUT = 1 HP_L_OUTPUT = 0 Headphone Left Channel Output On Output Off (OCL = 0) HP_R_OUTPUT = 1 Headphone Right Channel HP_R_OUTPUT = 0 Output On Output Off (OCL = 0) Output Mute (OCL = 1) EP_OUTPUT = 1 EP_OUTPUT = 0 Output On Output Off CD3 = 1 CD3 = 0 Outputs Toggled Via Register Control All Outputs Off Earpiece All Outputs Output Mute (OCL = 1) TABLE 10. Mono Differential Amplifier Input Gain Select (08h) MONO_IN_GAIN_2 MONO_IN_GAIN_1 MONO_IN_GAIN_0 Input Gain Setting 0 0 0 -12dB 0 0 1 -9dB 0 1 0 -6dB 0 1 1 -3dB 1 0 0 0dB 1 0 1 3dB 1 1 0 6dB 1 1 1 9dB TABLE 11. Analog Single-Ended Input Amplifier Gain Select (07h) ANA_L_GAIN_2 ANA_R_GAIN_2 ANA_L_GAIN_1 ANA_R_GAIN_1 ANA_L_GAIN_0 ANA_R_GAIN_0 Input Gain Setting 0 0 0 -6dB 0 0 1 -3dB 0 1 0 0dB 0 1 1 3dB 1 0 0 6dB 1 0 1 9dB 1 1 0 12dB 1 1 1 15dB TABLE 12. DAC Gain Select (08h) DIG_L_GAIN_1 DIG_R_GAIN_1 DIG_L_GAIN_0 DIG_R_GAIN_0 Input Gain Setting 0 0 -3dB 0 1 0dB 1 0 3dB 1 1 6dB 17 www.national.com LM4937 TABLE 9. Output Control (01h) LM4937 PLL Configuration Registers PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input divider of the PLL. PLL_M (0Ah) (Set = logic 1, Clear = logic 0) Bits Register Description 6:0 PLL_M Programs the PLL input divider to select: PLL_M Divide Ratio 0 Divider Off 1 1 2 1.5 3 2 4 2.5 ... 3 126 63.5 NOTES: The M divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The division of the M divider is derived from PLL_M as such: M = (PLL_M+1) / 2 PLL N DIVIDER CONFIGURATION REGISTER This register is used to control PLL N divider. PLL_N (0Bh) (Set = logic 1, Clear = logic 0) Bits Register Description 7:0 PLL_N Programs the PLL feedback divider: PLL_N Divide Ratio 0 Divider Off 1 10 10 11 11 12 12 ... ... 248 248 249 249 NOTES: The N divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N divider should never be set so that (Fin/M) * N > 55MHz (or 80MHz if FAST_VCO is set in the PLL_N_MOD register). The non-sigma-delta division of the N divider is derived from the PLL_N as such: N = PLL_N Fin /M is often referred to as Fcomp (Frequency of Comparison) or Fref (Reference Frequency). In this document, Fcomp is used. PLL P DIVIDER CONFIGURATION REGISTER This register is used to control the PLL's P divider. www.national.com 18 LM4937 PLL_P (0Dh) (Set = logic 1, Clear = logic 0) Bits Register Description 3:0 PLL_P Programs the PLL input divider to select: 0 Divider Off 1 1 2 1.5 3 2 ... -> 2.5 13 7 14 7.5 15 8 NOTES: The output of this divider should be either 12 or 24MHz in USB mode or 11.2896MHz, 12.288MHz or 24.576MHz in non-USB modes. The division of the P divider is derived from PLL_P as such: P = (PLL_P+1) / 2 PLL N MODULATOR AND DITHER SELECT CONFIGURATION REGISTER This register is used to control the Fractional component of the PLL. PLL_N_MOD (0Ch) (Set = logic 1, Clear = logic 0) Bits Register Description 4:0 PLL_N_MOD This programs the PLL N Modulator's fractional component: PLL_N_MOD Fractional Addition 0 0/32 1 1/32 2 30 6:5 7 DITHER_LEVEL FAST_VCO 2/32 30/32 Allows control over the dither used by the N Modulator DITHER_LEVEL DAC Sub-system Input Source 00 Medium (32) 01 Small (16) 10 Large (48) If set the VCO maximum and minimum frequencies are raised: FAST_VCO Maximum FVCO 0 40-55MHz NOTES: The complete N divider is a fractional divider as such: N = PLL_N + (PLL_N_MOD/32) If the modulus input is zero, then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula: Fout = (Fin * N) / (M * P) Please see over for more details on the PLL and common settings. 19 www.national.com LM4937 Further Notes on PLL Programming The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 25MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz sample rates from any common clock source when the oversampling rate of the audio system is 125fs. In systems where 128x oversampling must be used (for example with an isochronous I2S data stream) a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a clock that is accurate to within typical crystal tolerances of the real sample rate. 20202063 Example Of PLL Settings For 48Khz Sample Rates f_in (MHz) fsamp (kHz) M N P PLL_M PLL_N PLL_N_MOD PLL_P f_out (MHz) 11 48 11 60 5 21 60 0 9 12 12 48 5 25 5 9 25 0 9 12 12.288 48 4 19.53125 5 7 19 17 9 12 13 48 13 60 5 25 60 0 9 12 14.4 48 9 37.5 5 17 37 16 9 12 16.2 48 27 100 5 53 100 0 9 12 16.8 48 14 50 5 27 50 0 9 12 19.2 48 13 40.625 5 25 40 20 9 12 19.44 48 27 100 6 53 100 0 11 12 19.68 48 20.5 62.5 5 40 62 16 9 12 19.8 48 16.5 50 5 32 50 0 9 12 PLL_N_MOD PLL_P f_out (MHz) Example PLL Settings For 44.1Khz Sample Rates f_in (MHz) fsamp (kHz) M N P PLL_M PLL_N 11 44.1 11 55.125 5 21 55 4 9 11.025000 11.2896 44.1 8 39.0625 5 15 39 2 9 11.025000 12 44.1 5 22.96875 5 9 22 31 9 11.025000 13 44.1 13 55.125 5 25 55 4 9 11.025000 14.4 44.1 12 45.9375 5 23 45 30 9 11.025000 16.2 44.1 9 30.625 5 17 30 20 9 11.025000 16.8 44.1 17 55.78125 5 33 55 25 9 11.025000 19.2 44.1 16 45.9375 5 31 45 30 9 11.025000 19.44 44.1 13.5 38.28125 5 26 38 9 9 11.025000 19.68 44.1 20.5 45.9375 4 40 45 30 7 11.025000 19.8 44.1 11 30.625 5 21 30 20 9 11.025000 These tables cover the most common applications, obtaining clocks for sample rates such as 22.05kHz and 192kHz should be done by changing the P divider value or the R divider in the clock configuration diagram. www.national.com 20 Choose a small range of P so that the VCO frequency is swept between 45 and 55MHz (or 60-80MHz if VCOFAST is used). Remembering that the P divider can divide by half integers. So for P = 4.0 7.0 sweep the M inputs from 2.5 24. The most accurate N and N_MOD can be calculated by: N = FLOOR(((Fout/Fin)*(P*M)),1) N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0) This shows that setting M = 11.5, N = 75 N_MOD = 47 P = 7 gives a comparison frequency of just over 1MHz, a VCO frequency of just under 80MHz (so VCO_FAST must be set) and an output frequency of 11.289596 which gives a sample rate of 44.099985443kHz, or accurate to 0.33 ppm. Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used in the above mode. The I2S should be master on the LM4937 so that the data source can support appropriate SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems. Where a system clock exists at an integer multiple of the required DAC clock rate it is preferable to use this rather than the PLL. The LM4937 is designed to work in 8,12,16,24,32, and 48kHz modes from a 12MHz clock without the use of the PLL. This saves power and reduces clock jitter. Clock Configuration Register This register is used to control the multiplexers and clock R divider in the clock module. CLOCK (09h) (Set = logic 1, Clear = logic 0) Bits Register Description 0 FAST_CLOCK If set master clock is divided by two. FAST_CLOCK 1 PLL_INPUT Normal 1 Divided by 2 Programs the PLL input multiplexer to select: PLL_INPUT 2 AUDIO_CLK_SEL PLL_ENABLE PLL Input Source 0 MCLK 1 I2S Input Clock Selects which clock is passed to the audio sub-system DAC_CLK_SEL DAC Sub-system Input Source 0 PLL Input 1 3 MCLK Frequency 0 PLL Output If set enables the PLL. (MODES 4-7 only) 21 www.national.com LM4937 If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining 11.2896 from 12.000MHz is shown below. LM4937 Bits Register 7:4 R_DIV Description Programs the R divider R_DIV Divide Value 0000 1 0001 1 0010 1.5 0011 2 0100 2.5 0101 3 0110 3.5 0111 4 1000 4.5 1001 5 1010 5.5 1011 6 1100 6.5 1101 7 1110 7.5 1111 8 20202053 By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data. It is expected that the PLL be used to drive the audio system unless a 12.000MHz master clock is supplied. The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL. www.national.com 22 The DAC can work in 4 modes, each with different oversampling rates, 125,128,64 & 32. In normal operation 125x oversampling provides for the simplest clocking solution as it will work from 12.000MHz (common in most systems with Bluetooth or USB) at 48kHz exactly. The other modes are useful if data is being provided to the DAC from an uncontrollable isochronous source (such as a CD player, DAB, or other external digital source) rather than being decoded from memory. In this case the PLL can be used to derive a clock for the DAC from the I2S clock. The DAC oversampling rate can be changed to allow simpler clocking strategies, this is controlled in the DAC SETUP register but the oversampling rates are as follows: DAC MODE Over sampling Ratio Used 00 125 01 128 10 64 11 32 The following table describes the clock required at the clock generator input for various clock sample rates in the different DAC modes: Fs (kHz) DAC Oversampling Ratio 8 125 Required CLock at DAC Clock Generator Input (MHz) 2 8 128 2.048 11.025 125 2.75625 11.025 128 2.8224 12 125 3 12 128 3.072 16 125 4 16 128 4.096 22.05 125 5.5125 22.05 128 5.6448 24 125 6 24 128 6.144 32 125 8 32 128 8.192 44.1 125 11.025 44.1 128 11.2896 48 125 12 48 128 12.288 88.2 64 11.2896 96 64 12.288 176.4 32 22.5792 192 32 24.576 Methods for producing these clock frequencies are described in the PLL section. The R divider can be used when the master clock is exactly 12.00 MHz in order to generate different sample rates. The Table below shows different sample rates supported from 12.00MHz by using only the R divider and disabling the PLL. In this way we can save power and the clock jitter will be low. R_DIV Divide Value DAC Clock Generator Input Frequency <MHz> 11 6 2 Sample Rate Supported <KHz> 8 9 5 2.4 9.6 7 4 3 12 5 3 4 16 4 2.5 4.8 19.2 23 www.national.com LM4937 Common Clock Settings for the DAC LM4937 R_DIV Divide Value DAC Clock Generator Input Frequency <MHz> Sample Rate Supported <KHz> 3 2 6 24 2 1.5 8 32 0 1 12 48 The R divider can also be used along with the P divider in order to create the clock needed to support low sample rates. www.national.com 24 LM4937 DAC Setup Register This register is used to configure the basic operation of the stereo DAC. DAC_SETUP (0Eh) (Set = logic 1, Clear = logic 0) Bits Register Description 1:0 DAC_MODE The DAC used in the LM4937 can operate in one of 4 oversampling modes. The modes are described as follows: DAC_MODE 2 Oversampling Rate Typical FS Clock Required 00 125 48KHz 12.000MHz (USB Mode) 01 128 44.1KHz 48KHz 11.2896MHz 12.288MHz 10 64 96KHz 12.288MHz 11 32 192KHz 24.576MHz MUTE_L Mutes the left DAC channel on the next zero crossing. 3 MUTE_R Mutes the right DAC channel on the next zero crossing. 4 DITHER_OFF If set the dither in DAC is disabled. 5 DITHER ALWAYS_ON If set the dither in DAC is enabled all the time. 6 CUST_COMP If set the DAC frequency response can be programmed manually via a 5 tap FIR "compensation" filter. This can be used to enhance the frequency response of small loudspeakers or provide a crude tone control. The compensation Coefficients can be set by using registers 10h to 15h. 25 www.national.com LM4937 Interface Control Register This register is used to control the I2S and I2C compatible interface on the chip. INTERFACE (0Fh) (Set = logic 1, Clear = logic 0) Bits Register Description 0 I2S_MASTER_SLAVE If set the LM4937 acts as a master for I2S, so both I2S clock and I2S word select are configured as outputs. If cleared the LM4937 acts as a slave where both I2S clock and word select are configured as inputs. 1 I2S_RESOLUTION If set the I2S resolution is set to 32 bits. If clear, resolution is set to 16 bits. This bit only affects the I2S Interface in master mode. In slave mode the I2S Interface can support any I2S compatible resolution. In master mode the I2S resolution also depends on the DAC mode as the note below explains. 2 I2S_MODE If set the I2S is configured in left justified mode timing. If clear, the I2S interface is configured in normal I2S mode timing. 3 I2C_FAST If set enables the I2C to run in fast mode with an I2C clock up to 3.4MHz. If clear the I2C speed gets its default value of a maximum of 400kHz NOTES: The master I2S format depends on the DAC mode. In USB mode the number of bits per word is 25 (i.e. 2.4MHz for a 48kHz sample rate). The duty cycle is 40/60. In non-USB modes the format is 32 or 16 bits per word, depending on I2S_RESOLTION and the duty cycle is always 50-50. In slave mode it will decode any I2S compatible data stream. 20202027 I2S Mode Timing 20202028 Left Justified Mode Timing www.national.com 26 These registers are used to configure the DAC's FIR compensation filter. Three 16 bit coefficients are required and COMP_COEFF (10h 15h) (Set = logic 1, Clear = logic 0) Address Register Description 10h COMP_COEFF0_LSB Bits [7:0] of the 1st and 5th FIR tap (C0 and C4) 11h COMP_COEFF0_MSB Bits [15:8] of the 1st and 5th FIR tap (C0 and C4) 12h COMP_COEFF1_LSB Bits [7:0] of the 2nd and 4th FIR tap (C1 and C3) 13h COMP_COEFF1_MSB Bits [15:8] of the 2nd and 4th FIR tap (C1 and C3) 14h COMP_COEFF2_LSB Bits [7:0] of the 3rd FIR tap (C2) 15h COMP_COEFF2_MSB Bits [15:8] of the 3rd FIR tap (C2) NOTES: The filter must be phase linear to ensure the data keeps the correct stereo imaging so the second half of the FIR filter must be the reverse of the 1st half. 20202055 If the CUST_COMP option in register 0Eh is not set the FIR filter will use its default values for a linear response from the DAC into the analog mixer, these values are: DAC_OSR C0, C4 C1, C3 C2 00 434 -2291 26984 01, 10, 11 61 -371 25699 If using 96 or 192kHz data then the custom compensation may be required to obtain flat frequency responses above 24kHz. The total power of any custom filter must not exceed that of the above examples or the filters within the DAC will clip. The coefficient must be programmed in 2's complement. 27 www.national.com LM4937 must be programmed via the I2C/SPI Interface in bytes as follows: FIR Compensation Filter Configuration Registers LM4937 Typical Performance Characteristics THD+N vs Frequency 3.0V EP Out, RL = 32, PO = 20mW THD+N vs Frequency 3.0V HP Out, RL = 16, PO = 20mW 20202064 20202065 THD+N vs Frequency 3.0V LS Out, RL = 8, PO = 200mW THD+N vs Frequency 5.0V EP, RL = 32, PO = 40mW 20202066 20202067 THD+N vs Frequency 5.0V HP Out, RL = 16, PO = 60mW THD+N vs Frequency 5.0V HP Out, RL = 32, PO = 30mW 20202069 www.national.com 20202070 28 LM4937 THD+N vs Frequency 5.0V LS Out, RL = 8, PO = 500mW THD+N vs Output Power 3.0V EP Out, RL = 16, f = 1kHz 20202071 20202072 THD+N vs Output Power 3.0V EP Out, RL = 32, f = 1kHz THD+N vs Output Power 3.0V HP Out, RL = 16, f = 1kHz 20202073 20202076 THD+N vs Output Power 3.0V HP Out, RL = 32, f = 1kHz THD+N vs Output Power 3.0V LS Out, RL = 8, f = 1kHz 20202077 20202019 29 www.national.com LM4937 THD+N vs Output Power 5.0V EP Out, RL = 16, f = 1kHz THD+N vs Output Power 5.0V EP Out, RL = 32, f = 1kHz 20202078 20202079 THD+N vs Output Power 5.0V HP Out, RL = 16, f = 1kHz THD+N vs Output Power 5.0V HP Out, RL = 32, f = 1kHz 20202080 20202081 THD+N vs Output Power 5.0V LS Out, RL = 8, f = 1kHz THD+N vs I2S Level EP Out 20202083 20202082 www.national.com 30 LM4937 THD+N vs I2S Level HP Out THD+N vs I2S Level LS Out 20202085 20202084 PSRR vs Frequency 3.0V EP Out Mode 1 PSRR vs Frequency 3.0V EP Out Mode 4 20202086 20202087 PSRR vs Frequency 3.0V HP Out Mode 2 PSRR vs Frequency 3.0V HP Out Mode 4 20202088 20202089 31 www.national.com LM4937 PSRR vs Frequency 3.0V LS Out Mode 2 PSRR vs Frequency 3.0V LS Out Mode 4 20202090 20202091 PSRR vs Frequency 5.0V HP Out Mode 2 PSRR vs Frequency 5.0V HP Out Mode 4 20202092 20202093 PSRR vs Frequency 5.0V LS Out Mode 4 PSRR vs Frequency 5.0V LS Out Mode 2 20202094 www.national.com 20202095 32 LM4937 Output Power vs Supply Voltage EP Out , RL = 32, 1% THD+N Output Power vs Supply Voltage HP Out , RL = 32, 1% THD+N 20202097 20202096 Output Power vs Supply Voltage LS Out , RL = 8, 1% THD+N 20202098 33 www.national.com LM4937 3.072MHz (48kHz stereo, 32bit). The basic format is shown below: Application Information I2S The LM4937 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up to 20202007 FIGURE 4. Pin 4 -- I2S_WS JP20 -- Toslink SPDIF Input JP21 -- Coaxial SPDIF Input Coaxial and Toslink inputs may be toggled between by use of S25. Only one may be used at a time. Must be used in conjunction with on-board SPDIF receiver chip. MONO ONLY SETTING The LM4937 may be restricted to mono amplification only by setting D-6 in Output Control register 0x01h to 1. This may save an additional 400A from IDD. LM4937 DEMOBOARD OPERATION BOARD LAYOUT OUTPUTS JP5 -- BTL Loudspeaker Output JP1 -- Left Headphone Output (Single-Ended or OCL) JP3 -- Right Headphone Output (Single-Ended or OCL) P1 -- Stereo Headphone Jack (Same as JP1, JP2, SingleEnded or OCL) JP12 -- Mono BTL Earpiece Output DIGITAL SUPPLIES JP14 -- Digital Power DVDD JP10 -- I/O Power IOVDD JP13 -- PLL Supply PLLVDD JP16 -- USB Board Supply BBVDD JP15 -- I2C VDD All supplies may be set independently. All digital ground is common. Jumpers may be used to connect all the digital supplies together. S9 - connects VDD_PLL to VDD_D S10 - connects VDD_D to VDD_IO S11 - connects VDD_IO to VDD_I2C S12 - connects VDD_I2C to Analog VDD S17 - connects BB_VDD to USB3.3V (from USB board) S19 - connects VDD_D to USB3.3V (from USB board) S20 - connects VDD_D to SPDIF receiver chip CONTROL INTERFACE X1, X2 - USB Control Bus for I2C/SPI X1 Pin 9 - Mode Select (SPI or I2C) X2 Pin 1 - SDA Pin 3 - SCL Pin 15 - ADDR/END Pin 14 - USB5V Pin 16 - USB3.3V Pin 16 - USB GND ANALOG SUPPLY JP11 -- Analog Supply S12 -- connects Analog VDD with Digital VDD (I2C_VDD) S16 -- connects Analog Ground with Digital Ground S21 -- connects Analog VDD to SPDIF receiver chip MISCELLANEOUS I2S BUS SELECT S23, S24, S26, S27 - I2S Bus select. Toggles between onboard and external I2S (whether on-board SPDIF receiver is used). All jumpers must be set the same. Jumpers on top two pins selects external bus (JP19). Jumpers on bottom two pins selects on-board SPDIF receiver output. INPUTS Analog Inputs JP2 -- Mono Differential Input JP6 -- Left Input JP7 -- Right Input HEADPHONE OUTPUT CONFIGURATION Jumpers S1, S2, S3, and S4 are used to configure the headphone outputs for either cap-coupled outputs or output capacitorless (OCL) mode in addition to the register control internal to the LM4937 for this feature. Jumpers S1 and S3 bypass the output DC blocking capacitors when OCL mode Digital Inputs JP19 -- Digital Interface Pin 1 -- MCLK Pin 2 -- I2S_CLK Pin 3 -- I2S_SDI www.national.com 34 supply voltage testing of the LM4937 must be done on the external digital bus. The choice of using on-board or external digital bus is made usign jumpers S23, S24, S26, and S27 as described above. S25 selects whether the Toslink or Coaxial SPDIF input is used. The top two pins connects the toslink, the bottom two connect the coaxial input. Power on the digital side is routed through S20 (connecting to the other digital supplies), while on the analog side it is interrupted by S21. Both jumpers must be in place for the receiver to function. The part is already configured for I2S standard outputs. Jumper S28 allows the DATA output to be pulled either high or low. Default is high (jumper on right two pins). It may be necessary to quickly toggle S29 to reset the receiver and start it working upon initial power up.. A quick short across S29 should clear this condition. PLL FILTER CONFIGURATION The LM4937 demo board comes with a simple filter setup by connecting jumpers S5 and S6. Removing these and connecting jumpers S7 and S8 will allow for an alternate PLL filter configuration to be used at R2 and C23. LM4937 I2C/SPI INTERFACE SOFTWARE Convenient graphical user interface software is available for demonstration purposes of the LM4937. It allows for either SPI or I2C control via either USB or parallel port connections to a Windows computer. Control options include all mode and output settings, volume controls, PLL and DAC setup, FIR setting and on-the-fly adjustment by an easy to use graphical interface. An advanced option is also present to allow direct, register-level commands. Software is available from www.national.com and is compatible with Windows operating systems of Windows 98 or more (with USB support) with the latest .NET updates from Microsoft. ON-BOARD SPDIF RECEIVER The SPDIF receiver present on the LM4937 demo board allows quick demonstration of the capabilities of the LM4937 by using the common SPDIF output found on most CD/DVD players today. There are some limitations in its useage, as the receiver will not work with digital supplies of less than 3.0V and analog supplies of less than 4V. This means low analog 35 www.national.com LM4937 is required. S2 connects the center amplifer HPCOUT to the headphone ring when in OCL mode. S4 connects the center ring to GND when cap-coupled mode is desired. S4 must be removed for OCL mode to function properly. Jumper settings for each mode: OCL (CD_6 = 1) S1 = ON S2 = ON S3 = ON S4 = OFF Cap-Coupled (CD_6 = 0) S1 = OFF S2 = OFF S3 = OFF S4 = ON 20202003 Complete Board Schematic LM4937 Demonstration Board Schematic www.national.com 36 Enlarged Board Schematic Part 1 of 2 202020k6 LM4937 37 www.national.com www.national.com 38 Enlarged Board Schematic Part 2 of 2 202020k7 LM4937 LM4937 Revision History Rev Date 1.0 10/04/06 Initial release. Description 1.1 10/13/06 Text edits. 1.2 12/15/06 Changed the datasheet title from RF Resistant Topology to RF Suppression. 1.3 02/09/07 Replaced curve (THD+N vs Output Power, 3V LS Out) with the curve 20166975 from LM4934. These 2 curves have identical performance). 1.4 07/23/07 Changed the datasheet I2C Vdd & VDD_IO to 1.7V. 1.5 07/30/07 Added more tables (SPI/I2S). 1.6 08/03/07 Text edits. 1.7 10/12/07 Edited 20202001 and 58 and input some text edits. 1.8 10/31/07 Added the RL package. 39 www.national.com LM4937 Physical Dimensions inches (millimeters) unless otherwise noted 36-Bump micro SMD Order Number LM4937TL NS Package Number TLA36LVA X1 = 325530m, X2 = 351030m, X3 = 60075m www.national.com 40 LM4937 36-Bump micro SMD Order Number LM4937RL NS Package Number RLA36LVA X1 = 325530m, X2 = 351030m, X3 = 60075m 41 www.national.com LM4937 Audio Sub-System with OCL Stereo Headphone Output and RF Suppression Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION ("NATIONAL") PRODUCTS. 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