X9409 (R) Low Noise/Low Power/2-Wire Bus Data Sheet October 12, 2006 FN8192.4 DESCRIPTION Quad Digitally Controlled Potentiometers (XDCPTM) The X9409 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. FEATURES * Four potentiometers per package * 64 resistor taps * 2-wire serial interface for write, read, and transfer operations of the potentiometer * 50 Wiper resistance, typical at 5V. * Four non-volatile data registers for each potentiometer * Non-volatile storage of multiple wiper position * Power-on recall. Loads saved wiper position on power-up. * Standby current < 1A typical * System VCC: 2.7V to 5.5V operation * 10k, 2.5k End to end resistance * 100 yr. data retention * Endurance: 100,000 data changes per bit per register * Low power CMOS * 24 Ld SOIC, 24 Ld TSSOP * Pb-free plus anneal available (RoHS compliant) The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM Pot 0 VCC R0 R1 VSS R2 R3 WP SCL SDA A0 A1 A2 A3 Wiper Counter Register (WCR) VH0/RHO R0 R1 VL0/ RLO R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 2 VL2/RL2 VW0/ RWO Interface and Control Circuitry VH2/RH2 VW2/RW2 8 VW1/ RW1 Data R0 R1 R2 R3 1 Wiper Counter Register (WCR) Resistor Array Pot 1 VW3/RW3 VH1/ RH1 R0 R1 VL1/RL1 R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 3 VH3/RH3 VL3/RL3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9409 Ordering Information PART NUMBER X9409WS24I-2.7* PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (k) TEMP RANGE (C) 2.7 to 5.5 10 -40 to 85 24 Ld SOIC (300 mil) M24.3 -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027 MDP0044 X9409WS G X9409WS24IZ-2.7* (Note) X9409WS ZG PACKAGE PKG. DWG. # X9409WV24-2.7 X9409WV F 0 to 70 24 Ld TSSOP (4.4mm) X9409WV24Z-2.7 (Note) X9409WV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9409WV24I-2.7* X9409WV G -40 to 85 24 Ld TSSOP (4.4mm) -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9409WV24IZ-2.7* (Note) X9409WV ZG MDP0044 *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PIN DESCRIPTIONS VW0/RW0 - VW3/RW3 Host Interface Pins The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Serial Clock (SCL) Hardware Write Protect Input (WP) The SCL input is used to clock data into and out of the X9409. The WP pin when low prevents nonvolatile writes to the Data Registers. Serial Data (SDA) PIN NAMES SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Symbol SCL SDA A0-A3 VH0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3 VW0/RW0 - VW3/RW3 Device Address (A0 - A3) The address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9409. A maximum of 16 devices may occupy the 2-wire serial bus. WP VCC VSS NC Description Serial Clock Serial Data Device Address Potentiometer Pin (terminal equivalent) Potentiometer Pin (wiper equivalent) Hardware Write Protection System Supply Voltage System Ground (Digital) No Connection Potentiometer Pins VH0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3 The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. 2 FN8192.4 October 12, 2006 X9409 PIN CONFIGURATION SOIC VCC VL0/RL0 VH0/RH0 VW0/RW0 TSSOP 24 NC 2 23 VL3/RL3 3 22 VH3/RH3 4 21 VW3/RW3 20 1 A2 5 WP 6 SDA 7 X9409 SDA 1 24 WP A1 2 23 A2 VL1/RL1 VH1/RH1 3 22 VW0/RW0 4 21 VH0/RH0 A0 VW1/RW1 5 20 VL0/RL0 19 NC VSS 6 19 VCC 18 A3 NC 7 18 NC VW2/RW2 8 17 VL3/RL3 X9409 A1 8 17 SCL VL1/RL1 9 16 VL2/RL2 VH2/RH2 9 16 VH3/RH3 VL2/RL2 10 15 VW3/RW3 SCL 11 14 A0 A3 12 13 NC VH1/RH1 10 15 VH2/RH2 VW1/RW1 11 14 VW2/RW2 12 13 NC V SS PRINCIPLES OF OPERATION Stop Condition The X9409 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Serial Interface The X9409 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9409 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9409 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9409 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. 3 Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9409 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9409 will respond with a final acknowledge. Array Description The X9409 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are FN8192.4 October 12, 2006 X9409 controlled by the Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system. Flow 1. ACK Polling Sequence Nonvolatile Write Command Completed Enter ACK Polling Issue START Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9409 this is fixed as 0101[B]. Issue Slave Address YES Device Type Identifier 0 1 0 NO ACK Returned? Figure 1. Slave Address Issue STOP NO Further Operation? 1 A3 A2 A1 A0 Device Address YES Issue Instruction Issue STOP Proceed Proceed The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0 - A3 inputs. The X9409 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9409 to respond with an acknowledge. The A0 - A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Instruction Structure Acknowledge Polling Figure 2. Instruction Byte Format The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical nonvolatile write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9409 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9409 is still busy with the write operation no ACK will be returned. If the X9409 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. 4 The next byte sent to the X9409 contains the instruction and register pointer information. The format is shown in Figure 2. Register Select I3 I2 I1 Instructions I0 R1 R0 P1 P0 Pot Select The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bits (P1, P0) select which one of the four potentiometers is to be affected by the instruction. FN8192.4 October 12, 2006 X9409 wiper position of the selected pot), Write Wiper Counter Register (change current wiper position of the selected pot), Read Data Register (read the contents of the selected nonvolatile register) and Write Data Register (write a new value to the selected Data Register). The sequence of operations is shown in Figure 4. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the data registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the Wiper Counter Register (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. The Increment/Decrement command is different from the other commands. Once the command is issued and the X9409 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9409; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: Read Wiper Counter Register (read the current Table 1. Instruction Set I3 1 I2 0 Instruction Set I1 I0 R1 R0 0 1 0 0 1 0 1 0 0 0 P1 P0 1 0 1 1 R1 R0 P1 P0 Write Data Register 1 1 0 0 R1 R0 P1 P0 XFR Data Register to Wiper Counter Register 1 1 0 1 R1 R0 P1 P0 XFR Wiper Counter Register to Data Register Global XFR Data Registers to Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register Increment/Decrement Wiper Counter Register 1 1 1 0 R1 R0 P1 P0 0 0 0 1 R1 R0 0 0 1 0 0 0 R1 R0 0 0 0 0 1 0 0 0 P1 P0 Instruction Read Wiper Counter Register Write Wiper Counter Register Read Data Register Note: P1 P1 P0 P0 Operation Read the contents of the Wiper Counter Register pointed to by P1 - P0 Write new value to the Wiper Counter Register pointed to by P1 - P0 Read the contents of the Data Register pointed to by P1 - P0 and R1 - R0 Write new value to the Data Register pointed to by P1 - P0 and R1 - R0 Transfer the contents of the Data Register pointed to by P1 - P0 and R1 - R0 to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P1 - P0 to the Data Register pointed to by R1 - R0 Transfer the contents of the Data Registers pointed to by R1 - R0 of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective Data Registers pointed to by R1 - R0 of all four pots Enable Increment/decrement of the WCR Latch pointed to by P1 - P0 (7) 1/0 = data is one or zero 5 FN8192.4 October 12, 2006 X9409 Figure 3. Two-Byte Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K S T O P Figure 4. Three-Byte Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K 0 0 D5 D4 D3 D2 D1 D0 A C K S T O P Figure 5. Increment/Decrement Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P Figure 6. Increment/Decrement Timing Limits INC/DEC CMD Issued tWRID SCL SDA Voltage Out VW/RW 6 FN8192.4 October 12, 2006 X9409 Figure 7. Acknowledge Response from Receiver SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge START Figure 8. Detailed Potentiometer Block Diagram Serial Data Path Serial Bus Input From Interface Circuitry Register 0 Register 1 8 Register 2 If WCR = 00[H] then VW/RW = VL/RL If WCR = 3F[H] then VW/RW = VH/RH 6 Parallel Bus Input Wiper Counter Register (WCR) Register 3 UP/DN Modified SCL VH/RH C o u n t e r D e c o d e INC/DEC Logic UP/DN CLK VL/RL VW/RW 7 FN8192.4 October 12, 2006 X9409 DETAILED OPERATION All XDCP potentiometers share the serial interface and share a common architecture. Each potentiometer has a Wiper Counter Register and 4 Data Registers. A detailed discussion of the register organization and array operation follows. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Register Descriptions Data Registers, (6-Bit), Nonvolatile: Wiper Counter Register The X9409 contains four Wiper Counter Registers, one for each XDCP potentiometer. The Wiper Counter Register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of the four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The WCR is a volatile register; that is, its contents are lost when the X9409 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, it should be noted this may be different from the value present at power-down. Data Registers Each potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred between any of the four Data Registers and the Wiper Counter Register. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. 8 D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV (MSB) (LSB) Four 6-bit Data Registers for each XDCP. (sixteen 6bit registers in total). - {D5~D0}: These bits are for general purpose not volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0 are automatically moved to the wiper counter register on power-up. Wiper Counter Register, (6-Bit), Volatile: WP5 WP4 WP3 WP2 WP1 WP0 V V V V V V (MSB) (LSB) One 6-bit Wiper Counter Register for each XDCP. (Four 6-bit registers in total.) - {D5~D0}: These bits specify the wiper position of the respective XDCP. The Wiper Counter Register is loaded on power-up by the value in Data Register R0. The contents of the WCR can be loaded from any of the other Data Register or directly by command. The contents of the WCR can be saved in a DR. FN8192.4 October 12, 2006 X9409 Instruction Format Notes: (1) (2) (3) (4) (5) "MACK"/"SACK": stands for the acknowledge sent by the master/slave. "A3 ~ A0": stands for the device addresses sent by the master. "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition. "I": stands for the increment operation, SDA held high during active SCL phase (high). "D": stands for the decrement operation, SDA held low during active SCL phase (high). Read Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction WCR S opcode addresses A C P P 1 0 0 1 0 0 K 1 0 wiper position S (sent by slave on SDA) A W W W W W W C 0 0 P P P P P P K 5 4 3 2 1 0 M A C K S T O P wiper position S (sent by master on SDA) A W W W W W W C 0 0 P P P P P P K 5 4 3 2 1 0 S A C K S T O P Write Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction WCR S opcode addresses A C P P 1 0 1 0 0 0 K 1 0 Read Data Register (DR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction DR and WCR S opcode addresses A C R R P P K 1 0 1 1 1 0 1 0 wiper position S (sent by slave on SDA) A W W W W W W C 0 0 P P P P P P K 5 4 3 2 1 0 M A C K S T O P Write Data Register (DR) device instruction DR and WCR S device type S addresses opcode addresses T identifier A A C R R P P R 0 1 0 1 A A A A 1 1 0 0 3 2 1 0 K 1 0 1 0 T wiper position S (sent by master on SDA) A W W W W W W C 0 0 P P P P P P K 5 4 3 2 1 0 S A C K S T HIGH-VOLTAGE O WRITE CYCLE P Transfer Data Register (DR) to Wiper Counter Register (WCR) S device type device instruction DR and WCR S T identifier addresses opcode addresses A A C R R P P R 0 1 0 1 A A A A 1 1 0 1 3 2 1 0 K 1 0 1 0 T S A C K S T O P Write Wiper Counter Register (WCR) to Data Register (DR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T 9 instruction DR and WCR S opcode addresses A C R R P P 1 1 1 0 K 1 0 1 0 S A C K S T O P HIGH-VOLTAGE WRITE CYCLE FN8192.4 October 12, 2006 X9409 Increment/Decrement Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction WCR S opcode addresses A C P P K 0 0 1 0 0 0 1 0 increment/decrement S (sent by master on SDA) A C I/ I/ I/ I/ K D D . . . . D D S T O P Global Transfer Data Register (DR) to Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction DR S opcode addresses A C R R K 0 0 0 1 1 0 0 0 S A C K S T O P Global Transfer Wiper Counter Register (WCR) to Data Register (DR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction DR S opcode addresses A C R R 1 0 0 0 0 0 K 1 0 WAVEFORM S T O P HIGH-VOLTAGE WRITE CYCLE Guidelines for Calculating Typical Values of Bus Pull-Up Resistors INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don't Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 10 120 100 Resistance (K) SYMBOL TABLE S A C K 80 60 RMIN = VCC MAX =1.8k IOL MIN RMAX = tR CBUS Max. Resistance 40 20 Min. Resistance 0 0 20 40 60 80 100 120 BUS CAPACITANCE (pF) FN8192.4 October 12, 2006 X9409 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias .................... -65C to +135C Storage temperature ......................... -65C to +150C Voltage on SDA, SCL or any address input with respect to VSS ......................... -1V to +7V V = |VH - VL | ........................................................ 5V Lead temperature (soldering, 10s) .................. +300C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial Min. 0C -40C Max. Device +70C +85C X9409-2.7 Supply Voltage (VCC) Limits 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol Parameter Max. Unit End to end resistance tolerance 20 % Power rating 15 mW +3 mA 150 IW Wiper current RW Wiper resistance VTERM Voltage on any VH/RH or VL/RL pin Min. -3 50 VSS Noise Resolution (4) Absolute linearity (1) Relative linearity (2) Temperature coefficient of RTOTAL Typ. VCC Test Conditions 25C, each pot @5V, 2.5K IW = 3mA, VCC = 3V to 5V V VSS = 0V -120 dBV Ref: 1kHz 1.6 % -1 +1 MI(3) -0.2 +0.2 MI(3) 300 Ratiometric temp. coefficient Potentiometer capacitances 10/10/25 IAL RH, RL, RW leakage current 0.1 Vw(n + 1) - [Vw(n) + MI] ppm/C 20 CH/CL/CW Vw(n)(actual) - Vw(n)(expected) 10 ppm/C pF See Macro Model A VIN = VSS to VCC. Device is in stand-by mode. Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (VH - VL)/63, single pot 11 FN8192.4 October 12, 2006 X9409 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. ICC1 VCC supply current (Active) ICC2 Typ. Max. Unit Test Conditions 100 A fSCL = 400kHz, SDA = Open, Other Inputs = VSS VCC supply current (Nonvolatile Write) 1 mA fSCL = 400kHz, SDA = Open, Other Inputs = VSS ISB VCC current (standby) 1 A SCL = SDA = VCC, Addr. = VSS ILI Input leakage current 10 A VIN = VSS to VCC ILO Output leakage current 10 A VOUT = VSS to VCC VIH Input HIGH voltage VCC x 0.7 VCC + 0.5 V VIL Input LOW voltage -0.5 VCC x 0.1 V VOL Output LOW voltage 0.4 V IOL = 3mA ENDURANCE AND DATA RETENTION Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 Years CAPACITANCE Symbol CI/O (4) CIN(4) Test Max. Unit Test Conditions Input/output capacitance (SDA) 8 pF VI/O = 0V Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V POWER-UP TIMING Symbol tr VCC (6) Parameter VCC power-up rate Min. Max. Unit 0.2 50 V/ms POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First VCC, then the potentiometer pins, RH, RL, and RW. The VCC ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until VCC reaches its final value. Notes: (4) This parameter is periodically sampled and not 100% tested (5) tPUR and tPUW are the delays required from the time the (last) power supply (VCC) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (6) Sample tested only. 12 FN8192.4 October 12, 2006 X9409 A.C. TEST CONDITIONS Circuit #3 SPICE Macro Model Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 RTOTAL RH CH CW EQUIVALENT A.C. LOAD CIRCUIT 10pF 5V CL RL 10pF 25pF RW 1533 SDA Output 100pF AC TIMING (over recommended operating condition) Symbol Parameter Min. Max. Unit 400 kHz fSCL Clock frequency tCYC Clock cycle time tHIGH Clock high time 600 ns tLOW Clock low time 1300 ns tSU:STA Start setup time 600 ns tHD:STA Start hold time 600 ns tSU:STO Stop setup time 600 ns tSU:DAT SDA data input setup time 100 ns tHD:DAT SDA data input hold time 30 ns 2500 ns tR SCL and SDA rise time 300 ns tF SCL and SDA fall time 300 ns tAA SCL low to SDA data output valid time 900 ns tDH SDA data output hold time 50 ns Noise suppression time constant at SCL and SDA inputs 50 ns 1300 ns TI tBUF Bus free time (prior to any transmission) tSU:WPA WP, A0, A1, A2 and A3 setup time 0 ns tHD:WPA WP, A0, A1, A2 and A3 hold time 0 ns HIGH-VOLTAGE WRITE CYCLE TIMING Symbol tWR Parameter High-voltage write cycle time (store instructions) 13 Typ. Max. Unit 5 10 ms FN8192.4 October 12, 2006 X9409 XDCP TIMING Symbol tWRPO Parameter Min. Typ. Max. Unit Wiper response time after the third (last) power supply is stable 2 10 s tWRL Wiper response time after instruction issued (all load instructions) 2 10 s tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 2 10 s Note: (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. TIMING DIAGRAMS START and STOP Timing g (START) (STOP) tR tF SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tAA 14 tDH FN8192.4 October 12, 2006 X9409 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers +VR VR VW/RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits NONINVERTING AMPLIFIER VS VOLTAGE REGULATOR + VO - VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 OFFSET VOLTAGE ADJUSTMENT R1 COMPARATOR WITH HYSTERESIS R2 VS VS - + 100k - VO + 10k R1 } 10k } TL072 10k VO R2 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) VS 15 FN8192.4 October 12, 2006 X9409 Application Circuits (continued) ATTENUATOR FILTER C VS R2 R1 VO - - VS + R VO + R3 R4 R2 All RS = 10k R1 GO = 1 + R2/R1 fc = 1/(2RC) V O = G VS -1/2 G +1/2 R2 } VS R1 } INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT R2 C1 - VS VO + + - R1 ZIN VO = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 FUNCTION GENERATOR C R2 - + R1 - } RA + } RB frequency R1, R2, C amplitude RA, RB 16 FN8192.4 October 12, 2006 X9409 XDCP Timing (for All Load Instructions) (STOP) SCL LSB SDA tWRL VWx XDCP Timing (for Increment/Decrement Instruction) SCL SDA Wiper Register Address Inc/Dec Inc/Dec tWRID VW/RW Write Protect and Device Address Pins Timing (START) SCL (STOP) ... (Any Instruction) ... SDA ... tSU:WPA tHD:WPA WP A0, A1 A2, A3 17 FN8192.4 October 12, 2006 X9409 Small Outline Plastic Packages (SOIC) M24.3 (JEDEC MS-013-AD ISSUE C) N 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- A D h x 45 -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e B S 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N NOTES: MILLIMETERS 24 0 24 8 0 7 8 Rev. 1 4/06 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 18 FN8192.4 October 12, 2006 X9409 Small Outline Package Family (SO) A D h X 45 (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL "X" 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4 4 DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150") SO16 (0.300") (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference N 8 14 16 Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 19 FN8192.4 October 12, 2006 X9409 Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE (N/2)+1 N PIN #1 I.D. E E1 0.20 C B A 1 (N/2) B 2X N/2 LEAD TIPS TOP VIEW 0.05 e C H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 0.05 A2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. E 12/02 NOTES: SEATING PLANE 0.10 M C A B b 0.10 C N LEADS SIDE VIEW 1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions "D" and "E1" are measured at dAtum Plane H. SEE DETAIL "X" c 4. Dimensioning and tolerancing per ASME Y14.5M-1994. END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0 - 8 DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN8192.4 October 12, 2006