1
®X9409
Low Noise/Low Power/2-Wire Bus
Quad Digitally Controlled Potentiometers
(XDCP™)
FEATURES
• Four potentiometers per package
• 64 resistor taps
• 2-wire serial interface for write, read, and trans-
fer operations of the potentiometer
•50Ω Wiper resistance, typical at 5V.
• Four non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on
power-up.
• Standby current < 1µA typical
•System V
CC: 2.7V to 5.5V operation
•10kΩ, 2.5kΩ End to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per
register
• Low power CMOS
• 24 Ld SOIC, 24 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9409 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
Interface
and
Control
Circuitry
SCL
SDA
A0
A1
A2
A3
R0R1
R2R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
VH1/
VL1/RL1
R0R1
R2R3
Wiper
Counter
Register
(WCR)
VH0/RHO
Data
8
VW0/
VW1/
R0R1
R2R3
Resistor
Array
VH2/RH2
VL2/RL2
VW2/RW2
R0R1
R2R3
Resistor
Array
VH3/RH3
VL3/RL3
VW3/RW3
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR) Pot 3
Pot 2
WP
RW1
RH1
RWO
VL0/
RLO
Pot 0
VCC
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Data Sheet FN8192.4October 12, 2006
2FN8192.4
October 12, 2006
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9409.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Device Address (A0 - A3)
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9409. A maximum of 16 devices may occupy the
2-wire serial bus.
Potentiometer Pins
VH0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3
The VH/RH and VL/RL inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
VW0/RW0 - VW3/RW3
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
PIN NAMES
Ordering Information
PART NUMBER PART MARKING VCC LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(kΩ)
TEMP
RANGE
(°C) PACKAGE PKG.
DWG. #
X9409WS24I-2.7* X9409WS G 2.7 to 5.5 10 -40 to 85 24 Ld SOIC (300 mil) M24.3
X9409WS24IZ-2.7* (Note) X9409WS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027
X9409WV24-2.7 X9409WV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044
X9409WV24Z-2.7 (Note) X9409WV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9409WV24I-2.7* X9409WV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044
X9409WV24IZ-2.7* (Note) X9409WV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die att ach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Symbol Description
SCL Serial Clock
SDA Serial Data
A0-A3 Device Address
VH0/RH0 - VH3/RH3,
VL0/RL0 - VL3/RL3
Potentiometer Pin
(terminal equivalent)
VW0/RW0 - VW3/RW3 Potentiometer Pin
(wiper equivalent)
WP Hardware Write Protection
VCC System Supply Voltage
VSS System Ground (Digital)
NC No Connection
X9409
3FN8192.4
October 12, 2006
PIN CONFIGURATION
PRINCIPLES OF OPERATION
The X9409 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9409 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9409 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9409 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (tHIGH). The X9409 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9409 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9409 will respond with a final acknowledge.
Array Description
The X9409 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time. These switches are
VCC
VL0/RL0
VH0/RH0
WP
SDA
A1
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
NC
VL3/RL3
VH3/RH3
VW3/RW3
A0
NC
A3
SCL
VL2/RL2
VH2/RH2
SOIC
X9409
VSS
VW0/RW0
14
13
11
12
A2
VL1/RL1
VH1/RH1
VW1/RW1 VW2/RW2
NC
SDA
A1
VH2/RH2
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
WP
A2
VW0/RW0
VCC
NC
VL3/RL3
VH3/RH3
VW3/RW3
TSSOP
X9409
VW2/RW2
14
13
11
12
A3
VL1/RL1
VH1/RH1
VW1/RW1
A0
NC
VH0/RH0
NC
SCL
VL2/RL2
VL0/RL0
VSS
X9409
4FN8192.4
October 12, 2006
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9409
this is fixed as 0101[B].
Figure 1. Slave Address
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0 - A3 inputs. The X9409 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9409 to respond with an acknowledge. The
A0 - A3 inputs can be actively driven by CMOS input
signals or tied to VCC or VSS.
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical nonvolatile write cycle time.
Once the stop condition is issued to indicate the end of
the nonvolatile write command the X9409 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9409 is
still busy with the write operation no ACK will be
returned. If the X9409 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
Flow 1. ACK Polling Sequence
Instruction Structure
The next byte sent to the X9409 contains the
instruction and register pointer information. The format
is shown in Figure 2.
Figure 2. Instruction Byte Format
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued. The last bits (P1, P0)
select which one of the four potentiometers is to be
affected by the instruction.
100
A3 A2 A1 A0
Device Type
Identifier
Device Address
1
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Further
Operation?
Issue
Instruction Issue STOP
NO
YES
YES
Proceed
Issue STOP
NO
Proceed
I1I2I3 I0 R1 R0 P1 P0
Pot Select
Register
Select
Instructions
X9409
5FN8192.4
October 12, 2006
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed tWRL. A transfer from the Wiper
Counter Register (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9409; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected Data
Register). The sequence of operations is shown in
Figure 4.
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9409 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(tHIGH) while SDA is HIGH, the selected wiper will
move one resistor segment towards the VH/RH
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the VL/RL terminal. A detailed
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
Table 1. Instruction Set
Note: (7) 1/0 = data is one or zero
Instruction
Instruction Set
OperationI3I2I1I0R1R0P1P0
Read Wiper Counter
Register
10010 0P
1P0Read the contents of the Wiper Counter Register
pointed to by P1 - P0
Write Wiper Counter
Register
10100 0P
1P0Write new value to the Wiper Counter Register
pointed to by P1 - P0
Read Data Register 1 0 1 1 R1R0P1P0Read the contents of the Data Register pointed to
by P1 - P0 and R1 - R0
Write Data Register 1 1 0 0 R1R0P1P0Write new value to the Data Register pointed to
by P1 - P0 and R1 - R0
XFR Data Register to
Wiper Counter Register
1101R
1R0P1P0Transfer the contents of the Data Register
pointed to by P1 - P0 and R1 - R0 to its associated
Wiper Counter Register
XFR Wiper Counter
Register to Data
Register
1110R
1R0P1P0Transfer the contents of the Wiper Counter
Register pointed to by P1 - P0 to the Data
Register pointed to by R1 - R0
Global XFR Data
Registers to Wiper
Counter Registers
0001R
1R00 0 Transfer the contents of the Data Registers
pointed to by R1 - R0 of all four pots to their
respective Wiper Counter Registers
Global XFR Wiper
Counter Registers to
Data Register
1000R
1R00 0 Transfer the contents of both Wiper Counter
Registers to their respective Data Registers
pointed to by R1 - R0 of all four pots
Increment/Decrement
Wiper Counter Register
00100 0P
1P0Enable Increment/decrement of the WCR Latch
pointed to by P1 - P0
X9409
6FN8192.4
October 12, 2006
Figure 3. Two-Byte Instruction Sequence
Figure 4. Three-Byte Instruction Sequence
Figure 5. Increment/Decrement Instruction Sequence
Figure 6. Increment/Decrement Timing Limits
S
T
A
R
T
0101A3A2A1A0A
C
K
I3 I2 I1 I0 R1 R0 P1 P0 A
C
K
SCL
SDA
S
T
O
P
S
T
A
R
T
0 1 0 1 A3 A2 A1 A0 A
C
K
I3 I2 I1 I0 R1 R0 P1 P0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
0 0 D5 D4 D3 D2 D1 D0
S
T
A
R
T
0 1 0 1 A3 A2 A1 A0 A
C
K
I3 I2 I1 I0 R0 P1 P0 A
C
K
SCL
SDA
S
T
O
P
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
R1
SCL
SDA
VW/RW
INC/DEC
CMD
Issued
Voltage Out
tWRID
X9409
7FN8192.4
October 12, 2006
Figure 7. Acknowledge Response from Receiver
Figure 8. Detailed Potentiometer Block Diagram
SCL from
Data Output
from Transmitter
189
START Acknowledge
Master
Data Output
from Receiver
Serial Data Path
From Interface
Circuitry
Register 0 Register 1
Register 2 Register 3
Serial
Bus
Input
Parallel
Bus
Input
Wiper
Counter
Register
INC/DEC
Logic
UP/DN
CLK
Modified SCL
UP/DN
VH/RH
VL/RL
VW/RW
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
8 6
C
o
u
n
t
e
r
D
e
c
o
d
e
(WCR)
X9409
8FN8192.4
October 12, 2006
DETAILED OPERATION
All XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
has a Wiper Counter Register and 4 Data Registers. A
detailed discussion of the register organization and
array operation follows.
Wiper Counter Register
The X9409 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The Wiper Counter
Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
the four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/ Decrement
instruction. Finally, it is loaded with the contents of its
Data Register zero (DR0) upon power-up.
The WCR is a volatile register; that is, its contents are
lost when the X9409 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-down.
Data Registers
Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Register Descriptions
Data Registers, (6-Bit), Nonvolatile:
Four 6-bit Data Registers for each XDCP. (sixteen 6-
bit registers in total).
– {D5~D0}: These bits are for general purpose not vol-
atile data storage or for storage of up to four differ-
ent wiper values. The contents of Data Register 0
are automatically moved to the wiper counter regis-
ter on power-up.
Wiper Counter Register, (6-Bit), Volatile:
One 6-bit Wiper Counter Register for each XDCP.
(Four 6-bit registers in total.)
– {D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register
R0. The contents of the WCR can be loaded from
any of the other Data Register or directly by com-
mand. The contents of the WCR can be saved in a
DR.
D5 D4 D3 D2 D1 D0
NV NV NV NV NV NV
(MSB) (LSB)
WP5 WP4 WP3 WP2 WP1 WP0
VVVVVV
(MSB) (LSB)
X9409
9FN8192.4
October 12, 2006
Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
WCR
addresses S
A
C
K
wiper position
(sent by slave on SDA) M
A
C
K
S
T
O
P
0101A
3
A
2
A
1
A
0100100P
1
P
000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
WCR
addresses S
A
C
K
wiper position
(sent by master on SDA) S
A
C
K
S
T
O
P
0101A
3
A
2
A
1
A
0101000P
1
P
000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR and WCR
addresses S
A
C
K
wiper position
(sent by slave on SDA) M
A
C
K
S
T
O
P
0101A
3
A
2
A
1
A
01011R
1
R
0
P
1
P
000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR and WCR
addresses S
A
C
K
wiper position
(sent by master on SDA) S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A
3
A
2
A
1
A
01100R
1
R
0
P
1
P
000
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR and WCR
addresses S
A
C
K
S
T
O
P
0101A
3
A
2
A
1
A
01101R
1
R
0
P
1
P
0
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR and WCR
addresses S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A
3
A
2
A
1
A
01110R
1
R
0
P
1
P
0
X9409
10 FN8192.4
October 12, 2006
Increment/Decrement Wiper Counter Register (WCR)
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
WCR
addresses S
A
C
K
increment/decrement
(sent by master on SDA) S
T
O
P
0101A
3
A
2
A
1
A
0001000P
1
P
0
I/
D
I/
D....
I/
D
I/
D
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR
addresses S
A
C
K
S
T
O
P
0101A
3
A
2
A
1
A
00001R
1
R
000
S
T
A
R
T
device type
identifier
device
addresses S
A
C
K
instruction
opcode
DR
addresses S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A
3
A
2
A
1
A
01000R
1
R
000
SYMBOL TABLE Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
WAVEFORM INPUTS OUTPUTS
Must be
steady Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
120
100
80
40
60
20
20 40 60 80 100 120
00
Resistance (K)
BUS CAPACITANCE (pF)
Min.
Resistance
Max.
Resistance
RMAX
= CBUS
tR
RMIN
= IOL MIN
VCC MAX=1.8kΩ
X9409
11 FN8192.4
October 12, 2006
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address
input with respect to VSS......................... -1V to +7V
Δ V = |VH - VL | ........................................................ 5V
Lead temperature (soldering, 10s) .................. +300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as
a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (VH - VL)/63, single pot
RECOMMENDED OPERATING CONDITIONS
Temp Min. Max.
Commercial 0°C+70°C
Industrial -40°C+85
°C
Device Supply Voltage (VCC) Limits
X9409-2.7 2.7V to 5.5V
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
End to end resistance tolerance ±20 %
Power rating 15 mW 25°C, each pot @5V, 2.5K
IW Wiper current -3 +3 mA
RWWiper resistance 50 150 ΩIW = ± 3mA, VCC = 3V to 5V
VTERM Voltage on any VH/RH or VL/RL pin VSS VCC VV
SS = 0V
Noise -120 dBV Ref: 1kHz
Resolution (4) 1.6 %
Absolute linearity (1) -1 +1 MI(3) Vw(n)(actual) - Vw(n)(expected)
Relative linearity (2) -0.2 +0.2 MI(3) Vw(n + 1) - [Vw(n) + MI]
Temperature coefficient of RTOTAL ±300 ppm/°C
Ratiometric temp. coefficient 20 ppm/°C
CH/CL/CWPotentiometer capacitances 10/10/25 pF See Macro Model
IAL RH, RL, RW leakage current 0.1 10 µA VIN = VSS to VCC. Device is
in stand-by mode.
X9409
12 FN8192.4
October 12, 2006
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then the potentiometer pins, RH, RL, and RW. The VCC
ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if
possible. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order
for proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will
not be complete until VCC reaches its final value.
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) tPUR and tPUW are the delays required from the time the (last) power supply (VCC) is stable until the specific instruction can be issued.
These parameters are periodically sampled and not 100% tested.
(6) Sample tested only.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
ICC1 VCC supply current (Active) 100 µA fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ICC2 VCC supply current
(Nonvolatile Write)
1mAf
SCL = 400kHz, SDA = Open,
Other Inputs = VSS
ISB VCC current (standby) 1 µA SCL = SDA = VCC, Addr. = VSS
ILI Input leakage current 10 µA VIN = VSS to VCC
ILO Output leakage current 10 µA VOUT = VSS to VCC
VIH Input HIGH voltage VCC x 0.7 VCC + 0.5 V
VIL Input LOW voltage -0.5 VCC x 0.1 V
VOL Output LOW voltage 0.4 V IOL = 3mA
Parameter Min. Unit
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 Years
Symbol Test Max. Unit Test Conditions
CI/O(4) Input/output capacitance (SDA) 8 pF VI/O = 0V
CIN(4) Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V
Symbol Parameter Min. Max. Unit
tr VCC(6) VCC power-up rate 0.2 50 V/ms
X9409
13 FN8192.4
October 12, 2006
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Circuit #3 SPICE Macro Model
AC TIMING (over recommended operating condition)
HIGH-VOLTAGE WRITE CYCLE TIMING
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
5V
1533Ω
100pF
SDA Output
10pF
RH
RTOTAL
CH
25pF
CW
CL
10pF
RW
RL
Symbol Parameter Min. Max. Unit
fSCL Clock frequency 400 kHz
tCYC Clock cycle time 2500 ns
tHIGH Clock high time 600 ns
tLOW Clock low time 1300 ns
tSU:STA Start setup time 600 ns
tHD:STA Start hold time 600 ns
tSU:STO Stop setup time 600 ns
tSU:DAT SDA data input setup time 100 ns
tHD:DAT SDA data input hold time 30 ns
tRSCL and SDA rise time 300 ns
tF SCL and SDA fall time 300 ns
tAA SCL low to SDA data output valid time 900 ns
tDH SDA data output hold time 50 ns
TINoise suppression time constant at SCL and SDA inputs 50 ns
tBUF Bus free time (prior to any transmission) 1300 ns
tSU:WPA WP, A0, A1, A2 and A3 setup time 0 ns
tHD:WPA WP, A0, A1, A2 and A3 hold time 0 ns
Symbol Parameter Typ. Max. Unit
tWR High-voltage write cycle time (store instructions) 5 10 ms
X9409
14 FN8192.4
October 12, 2006
XDCP TIMING
Note: (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS
START and STOP Timing
g
Input Timing
Output Timing
Symbol Parameter Min. Typ. Max. Unit
tWRPO Wiper response time after the third (last) power supply is stable 2 10 µs
tWRL Wiper response time after instruction issued (all load instructions) 2 10 µs
tWRID Wiper response time from an active SCL/SCK edge (increment/decrement
instruction)
210µs
tSU:STA tHD:STA tSU:STO
SCL
SDA
tR
(START) (STOP)
tF
tRtF
SCL
SDA
tHIGH
tLOW
tCYC
tHD:DAT
tSU:DAT tBUF
SCL
SDA
tDH
tAA
X9409
15 FN8192.4
October 12, 2006
X9409
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
VW/RW
+VR
I
Three terminal Potentiometer;
Variable voltage divider Two terminal Variable Resistor;
Variable current
NONINVERTING AMPLIFIER VOLTAGE REGULATOR
OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
100kΩ
10kΩ10kΩ
10kΩ
VS
TL072
+
–
VSVO
R2
R1
}
}
16 FN8192.4
October 12, 2006
X9409
Application Circuits (continued)
INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
FUNCTION GENERATOR
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
ATTENUATOR FILTER
+
–
VS
VO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2
GO = 1 + R2/R1
fc = 1/(2πRC)
R2
R4All RS = 10kΩ
+
–
VS
R2
R1
R
C
VO
17 FN8192.4
October 12, 2006
XDCP Timing (for All Load Instructions)
XDCP Timing (for Increment/Decrement Instruction)
Write Protect and Device Address Pins Timing
SCL
SDA
VWx
(STOP)
LSB
tWRL
SCL
SDA
VW/RW
tWRID
Wiper Register Address Inc/Dec Inc/Dec
SDA
SCL ...
...
...
WP
A0, A1
A2, A3
tSU:WPA tHD:WPA
(START) (STOP)
(Any Instruction)
X9409
18 FN8192.4
October 12, 2006
X9409
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N24 247
α0° 8° 0° 8° -
Rev. 1 4/06
19 FN8192.4
October 12, 2006
X9409
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1 L
L1
DETAIL X 4° ±4°
SEATING
PLANE
eH
b
C
0.010 BMCA
0.004 C
0.010 BMCA
B
D
(N/2)
1
E1
E
NN (N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL SO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28) TOLERANCE NOTES
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8192.4
October 12, 2006
X9409
Thin Shrink Small Outline Package Family (TSSOP)
N(N/2)+1
(N/2)
TOP VIEW
AD
0.20 C
2X B A
N/2 LEAD TIPS
B
E1
E
0.25 CAB
M
1
H
PIN #1 I.D.
0.05
e
C
0.10 C
N LEADS SIDE VIEW
0.10 CABM
b
c
SEE DETAIL “X”
END VIEW
DETAIL X
A2
0° - 8°
GAUGE
PLANE
0.25
L
A1
A
L1
SEATING
PLANE
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A 1.20 1.20 1.20 1.20 1.20 Max
A1 0.10 0.10 0.10 0.10 0.10 ±0.05
A2 0.90 0.90 0.90 0.90 0.90 ±0.05
b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06
c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06
D 5.00 5.00 6.50 7.80 9.70 ±0.10
E 6.40 6.40 6.40 6.40 6.40 Basic
E1 4.40 4.40 4.40 4.40 4.40 ±0.10
e 0.65 0.65 0.65 0.65 0.65 Basic
L 0.60 0.60 0.60 0.60 0.60 ±0.15
L1 1.00 1.00 1.00 1.00 1.00 Reference
Rev. E 12/02
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
