PTFA180701E
PTFA180701F
All published data at TCASE = 25°C unless otherwise indicated
ESD: Electrostatic discharge sensitive device—observe handling precautions!
Data Sheet 1 of 11 Rev. 03.1, 2009-02-20
Description
The PTFA180701E and PTFA180701F are 70-watt LDMOS FETs designed
for GSM and GSM EDGE power amplifier applications in the 1805 MHz to
1880 MHz band. Features include input and output matching, and thermally-
enhanced packages with slotted or earless flanges. Manufactured with
Infineon's advanced LDMOS process, these devices provide excellent
thermal performance and superior reliability.
Features
Thermally-enhanced packages, Pb-free and
RoHS-compliant
Broadband internal matching
Typical EDGE performance
- Average output power = 44 dBm
- Gain = 16.5 dB
- Efficiency = 40.5%
- EVM = 2.0%
Typical CW performance
- Output power at P–1dB = 72 W
- Gain = 15.5 dB
- Efficiency = 59%
Integrated ESD protection: Human Body
Model, Class 2 (minimum)
Excellent thermal stability, low HCI drift
Capable of handling 10:1 VSWR @ 28 V,
70 W (CW) output power
RF Characteristics
EDGE Measurements (not subject to production test—verified by design/characterization in Infineon test fixture)
VDD = 28 V, IDQ = 550 mA, POUT = 44 dBm, ƒ = 1836.6 MHz
Characteristic Symbol Min Typ Max Unit
Error Vector Magnitude EVM RMS 2.0 %
Modulation Spectrum @ 400 kHz ACPR –62 dBc
@ 600 kHz ACPR –76 dBc
Gain Gps 16.5 dB
Drain Efficiency ηD40.5 %
Thermally-Enhanced High Power RF LDMOS FETs
70 W, 1805 – 1880 MHz
*See Infineon distributor for future availability.
EDGE EVM Performance
VDD = 28 V, IDQ = 550 mA, ƒ = 1836.6 MHz
0
1
2
3
4
5
30 32 34 36 38 40 42 44 46
Output Power, avg. (dBm)
EVM RMS (avg. %) .
0
10
20
30
40
50
Drain Efficiency (%)
EVM
Efficiency
PTFA180701E
Package H-36265-2
PTFA180701F
Package H-37265-2
PTFA180701E
PTFA180701F
Data Sheet 2 of 11 Rev. 03.1, 2009-02-20
RF Characteristics (cont.)
Two-tone Measurements (tested in Infineon test fixture)
VDD = 28 V, IDQ = 550 mA, POUT = 60 W PEP, ƒ = 1840 MHz, tone spacing = 1 MHz
Characteristic Symbol Min Typ Max Unit
Gain Gps 15.5 16.5 dB
Drain Efficiency ηD44 45 %
Intermodulation Distortion IMD –30 –29 dBc
DC Characteristics
Characteristic Conditions Symbol Min Typ Max Unit
Drain-Source Breakdown Voltage VGS = 0 V, IDS = 10 mA V(BR)DSS 65 V
Drain Leakage Current VDS = 28 V, VGS = 0 V IDSS 1.0 µA
VDS = 63 V, VGS = 0 V IDSS 10.0 µA
On-State Resistance VGS = 10 V, VDS = 0.1 V RDS(on) 0.125
Operating Gate Voltage VDS = 28 V, ID = 550 mA VGS 2.0 2.5 3.0 V
Gate Leakage Current VGS = 10 V, VDS = 0 V IGSS 1.0 µA
Maximum Ratings
Parameter Symbol Value Unit
Drain-Source Voltage VDSS 65 V
Gate-Source Voltage VGS –0.5 to +12 V
Junction Temperature TJ200 °C
Total Device Dissipation PD201 W
Above 25°C derate by 1.15 W/°C
Storage Temperature Range TSTG –40 to +150 °C
Thermal Resistance (TCASE = 70°C, 70 W CW) RθJC 0.87 °C/W
Ordering Information
Type and Version Package Type Package Description Marking
PTFA180701E V4 H-36265-2 Thermally-enhanced slotted flange, single-ended PTFA180701E
PTFA180701E V4 H-37265-2 Thermally-enhanced earless flange, single-ended PTFA180701F
*See Infineon distributor for future availability.
Data Sheet 3 of 11 Rev. 03.1, 2009-02-20
PTFA180701E
PTFA180701F
Three-Carrier CDMA2000 Performance
VDD = 28 V, IDQ = 550 mA, ƒ = 1840 MHz
0
10
20
30
40
50
60
30 32 34 36 38 40 42 44 46
Output Power, Avg. (dBm)
Drain Efficiency (%)
-70
-65
-60
-55
-50
-45
-40
Adj. Ch. Power Ratio (dBc)
ALT Up
ACP Up
Efficiency
ACP Low
Edge EVM and Modulation Spectrum
vs. Quiescent Current
VDD = 28 V, ƒ = 1836.6 MHz, POUT = 44 dBm
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
0.40 0.50 0.60 0.70
Quiescent Current (A)
EVM RMS (avg. %) .
-90
-80
-70
-60
-50
-40
-30
-20
-10
Modulation Spectrum (dBc)
EVM
400 kHz
600 kHz
Typical Performance (measurements taken in production test fixture)
Intermodulation Distortion vs. Output Power
VDD = 28 V, IDQ = 550 mA, ƒ = 1840 MHz,
tone spacing = 1 MHz
-60
-55
-50
-45
-40
-35
-30
-25
30 35 40 45 50
Output Power, PEP (dBm)
IMD (dBc)
0
10
20
30
40
50
60
70
Efficiency (%)
3rd Order
7th
5th
Efficiency
EDGE Modulation Spectrum Performance
VDD = 28 V, IDQ = 550 mA, ƒ = 1836.6 MHz
-90
-80
-70
-60
-50
-40
30 32 34 36 38 40 42 44 46
Output Power (dBm)
Modulation Spectrum (dBc)
0
10
20
30
40
50
Drain Efficiency (%)
Efficiency
400 kHz
600 kHz
Data Sheet 4 of 11 Rev. 03.1, 2009-02-20
PTFA180701E
PTFA180701F
IM3 vs. Output Power at Selected Biases
VDD = 28 V, ƒ1 = 1849, ƒ2 = 1840 MHz
-60
-55
-50
-45
-40
-35
-30
-25
-20
26 30 34 38 42 46
Output Power, Avg. (dBm)
IMD (dBc)
IDQ = 825 mA
IDQ = 275 mA
IDQ = 550 mA
Power Sweep
VDD = 28 V, ƒ = 1880 MHz
14.5
15.0
15.5
16.0
16.5
17.0
17.5
18.0
35 37 39 41 43 45 47 49
Output Power (dBm)
Power Gain (dB)
IDQ = 825 mA
IDQ = 275 mA
IDQ = 550 mA
Broadband Test Fixture Performance (P–1dB)
VDD = 28 V, IDQ = 550mA
14
15
16
17
18
19
1760 1800 1840 1880 1920
Frequency (MHz)
Gain (dB)
20
30
40
50
60
70
Output Power (dBm) &
Efficiency (%)
Gain
Drain Efficiency
Output Power
CW Broadband Performance
VDD = 28 V, IDQ = 550 mA, POUT = 43 dBm
20
25
30
35
40
45
50
55
1760 1780 1800 1820 1840 1860 1880 1900 1920
Frequency (MHz)
Efficiency (%)
-30
-20
-10
0
10
20
30
40
Gain, Return Loss (dB)
Gain
Return Loss
Efficiency
Typical Performance (cont.)
Data Sheet 5 of 11 Rev. 03.1, 2009-02-20
PTFA180701E
PTFA180701F
Gain & Efficiency vs. Output Power
VDD = 28 V, IDQ = 550 mA, ƒ = 1880 MHz
12
13
14
15
16
17
18
19
20
010 20 30 40 50 60 70 80
Output Power (W)
Gain (dB)
10
16
22
28
34
40
46
52
58
64
Drain Efficiency (%)
Efficiency
Gain
Output Power (P–1dB) vs. Drain Voltage
IDQ = 550 mA, ƒ = 1880 MHz
46
47
48
49
50
24 26 28 30 32
Drain Voltage (V)
Output Power (dBm)
Typical Performance (cont.)
IS-95 CDMA Performance
VDD = 28 V, IDQ = 550 mA, ƒ = 1840 MHz
0
5
10
15
20
25
30
35
40
45
30 32 34 36 38 40 42 44 46
Output Power, Avg. (dBm)
Drain Efficiency (%)
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
Adj. Ch. Power Ratio (dBc)
Efficiency
TCASE = 25°C
TCASE = 90°C
ACP ƒC – 0.75 MHz
ACPR ƒC + 1.98 MHz
Bias Voltage vs. Temperature
Voltage normalized to typical gate voltage,
series show current
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
-20 0 20 40 60 80 100
Case Temperature (°C)
Normalized Bias Voltage (V)
0.15 A
0.44 A
0.73 A
1.10 A
2.20 A
3.30 A
4.41 A
5.51 A
PTFA180701E
PTFA180701F
Data Sheet 6 of 11 Rev. 03.1, 2009-02-20
Frequency Z Source Z Load
MHz RjX RjX
1760 7.9 –10.3 4.6 –1.4
1800 7.4 –10.0 4.5 –1.1
1840 7.0 –9.7 4.5 –0.8
1880 6.5 –9.3 4.4 –0.3
1920 6.1 –8.9 4.3 –0.1
See next page for circuit information
Broadband Circuit Impedance
0.1
0.3
0.2
.
1
0.1
0
.2
<
-
-
-
W
A
V
E
L
0
.0
Z Source
1760 MHz
1920 MHz
Z Load
0.1
0
.0
1760 MHz
1920 MHz
Z0 = 50
Z Source Z Load
G
S
D
PTFA180701E
PTFA180701F
Data Sheet 7 of 11 Rev. 03.1, 2009-02-20
RF_IN
a 1 8 0 7 01e f_s ch
RF_OUT
R3
2K V
C3
0.001µF
C2
0.001µF
Q1
BCP56
R2
1.3KV
QQ1
LM7805
C1
0.001µF
R5
10 V
R4
2K V
R1
1.2KV
C8
10pF
l1
l6
R8
10 V
DUT
C6
0.01µF
C5
0.1µF
C4
10µF
35V
C7
10pF
R7
1KV
R6
1K V
C9
10pF
C10
1µF
C11
100µF
50V
C12
1.2pF
C13
10pF
l2l3l4l5l8l9l13 l14 l15
l7
l12
l10
l11
VDD
Reference Circuit
Reference circuit schematic for 1840 MHz
Circuit Assembly Information
DUT PTFA180701E or PTFA180701F LDMOS Transistor
PCB 0.76 mm [.030"], εr = 3.48 Rogers, RO4350 1 oz. copper
Microstrip Electrical Characteristics at 1840 MHz1Dimensions: L x W ( mm) Dimensions: L x W (in.)
l10.034 λ, 50.0 3.33 x 1.70 0.131 x 0.067
l20.149 λ, 50.0 14.68 x 1.70 0.578 x 0.067
l30.014 λ, 10.2 1.27 x 13.28 0.050 x 0.523
l40.044 λ, 7.1 3.86 x 19.61 0.152 x 0.772
l50.014 λ, 7.1 1.27 x 19.61 0.050 x 0.772
l60.012 λ, 78.0 1.22 x 0.74 0.048 x 0.029
l70.115 λ, 65.0 11.51 x 1.07 0.453 x 0.042
l80.016 λ, 8.9 1.37 x 15.34 0.054 x 0.604
l90.090 λ, 8.9 8.13 x 15.34 0.320 x 0.604
l10, l11 0.020 λ, 21.8 1.91 x 5.36 0.075 x 0.211
l12 0.162 λ, 64.0 16.18 x 1.12 0.637 x 0.044
l13 0.042 λ, 50.0 4.11 x 1.70 0.162 x 0.067
l14 0.074 λ, 50.0 7.29 x 1.70 0.287 x 0.067
l15 0.032 λ, 50.0 3.12 x 1.70 0.123 x 0.067
1Electrical characteristics are rounded
PTFA180701E
PTFA180701F
Data Sheet 8 of 11 Rev. 03.1, 2009-02-20
QQ1
C3 C1
R2
C2
R1
R5
R3
C5
R8
R6 R7
C7
C10
C6
C9
C12
C11
C8
C13
A180701_01 RO4350
a180701ef_assy
LM
RF_IN RF_OUT
VDD
R4
C4
Q1
Reference Circuit (cont.)
Reference circuit assembly diagram* (not to scale)
Component Description Suggested Manufacturer P/N or Comment
C1, C2, C3 Capacitor, 0.001 µF Digi-Key PCC1772CT-ND
C4 Tantalum capacitor, 10 µF, 35 V Digi-Key 399-1655-2-ND
C5 Capacitor, 0.1 µF Digi-Key PCC104BCT-ND
C6 Capacitor, 0.01 µF ATC 200B 103
C7, C9 Ceramic capacitor, 10 pF ATC 100B 100
C8, C13 Ceramic capacitor, 10 pF ATC 100A 100
C10 Ceramic capacitor, 1 µF Digi-Key 445-1411-1-ND
C11 Electrolytic capacitor, 100 µF, 50 VDigi-Key PCE3718CT-ND
C12 Ceramic capacitor, 1.2 pF ATC 100B 1R2
Q1 Transistor Infineon Technologies BCP56
QQ1 Voltage regulator National Semiconductor LM7805
R1 Chip resistor 1.2 k-ohms Digi-Key P1.2KGCT-ND
R2 Chip resistor 1.3 k-ohms Digi-Key P1.3KGCT-ND
R3 Chip resistor 2 k-ohms Digi-Key P2KECT-ND
R4 Potentiometer 2 k-ohms Digi-Key 3224W-202ETR-ND
R5, R8 Chip resistor 10 ohms Digi-Key P10ECT-ND
R6, R7 Chip resistor 1 k-ohms Digi-Key P1KECT-ND
*Gerber files for this circuit available on request.
PTFA180701E
PTFA180701F
Data Sheet 9 of 11 Rev. 03.1, 2009-02-20
Diagram Notes—unless otherwise specified:
1. Lead thickness: 0.10 +0.051/–0.025 [.004 +.002/–.001].
2. All tolerances ± 0.127 [.005] unless specified otherwise.
3. Pins: D = drain, S = source, G = gate.
4. Interpret dimensions and tolerances per ASME Y14.5M-1994.
5. Primary dimensions are mm. Alternate dimensions are inches.
6. Gold plating thickness:
S, D, G - flange & leads: 1.14 ± 0.38 micron [45 ± 15 microinch]
Package Outline Specifications
Package H-36265-2
Find the latest and most complete information about products and packaging at the Infineon Internet page
http://www.infineon.com/products
20.31
[.800]
10.16±0.25
[.400±.010]
FLANGE 9.78
[.385]
2x 7.11
[.280]
2X 7.11
[.280]
15.23
[.600]
4X R1.52
[R.060]
C
L
C
L
(45° X 2.03
[.080])
S
D
G
LID 10.16±0.25
[.400±.010]
0.0381 [.0015] -A-
3.56±0.38
[.140±.015
1.02
[.040]
SPH 1.57
[.062]
2007-11-16_h-36+37265_POs.vsd_h-36265-2
2X R1.60
[R.063]
15.34±0.51
[.604±.020]
2.59±0.51
[.102±.020]
PTFA180701E
PTFA180701F
Data Sheet 10 of 11 Rev. 03.1, 2009-02-20
Package Outline Specifications (cont.)
Package H-37265-2
Diagram Notes—unless otherwise specified:
1. Lead thickness: 0.10 +0.051/–0.025 [.004 +.002/–.001].
2. All tolerances ± 0.127 [.005] unless specified otherwise.
3. Pins: D = drain, S = source, G = gate.
4. Interpret dimensions and tolerances per ASME Y14.5M-1994.
5. Primary dimensions are mm. Alternate dimensions are inches.
6. Gold plating thickness:
S, D, G - flange & leads: 1.14 ± 0.38 micron [45 ± 15 microinch]
Find the latest and most complete information about products and packaging at the Infineon Internet page
http://www.infineon.com/products
071119_h-36+37265_POs_h-37265-2
(45° X 2.03
[.080])
2.59±0.51
[.102±.020]
S
D
G
LID 10.16±0.25
[.400±.010]
FLANGE 10.16
[.400]
2X 7.11
[.280]
LID
10.16±0.25
[.400±.010]
10.16
[.400]
1.02
[.040]
3.56±.38
[.140±.015]
SPH 1.57
[.062]
10.16
[.400]
15.34±.51
[.604±.020]
FLANGE
4X R0.63
[R.025] MAX
|0.025 [.001]|-A-
C
L
C
L
Data Sheet 11 of 11 Rev. 03.1, 2009-02-20
PTF180701E/F
Confidential, Limited Internal Distribution
Revision History: 2009-02-20 Data Sheet
Previous Version: 2006-08-10, Data Sheet
Page Subjects (major changes since last revision)
1, 3, 9, 10 Update to product V4, with new package technologies. Update package outline diagrams.
8Fixed typing error
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GOLDMOS® is a registered trademark of Infineon Technologies AG.
Edition 2009-02-20
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
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question, please contact the nearest Infineon Technologies Office.
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