INTEGRATED CIRCUITS DIVISION
DS-IX21844-R01 www.ixysic.com 1
Driver Characteristics
Features
•Floating Channel for Bootstrap Operation to +600V
with an Absolute Maximum Rating of +700V
•Programmable Dead-Time
•Outputs Can Source 1.4A and Sink 1.8A
•Gate Drive Supply Range From 10V to 20V
•Tolerant to Negative Voltage Transients:
dV/dt Immune
•3.3V and 5V Logic Compatible
•Undervoltage Lockout for Both High-side and
Low-Side Outputs
•Matched Propagation Delays
Applications
•Switch Mode Power Supply
•Motor Driver Inverter
•DC/DC Converter
•Uninterruptible Power Supplies (UPS)
Description
The IX21844 is a high voltage IC that can drive high
speed MOSFETs and IGBTs that operate up to
+600V. The IX21844 is configured with dependent
high-side and low side referenced output channels
which can source 1.4A and sink 1.8A. The floating
high-side channel can drive an N-channel power
MOSFET or IGBT 600V from the common reference.
Manufactured on IXYS Integrated Circuits Division's
proprietary high-voltage BCDMOS on SOI (silicon on
isolator) process, the IX21844 is extremely robust and
virtually immune to negative transients. The UVLO
circuit prevents the turn-on of the MOSFET or IGBT
until there is sufficient VBS or VCC supply voltage. A
programmable dead-time can be set between 400ns
and 5us to insure that both the high-side and low-side
power MOSFET or IGBT are not enabled at the same
time. Propagation delays are matched for use in high
frequency applications.
The IX21844 is available in 14-pin DIP and 14-pin
SOIC (narrow body) packages. The 14-pin SOIC
(narrow body) package is also available in tape & reel.
Ordering Information
IX21844 Functional Block Diagram
Parameter Rating Units
VOFFSET 600 V
IO +/- (Source/Sink) 1.4 / 1.8 A
VBIAS 10-20 V
Part Description
IX21844G 14-Pin DIP (25/Tube)
IX21844N 14-Pin SOIC (Narrow Body) (50/Tube)
IX21844NTR 14-Pin SOIC (Narrow Body) (2000/Reel)
Level
Shift
VSS / COM
LS Delay
Control
Level
Shift
VSS / COM
UVLO
High
Voltage
Level
Shift
UVLO
Pulse
Generator R
R
S
QBuffer
IN
DT
VSS
VB
HO
VS
VCC
LO
COM
Input
&
Dead-Time
Control Logic
Buffer
+5V
SD
IX21844
High Voltage Half-Bridge
Gate Driver
INTEGRATED CIRCUITS DIVISION
IX21844
2www.ixysic.com R01
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin Description (DIP & SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6 Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.7 Test Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
INTEGRATED CIRCUITS DIVISION
IX21844
R01 www.ixysic.com 3
1 Specifications
1.1 Package Pinout
1.2 Pin Description (DIP & SOIC)
IN 1
VCC 7
VSS 3
COM 5
LO 6
DT 4
14 N/C
8 N/C
13 VB
12 HO
10 N/C
9 N/C
11 VS
SD 2
Pin# Name Description
1IN
Logic input for both high-side gate
drive output (HO) and low-side gate
drive output (LO). In phase with HO.
2SD
Shut-down logic input. Active low.
3VSS Logic ground
4DT
Programmable Dead-Time input
5COM
Low-side return
6LO
Low-side gate drive output
7VCC Low-side and logic supply
8N/C No connection
9N/C No connection
10 N/C No connection
11 VSHigh-side floating supply return
12 HO High-side gate drive output
13 VBHigh-side floating supply
14 N/C No connection
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IX21844
1.3 Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM.
1.4 Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions. The VS and VSS offset ratings
are tested with all supplies biased at a 15V differential.
Parameter Symbol Min Max Units
High-Side Floating Absolute Voltage VB-0.3 700
V
High-Side Floating Supply Offset Voltage VSVB-20 VB+0.3
High-Side Floating Output Voltage VHO VS-0.3 VB+0.3
Low-Side and Logic Fixed Supply Voltage VCC -0.3 20
Low-Side Output Voltage VLO -0.3 VCC+0.3
Programmable Dead-Time Pin Voltage DT VSS-0.3 VCC+0.3
Logic Input Voltage VIN, VSD VSS-0.3 VCC+0.3
Logic ground VSS VCC-20 VCC+0.3
Allowable Offset Supply Voltage Transient dVS/dt -50V/ns
Package Power Dissipation @ TA 25°C 14-Pin PDIP PD -1.6
W
14-Pin SOIC -1
Thermal Resistance, Junction to Ambient 14-Pin PDIP RJA
-75
°C/W
14-Pin SOIC -120
Junction Temperature TJ-150
°C
Storage Temperature TS-50 150
Lead Temperature (Soldering, 10 Seconds) TL-300
Parameter Symbol Min Max Units
High-Side Floating Supply Absolute Voltage VBVS+10 VS+20
V
High-Side Floating Supply Offset Voltage VS-5 600
High-Side Floating Output Voltage VHO VSVB
Low-Side and Logic Fixed Supply Voltage VCC 10 20
Low-Side Output Voltage VLO 0VCC
Logic Input Voltage VIN, VSD VSS VSS + 5
Programmable Dead-Time Pin Voltage DT VSS VCC
Logic Ground VSS -5 5
Ambient Temperature T
A-40 +125 °C
INTEGRATED CIRCUITS DIVISION
IX21844
R01 www.ixysic.com 5
1.5 Static Electrical Characteristics
VBIAS (VCC, VBS)=15V, VSS=COM, DT=VSS, and TA=25°C unless otherwise specified. The VIL, VIH, and IIN
parameters are referenced to VSS/COM and are applicable to the respective input leads: IN and SD. VO and IO are
referenced to COM and are applicable to the respective output leads: HO and LO.
1.6 Dynamic Electrical Characteristics
VBIAS (VCC, VBS)=15V, CL=1000pF, TA=25°C, DT=VSS, and VSS=COM unless otherwise specified.
Parameter Conditions Symbol Min Typ Max Units
Logic “1” Input Voltage
VCC=10V to 20V
VIH 2--
V
Logic “0” Input Voltage VIL --0.8
SD Input Positive Going Threshold VSD,TH+ 2- -
SD Input Negative Going Threshold VSD,TH- --0.8
High Level Output Voltage, VBIAS - VOIO=0A VOH --2.5
Low Level Output Voltage, VOIO=20mA VOL --0.2
Offset Supply Leakage Current VB=VS=600VILK -3360
A
Quiescent VBS Supply Current
VIN=0V or 5VIQBS 20 87 150
Quiescent VCC Supply Current IQCC 0.4 1.8 2.2 mA
Logic “1” Input Bias Current IN=5VIIN+-3560
A
Logic “0” Input Bias Current IN=0VIIN---1
SD Logic “1” Input Bias Current VSD=5VISD+ --30A
SD Logic “0” Input Bias Current VSD=0VISD- -1560A
VCC and VBS Supply
Under-voltage Positive Going Threshold
-
VCCUV+
VBSUV+
88.69.8
V
VCC and VBS Supply
Under-voltage Negative Going Threshold
VCCUV-
VBSUV-
7.4 7.9 9
Hysteresis
VCCUVH
VBSUVH
0.3 0.7 -
Output High Short Circuit Pulsed Current VO=0V, PW<10sIO+1.4 2.2 - A
Output Low Short Circuit Pulsed Current VO=15V, PW<10sIO-1.8 2.5 -
Parameter Conditions Symbol Min Typ Max Units
Turn-On Propagation Delay VS=0Vton -560900
ns
Turn-Off Propagation Delay VS=0V or 600Vtoff -200400
Shutdown propagation Delay - tSD -225400
Delay Matching, HS & LS Turn-on MTon - 0 90
Delay Matching, HS & LS Turn-off MToff - 0 40
Turn-On Rise Time VS=0Vtr-2360
Turn-Off Fall Time tf-1435
Dead-Time: LO Turn-off to HO Turn-on (DTLO-HO)
& HO Turn-off to LO Turn-on (DTHO-LO)
RDT=0DT 280 355 520
RDT=200k456s
Dead-Time Matching: (DTLO-HO) - (DTHO-LO)RDT=0MDT -050
ns
RDT=200k-0600
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IX21844
1.7 Test Waveforms
1.7.1 Switching Time Test Circuit
1.7.2 Input/Output Timing Diagram
1.7.3 Shutdown Waveform Definition
1.7.4 Dead-Time Waveform Definition
1.7.5 Delay Matching Waveform Definitions
1.7.6 Switching Time Waveform Definitions
1.7.7 Truth Table
1
2
3 VSS
4 DT
5 COM
6
7 VCC
14
13
12
VS 11
10
9
8
10μF0.1μFCL
10μF0.1μF
CL
IN
SD
LO
VCC=15V
VB=15V
HO
IN
SD
HO
LO
SD
HO
LO
50%
90%
t
sd
IN
HO
LO
50% 50%
10%
10%
90%
90%
DT
LO-HO
DT
HO-LO
MDT= DT
LO-HO
- DT
HO-LO
IN SD HO LO
11
HL
01LH
X0LL
LO HO
MT MT
10%
90%
LO HO
IN
(LO)
IN
(HO)
50% 50%
IN(LO)
IN(HO)
LO
HO
50% 50%
10% 10%
90% 90%
toff
ton trtf
INTEGRATED CIRCUITS DIVISION
IX21844
R01 www.ixysic.com 7
2 Performance Characteristics
Temperature (ºC)
-50 0 50 100 150
Delay (ns)
300
400
500
600
700
800
900
1000
Turn-On Propagation Delay
vs. Temperature
-25 25 75 125
Supply Voltage (V)
10 12 14 16 1820
Delay (ns)
300
400
500
600
700
800
900
1000
Turn-On Propagation Delay
vs. VBIAS Supply Voltage
Supply Voltage (V)
10 12 14 16 1820
Delay (ns)
0
100
200
300
400
500
Turn-Off Propagation Delay
vs. VBIAS Supply Voltage
Supply Voltage (V)
10 12 14 16 1820
Rise Time (ns)
0
10
20
30
40
50
Turn-On Rise Time
vs. VBIAS Supply Voltage
Temperature (ºC)
Delay (ns)
0
100
200
300
400
500
Turn-Off Propagation Delay
vs. Temperature
-50 0 50 100 150-25 25 75 125
Temperature (ºC)
Rise Time (ns)
0
10
20
30
40
50
Turn-On Rise Time
vs. Temperature
-50 0 50 100 150-25 25 75 125
Temperature (ºC)
Fall Time (ns)
0
10
20
30
40
50
Turn-Off Fall Time
vs. Temperature
-50 0 50 100 150-25 25 75 125
Supply Voltage (V)
10 12 14 16 1820
Fall Time (ns)
0
10
20
30
40
50
Turn-Off Fall Time
vs. VBIAS Supply Voltage
Supply Voltage (V)
10 12 14 16 1820
Deadtime (ns)
0
100
200
300
400
500
600
Deadtime
vs. VBIAS Supply Voltage
(RDT=0Ω)
R
DT
(kΩ)
0 50 100 150 200
Deadtime (μs)
0
1
2
3
4
5
6
Deadtime
vs. RDT
Temperature (ºC)
Deadtime (ns)
0
100
200
300
400
500
600
Deadtime
vs. Temperature
(RDT=0Ω)
-50 0 50 100 150-25 25 75 125
Supply Voltage (V)
10 12 14 16 1820
Delay (ns)
0
50
100
150
200
250
300
350
400
SD Propagation Delay
vs. VBIAS Supply Voltage
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IX21844
Supply Voltage (V)
10 12 14 16 1820
Threshold (V)
0
1
2
3
4
5
SD Input Positive Going Threshold
vs. VBIAS Supply Voltage
Temperature (ºC)
Delay (ns)
0
50
100
150
200
250
300
350
400
SD Propagation Delay
vs. Temperature
-50 0 50 100 150-25 25 75 125
Temperature (ºC)
Threshold (V)
0
1
2
3
4
5
SD Input Positive Going Threshold
vs. Temperature
-50 0 50 100 150-25 25 75 125
Temperature (ºC)
Threshold (V)
0
1
2
3
4
5
SD Input Negative Going Threshold
vs. Temperature
-50 0 50 100 150-25 25 75 125
Supply Voltage (V)
10 12 14 16 1820
Threshold (V)
0
1
2
3
4
5
SD Input Negative Going Threshold
vs. VBIAS Supply Voltage
Temperature (ºC)
UV Threshold (-) (V)
VCC and VBS Undervoltage Threshold (-)
vs. Temperature
-50 0 50 100 150-25 25 75 125
0
3
6
9
12
15
Supply Voltage (V)
10 12 14 16 1820
Supply Current (μA)
0
50
100
150
200
250
VBS Floating Supply Current
vs. VBS Floating Supply Voltage
Temperature (ºC)
UV Threshold (+) (V)
0
3
6
9
12
15
VCC and VBS Undervoltage Threshold (+)
vs Temperature
-50 0 50 100 150-25 25 75 125
Temperature (ºC)
Supply Current (μA)
0
50
100
150
200
250
VBS Supply Current
vs. Temperature
-50 0 50 100 150-25 25 75 125
Temperature (ºC)
Supply Current (mA)
0
1
2
3
4
5
VCC Supply Current
vs. Temperature
(VCC=15V)
-50 0 50 100 150-25 25 75 125
Supply Voltage (V)
10 12 14 16 1820
Supply Current (mA)
0
1
2
3
4
5
VCC Supply Current
vs. VCC Supply Voltage
Temperature (ºC)
Leakage Current (μA)
0
25
50
75
100
Offset Supply Leakage Current
vs. Temperature
-50 0 50 100 150-25 25 75 125
INTEGRATED CIRCUITS DIVISION
IX21844
R01 www.ixysic.com 9
Temperature (ºC)
Bias Current (μA)
0
20
40
60
80
100
Logic "1" Input Bias Current
vs. Temperature
-50 0 50 100 150-25 25 75 125
Supply Voltage (V)
10 12 14 16 1820
Bias Current (μA)
0
20
40
60
80
100
Logic "1" Input Bias Current
vs. VCC Supply Voltage
Supply Voltage (V)
10 12 14 16 1820
Bias Current (μA)
0
1
2
3
4
5
Logic "0" Input Bias Current
vs. VCC Supply Voltage
Supply Voltage (V)
10 12 14 16 1820
Input Voltage (V)
0
1
2
3
4
5
6
Logic "1" Input Voltage
vs. VCC Supply Voltage
Temperature (ºC)
Bias Current (μA)
0
1
2
3
4
5
Logic "0" Input Bias Current
vs. Temperature
-50 0 50 100 150-25 25 75 125
Temperature (ºC)
Input Voltage (V)
0
1
2
3
4
5
6
Logic "1" Input Voltage
vs. Temperature
-50 0 50 100 150-25 25 75 125
Temperature (ºC)
Input Voltage (V)
0
1
2
3
4
5
6
Logic "0" Input Voltage
vs. Temperature
-50 0 50 100 150-25 25 75 125
Supply Voltage (V)
10 12 14 16 1820
Input Voltage (V)
0
1
2
3
4
5
6
Logic "0" Input Voltage
vs. VCC Supply Voltage
Supply Voltage (V)
10 12 14 16 1820
Output Voltage (V)
0
1
2
3
4
5
High Level Output (VBIAS-VO)
vs. VBIAS Supply Voltage
Supply Voltage (V)
10 12 14 16 1820
Output Voltage (V)
0
0.2
0.4
0.6
0.8
1.0
Low Level Output Voltage (VO)
vs. VBIAS Supply Voltage
Temperature (ºC)
Output Voltage (V)
0
1
2
3
4
5
High Level Output Voltage (VBIAS - VO)
vs. Temperature
-50 0 50 100 150-25 25 75 125
Temperature (ºC)
-50 0 50 100 150
Output Voltage (V)
0.0
0.2
0.4
0.6
0.8
1.0
Low Level Output Voltage (VO)
vs. Temperature
-50 0 50 100 150-25 25 75 125
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IX21844
Supply Voltage (V)
10 12 14 16 1820
Output Sink Current (A)
0
1
2
3
4
5
Output Sink Current
vs. VBIAS Supply Voltage
Temperature (ºC)
-50 -25 0 25 50 75 100 125 150
Output Source Current (A)
0
1
2
3
4
5
Output Source Current
vs. Temperature
Supply Voltage (V)
10 12 14 16 1820
Output Source Current (A)
0
1
2
3
4
5
Output Source Current
vs. VBIAS Supply Voltage
Temperature (ºC)
-50 -25 0 25 50 75 100 125 150
Output Source Current (A)
0
1
2
3
4
5
Output Sink Current
vs. Temperature
INTEGRATED CIRCUITS DIVISION
IX21844
R01 www.ixysic.com 11
Figure 1. Typical Connection Diagram
VCC VCC
IN IN
DT
VSS VSS
COM
LO
VS
VB
HO
LOAD
up to 600V
SD SD
RDT
INTEGRATED CIRCUITS DIVISION
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IX21844
3 Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
3.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
3.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
3.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
Device Moisture Sensitivity Level (MSL) Rating
IX21844G / IX21844NMSL 1
Device Maximum Temperature x Time
IX21844G (DIP) 245°C for 30 seconds
IX21844N (SOIC) 260°C for 30 seconds
INTEGRATED CIRCUITS DIVISION
IX21844
R01 www.ixysic.com 13
3.5 Mechanical Dimensions
3.5.1 IX21844G 14-Pin DIP Package
3.5.2 IX21844N 14-Pin SOIC (Narrow Body) Package
NOTES:
1. JEDEC outline: MS-001 AA.
2. This dimension does not include mold flash or
protrusions. Mold flash or protrusions shall not
exceed 0.254 (0.010).
3. Measured at the lead tips with the leads
unconstrained.
4. Pointed or rounded lead tips are preferred to
ease insertion.
5. Distance between leads including dam bar
protrusions to be 0.127 (0.005).
6. Datum plane H coincident with the bottom of
lead where lead exits body.
DIMENSIONS
(min / max)
mm
(inches)
Pin 1
8.509 / 9.525
(0.335 / 0.375)
See Note 3
7.62 BSC
(0.300 BSC)
18.542 / 19.050
(0.730 / 0.750)
See Note 2
2.921 / 3.810
(0.115 / 0.150)
0.381 min
(0.015 min)
0.457 typ
(0.018 typ)
2.542
(0.100)
3.175 / 3.429
(0.125 / 0.135)
1.524 typ
(0.06 typ)
6.223 / 6.477
(0.245 / 0.255)
See Note 2
PCB Hole Pattern
7.62
(0.300)
2.54
(0.100)
1.35
(0.053)
0.85
(0.0335)
Hole Size =
5.334 max
(0.210 max)
H
Seating Plane
0º / 15º
NOTES:
1. JEDEC outline: MS-012 AB Rev F. (reference)
2. Molded package dimension do not include mold flash,
protrusions, or gate burrs. Mold flash, protrusions, and
gate burrs shall not exceed 0.15 (0.006) per side.
3. Lead dimensions do not include inter-lead flash or
protrusions. Inter-lead flash and protrusions shall not
exceed 0.25 (0.010) per side.
DIMENSIONS
min / max
mm
(inches)
PCB Pattern
5.98 / 6.02
(0.235 / 0.237)
8.65 BSC
(0.341 BSC)
See Note 2
0.4 / 0.95
(0.016 / 0.037)
1.27 TYP
(0.05 TYP)
0.15 / 0.25
(0.006 / 0.010)
0.37 x 45º
(0.015 x 45º)
0.31 / 0.51
(0.012 / 0.020)
3.90 BSC
(0.154 BSC)
See Note 3
1.25 min
(0.049 min)
0.10 / 0.25
(0.004 / 0.010)
1.75 max
(0.069 max)
0º / 8º
5.30
(0.209)
1.50
(0.059)
0.60
(0.024) 1.27
(0.05)
INTEGRATED CIRCUITS DIVISION
14 www.ixysic.com R01
IX21844
3.5.3 IX21844NTR Tape & Reel Packaging
NOTES:
1. All dimensions in millimeters
2. 10 sprocket hole pitch cumulative tolerance ± 0.20.
3. Carrier camber is within 1mm in 250mm.
4. Tape material : Black Conductive Polystyrene Alloy.
5. All dimensions meet EIA-481-C requirements.
6. Thickness : 0.30 ± 0.05mm.
7.50 ± 0.10
16.00 ± 0.30
1.75 ± 0.10 8.00 ± 0.104.00 ± 0.10
2.00 ± 0.10
9.65 ± 0.106.50
1.20
2.85 ± 0.10
2.35 ± 0.10
6.55 ± 0.10
3.50
Ø1.50
+0.1, -0
Ø1.50 MIN
Embossment
Embossed Carrier
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
330.2 DIA.
(13.00 DIA.)
For additional information please visit our website at: www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated
Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its
products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other
applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe
property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-IX21844-R01
©Copyright 2013, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/19/2013
