CY7C09079/89/99 SRELISUNS RY CY7C09179/89/99 2 CYPRESS 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM Features + High-speed clock to data access 6.5/7.5/9/12 ns (max.) + Low operating power * True Dual-Ported memory cells which allow simulta- Active= 195 mA (typical) neous access of the same memory location + 6 Flow-Through/Pipelined devices Standby= 0.05 mA (typical) 32K x 8/9 organizations (CY7C09079/179) + Fully synchronous interface for easier operation 64K x 8/9 organizations (CY7C09089/189) + Burst counters increment addresses internally 128K x 8/9 organizations (CY7C09099/1 99) Shorten cycle times * 3 Modes Minimize bus noise Flow-Through Supported in Flow-Through and Pipelined modes Pipelined Dual Chip Enables for easy depth expansion Burst + Automatic power-down + Commercial and Industrial temperature ranges + Available in 100-pin TQFP * Pin-compatible and functionally equivalent to IDT709079, IDT70908, and IDT7039089 + Pipelined output mode on both ports allows fast 100-MHz cycle time * 0.35-micron CMOS for optimum speed/power Logic Block Diagram Ri RW, OE, OER CE CEor CE, CEip FT/Pipe, FT/Piper (4] 8/9 VO 9 _-VOzaL g/g [1] VOgRVOsz aR vO Control vO Control [2] 15A6A7 1567 2] AgAran site Ag-Atanisi6r CLK, Counter/ Counter/ CLK ADS Address True Dual-Ported Address ADS ee Register RAM Array Register A CNTENL Decode Decode CNTENR CNTRST_ CNTRSTp Notes: 1. /O,-1/0, for x8 devices; I/0,-l/O, for x9 devices. 2. Ao-Ay,4 tor 32K; ApAys for 64K; and Aj-Ai, for 128K devices. For the most recent information, visit the Cypress web site af www.cypress.com Cypress Semiconductor Corporation + 3901 North First Street + SanJose CA95134 + 408-943-2600 November 23, 1998FRSECUMINARY CY7C09079/89/99 CY7C09179/89/99 Functional Description The CY7Cogo7g/ag/sg and CY/C09179/89/99 are high speed synchronous CMOS 32K, 64K, and 128K x a/9 du- al-port static RAMs. Two ports are provided, permitting inde- pendent, simultaneous access for reads and writes to any lo- cation in memory*! Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined out- put mode, data is registered for decreased cycle time. Clock to data valid teps = 6.5 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to elimi- nate access latency. In flow-through mode data will be avail- able tep; = 15 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address regis- ter. The internal write pulse width is independent of the LOW- to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. Note: A HIGH on CE, or LOW on CE, for one clock cycle will power down the internal circuitry to reduce the static power consump- tion. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE, LOW and CE, HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's address strobe (ADS). When the port's count enable (CNTEN) is asserted, the address counter will incrernent on each LOW-to-HIGH transi- tion of that ports clock signal. This will read/write_one word fromAnto each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter reset (CNTRST} is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatoack (TQFP} packages. 3. When writing simultaneously to the same location, the final value cannot be guaranteed.Pin Configurations FRSECUMINARY CY7C09079/89/99 CY7C09179/89/99 100-Pin TQFP (Top View) jt cc = = i E z Bf bstsses jam 2222228 6 z & le 625 2 = AEA i Hn nn ! wet a oO 90 100 99 98 97 96 95 94 93 97 91 88 87 86 85 84 83 82 81 80 79 78 77 76 nc Cl) 1 7 [_] nc nc [-] 2 74 [-] no ar_(l_] 3 73 [~_] avr as_Ci_] 4 72 [__] aan ao. CZ) 5 71 (=) aor Ato. L__] 6 70 [-_] ator AiLo_] 7 so [1] atir AizL L_] a 6s (__] Aten Ais L_] 9 67 [_] aisr Al4L LJ 10 66 [_] aR (Note 4] Aish. J 14 CY7C09099 (1 BK x 8) 65 [__] aisriNote 4) [Note 5] Aish [__] 12 64 [-__] Aten [Note 5] voc EJ 1s CY7C09089 (64K x 8) cs [5 exo nc (=) 14 62 [.__I NC no 1 CY7C09079 (32K x 8) a Fae ne ==) 16 co [7 _I] nc nc LJ 17 59 (__] nc ceo. [==] 18 53 [-__] CEor ceE1_[C_] 19 57 [-_1 CE1A ontAstL [2] 20 56 [___] CNTRSTR AW CJ 21 55 [] pawn on Cl] 2 54 [__] dER [Note 6]FT/PIPEL [7] 23 53 [-__] FT/PIPERINote 6] ne [_] 24 52 [=] end nc] 25 51 [_] nc 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes: 4. This pinis NC for CY7C09079. 5. This pinis NC tor CY7C09079 and CY7CO9089. 6. For CY7C09079 and CY7C09089, pin #23 connected to Voc is equivalent to an IDT x8 pipelined device; connecting pin #23 and #53 to GND is equivalent to an IDT x8 flow-through device.CY7C09079/89/99 Pin Configurations (continued) BSS IAIN a SY CY7C09179/89/99 100-Pin TQ@FP (Top View) ANA INNA nc] 1 ncoL-_] 2 A7_[L_] 3 As_Ll_] 4 Fy a Ato. [==] 6 AtiLL-_] 7 AtzL ==] 8 AiLL__] 9 At4L ==] 10 [Note 7] AisL LJ 11 [Note 8] AtsL L] 12 vec LJ 13 nc(L_] 14 no C=] 15 nc C=] 16 nce(l] 17 ceo. _] is ceEi_[C_] 19 CNIASTIL [__] 20 RAWL [ZS] 21 SEL [T=] 22 FTPIPEL [__] 23 no [==] 24 NnoL__] 25 26 27 28 CY7C09199 (128K x 9) CY7C09189 (64K x 9) CY7C09179 (32K x 9) 100 99 98 97 96 95 94 93 92 91 90 89 88 37 86 85 84 8 82 81 8 79 78 TF 76 75 (_] nc 74 [__I] no 73 [-__] A7R 72 [J] ask 71 [J aor 70 [_] ator 69 [- 1 AtiR 68 [_] ater 67 L__] Ai3A 66 [__] A14A 65 [-_] Aish [Note 7] a | AIBA Note 8] 63 [-_] end ez ((_I] nc 61 LJ] nc so [__] nc 59 [_] nc 538 [__] CEor 57 [-__] CEIR 56 [__] CNTRSTR 55 ( _] AWA 54 [__] d&R 53 [- _] FrPiPer 52 [=] end 51 L_] nc = Sf = Selection Guide eee wo enon oe on] os. ] 8 os.[[7] & oe ov cno tL _ voiLl_] vooL [7] vec CJ cxno Cl voon[L_] voir Cc co sa Cc a a xcL__] = ~ ee (Both ports CMOS level) Cy7C09079/89/99 | CY7C09079/89/99 | CY7C09079/89/99 | CY7C09079/89/99 cy7C09179/89/99 | CY7C09179/89/99 | CY7C09179/89/99 | CY7C09179/89/99 -6 7 3 -12 fmax2 (MHz} (Pipelined) 100 83 67 50 Max Access Time (ns) (Clock to Data, 6.5 75 9 12 Pipelined) Typical Operating Current lee (mA) 250 235 215 195 Typical Standby Current for Igg, (mA) 45 40 35 30 (Both ports TTL Level) Typical Standby Current for logs (mA) 0.05 0.05 0.05 0.05 Notes: 7. This pin is NC for CY7C09179. 8. This pin is NC for CY7C09179 and CY7C09189.CY7C09079/89/99 SELINA RY CY7C09179/89/99 a Pin Definitions Left Port Right Port Description AogtAiei AorAi6r Address Inputs (AgAy4 for 32K; Aj-Ays for 64K; and AgAy, for 128K devices). ADSL ADSp Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. CE g,,CEy, | CEgR.CE;q_ | Chip Enable Input. To select either the left or right port, both CEy AND CE, must be asserted to their active states (CE) < V|_ and CE, > Vj). CLK. GLK Glock Signal. This input can be free running or strobed. Maximum clock input rate is fyyax. CNTEN_ CNTEN|, Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. CNTRST_, CNTRSTR Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. VOo_-VOg_. | VOgR-l/Og, | Data Bus Input/Output (l/Og/O-7 for x8 devices; |/OgI/Og for x9 devices). OE, OER Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. RW, RiWar Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. FT/PIPE, FT/PIPER Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. GND Ground Input. NG No Gonnect. Vec Power Input. Maximum Ratings Static Discharge Voltage oo... ee >1100V Lateh-Up Current... eee eee: >200mA (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature Ambient Temperature with Power Applied .55C to +125C beet eeeaeeneeeaeeees 65C to +150G Operating Range Ambient Supply Voltage to Ground Potential ............... 0.3V to +7.0V Range Temperature Vec DC Voltage Applied to Commercial 0C to +70C 5V + 10% Outputs in High Z State oo es 0.5V to +7.0V Industrial 40C to +85C 5V + 10% DG IMPUt VOIAGE sees teses ieee ieee 0.5V to +7.0V Shaded area contains advance information. Output Current into Outputs (LOW) oo... 20 mACY7C09079/89/99 ee SELINA RY CY7C09179/89/99 Le Electrical Characteristics Over the Operating Range C7C09079/89/99 CY7C09179/89/99 -6 7 -9 -12 Symbol Parameter Min | Typ | Max | Min | Typ | Max} Min | Typ | Max | Min | Typ | Max] Units Vou Output HIGH Voltage (Voc=Min, | 2.4 24 24 24 Vv VoL Output LOW Voltage (Vcc=Min, 04 04 0.4 0.4 Vv loH= +4.0 mA) Vi Input HIGH Voltage 2.2 22 22 2.2 Vv VIL Input LOW Voltage 0.8 0.8 0.8 0.8 Vv loz Output Leakage Current 10 10 |-10 10 | -10 10 | -10 10 | pA lec Operating Current Gom'l. 250 | 450 235 | 420 215 | 360 195 | 300) mA WVeo=Max, Iour=0 MA) [Tndust. 260 | 445 245 | 410 225 | 375 | mA Outputs Disabled Isp Standby Current (Bath Com. 45 | 115 40 | 105 35 | 95 30 | 85 | mA Ports TTL Level) CE, & CEp > Vin, fefyax Indust. 55 | 120 50 | 110 45 | 100) mA Isp Standby Current (One Com. 175 | 235 160 | 220 145 | 205 125 | 190] mA Port TTL Level)" CEL! | Tndust. 175 | 235 160 | 220 140 | 205 | mA CER 2 Vin. f=fmax Isa3 Standby Current (Both Com. 0.05] 0.25 0.05 | 0.25 05 [0.25 0.05/025| mA Ports CMOS Level) CE, & CEq> Voo-0.2V, Indust. 0.05] 0.25 0.05 | 0.25 0.05/0.25| mA f=0 lopa Standby Current (One Com'l. 160 | 200 145 | 185 130 | 170 110 | 150] mA Port GMOS Level) CE, | CEn > Vin, f=fmax Indust. 160 | 200 145 | 185 125 | 165] mA Shaded area contains advance information. Capacitance Parameter Description Test Conditions Max. Unit Cw Input Capacitance Ta =25C, f=1 MHz, 10 pF Cour Output Capacitance Voc = 5.0V 10 pF AC Test Loads 5V 5V Ri = 3932 Rr = 2502 OUTPUT, OUTPUT Ri = 8930 C= 300F OUTPUT re er'Lke R2= 3470 Ll Ca5 = pF R2 = 3470 (b) Thvenin Equivalent (Load 1) Note: ALL INPUT PULSES = VOH = 1.4V <3ns (c) Three-State Delay (Load 2) (Used for texiz, torz, & tonz including scope and jig) 9. CE, and CER are internal signals. To select either the left or right port, both CE, AND CE, must be asserted to their active states (CE, < Vi, and CE, > Vjy).CY7C09079/89/99 SELINA RY CY7C09179/89/99 Switching Characteristics Over the Operating Range CY7C09079/89/99 CY7C091 79/89/99 6 7 -3 -12 Symbol Parameter Min | Max | Min | Max | Min | Max | Min | Max | Units iMaAxt fmax Flow-Through 53 45 40 33 MHz IMAXK? fvax Pipelined 100 83 67 50 MHz teyet Clock Cycle Time - Flow-Through 19 22 25 30 ns teycs Clock Cycle Time - Pipelined 10 12 15 20 ns tou4 Glock HIGH Time - Flow-Through 6.5 75 12 12 ns teu Glock LOW Time - Flow-Through 6.5 75 12 12 ns toue Glock HIGH Time - Pipelined 4 8 ns tote Clack LOW Time - Pipelined 4 8 ns tr Clock Rise Time ns tr Clock Fall Time ns tsa Address Set-Up Time 3.5 4 4 4 ns tHa Address Hold Time 0 0 1 1 ns tsc Chip Enable Set-Up Time 3.5 4 4 4 ns tuc Chip Enable Hold Time 0 0 1 1 ns tsw RW Set-Up Time 3.5 4 4 4 ns tuw RAW Hold Time ) ) 1 1 ns tsp Input Data Set-Up Time 3.5 4 4 4 ns tub Input Data Hold Time 0 0 1 1 ns tsap ADS Set-Up Time 3.5 4 4 4 ns tap ADS Hold Time 0 0 1 1 ns tscn CNTEN Set-Up Time 3.5 4 4 4 ns ton CNTEN Hold Time ) ) 1 1 ns tsast CNTRST Set-Up Time 3.5 4 4 4 ns tuRst CNTRST Hold Time 0 0 1 1 ns toe Output Enable to Data Valid 8 9 10 12 ns to zl!@"l | OE to Low Z 2 2 ns tonz!!0-"l | OE to High Z 1 7 1 7 7 7 ns tep1 Clock to Data Valid - Flow-Through 15 18 20 25 ns tepe Clock to Data Valid - Pipelined 6.5 79 9 12 ns toc Data Output Hold After Clock HIGH ns toxuz!!9""l | Glock HIGH to Output High Z 9 9 9 9 ns toqp zt!" | Clock HIGH to Output Low Z ns Port to Port Delays tewop Write Port Clock HIGH to Read Data Delay 30 35 40 40 ns tecs Clock to Glock Set-Up Time 9 10 15 15 ns Note: 10. Test conditions used are Load 2. 11. This parameter is guaranteed by design, but is not production tested.CY7C09079/89/99 BRSLIMINASY CY7C09179/89/99 Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V,, )!!2-13-14.151 teyer He toy + tol clk __ fON FN NN tse tue nit DN | KOKI | OOO ODIO | XOXO tow tw tga ADDRESS DATAgut Read Cycle for Pipelined Operation (FT/PIPE = Vj4)!'2 19.1415) teyee bh boHoye tole a] FEo DON LAX, | AKAN LAX | KKK tsc tue OY [ROO OOK | ROOOOKN, | KX KKK MY IO | OOOO | XO XOAOOOK | XK tgw thw tsa tHaA ADDRESS An Ana Anse Ans DATA 1 Latency + tops toe OUT Q, Qn Qhie toHz"4 texLz 1 toLz OE ~\ toe Notes: 12. OEis asynchronously controlled; all other inputs are synchronous to the rising clock edge. 13. ADS = ., CNTEN and CNTRST = Vix. 14. The output is disabled (high-impedance state) by CEp=Vj4 or CE, = V1, following the next rising edge of the clock. 15. Addresses do not have to be accessed sequentially since ADS = V|, constantly loads the address on the rising edge of the CLK. Numbers are for reference only.CY7C09079/89/99 BRSLIMINASY CY7C09179/89/99 Switching Waveforms (continued) Bank Select Pipelined Read!''7] levee tone CLK, ADDRESS gy CEg pty DATAoutiet ADDRESS ip) CE (B2} DATAguT Be) Left Port Write to Flow-Through Right Port Read!!-19.20.21) CLK, RW, ADDRESS, DATA CLK RW ADDRESSR DATAoutR toc toe Notes: 16. Inthis depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS,a1) = ADDRESS pp). _ 17. OE and ADS = V): CEy 54), CEy52), R/W, CNTEN, and CNTRST = Vip. 18. The same waveforms apply for a right port write to flow-through left port read. 19. CE, and ADS = V,. CE,, CNTEN, and CNTRST = Vy. 20. OE=V;, for the Right Port, which is being read from. OE = V/,, for the Lett Port, which is being written to. 21. Itteggs maximum specified, then data from right port READ is not valid until the maximum specitied for toywpp. Ifteag>maximum specified, then data is not valid until tees + tepy. tewop does not apply in this case.FRSECUMINARY CY7C09079/89/99 CY7C09179/89/99 Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE = Vj, )!'5:22.28 24] ADDRESS DATA CLK lovee = toHe { tela | AXX te DATAout NO OPERATION WRITE Pipelined Read-to-Write-to-Read (OE Controlled)!'522.23.24] teve2 , clk COA ze, On | OX | AKAN | OOX | AON | OON | AON ce, aw XO A tsw tuw ADDRESS toa tua tsp| typ | ONT Bs KKK KX tepe texLz tepe DATAgut Q, Qhia yy LL OE PIRI. - - READ WRITE READ - - Notes: 22. Output state (HIGH, LOW,_or High-Impedance} is determined by the previous cycle control signals. 23. CE, and ADS = Vi; CEy, CNTEN, and CNTRST = V IH: 24. During No operation, data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. 10CY7C09079/89/99 BRSLIMINASY CY7C09179/89/99 Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read (OE = V,, )!19-16:22.23] tover tout tou CLK fa sf ADDRESS DATA DATAout NO OPERATIO Flow-Through Read-to-Write-to-Read (OE Controlled)!'3.16.22.23] teyer tcHi tou ADDRESS DATAin DATAout Ona toe OE READ - 11CY7C09079/89/99 BRSLIMINASY CY7C09179/89/99 Switching Waveforms (continued) Pipelined Read with Address Counter Advance!25] lovee tele tone CLK tHA ADDRESS DATAgut Qe Qn43 Q, Q, One Qy4 READ - EXTERNAL ADDRESS Flow-Through Read with Address Counter Advance!=l toc COUNTER HOLD READ WITH COUNTER READ WITH COUNTER teyci toy tou CLK ADDRESS tHaD tHoN Ona Qn Qnee DATAgut Q, toe READ READ EXTERNAL READ WITH COUNTER COUNTER HOLD WITH ADDRESS COUNTER Note: 25. CE, and OF = V; CE,, RAV and CNTRST = Vi. 12FRSECUMINARY CY7C09079/89/99 CY7C09179/89/99 SESE Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs)}?6.27] teyc2 toHe | tote ork XY KV VV KV KH \ __ tsa ta INTERNAL ADDRESS KKK An x Anat DK Ane DK Ans DK Ani tsap tab XN AXY | XXY XY OY N NON onTen XY | SOON tsen tHoN DATA BD, Der KKK Oe Dniz Drig Disa tsp tub WRITE EXTERNAL WRITE WITH | WRITE COUNTER ADDRESS ~M COUNTER HOLD ~ WRITE WITH COUNTER Notes: 26. CE, and RW = V\; CE, and CNTRST = Vj. 27. The Internal Address is equal to the External Address when ADS = V|, and equals the counter output when ADS = Vy. 13CY7C09079/89/99 = SELINA RY CY7C09179/89/99 Switching Waveforms (continued) Counter Reset (Pipelined Outputs)!'5.22.28.2] teve2 tone | tere _/ tsa | tua INTERNAL A 0 1 A A ADDRESS xX x x 0K Ana tow | tow ni XD | KXY (XXY OY RO SAD HAD ADS XK YY KY YY AXKXX BX tscn tuen onTEN KY | NOX | OOK OOK KOO ROO IXY tsrst tHRST CNTRST xr AK ts ix KY KY KY COUNTER | WRITE (|) READ _ | = = READ |) READ RESET ADDRESS 0 ADDRESS 0 ADDRESS 1 ADDRESS n Notes: 28. CEg=V\; CEy =Viy. 29. Nodead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 14CY7C09079/89/99 got SRSL MN A RY CY7C09179/89/99 =e Read/Write and Enable Operation!**" #2! Inputs Outputs OE | CLK CE, CE, | R/W VOo4/O, Operation igh- 133] xX H x xX High-2 Deselected igh- [33] xX _ x L xX High-7 Deselected x _ L H L Din Write Lf oe L H H Dout Readl?= H X L H x High-7 Outputs Disabled Address Counter Control Operation!4 5.341 Previous Address | Address | CLK DS | CNTEN | CNTRST He) Mode Operation Xx x _ Xx x L Deui(o) Reset Counter Reset to Address 0 An X ir L x H Doutiny Load Address Load into Counter Xx An cr H H H Doutiny Hold External Address BlockedCounter Disabled x Ay _ H L Doutinet) | Increment | Counter EnabledInternal Address Generation Notes: 30. X"= Dont Care, H" = Vj, Ll = Vj. 31. ADS, CNTEN, CNTRST = Don't Care. 32. OEis an asynchronous input signal. 33. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle. 34. CE, and OF = V; Ce, and R/W= VL. 35. Data shown for flow-through mode: pipelined mode output will be delayed by one cycle. 36. Counter operation is independent of CE, and GE. 15CY7C09079/89/99 SELINA RY CY7C09179/89/99 Ordering Information 32K x8 Synchronous Dual-Port SRAM Speed Package Operating ns) Ordering Code Name Package Type ange 6.5 CY7C03079-6AG A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C09079-7AG A100 100-Pin Thin Quad Flat Pack Commercial C7G09079-7Al At0G 100-Pin Thin Quad Flat Pack Industrial 9 CY7C03079-9AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09079-9Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09079-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09079-12Al Atoo 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 64K x8 Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 6.5 CY7C0390893-6AC A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C09089-7AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09089-7Al Atoo 100-Pin Thin Quad Flat Pack Industrial 9 CY7C09089-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09089-9Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09089-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09089-12Al A100 106-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 128K x8 Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 6.5 CY7C09099-6AC A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C03099-7AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09099-7Al A100 106-Pin Thin Quad Flat Pack Industrial 9 CY7C09099-9AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09099-9Al AtoG 100-Pin Thin Quad Flat Pack Industrial 12 CY7C03099-12AC A100 100-Pin Thin Quad Flat Pack Commercial GY7C09099-12Al A100 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 16CY7C09079/89/99 SELINA RY CY7C09179/89/99 Ordering Information (continued) 32K x9 Synchronous Dual-Port SRAM Speed Package Operating ns) Ordering Code Name Package Type ange 6.5 CY7C09179-6AG A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C09179-7AG A100 100-Pin Thin Quad Flat Pack Commercial C7G09179-7Al At0G 100-Pin Thin Quad Flat Pack Industrial 9 CY7C09179-9AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09179-9Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09179-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09179-12Al Atoo 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 64K x9 Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 6.5 CY7C09189-6AC A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C09189-7AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09189-7Al Atoo 100-Pin Thin Quad Flat Pack Industrial 9 CY7C09189-9AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09189-9Al A100 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09189-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09189-12Al A100 106-Pin Thin Quad Flat Pack Industrial Shaded area contains advance information. 128K x9 Synchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 6.5 CY7C09199-6AC A100 100-Pin Thin Quad Flat Pack Commercial 75 CY7C09199-7AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09199-7Al A100 106-Pin Thin Quad Flat Pack Industrial 9 CY7C09199-9AG A100 100-Pin Thin Quad Flat Pack Commercial CY7C09199-9Al AtoG 100-Pin Thin Quad Flat Pack Industrial 12 CY7C09199-12AC A100 100-Pin Thin Quad Flat Pack Commercial GY7G09199-12Al A100 100-Pin Thin Quad Flat Pack Industrial Shaded area contains advanced information. Document #: 38-00663-D 17CY7C09079/89/99 OSHRSS PRE UANNARY CY7C09179/89/99 Sao ke EE ead Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 16002025 SO 14.0020.05 $0 DIMENSIONS ARE IN MILLIMETERS. 0222005 R 0.09 MIN. O MIN. 20 MAX. STAND-DFF 0.05 MIN. ( oo \ | 0.25 | O15 MAX. | C GAUGE PLANE r =-3-5 = ite om 050 020 MIN. TYP. == 1.602015 1.00 REF. - 51-85048-A DETAIL A SEE DETAIL A Cypress Semiconductor Corporation, 1998. The information contained herein is subject io change without notice. Cypress Semiconductor Corporation assumes no responsibility tor the use ofany circuitry other than circuliry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical componenis in life-support systems where a maliunction or failure may reasonably be expected io resull in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.